drivers/gpu/drm/radeon/evergreen_hdmi.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Christian König.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Christian König
  25  *          Rafał Miłecki
  26  */
  27 #include <linux/hdmi.h>
  28 #include <drm/drmP.h>
  29 #include <drm/radeon_drm.h>
  30 #include "radeon.h"
  31 #include "radeon_asic.h"
  32 #include "radeon_audio.h"
  33 #include "evergreend.h"
  34 #include "atom.h"
  35
  36 extern void dce6_afmt_select_pin(struct drm_encoder *encoder);
  37 extern void dce6_afmt_write_latency_fields(struct drm_encoder *encoder,
  38                                            struct drm_display_mode *mode);
  39
  40 /* enable the audio stream */
  41 static void dce4_audio_enable(struct radeon_device *rdev,
  42                               struct r600_audio_pin *pin,
  43                               u8 enable_mask)
  44 {
  45         u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);
  46
  47         if (!pin)
  48                 return;
  49
  50         if (enable_mask) {
  51                 tmp |= AUDIO_ENABLED;
  52                 if (enable_mask & 1)
  53                         tmp |= PIN0_AUDIO_ENABLED;
  54                 if (enable_mask & 2)
  55                         tmp |= PIN1_AUDIO_ENABLED;
  56                 if (enable_mask & 4)
  57                         tmp |= PIN2_AUDIO_ENABLED;
  58                 if (enable_mask & 8)
  59                         tmp |= PIN3_AUDIO_ENABLED;
  60         } else {
  61                 tmp &= ~(AUDIO_ENABLED |
  62                          PIN0_AUDIO_ENABLED |
  63                          PIN1_AUDIO_ENABLED |
  64                          PIN2_AUDIO_ENABLED |
  65                          PIN3_AUDIO_ENABLED);
  66         }
  67
  68         WREG32(AZ_HOT_PLUG_CONTROL, tmp);
  69 }
  70
  71 /*
  72  * update the N and CTS parameters for a given pixel clock rate
  73  */
  74 static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
  75 {
  76         struct drm_device *dev = encoder->dev;
  77         struct radeon_device *rdev = dev->dev_private;
  78         struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
  79         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  80         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  81         uint32_t offset = dig->afmt->offset;
  82
  83         WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz));
  84         WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz);
  85
  86         WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz));
  87         WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz);
  88
  89         WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr.cts_48khz));
  90         WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz);
  91 }
  92
  93 static void dce4_afmt_write_latency_fields(struct drm_encoder *encoder,
  94                                            struct drm_display_mode *mode)
  95 {
  96         struct radeon_device *rdev = encoder->dev->dev_private;
  97         struct drm_connector *connector;
  98         struct radeon_connector *radeon_connector = NULL;
  99         u32 tmp = 0;
 100
 101         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
 102                 if (connector->encoder == encoder) {
 103                         radeon_connector = to_radeon_connector(connector);
 104                         break;
 105                 }
 106         }
 107
 108         if (!radeon_connector) {
 109                 DRM_ERROR("Couldn't find encoder's connector\n");
 110                 return;
 111         }
 112
 113         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 114                 if (connector->latency_present[1])
 115                         tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |
 116                                 AUDIO_LIPSYNC(connector->audio_latency[1]);
 117                 else
 118                         tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
 119         } else {
 120                 if (connector->latency_present[0])
 121                         tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
 122                                 AUDIO_LIPSYNC(connector->audio_latency[0]);
 123                 else
 124                         tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
 125         }
 126         WREG32(AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp);
 127 }
 128
 129 void dce4_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
 130         u8 *sadb, int sad_count)
 131 {
 132         struct radeon_device *rdev = encoder->dev->dev_private;
 133         u32 tmp;
 134
 135         /* program the speaker allocation */
 136         tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
 137         tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
 138         /* set HDMI mode */
 139         tmp |= HDMI_CONNECTION;
 140         if (sad_count)
 141                 tmp |= SPEAKER_ALLOCATION(sadb[0]);
 142         else
 143                 tmp |= SPEAKER_ALLOCATION(5); /* stereo */
 144         WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
 145 }
 146
 147 void dce4_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
 148         u8 *sadb, int sad_count)
 149 {
 150         struct radeon_device *rdev = encoder->dev->dev_private;
 151         u32 tmp;
 152
 153         /* program the speaker allocation */
 154         tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
 155         tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK);
 156         /* set DP mode */
 157         tmp |= DP_CONNECTION;
 158         if (sad_count)
 159                 tmp |= SPEAKER_ALLOCATION(sadb[0]);
 160         else
 161                 tmp |= SPEAKER_ALLOCATION(5); /* stereo */
 162         WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
 163 }
 164
 165 void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder,
 166         struct cea_sad *sads, int sad_count)
 167 {
 168         int i;
 169         struct radeon_device *rdev = encoder->dev->dev_private;
 170         static const u16 eld_reg_to_type[][2] = {
 171                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
 172                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
 173                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
 174                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
 175                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
 176                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
 177                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
 178                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
 179                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
 180                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
 181                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
 182                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
 183         };
 184
 185         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
 186                 u32 value = 0;
 187                 u8 stereo_freqs = 0;
 188                 int max_channels = -1;
 189                 int j;
 190
 191                 for (j = 0; j < sad_count; j++) {
 192                         struct cea_sad *sad = &sads[j];
 193
 194                         if (sad->format == eld_reg_to_type[i][1]) {
 195                                 if (sad->channels > max_channels) {
 196                                         value = MAX_CHANNELS(sad->channels) |
 197                                                 DESCRIPTOR_BYTE_2(sad->byte2) |
 198                                                 SUPPORTED_FREQUENCIES(sad->freq);
 199                                         max_channels = sad->channels;
 200                                 }
 201
 202                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
 203                                         stereo_freqs |= sad->freq;
 204                                 else
 205                                         break;
 206                         }
 207                 }
 208
 209                 value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);
 210
 211                 WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value);
 212         }
 213 }
 214
 215 /*
 216  * build a HDMI Video Info Frame
 217  */
 218 static void evergreen_hdmi_update_avi_infoframe(struct drm_encoder *encoder,
 219                                                 void *buffer, size_t size)
 220 {
 221         struct drm_device *dev = encoder->dev;
 222         struct radeon_device *rdev = dev->dev_private;
 223         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 224         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 225         uint32_t offset = dig->afmt->offset;
 226         uint8_t *frame = buffer + 3;
 227         uint8_t *header = buffer;
 228
 229         WREG32(AFMT_AVI_INFO0 + offset,
 230                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
 231         WREG32(AFMT_AVI_INFO1 + offset,
 232                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
 233         WREG32(AFMT_AVI_INFO2 + offset,
 234                 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
 235         WREG32(AFMT_AVI_INFO3 + offset,
 236                 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
 237 }
 238
 239 static void evergreen_audio_set_dto(struct drm_encoder *encoder, u32 clock)
 240 {
 241         struct drm_device *dev = encoder->dev;
 242         struct radeon_device *rdev = dev->dev_private;
 243         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 244         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 245         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 246         u32 base_rate = 24000;
 247         u32 max_ratio = clock / base_rate;
 248         u32 dto_phase;
 249         u32 dto_modulo = clock;
 250         u32 wallclock_ratio;
 251         u32 dto_cntl;
 252
 253         if (!dig || !dig->afmt)
 254                 return;
 255
 256         if (ASIC_IS_DCE6(rdev)) {
 257                 dto_phase = 24 * 1000;
 258         } else {
 259                 if (max_ratio >= 8) {
 260                         dto_phase = 192 * 1000;
 261                         wallclock_ratio = 3;
 262                 } else if (max_ratio >= 4) {
 263                         dto_phase = 96 * 1000;
 264                         wallclock_ratio = 2;
 265                 } else if (max_ratio >= 2) {
 266                         dto_phase = 48 * 1000;
 267                         wallclock_ratio = 1;
 268                 } else {
 269                         dto_phase = 24 * 1000;
 270                         wallclock_ratio = 0;
 271                 }
 272                 dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
 273                 dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
 274                 WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl);
 275         }
 276
 277         /* XXX two dtos; generally use dto0 for hdmi */
 278         /* Express [24MHz / target pixel clock] as an exact rational
 279          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
 280          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
 281          */
 282         WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id));
 283         WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);
 284         WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo);
 285 }
 286
 287
 288 /*
 289  * update the info frames with the data from the current display mode
 290  */
 291 void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
 292 {
 293         struct drm_device *dev = encoder->dev;
 294         struct radeon_device *rdev = dev->dev_private;
 295         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 296         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 297         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 298         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
 299         struct hdmi_avi_infoframe frame;
 300         uint32_t offset;
 301         ssize_t err;
 302         uint32_t val;
 303         int bpc = 8;
 304
 305         if (!dig || !dig->afmt)
 306                 return;
 307
 308         /* Silent, r600_hdmi_enable will raise WARN for us */
 309         if (!dig->afmt->enabled)
 310                 return;
 311         offset = dig->afmt->offset;
 312
 313         /* hdmi deep color mode general control packets setup, if bpc > 8 */
 314         if (encoder->crtc) {
 315                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 316                 bpc = radeon_crtc->bpc;
 317         }
 318
 319         /* disable audio prior to setting up hw */
 320         if (ASIC_IS_DCE6(rdev)) {
 321                 dig->afmt->pin = dce6_audio_get_pin(rdev);
 322                 dce6_audio_enable(rdev, dig->afmt->pin, 0);
 323         } else {
 324                 dig->afmt->pin = r600_audio_get_pin(rdev);
 325                 dce4_audio_enable(rdev, dig->afmt->pin, 0);
 326         }
 327
 328         evergreen_audio_set_dto(encoder, mode->clock);
 329
 330         WREG32(HDMI_VBI_PACKET_CONTROL + offset,
 331                HDMI_NULL_SEND); /* send null packets when required */
 332
 333         WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
 334
 335         val = RREG32(HDMI_CONTROL + offset);
 336         val &= ~HDMI_DEEP_COLOR_ENABLE;
 337         val &= ~HDMI_DEEP_COLOR_DEPTH_MASK;
 338
 339         switch (bpc) {
 340                 case 0:
 341                 case 6:
 342                 case 8:
 343                 case 16:
 344                 default:
 345                         DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
 346                                          connector->name, bpc);
 347                         break;
 348                 case 10:
 349                         val |= HDMI_DEEP_COLOR_ENABLE;
 350                         val |= HDMI_DEEP_COLOR_DEPTH(HDMI_30BIT_DEEP_COLOR);
 351                         DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
 352                                          connector->name);
 353                         break;
 354                 case 12:
 355                         val |= HDMI_DEEP_COLOR_ENABLE;
 356                         val |= HDMI_DEEP_COLOR_DEPTH(HDMI_36BIT_DEEP_COLOR);
 357                         DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
 358                                          connector->name);
 359                         break;
 360         }
 361
 362         WREG32(HDMI_CONTROL + offset, val);
 363
 364         WREG32(HDMI_VBI_PACKET_CONTROL + offset,
 365                HDMI_NULL_SEND | /* send null packets when required */
 366                HDMI_GC_SEND | /* send general control packets */
 367                HDMI_GC_CONT); /* send general control packets every frame */
 368
 369         WREG32(HDMI_INFOFRAME_CONTROL0 + offset,
 370                HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
 371                HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */
 372
 373         WREG32(AFMT_INFOFRAME_CONTROL0 + offset,
 374                AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
 375
 376         WREG32(HDMI_INFOFRAME_CONTROL1 + offset,
 377                HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */
 378
 379         WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
 380
 381         WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
 382                HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */
 383                HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
 384
 385         WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
 386                AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
 387
 388         /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
 389
 390         if (bpc > 8)
 391                 WREG32(HDMI_ACR_PACKET_CONTROL + offset,
 392                        HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
 393         else
 394                 WREG32(HDMI_ACR_PACKET_CONTROL + offset,
 395                        HDMI_ACR_SOURCE | /* select SW CTS value */
 396                        HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
 397
 398         evergreen_hdmi_update_ACR(encoder, mode->clock);
 399
 400         WREG32(AFMT_60958_0 + offset,
 401                AFMT_60958_CS_CHANNEL_NUMBER_L(1));
 402
 403         WREG32(AFMT_60958_1 + offset,
 404                AFMT_60958_CS_CHANNEL_NUMBER_R(2));
 405
 406         WREG32(AFMT_60958_2 + offset,
 407                AFMT_60958_CS_CHANNEL_NUMBER_2(3) |
 408                AFMT_60958_CS_CHANNEL_NUMBER_3(4) |
 409                AFMT_60958_CS_CHANNEL_NUMBER_4(5) |
 410                AFMT_60958_CS_CHANNEL_NUMBER_5(6) |
 411                AFMT_60958_CS_CHANNEL_NUMBER_6(7) |
 412                AFMT_60958_CS_CHANNEL_NUMBER_7(8));
 413
 414         radeon_audio_write_speaker_allocation(encoder);
 415
 416         WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset,
 417                AFMT_AUDIO_CHANNEL_ENABLE(0xff));
 418
 419         /* fglrx sets 0x40 in 0x5f80 here */
 420
 421         if (ASIC_IS_DCE6(rdev)) {
 422                 dce6_afmt_select_pin(encoder);
 423                 dce6_afmt_write_latency_fields(encoder, mode);
 424         } else {
 425                 dce4_afmt_write_latency_fields(encoder, mode);
 426         }
 427
 428         radeon_audio_write_sad_regs(encoder);
 429
 430         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
 431         if (err < 0) {
 432                 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
 433                 return;
 434         }
 435
 436         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
 437         if (err < 0) {
 438                 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
 439                 return;
 440         }
 441
 442         evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
 443
 444         WREG32_OR(HDMI_INFOFRAME_CONTROL0 + offset,
 445                   HDMI_AVI_INFO_SEND | /* enable AVI info frames */
 446                   HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */
 447
 448         WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset,
 449                  HDMI_AVI_INFO_LINE(2), /* anything other than 0 */
 450                  ~HDMI_AVI_INFO_LINE_MASK);
 451
 452         WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset,
 453                   AFMT_AUDIO_SAMPLE_SEND); /* send audio packets */
 454
 455         /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
 456         WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
 457         WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
 458         WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001);
 459         WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001);
 460
 461         /* enable audio after to setting up hw */
 462         if (ASIC_IS_DCE6(rdev))
 463                 dce6_audio_enable(rdev, dig->afmt->pin, 1);
 464         else
 465                 dce4_audio_enable(rdev, dig->afmt->pin, 0xf);
 466 }
 467
 468 void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)
 469 {
 470         struct drm_device *dev = encoder->dev;
 471         struct radeon_device *rdev = dev->dev_private;
 472         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 473         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 474
 475         if (!dig || !dig->afmt)
 476                 return;
 477
 478         /* Silent, r600_hdmi_enable will raise WARN for us */
 479         if (enable && dig->afmt->enabled)
 480                 return;
 481         if (!enable && !dig->afmt->enabled)
 482                 return;
 483
 484         if (!enable && dig->afmt->pin) {
 485                 if (ASIC_IS_DCE6(rdev))
 486                         dce6_audio_enable(rdev, dig->afmt->pin, 0);
 487                 else
 488                         dce4_audio_enable(rdev, dig->afmt->pin, 0);
 489                 dig->afmt->pin = NULL;
 490         }
 491
 492         dig->afmt->enabled = enable;
 493
 494         DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
 495                   enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
 496 }