drivers/gpu/drm/radeon/evergreen.c

   1 /*
   2  * Copyright 2010 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/slab.h>
  27 #include "drmP.h"
  28 #include "radeon.h"
  29 #include "radeon_asic.h"
  30 #include "radeon_drm.h"
  31 #include "evergreend.h"
  32 #include "atom.h"
  33 #include "avivod.h"
  34 #include "evergreen_reg.h"
  35 #include "evergreen_blit_shaders.h"
  36
  37 #define EVERGREEN_PFP_UCODE_SIZE 1120
  38 #define EVERGREEN_PM4_UCODE_SIZE 1376
  39
  40 static void evergreen_gpu_init(struct radeon_device *rdev);
  41 void evergreen_fini(struct radeon_device *rdev);
  42 void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
  43 extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
  44                                      int ring, u32 cp_int_cntl);
  45
  46 void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
  47                              unsigned *bankh, unsigned *mtaspect,
  48                              unsigned *tile_split)
  49 {
  50         *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
  51         *bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
  52         *mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
  53         *tile_split = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
  54         switch (*bankw) {
  55         default:
  56         case 1: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_1; break;
  57         case 2: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_2; break;
  58         case 4: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_4; break;
  59         case 8: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_8; break;
  60         }
  61         switch (*bankh) {
  62         default:
  63         case 1: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_1; break;
  64         case 2: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_2; break;
  65         case 4: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_4; break;
  66         case 8: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_8; break;
  67         }
  68         switch (*mtaspect) {
  69         default:
  70         case 1: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1; break;
  71         case 2: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2; break;
  72         case 4: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4; break;
  73         case 8: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8; break;
  74         }
  75 }
  76
  77 void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
  78 {
  79         u16 ctl, v;
  80         int cap, err;
  81
  82         cap = pci_pcie_cap(rdev->pdev);
  83         if (!cap)
  84                 return;
  85
  86         err = pci_read_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, &ctl);
  87         if (err)
  88                 return;
  89
  90         v = (ctl & PCI_EXP_DEVCTL_READRQ) >> 12;
  91
  92         /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it
  93          * to avoid hangs or perfomance issues
  94          */
  95         if ((v == 0) || (v == 6) || (v == 7)) {
  96                 ctl &= ~PCI_EXP_DEVCTL_READRQ;
  97                 ctl |= (2 << 12);
  98                 pci_write_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, ctl);
  99         }
 100 }
 101
 102 void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc)
 103 {
 104         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
 105         int i;
 106
 107         if (RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_MASTER_EN) {
 108                 for (i = 0; i < rdev->usec_timeout; i++) {
 109                         if (!(RREG32(EVERGREEN_CRTC_STATUS + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_V_BLANK))
 110                                 break;
 111                         udelay(1);
 112                 }
 113                 for (i = 0; i < rdev->usec_timeout; i++) {
 114                         if (RREG32(EVERGREEN_CRTC_STATUS + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_V_BLANK)
 115                                 break;
 116                         udelay(1);
 117                 }
 118         }
 119 }
 120
 121 void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
 122 {
 123         /* enable the pflip int */
 124         radeon_irq_kms_pflip_irq_get(rdev, crtc);
 125 }
 126
 127 void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
 128 {
 129         /* disable the pflip int */
 130         radeon_irq_kms_pflip_irq_put(rdev, crtc);
 131 }
 132
 133 u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
 134 {
 135         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 136         u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
 137         int i;
 138
 139         /* Lock the graphics update lock */
 140         tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
 141         WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
 142
 143         /* update the scanout addresses */
 144         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
 145                upper_32_bits(crtc_base));
 146         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 147                (u32)crtc_base);
 148
 149         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
 150                upper_32_bits(crtc_base));
 151         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 152                (u32)crtc_base);
 153
 154         /* Wait for update_pending to go high. */
 155         for (i = 0; i < rdev->usec_timeout; i++) {
 156                 if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING)
 157                         break;
 158                 udelay(1);
 159         }
 160         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
 161
 162         /* Unlock the lock, so double-buffering can take place inside vblank */
 163         tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
 164         WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
 165
 166         /* Return current update_pending status: */
 167         return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
 168 }
 169
 170 /* get temperature in millidegrees */
 171 int evergreen_get_temp(struct radeon_device *rdev)
 172 {
 173         u32 temp, toffset;
 174         int actual_temp = 0;
 175
 176         if (rdev->family == CHIP_JUNIPER) {
 177                 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
 178                         TOFFSET_SHIFT;
 179                 temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >>
 180                         TS0_ADC_DOUT_SHIFT;
 181
 182                 if (toffset & 0x100)
 183                         actual_temp = temp / 2 - (0x200 - toffset);
 184                 else
 185                         actual_temp = temp / 2 + toffset;
 186
 187                 actual_temp = actual_temp * 1000;
 188
 189         } else {
 190                 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
 191                         ASIC_T_SHIFT;
 192
 193                 if (temp & 0x400)
 194                         actual_temp = -256;
 195                 else if (temp & 0x200)
 196                         actual_temp = 255;
 197                 else if (temp & 0x100) {
 198                         actual_temp = temp & 0x1ff;
 199                         actual_temp |= ~0x1ff;
 200                 } else
 201                         actual_temp = temp & 0xff;
 202
 203                 actual_temp = (actual_temp * 1000) / 2;
 204         }
 205
 206         return actual_temp;
 207 }
 208
 209 int sumo_get_temp(struct radeon_device *rdev)
 210 {
 211         u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
 212         int actual_temp = temp - 49;
 213
 214         return actual_temp * 1000;
 215 }
 216
 217 void sumo_pm_init_profile(struct radeon_device *rdev)
 218 {
 219         int idx;
 220
 221         /* default */
 222         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 223         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 224         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 225         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 226
 227         /* low,mid sh/mh */
 228         if (rdev->flags & RADEON_IS_MOBILITY)
 229                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 230         else
 231                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 232
 233         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
 234         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
 235         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 236         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 237
 238         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
 239         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
 240         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 241         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 242
 243         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
 244         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
 245         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 246         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 247
 248         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
 249         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
 250         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 251         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 252
 253         /* high sh/mh */
 254         idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 255         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
 256         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
 257         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 258         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx =
 259                 rdev->pm.power_state[idx].num_clock_modes - 1;
 260
 261         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
 262         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
 263         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 264         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx =
 265                 rdev->pm.power_state[idx].num_clock_modes - 1;
 266 }
 267
 268 void evergreen_pm_misc(struct radeon_device *rdev)
 269 {
 270         int req_ps_idx = rdev->pm.requested_power_state_index;
 271         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 272         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 273         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 274
 275         if (voltage->type == VOLTAGE_SW) {
 276                 /* 0xff01 is a flag rather then an actual voltage */
 277                 if (voltage->voltage == 0xff01)
 278                         return;
 279                 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
 280                         radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
 281                         rdev->pm.current_vddc = voltage->voltage;
 282                         DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
 283                 }
 284                 /* 0xff01 is a flag rather then an actual voltage */
 285                 if (voltage->vddci == 0xff01)
 286                         return;
 287                 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
 288                         radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
 289                         rdev->pm.current_vddci = voltage->vddci;
 290                         DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci);
 291                 }
 292         }
 293 }
 294
 295 void evergreen_pm_prepare(struct radeon_device *rdev)
 296 {
 297         struct drm_device *ddev = rdev->ddev;
 298         struct drm_crtc *crtc;
 299         struct radeon_crtc *radeon_crtc;
 300         u32 tmp;
 301
 302         /* disable any active CRTCs */
 303         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 304                 radeon_crtc = to_radeon_crtc(crtc);
 305                 if (radeon_crtc->enabled) {
 306                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
 307                         tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
 308                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 309                 }
 310         }
 311 }
 312
 313 void evergreen_pm_finish(struct radeon_device *rdev)
 314 {
 315         struct drm_device *ddev = rdev->ddev;
 316         struct drm_crtc *crtc;
 317         struct radeon_crtc *radeon_crtc;
 318         u32 tmp;
 319
 320         /* enable any active CRTCs */
 321         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 322                 radeon_crtc = to_radeon_crtc(crtc);
 323                 if (radeon_crtc->enabled) {
 324                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
 325                         tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
 326                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 327                 }
 328         }
 329 }
 330
 331 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 332 {
 333         bool connected = false;
 334
 335         switch (hpd) {
 336         case RADEON_HPD_1:
 337                 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 338                         connected = true;
 339                 break;
 340         case RADEON_HPD_2:
 341                 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 342                         connected = true;
 343                 break;
 344         case RADEON_HPD_3:
 345                 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 346                         connected = true;
 347                 break;
 348         case RADEON_HPD_4:
 349                 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 350                         connected = true;
 351                 break;
 352         case RADEON_HPD_5:
 353                 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 354                         connected = true;
 355                 break;
 356         case RADEON_HPD_6:
 357                 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 358                         connected = true;
 359                         break;
 360         default:
 361                 break;
 362         }
 363
 364         return connected;
 365 }
 366
 367 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
 368                                 enum radeon_hpd_id hpd)
 369 {
 370         u32 tmp;
 371         bool connected = evergreen_hpd_sense(rdev, hpd);
 372
 373         switch (hpd) {
 374         case RADEON_HPD_1:
 375                 tmp = RREG32(DC_HPD1_INT_CONTROL);
 376                 if (connected)
 377                         tmp &= ~DC_HPDx_INT_POLARITY;
 378                 else
 379                         tmp |= DC_HPDx_INT_POLARITY;
 380                 WREG32(DC_HPD1_INT_CONTROL, tmp);
 381                 break;
 382         case RADEON_HPD_2:
 383                 tmp = RREG32(DC_HPD2_INT_CONTROL);
 384                 if (connected)
 385                         tmp &= ~DC_HPDx_INT_POLARITY;
 386                 else
 387                         tmp |= DC_HPDx_INT_POLARITY;
 388                 WREG32(DC_HPD2_INT_CONTROL, tmp);
 389                 break;
 390         case RADEON_HPD_3:
 391                 tmp = RREG32(DC_HPD3_INT_CONTROL);
 392                 if (connected)
 393                         tmp &= ~DC_HPDx_INT_POLARITY;
 394                 else
 395                         tmp |= DC_HPDx_INT_POLARITY;
 396                 WREG32(DC_HPD3_INT_CONTROL, tmp);
 397                 break;
 398         case RADEON_HPD_4:
 399                 tmp = RREG32(DC_HPD4_INT_CONTROL);
 400                 if (connected)
 401                         tmp &= ~DC_HPDx_INT_POLARITY;
 402                 else
 403                         tmp |= DC_HPDx_INT_POLARITY;
 404                 WREG32(DC_HPD4_INT_CONTROL, tmp);
 405                 break;
 406         case RADEON_HPD_5:
 407                 tmp = RREG32(DC_HPD5_INT_CONTROL);
 408                 if (connected)
 409                         tmp &= ~DC_HPDx_INT_POLARITY;
 410                 else
 411                         tmp |= DC_HPDx_INT_POLARITY;
 412                 WREG32(DC_HPD5_INT_CONTROL, tmp);
 413                         break;
 414         case RADEON_HPD_6:
 415                 tmp = RREG32(DC_HPD6_INT_CONTROL);
 416                 if (connected)
 417                         tmp &= ~DC_HPDx_INT_POLARITY;
 418                 else
 419                         tmp |= DC_HPDx_INT_POLARITY;
 420                 WREG32(DC_HPD6_INT_CONTROL, tmp);
 421                 break;
 422         default:
 423                 break;
 424         }
 425 }
 426
 427 void evergreen_hpd_init(struct radeon_device *rdev)
 428 {
 429         struct drm_device *dev = rdev->ddev;
 430         struct drm_connector *connector;
 431         u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
 432                 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
 433
 434         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 435                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 436                 switch (radeon_connector->hpd.hpd) {
 437                 case RADEON_HPD_1:
 438                         WREG32(DC_HPD1_CONTROL, tmp);
 439                         rdev->irq.hpd[0] = true;
 440                         break;
 441                 case RADEON_HPD_2:
 442                         WREG32(DC_HPD2_CONTROL, tmp);
 443                         rdev->irq.hpd[1] = true;
 444                         break;
 445                 case RADEON_HPD_3:
 446                         WREG32(DC_HPD3_CONTROL, tmp);
 447                         rdev->irq.hpd[2] = true;
 448                         break;
 449                 case RADEON_HPD_4:
 450                         WREG32(DC_HPD4_CONTROL, tmp);
 451                         rdev->irq.hpd[3] = true;
 452                         break;
 453                 case RADEON_HPD_5:
 454                         WREG32(DC_HPD5_CONTROL, tmp);
 455                         rdev->irq.hpd[4] = true;
 456                         break;
 457                 case RADEON_HPD_6:
 458                         WREG32(DC_HPD6_CONTROL, tmp);
 459                         rdev->irq.hpd[5] = true;
 460                         break;
 461                 default:
 462                         break;
 463                 }
 464                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
 465         }
 466         if (rdev->irq.installed)
 467                 evergreen_irq_set(rdev);
 468 }
 469
 470 void evergreen_hpd_fini(struct radeon_device *rdev)
 471 {
 472         struct drm_device *dev = rdev->ddev;
 473         struct drm_connector *connector;
 474
 475         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 476                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 477                 switch (radeon_connector->hpd.hpd) {
 478                 case RADEON_HPD_1:
 479                         WREG32(DC_HPD1_CONTROL, 0);
 480                         rdev->irq.hpd[0] = false;
 481                         break;
 482                 case RADEON_HPD_2:
 483                         WREG32(DC_HPD2_CONTROL, 0);
 484                         rdev->irq.hpd[1] = false;
 485                         break;
 486                 case RADEON_HPD_3:
 487                         WREG32(DC_HPD3_CONTROL, 0);
 488                         rdev->irq.hpd[2] = false;
 489                         break;
 490                 case RADEON_HPD_4:
 491                         WREG32(DC_HPD4_CONTROL, 0);
 492                         rdev->irq.hpd[3] = false;
 493                         break;
 494                 case RADEON_HPD_5:
 495                         WREG32(DC_HPD5_CONTROL, 0);
 496                         rdev->irq.hpd[4] = false;
 497                         break;
 498                 case RADEON_HPD_6:
 499                         WREG32(DC_HPD6_CONTROL, 0);
 500                         rdev->irq.hpd[5] = false;
 501                         break;
 502                 default:
 503                         break;
 504                 }
 505         }
 506 }
 507
 508 /* watermark setup */
 509
 510 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
 511                                         struct radeon_crtc *radeon_crtc,
 512                                         struct drm_display_mode *mode,
 513                                         struct drm_display_mode *other_mode)
 514 {
 515         u32 tmp;
 516         /*
 517          * Line Buffer Setup
 518          * There are 3 line buffers, each one shared by 2 display controllers.
 519          * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
 520          * the display controllers.  The paritioning is done via one of four
 521          * preset allocations specified in bits 2:0:
 522          * first display controller
 523          *  0 - first half of lb (3840 * 2)
 524          *  1 - first 3/4 of lb (5760 * 2)
 525          *  2 - whole lb (7680 * 2), other crtc must be disabled
 526          *  3 - first 1/4 of lb (1920 * 2)
 527          * second display controller
 528          *  4 - second half of lb (3840 * 2)
 529          *  5 - second 3/4 of lb (5760 * 2)
 530          *  6 - whole lb (7680 * 2), other crtc must be disabled
 531          *  7 - last 1/4 of lb (1920 * 2)
 532          */
 533         /* this can get tricky if we have two large displays on a paired group
 534          * of crtcs.  Ideally for multiple large displays we'd assign them to
 535          * non-linked crtcs for maximum line buffer allocation.
 536          */
 537         if (radeon_crtc->base.enabled && mode) {
 538                 if (other_mode)
 539                         tmp = 0; /* 1/2 */
 540                 else
 541                         tmp = 2; /* whole */
 542         } else
 543                 tmp = 0;
 544
 545         /* second controller of the pair uses second half of the lb */
 546         if (radeon_crtc->crtc_id % 2)
 547                 tmp += 4;
 548         WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
 549
 550         if (radeon_crtc->base.enabled && mode) {
 551                 switch (tmp) {
 552                 case 0:
 553                 case 4:
 554                 default:
 555                         if (ASIC_IS_DCE5(rdev))
 556                                 return 4096 * 2;
 557                         else
 558                                 return 3840 * 2;
 559                 case 1:
 560                 case 5:
 561                         if (ASIC_IS_DCE5(rdev))
 562                                 return 6144 * 2;
 563                         else
 564                                 return 5760 * 2;
 565                 case 2:
 566                 case 6:
 567                         if (ASIC_IS_DCE5(rdev))
 568                                 return 8192 * 2;
 569                         else
 570                                 return 7680 * 2;
 571                 case 3:
 572                 case 7:
 573                         if (ASIC_IS_DCE5(rdev))
 574                                 return 2048 * 2;
 575                         else
 576                                 return 1920 * 2;
 577                 }
 578         }
 579
 580         /* controller not enabled, so no lb used */
 581         return 0;
 582 }
 583
 584 u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
 585 {
 586         u32 tmp = RREG32(MC_SHARED_CHMAP);
 587
 588         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
 589         case 0:
 590         default:
 591                 return 1;
 592         case 1:
 593                 return 2;
 594         case 2:
 595                 return 4;
 596         case 3:
 597                 return 8;
 598         }
 599 }
 600
 601 struct evergreen_wm_params {
 602         u32 dram_channels; /* number of dram channels */
 603         u32 yclk;          /* bandwidth per dram data pin in kHz */
 604         u32 sclk;          /* engine clock in kHz */
 605         u32 disp_clk;      /* display clock in kHz */
 606         u32 src_width;     /* viewport width */
 607         u32 active_time;   /* active display time in ns */
 608         u32 blank_time;    /* blank time in ns */
 609         bool interlaced;    /* mode is interlaced */
 610         fixed20_12 vsc;    /* vertical scale ratio */
 611         u32 num_heads;     /* number of active crtcs */
 612         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 613         u32 lb_size;       /* line buffer allocated to pipe */
 614         u32 vtaps;         /* vertical scaler taps */
 615 };
 616
 617 static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
 618 {
 619         /* Calculate DRAM Bandwidth and the part allocated to display. */
 620         fixed20_12 dram_efficiency; /* 0.7 */
 621         fixed20_12 yclk, dram_channels, bandwidth;
 622         fixed20_12 a;
 623
 624         a.full = dfixed_const(1000);
 625         yclk.full = dfixed_const(wm->yclk);
 626         yclk.full = dfixed_div(yclk, a);
 627         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 628         a.full = dfixed_const(10);
 629         dram_efficiency.full = dfixed_const(7);
 630         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 631         bandwidth.full = dfixed_mul(dram_channels, yclk);
 632         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 633
 634         return dfixed_trunc(bandwidth);
 635 }
 636
 637 static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
 638 {
 639         /* Calculate DRAM Bandwidth and the part allocated to display. */
 640         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 641         fixed20_12 yclk, dram_channels, bandwidth;
 642         fixed20_12 a;
 643
 644         a.full = dfixed_const(1000);
 645         yclk.full = dfixed_const(wm->yclk);
 646         yclk.full = dfixed_div(yclk, a);
 647         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 648         a.full = dfixed_const(10);
 649         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 650         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 651         bandwidth.full = dfixed_mul(dram_channels, yclk);
 652         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 653
 654         return dfixed_trunc(bandwidth);
 655 }
 656
 657 static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
 658 {
 659         /* Calculate the display Data return Bandwidth */
 660         fixed20_12 return_efficiency; /* 0.8 */
 661         fixed20_12 sclk, bandwidth;
 662         fixed20_12 a;
 663
 664         a.full = dfixed_const(1000);
 665         sclk.full = dfixed_const(wm->sclk);
 666         sclk.full = dfixed_div(sclk, a);
 667         a.full = dfixed_const(10);
 668         return_efficiency.full = dfixed_const(8);
 669         return_efficiency.full = dfixed_div(return_efficiency, a);
 670         a.full = dfixed_const(32);
 671         bandwidth.full = dfixed_mul(a, sclk);
 672         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 673
 674         return dfixed_trunc(bandwidth);
 675 }
 676
 677 static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
 678 {
 679         /* Calculate the DMIF Request Bandwidth */
 680         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
 681         fixed20_12 disp_clk, bandwidth;
 682         fixed20_12 a;
 683
 684         a.full = dfixed_const(1000);
 685         disp_clk.full = dfixed_const(wm->disp_clk);
 686         disp_clk.full = dfixed_div(disp_clk, a);
 687         a.full = dfixed_const(10);
 688         disp_clk_request_efficiency.full = dfixed_const(8);
 689         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
 690         a.full = dfixed_const(32);
 691         bandwidth.full = dfixed_mul(a, disp_clk);
 692         bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
 693
 694         return dfixed_trunc(bandwidth);
 695 }
 696
 697 static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
 698 {
 699         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
 700         u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
 701         u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
 702         u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
 703
 704         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
 705 }
 706
 707 static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
 708 {
 709         /* Calculate the display mode Average Bandwidth
 710          * DisplayMode should contain the source and destination dimensions,
 711          * timing, etc.
 712          */
 713         fixed20_12 bpp;
 714         fixed20_12 line_time;
 715         fixed20_12 src_width;
 716         fixed20_12 bandwidth;
 717         fixed20_12 a;
 718
 719         a.full = dfixed_const(1000);
 720         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
 721         line_time.full = dfixed_div(line_time, a);
 722         bpp.full = dfixed_const(wm->bytes_per_pixel);
 723         src_width.full = dfixed_const(wm->src_width);
 724         bandwidth.full = dfixed_mul(src_width, bpp);
 725         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
 726         bandwidth.full = dfixed_div(bandwidth, line_time);
 727
 728         return dfixed_trunc(bandwidth);
 729 }
 730
 731 static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
 732 {
 733         /* First calcualte the latency in ns */
 734         u32 mc_latency = 2000; /* 2000 ns. */
 735         u32 available_bandwidth = evergreen_available_bandwidth(wm);
 736         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
 737         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
 738         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
 739         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
 740                 (wm->num_heads * cursor_line_pair_return_time);
 741         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
 742         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
 743         fixed20_12 a, b, c;
 744
 745         if (wm->num_heads == 0)
 746                 return 0;
 747
 748         a.full = dfixed_const(2);
 749         b.full = dfixed_const(1);
 750         if ((wm->vsc.full > a.full) ||
 751             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
 752             (wm->vtaps >= 5) ||
 753             ((wm->vsc.full >= a.full) && wm->interlaced))
 754                 max_src_lines_per_dst_line = 4;
 755         else
 756                 max_src_lines_per_dst_line = 2;
 757
 758         a.full = dfixed_const(available_bandwidth);
 759         b.full = dfixed_const(wm->num_heads);
 760         a.full = dfixed_div(a, b);
 761
 762         b.full = dfixed_const(1000);
 763         c.full = dfixed_const(wm->disp_clk);
 764         b.full = dfixed_div(c, b);
 765         c.full = dfixed_const(wm->bytes_per_pixel);
 766         b.full = dfixed_mul(b, c);
 767
 768         lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
 769
 770         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
 771         b.full = dfixed_const(1000);
 772         c.full = dfixed_const(lb_fill_bw);
 773         b.full = dfixed_div(c, b);
 774         a.full = dfixed_div(a, b);
 775         line_fill_time = dfixed_trunc(a);
 776
 777         if (line_fill_time < wm->active_time)
 778                 return latency;
 779         else
 780                 return latency + (line_fill_time - wm->active_time);
 781
 782 }
 783
 784 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
 785 {
 786         if (evergreen_average_bandwidth(wm) <=
 787             (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
 788                 return true;
 789         else
 790                 return false;
 791 };
 792
 793 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
 794 {
 795         if (evergreen_average_bandwidth(wm) <=
 796             (evergreen_available_bandwidth(wm) / wm->num_heads))
 797                 return true;
 798         else
 799                 return false;
 800 };
 801
 802 static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
 803 {
 804         u32 lb_partitions = wm->lb_size / wm->src_width;
 805         u32 line_time = wm->active_time + wm->blank_time;
 806         u32 latency_tolerant_lines;
 807         u32 latency_hiding;
 808         fixed20_12 a;
 809
 810         a.full = dfixed_const(1);
 811         if (wm->vsc.full > a.full)
 812                 latency_tolerant_lines = 1;
 813         else {
 814                 if (lb_partitions <= (wm->vtaps + 1))
 815                         latency_tolerant_lines = 1;
 816                 else
 817                         latency_tolerant_lines = 2;
 818         }
 819
 820         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
 821
 822         if (evergreen_latency_watermark(wm) <= latency_hiding)
 823                 return true;
 824         else
 825                 return false;
 826 }
 827
 828 static void evergreen_program_watermarks(struct radeon_device *rdev,
 829                                          struct radeon_crtc *radeon_crtc,
 830                                          u32 lb_size, u32 num_heads)
 831 {
 832         struct drm_display_mode *mode = &radeon_crtc->base.mode;
 833         struct evergreen_wm_params wm;
 834         u32 pixel_period;
 835         u32 line_time = 0;
 836         u32 latency_watermark_a = 0, latency_watermark_b = 0;
 837         u32 priority_a_mark = 0, priority_b_mark = 0;
 838         u32 priority_a_cnt = PRIORITY_OFF;
 839         u32 priority_b_cnt = PRIORITY_OFF;
 840         u32 pipe_offset = radeon_crtc->crtc_id * 16;
 841         u32 tmp, arb_control3;
 842         fixed20_12 a, b, c;
 843
 844         if (radeon_crtc->base.enabled && num_heads && mode) {
 845                 pixel_period = 1000000 / (u32)mode->clock;
 846                 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
 847                 priority_a_cnt = 0;
 848                 priority_b_cnt = 0;
 849
 850                 wm.yclk = rdev->pm.current_mclk * 10;
 851                 wm.sclk = rdev->pm.current_sclk * 10;
 852                 wm.disp_clk = mode->clock;
 853                 wm.src_width = mode->crtc_hdisplay;
 854                 wm.active_time = mode->crtc_hdisplay * pixel_period;
 855                 wm.blank_time = line_time - wm.active_time;
 856                 wm.interlaced = false;
 857                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 858                         wm.interlaced = true;
 859                 wm.vsc = radeon_crtc->vsc;
 860                 wm.vtaps = 1;
 861                 if (radeon_crtc->rmx_type != RMX_OFF)
 862                         wm.vtaps = 2;
 863                 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
 864                 wm.lb_size = lb_size;
 865                 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
 866                 wm.num_heads = num_heads;
 867
 868                 /* set for high clocks */
 869                 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
 870                 /* set for low clocks */
 871                 /* wm.yclk = low clk; wm.sclk = low clk */
 872                 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
 873
 874                 /* possibly force display priority to high */
 875                 /* should really do this at mode validation time... */
 876                 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
 877                     !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
 878                     !evergreen_check_latency_hiding(&wm) ||
 879                     (rdev->disp_priority == 2)) {
 880                         DRM_DEBUG_KMS("force priority to high\n");
 881                         priority_a_cnt |= PRIORITY_ALWAYS_ON;
 882                         priority_b_cnt |= PRIORITY_ALWAYS_ON;
 883                 }
 884
 885                 a.full = dfixed_const(1000);
 886                 b.full = dfixed_const(mode->clock);
 887                 b.full = dfixed_div(b, a);
 888                 c.full = dfixed_const(latency_watermark_a);
 889                 c.full = dfixed_mul(c, b);
 890                 c.full = dfixed_mul(c, radeon_crtc->hsc);
 891                 c.full = dfixed_div(c, a);
 892                 a.full = dfixed_const(16);
 893                 c.full = dfixed_div(c, a);
 894                 priority_a_mark = dfixed_trunc(c);
 895                 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
 896
 897                 a.full = dfixed_const(1000);
 898                 b.full = dfixed_const(mode->clock);
 899                 b.full = dfixed_div(b, a);
 900                 c.full = dfixed_const(latency_watermark_b);
 901                 c.full = dfixed_mul(c, b);
 902                 c.full = dfixed_mul(c, radeon_crtc->hsc);
 903                 c.full = dfixed_div(c, a);
 904                 a.full = dfixed_const(16);
 905                 c.full = dfixed_div(c, a);
 906                 priority_b_mark = dfixed_trunc(c);
 907                 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
 908         }
 909
 910         /* select wm A */
 911         arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
 912         tmp = arb_control3;
 913         tmp &= ~LATENCY_WATERMARK_MASK(3);
 914         tmp |= LATENCY_WATERMARK_MASK(1);
 915         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
 916         WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
 917                (LATENCY_LOW_WATERMARK(latency_watermark_a) |
 918                 LATENCY_HIGH_WATERMARK(line_time)));
 919         /* select wm B */
 920         tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
 921         tmp &= ~LATENCY_WATERMARK_MASK(3);
 922         tmp |= LATENCY_WATERMARK_MASK(2);
 923         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
 924         WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
 925                (LATENCY_LOW_WATERMARK(latency_watermark_b) |
 926                 LATENCY_HIGH_WATERMARK(line_time)));
 927         /* restore original selection */
 928         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
 929
 930         /* write the priority marks */
 931         WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
 932         WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
 933
 934 }
 935
 936 void evergreen_bandwidth_update(struct radeon_device *rdev)
 937 {
 938         struct drm_display_mode *mode0 = NULL;
 939         struct drm_display_mode *mode1 = NULL;
 940         u32 num_heads = 0, lb_size;
 941         int i;
 942
 943         radeon_update_display_priority(rdev);
 944
 945         for (i = 0; i < rdev->num_crtc; i++) {
 946                 if (rdev->mode_info.crtcs[i]->base.enabled)
 947                         num_heads++;
 948         }
 949         for (i = 0; i < rdev->num_crtc; i += 2) {
 950                 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
 951                 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
 952                 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
 953                 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
 954                 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
 955                 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
 956         }
 957 }
 958
 959 int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
 960 {
 961         unsigned i;
 962         u32 tmp;
 963
 964         for (i = 0; i < rdev->usec_timeout; i++) {
 965                 /* read MC_STATUS */
 966                 tmp = RREG32(SRBM_STATUS) & 0x1F00;
 967                 if (!tmp)
 968                         return 0;
 969                 udelay(1);
 970         }
 971         return -1;
 972 }
 973
 974 /*
 975  * GART
 976  */
 977 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
 978 {
 979         unsigned i;
 980         u32 tmp;
 981
 982         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 983
 984         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 985         for (i = 0; i < rdev->usec_timeout; i++) {
 986                 /* read MC_STATUS */
 987                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 988                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 989                 if (tmp == 2) {
 990                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 991                         return;
 992                 }
 993                 if (tmp) {
 994                         return;
 995                 }
 996                 udelay(1);
 997         }
 998 }
 999
1000 int evergreen_pcie_gart_enable(struct radeon_device *rdev)
1001 {
1002         u32 tmp;
1003         int r;
1004
1005         if (rdev->gart.robj == NULL) {
1006                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1007                 return -EINVAL;
1008         }
1009         r = radeon_gart_table_vram_pin(rdev);
1010         if (r)
1011                 return r;
1012         radeon_gart_restore(rdev);
1013         /* Setup L2 cache */
1014         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1015                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1016                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1017         WREG32(VM_L2_CNTL2, 0);
1018         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1019         /* Setup TLB control */
1020         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1021                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1022                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1023                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1024         if (rdev->flags & RADEON_IS_IGP) {
1025                 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
1026                 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
1027                 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
1028         } else {
1029                 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1030                 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1031                 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1032         }
1033         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1034         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1035         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1036         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1037         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1038         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1039         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1040         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1041                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1042         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1043                         (u32)(rdev->dummy_page.addr >> 12));
1044         WREG32(VM_CONTEXT1_CNTL, 0);
1045
1046         evergreen_pcie_gart_tlb_flush(rdev);
1047         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1048                  (unsigned)(rdev->mc.gtt_size >> 20),
1049                  (unsigned long long)rdev->gart.table_addr);
1050         rdev->gart.ready = true;
1051         return 0;
1052 }
1053
1054 void evergreen_pcie_gart_disable(struct radeon_device *rdev)
1055 {
1056         u32 tmp;
1057
1058         /* Disable all tables */
1059         WREG32(VM_CONTEXT0_CNTL, 0);
1060         WREG32(VM_CONTEXT1_CNTL, 0);
1061
1062         /* Setup L2 cache */
1063         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1064                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1065         WREG32(VM_L2_CNTL2, 0);
1066         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1067         /* Setup TLB control */
1068         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1069         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1070         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1071         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1072         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1073         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1074         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1075         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1076         radeon_gart_table_vram_unpin(rdev);
1077 }
1078
1079 void evergreen_pcie_gart_fini(struct radeon_device *rdev)
1080 {
1081         evergreen_pcie_gart_disable(rdev);
1082         radeon_gart_table_vram_free(rdev);
1083         radeon_gart_fini(rdev);
1084 }
1085
1086
1087 void evergreen_agp_enable(struct radeon_device *rdev)
1088 {
1089         u32 tmp;
1090
1091         /* Setup L2 cache */
1092         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1093                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1094                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1095         WREG32(VM_L2_CNTL2, 0);
1096         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1097         /* Setup TLB control */
1098         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1099                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1100                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1101                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1102         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1103         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1104         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1105         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1106         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1107         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1108         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1109         WREG32(VM_CONTEXT0_CNTL, 0);
1110         WREG32(VM_CONTEXT1_CNTL, 0);
1111 }
1112
1113 void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
1114 {
1115         save->vga_control[0] = RREG32(D1VGA_CONTROL);
1116         save->vga_control[1] = RREG32(D2VGA_CONTROL);
1117         save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
1118         save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
1119         save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
1120         save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
1121         if (rdev->num_crtc >= 4) {
1122                 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
1123                 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
1124                 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
1125                 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
1126         }
1127         if (rdev->num_crtc >= 6) {
1128                 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
1129                 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
1130                 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
1131                 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
1132         }
1133
1134         /* Stop all video */
1135         WREG32(VGA_RENDER_CONTROL, 0);
1136         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1137         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1138         if (rdev->num_crtc >= 4) {
1139                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1140                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1141         }
1142         if (rdev->num_crtc >= 6) {
1143                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1144                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1145         }
1146         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1147         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1148         if (rdev->num_crtc >= 4) {
1149                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1150                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1151         }
1152         if (rdev->num_crtc >= 6) {
1153                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1154                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1155         }
1156         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1157         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1158         if (rdev->num_crtc >= 4) {
1159                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1160                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1161         }
1162         if (rdev->num_crtc >= 6) {
1163                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1164                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1165         }
1166
1167         WREG32(D1VGA_CONTROL, 0);
1168         WREG32(D2VGA_CONTROL, 0);
1169         if (rdev->num_crtc >= 4) {
1170                 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1171                 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1172         }
1173         if (rdev->num_crtc >= 6) {
1174                 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1175                 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1176         }
1177 }
1178
1179 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
1180 {
1181         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1182                upper_32_bits(rdev->mc.vram_start));
1183         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1184                upper_32_bits(rdev->mc.vram_start));
1185         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1186                (u32)rdev->mc.vram_start);
1187         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1188                (u32)rdev->mc.vram_start);
1189
1190         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1191                upper_32_bits(rdev->mc.vram_start));
1192         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1193                upper_32_bits(rdev->mc.vram_start));
1194         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1195                (u32)rdev->mc.vram_start);
1196         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1197                (u32)rdev->mc.vram_start);
1198
1199         if (rdev->num_crtc >= 4) {
1200                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1201                        upper_32_bits(rdev->mc.vram_start));
1202                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1203                        upper_32_bits(rdev->mc.vram_start));
1204                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1205                        (u32)rdev->mc.vram_start);
1206                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1207                        (u32)rdev->mc.vram_start);
1208
1209                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1210                        upper_32_bits(rdev->mc.vram_start));
1211                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1212                        upper_32_bits(rdev->mc.vram_start));
1213                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1214                        (u32)rdev->mc.vram_start);
1215                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1216                        (u32)rdev->mc.vram_start);
1217         }
1218         if (rdev->num_crtc >= 6) {
1219                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1220                        upper_32_bits(rdev->mc.vram_start));
1221                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1222                        upper_32_bits(rdev->mc.vram_start));
1223                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1224                        (u32)rdev->mc.vram_start);
1225                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1226                        (u32)rdev->mc.vram_start);
1227
1228                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1229                        upper_32_bits(rdev->mc.vram_start));
1230                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1231                        upper_32_bits(rdev->mc.vram_start));
1232                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1233                        (u32)rdev->mc.vram_start);
1234                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1235                        (u32)rdev->mc.vram_start);
1236         }
1237
1238         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1239         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1240         /* Unlock host access */
1241         WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1242         mdelay(1);
1243         /* Restore video state */
1244         WREG32(D1VGA_CONTROL, save->vga_control[0]);
1245         WREG32(D2VGA_CONTROL, save->vga_control[1]);
1246         if (rdev->num_crtc >= 4) {
1247                 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
1248                 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
1249         }
1250         if (rdev->num_crtc >= 6) {
1251                 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
1252                 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
1253         }
1254         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1255         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1256         if (rdev->num_crtc >= 4) {
1257                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1258                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1259         }
1260         if (rdev->num_crtc >= 6) {
1261                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1262                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1263         }
1264         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1265         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
1266         if (rdev->num_crtc >= 4) {
1267                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1268                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
1269         }
1270         if (rdev->num_crtc >= 6) {
1271                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1272                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1273         }
1274         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1275         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1276         if (rdev->num_crtc >= 4) {
1277                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1278                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1279         }
1280         if (rdev->num_crtc >= 6) {
1281                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1282                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1283         }
1284         WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1285 }
1286
1287 void evergreen_mc_program(struct radeon_device *rdev)
1288 {
1289         struct evergreen_mc_save save;
1290         u32 tmp;
1291         int i, j;
1292
1293         /* Initialize HDP */
1294         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1295                 WREG32((0x2c14 + j), 0x00000000);
1296                 WREG32((0x2c18 + j), 0x00000000);
1297                 WREG32((0x2c1c + j), 0x00000000);
1298                 WREG32((0x2c20 + j), 0x00000000);
1299                 WREG32((0x2c24 + j), 0x00000000);
1300         }
1301         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1302
1303         evergreen_mc_stop(rdev, &save);
1304         if (evergreen_mc_wait_for_idle(rdev)) {
1305                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1306         }
1307         /* Lockout access through VGA aperture*/
1308         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1309         /* Update configuration */
1310         if (rdev->flags & RADEON_IS_AGP) {
1311                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1312                         /* VRAM before AGP */
1313                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1314                                 rdev->mc.vram_start >> 12);
1315                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1316                                 rdev->mc.gtt_end >> 12);
1317                 } else {
1318                         /* VRAM after AGP */
1319                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1320                                 rdev->mc.gtt_start >> 12);
1321                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1322                                 rdev->mc.vram_end >> 12);
1323                 }
1324         } else {
1325                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1326                         rdev->mc.vram_start >> 12);
1327                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1328                         rdev->mc.vram_end >> 12);
1329         }
1330         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1331         /* llano/ontario only */
1332         if ((rdev->family == CHIP_PALM) ||
1333             (rdev->family == CHIP_SUMO) ||
1334             (rdev->family == CHIP_SUMO2)) {
1335                 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1336                 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1337                 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1338                 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1339         }
1340         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1341         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1342         WREG32(MC_VM_FB_LOCATION, tmp);
1343         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1344         WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
1345         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1346         if (rdev->flags & RADEON_IS_AGP) {
1347                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1348                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1349                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1350         } else {
1351                 WREG32(MC_VM_AGP_BASE, 0);
1352                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1353                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1354         }
1355         if (evergreen_mc_wait_for_idle(rdev)) {
1356                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1357         }
1358         evergreen_mc_resume(rdev, &save);
1359         /* we need to own VRAM, so turn off the VGA renderer here
1360          * to stop it overwriting our objects */
1361         rv515_vga_render_disable(rdev);
1362 }
1363
1364 /*
1365  * CP.
1366  */
1367 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1368 {
1369         struct radeon_ring *ring = &rdev->ring[ib->fence->ring];
1370
1371         /* set to DX10/11 mode */
1372         radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1373         radeon_ring_write(ring, 1);
1374         /* FIXME: implement */
1375         radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1376         radeon_ring_write(ring,
1377 #ifdef __BIG_ENDIAN
1378                           (2 << 0) |
1379 #endif
1380                           (ib->gpu_addr & 0xFFFFFFFC));
1381         radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
1382         radeon_ring_write(ring, ib->length_dw);
1383 }
1384
1385
1386 static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1387 {
1388         const __be32 *fw_data;
1389         int i;
1390
1391         if (!rdev->me_fw || !rdev->pfp_fw)
1392                 return -EINVAL;
1393
1394         r700_cp_stop(rdev);
1395         WREG32(CP_RB_CNTL,
1396 #ifdef __BIG_ENDIAN
1397                BUF_SWAP_32BIT |
1398 #endif
1399                RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1400
1401         fw_data = (const __be32 *)rdev->pfp_fw->data;
1402         WREG32(CP_PFP_UCODE_ADDR, 0);
1403         for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1404                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1405         WREG32(CP_PFP_UCODE_ADDR, 0);
1406
1407         fw_data = (const __be32 *)rdev->me_fw->data;
1408         WREG32(CP_ME_RAM_WADDR, 0);
1409         for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1410                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1411
1412         WREG32(CP_PFP_UCODE_ADDR, 0);
1413         WREG32(CP_ME_RAM_WADDR, 0);
1414         WREG32(CP_ME_RAM_RADDR, 0);
1415         return 0;
1416 }
1417
1418 static int evergreen_cp_start(struct radeon_device *rdev)
1419 {
1420         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1421         int r, i;
1422         uint32_t cp_me;
1423
1424         r = radeon_ring_lock(rdev, ring, 7);
1425         if (r) {
1426                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1427                 return r;
1428         }
1429         radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1430         radeon_ring_write(ring, 0x1);
1431         radeon_ring_write(ring, 0x0);
1432         radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1);
1433         radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1434         radeon_ring_write(ring, 0);
1435         radeon_ring_write(ring, 0);
1436         radeon_ring_unlock_commit(rdev, ring);
1437
1438         cp_me = 0xff;
1439         WREG32(CP_ME_CNTL, cp_me);
1440
1441         r = radeon_ring_lock(rdev, ring, evergreen_default_size + 19);
1442         if (r) {
1443                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1444                 return r;
1445         }
1446
1447         /* setup clear context state */
1448         radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1449         radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1450
1451         for (i = 0; i < evergreen_default_size; i++)
1452                 radeon_ring_write(ring, evergreen_default_state[i]);
1453
1454         radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1455         radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1456
1457         /* set clear context state */
1458         radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1459         radeon_ring_write(ring, 0);
1460
1461         /* SQ_VTX_BASE_VTX_LOC */
1462         radeon_ring_write(ring, 0xc0026f00);
1463         radeon_ring_write(ring, 0x00000000);
1464         radeon_ring_write(ring, 0x00000000);
1465         radeon_ring_write(ring, 0x00000000);
1466
1467         /* Clear consts */
1468         radeon_ring_write(ring, 0xc0036f00);
1469         radeon_ring_write(ring, 0x00000bc4);
1470         radeon_ring_write(ring, 0xffffffff);
1471         radeon_ring_write(ring, 0xffffffff);
1472         radeon_ring_write(ring, 0xffffffff);
1473
1474         radeon_ring_write(ring, 0xc0026900);
1475         radeon_ring_write(ring, 0x00000316);
1476         radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1477         radeon_ring_write(ring, 0x00000010); /*  */
1478
1479         radeon_ring_unlock_commit(rdev, ring);
1480
1481         return 0;
1482 }
1483
1484 int evergreen_cp_resume(struct radeon_device *rdev)
1485 {
1486         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1487         u32 tmp;
1488         u32 rb_bufsz;
1489         int r;
1490
1491         /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1492         WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1493                                  SOFT_RESET_PA |
1494                                  SOFT_RESET_SH |
1495                                  SOFT_RESET_VGT |
1496                                  SOFT_RESET_SPI |
1497                                  SOFT_RESET_SX));
1498         RREG32(GRBM_SOFT_RESET);
1499         mdelay(15);
1500         WREG32(GRBM_SOFT_RESET, 0);
1501         RREG32(GRBM_SOFT_RESET);
1502
1503         /* Set ring buffer size */
1504         rb_bufsz = drm_order(ring->ring_size / 8);
1505         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1506 #ifdef __BIG_ENDIAN
1507         tmp |= BUF_SWAP_32BIT;
1508 #endif
1509         WREG32(CP_RB_CNTL, tmp);
1510         WREG32(CP_SEM_WAIT_TIMER, 0x0);
1511         WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1512
1513         /* Set the write pointer delay */
1514         WREG32(CP_RB_WPTR_DELAY, 0);
1515
1516         /* Initialize the ring buffer's read and write pointers */
1517         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1518         WREG32(CP_RB_RPTR_WR, 0);
1519         ring->wptr = 0;
1520         WREG32(CP_RB_WPTR, ring->wptr);
1521
1522         /* set the wb address wether it's enabled or not */
1523         WREG32(CP_RB_RPTR_ADDR,
1524                ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
1525         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1526         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1527
1528         if (rdev->wb.enabled)
1529                 WREG32(SCRATCH_UMSK, 0xff);
1530         else {
1531                 tmp |= RB_NO_UPDATE;
1532                 WREG32(SCRATCH_UMSK, 0);
1533         }
1534
1535         mdelay(1);
1536         WREG32(CP_RB_CNTL, tmp);
1537
1538         WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
1539         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1540
1541         ring->rptr = RREG32(CP_RB_RPTR);
1542
1543         evergreen_cp_start(rdev);
1544         ring->ready = true;
1545         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1546         if (r) {
1547                 ring->ready = false;
1548                 return r;
1549         }
1550         return 0;
1551 }
1552
1553 /*
1554  * Core functions
1555  */
1556 static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1557                                                   u32 num_tile_pipes,
1558                                                   u32 num_backends,
1559                                                   u32 backend_disable_mask)
1560 {
1561         u32 backend_map = 0;
1562         u32 enabled_backends_mask = 0;
1563         u32 enabled_backends_count = 0;
1564         u32 cur_pipe;
1565         u32 swizzle_pipe[EVERGREEN_MAX_PIPES];
1566         u32 cur_backend = 0;
1567         u32 i;
1568         bool force_no_swizzle;
1569
1570         if (num_tile_pipes > EVERGREEN_MAX_PIPES)
1571                 num_tile_pipes = EVERGREEN_MAX_PIPES;
1572         if (num_tile_pipes < 1)
1573                 num_tile_pipes = 1;
1574         if (num_backends > EVERGREEN_MAX_BACKENDS)
1575                 num_backends = EVERGREEN_MAX_BACKENDS;
1576         if (num_backends < 1)
1577                 num_backends = 1;
1578
1579         for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1580                 if (((backend_disable_mask >> i) & 1) == 0) {
1581                         enabled_backends_mask |= (1 << i);
1582                         ++enabled_backends_count;
1583                 }
1584                 if (enabled_backends_count == num_backends)
1585                         break;
1586         }
1587
1588         if (enabled_backends_count == 0) {
1589                 enabled_backends_mask = 1;
1590                 enabled_backends_count = 1;
1591         }
1592
1593         if (enabled_backends_count != num_backends)
1594                 num_backends = enabled_backends_count;
1595
1596         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES);
1597         switch (rdev->family) {
1598         case CHIP_CEDAR:
1599         case CHIP_REDWOOD:
1600         case CHIP_PALM:
1601         case CHIP_SUMO:
1602         case CHIP_SUMO2:
1603         case CHIP_TURKS:
1604         case CHIP_CAICOS:
1605                 force_no_swizzle = false;
1606                 break;
1607         case CHIP_CYPRESS:
1608         case CHIP_HEMLOCK:
1609         case CHIP_JUNIPER:
1610         case CHIP_BARTS:
1611         default:
1612                 force_no_swizzle = true;
1613                 break;
1614         }
1615         if (force_no_swizzle) {
1616                 bool last_backend_enabled = false;
1617
1618                 force_no_swizzle = false;
1619                 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1620                         if (((enabled_backends_mask >> i) & 1) == 1) {
1621                                 if (last_backend_enabled)
1622                                         force_no_swizzle = true;
1623                                 last_backend_enabled = true;
1624                         } else
1625                                 last_backend_enabled = false;
1626                 }
1627         }
1628
1629         switch (num_tile_pipes) {
1630         case 1:
1631         case 3:
1632         case 5:
1633         case 7:
1634                 DRM_ERROR("odd number of pipes!\n");
1635                 break;
1636         case 2:
1637                 swizzle_pipe[0] = 0;
1638                 swizzle_pipe[1] = 1;
1639                 break;
1640         case 4:
1641                 if (force_no_swizzle) {
1642                         swizzle_pipe[0] = 0;
1643                         swizzle_pipe[1] = 1;
1644                         swizzle_pipe[2] = 2;
1645                         swizzle_pipe[3] = 3;
1646                 } else {
1647                         swizzle_pipe[0] = 0;
1648                         swizzle_pipe[1] = 2;
1649                         swizzle_pipe[2] = 1;
1650                         swizzle_pipe[3] = 3;
1651                 }
1652                 break;
1653         case 6:
1654                 if (force_no_swizzle) {
1655                         swizzle_pipe[0] = 0;
1656                         swizzle_pipe[1] = 1;
1657                         swizzle_pipe[2] = 2;
1658                         swizzle_pipe[3] = 3;
1659                         swizzle_pipe[4] = 4;
1660                         swizzle_pipe[5] = 5;
1661                 } else {
1662                         swizzle_pipe[0] = 0;
1663                         swizzle_pipe[1] = 2;
1664                         swizzle_pipe[2] = 4;
1665                         swizzle_pipe[3] = 1;
1666                         swizzle_pipe[4] = 3;
1667                         swizzle_pipe[5] = 5;
1668                 }
1669                 break;
1670         case 8:
1671                 if (force_no_swizzle) {
1672                         swizzle_pipe[0] = 0;
1673                         swizzle_pipe[1] = 1;
1674                         swizzle_pipe[2] = 2;
1675                         swizzle_pipe[3] = 3;
1676                         swizzle_pipe[4] = 4;
1677                         swizzle_pipe[5] = 5;
1678                         swizzle_pipe[6] = 6;
1679                         swizzle_pipe[7] = 7;
1680                 } else {
1681                         swizzle_pipe[0] = 0;
1682                         swizzle_pipe[1] = 2;
1683                         swizzle_pipe[2] = 4;
1684                         swizzle_pipe[3] = 6;
1685                         swizzle_pipe[4] = 1;
1686                         swizzle_pipe[5] = 3;
1687                         swizzle_pipe[6] = 5;
1688                         swizzle_pipe[7] = 7;
1689                 }
1690                 break;
1691         }
1692
1693         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1694                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1695                         cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1696
1697                 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
1698
1699                 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1700         }
1701
1702         return backend_map;
1703 }
1704
1705 static void evergreen_gpu_init(struct radeon_device *rdev)
1706 {
1707         u32 cc_rb_backend_disable = 0;
1708         u32 cc_gc_shader_pipe_config;
1709         u32 gb_addr_config = 0;
1710         u32 mc_shared_chmap, mc_arb_ramcfg;
1711         u32 gb_backend_map;
1712         u32 grbm_gfx_index;
1713         u32 sx_debug_1;
1714         u32 smx_dc_ctl0;
1715         u32 sq_config;
1716         u32 sq_lds_resource_mgmt;
1717         u32 sq_gpr_resource_mgmt_1;
1718         u32 sq_gpr_resource_mgmt_2;
1719         u32 sq_gpr_resource_mgmt_3;
1720         u32 sq_thread_resource_mgmt;
1721         u32 sq_thread_resource_mgmt_2;
1722         u32 sq_stack_resource_mgmt_1;
1723         u32 sq_stack_resource_mgmt_2;
1724         u32 sq_stack_resource_mgmt_3;
1725         u32 vgt_cache_invalidation;
1726         u32 hdp_host_path_cntl, tmp;
1727         int i, j, num_shader_engines, ps_thread_count;
1728
1729         switch (rdev->family) {
1730         case CHIP_CYPRESS:
1731         case CHIP_HEMLOCK:
1732                 rdev->config.evergreen.num_ses = 2;
1733                 rdev->config.evergreen.max_pipes = 4;
1734                 rdev->config.evergreen.max_tile_pipes = 8;
1735                 rdev->config.evergreen.max_simds = 10;
1736                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1737                 rdev->config.evergreen.max_gprs = 256;
1738                 rdev->config.evergreen.max_threads = 248;
1739                 rdev->config.evergreen.max_gs_threads = 32;
1740                 rdev->config.evergreen.max_stack_entries = 512;
1741                 rdev->config.evergreen.sx_num_of_sets = 4;
1742                 rdev->config.evergreen.sx_max_export_size = 256;
1743                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1744                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1745                 rdev->config.evergreen.max_hw_contexts = 8;
1746                 rdev->config.evergreen.sq_num_cf_insts = 2;
1747
1748                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1749                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1750                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1751                 break;
1752         case CHIP_JUNIPER:
1753                 rdev->config.evergreen.num_ses = 1;
1754                 rdev->config.evergreen.max_pipes = 4;
1755                 rdev->config.evergreen.max_tile_pipes = 4;
1756                 rdev->config.evergreen.max_simds = 10;
1757                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1758                 rdev->config.evergreen.max_gprs = 256;
1759                 rdev->config.evergreen.max_threads = 248;
1760                 rdev->config.evergreen.max_gs_threads = 32;
1761                 rdev->config.evergreen.max_stack_entries = 512;
1762                 rdev->config.evergreen.sx_num_of_sets = 4;
1763                 rdev->config.evergreen.sx_max_export_size = 256;
1764                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1765                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1766                 rdev->config.evergreen.max_hw_contexts = 8;
1767                 rdev->config.evergreen.sq_num_cf_insts = 2;
1768
1769                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1770                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1771                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1772                 break;
1773         case CHIP_REDWOOD:
1774                 rdev->config.evergreen.num_ses = 1;
1775                 rdev->config.evergreen.max_pipes = 4;
1776                 rdev->config.evergreen.max_tile_pipes = 4;
1777                 rdev->config.evergreen.max_simds = 5;
1778                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1779                 rdev->config.evergreen.max_gprs = 256;
1780                 rdev->config.evergreen.max_threads = 248;
1781                 rdev->config.evergreen.max_gs_threads = 32;
1782                 rdev->config.evergreen.max_stack_entries = 256;
1783                 rdev->config.evergreen.sx_num_of_sets = 4;
1784                 rdev->config.evergreen.sx_max_export_size = 256;
1785                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1786                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1787                 rdev->config.evergreen.max_hw_contexts = 8;
1788                 rdev->config.evergreen.sq_num_cf_insts = 2;
1789
1790                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1791                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1792                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1793                 break;
1794         case CHIP_CEDAR:
1795         default:
1796                 rdev->config.evergreen.num_ses = 1;
1797                 rdev->config.evergreen.max_pipes = 2;
1798                 rdev->config.evergreen.max_tile_pipes = 2;
1799                 rdev->config.evergreen.max_simds = 2;
1800                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1801                 rdev->config.evergreen.max_gprs = 256;
1802                 rdev->config.evergreen.max_threads = 192;
1803                 rdev->config.evergreen.max_gs_threads = 16;
1804                 rdev->config.evergreen.max_stack_entries = 256;
1805                 rdev->config.evergreen.sx_num_of_sets = 4;
1806                 rdev->config.evergreen.sx_max_export_size = 128;
1807                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1808                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1809                 rdev->config.evergreen.max_hw_contexts = 4;
1810                 rdev->config.evergreen.sq_num_cf_insts = 1;
1811
1812                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1813                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1814                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1815                 break;
1816         case CHIP_PALM:
1817                 rdev->config.evergreen.num_ses = 1;
1818                 rdev->config.evergreen.max_pipes = 2;
1819                 rdev->config.evergreen.max_tile_pipes = 2;
1820                 rdev->config.evergreen.max_simds = 2;
1821                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1822                 rdev->config.evergreen.max_gprs = 256;
1823                 rdev->config.evergreen.max_threads = 192;
1824                 rdev->config.evergreen.max_gs_threads = 16;
1825                 rdev->config.evergreen.max_stack_entries = 256;
1826                 rdev->config.evergreen.sx_num_of_sets = 4;
1827                 rdev->config.evergreen.sx_max_export_size = 128;
1828                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1829                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1830                 rdev->config.evergreen.max_hw_contexts = 4;
1831                 rdev->config.evergreen.sq_num_cf_insts = 1;
1832
1833                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1834                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1835                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1836                 break;
1837         case CHIP_SUMO:
1838                 rdev->config.evergreen.num_ses = 1;
1839                 rdev->config.evergreen.max_pipes = 4;
1840                 rdev->config.evergreen.max_tile_pipes = 2;
1841                 if (rdev->pdev->device == 0x9648)
1842                         rdev->config.evergreen.max_simds = 3;
1843                 else if ((rdev->pdev->device == 0x9647) ||
1844                          (rdev->pdev->device == 0x964a))
1845                         rdev->config.evergreen.max_simds = 4;
1846                 else
1847                         rdev->config.evergreen.max_simds = 5;
1848                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1849                 rdev->config.evergreen.max_gprs = 256;
1850                 rdev->config.evergreen.max_threads = 248;
1851                 rdev->config.evergreen.max_gs_threads = 32;
1852                 rdev->config.evergreen.max_stack_entries = 256;
1853                 rdev->config.evergreen.sx_num_of_sets = 4;
1854                 rdev->config.evergreen.sx_max_export_size = 256;
1855                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1856                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1857                 rdev->config.evergreen.max_hw_contexts = 8;
1858                 rdev->config.evergreen.sq_num_cf_insts = 2;
1859
1860                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1861                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1862                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1863                 break;
1864         case CHIP_SUMO2:
1865                 rdev->config.evergreen.num_ses = 1;
1866                 rdev->config.evergreen.max_pipes = 4;
1867                 rdev->config.evergreen.max_tile_pipes = 4;
1868                 rdev->config.evergreen.max_simds = 2;
1869                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1870                 rdev->config.evergreen.max_gprs = 256;
1871                 rdev->config.evergreen.max_threads = 248;
1872                 rdev->config.evergreen.max_gs_threads = 32;
1873                 rdev->config.evergreen.max_stack_entries = 512;
1874                 rdev->config.evergreen.sx_num_of_sets = 4;
1875                 rdev->config.evergreen.sx_max_export_size = 256;
1876                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1877                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1878                 rdev->config.evergreen.max_hw_contexts = 8;
1879                 rdev->config.evergreen.sq_num_cf_insts = 2;
1880
1881                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1882                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1883                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1884                 break;
1885         case CHIP_BARTS:
1886                 rdev->config.evergreen.num_ses = 2;
1887                 rdev->config.evergreen.max_pipes = 4;
1888                 rdev->config.evergreen.max_tile_pipes = 8;
1889                 rdev->config.evergreen.max_simds = 7;
1890                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1891                 rdev->config.evergreen.max_gprs = 256;
1892                 rdev->config.evergreen.max_threads = 248;
1893                 rdev->config.evergreen.max_gs_threads = 32;
1894                 rdev->config.evergreen.max_stack_entries = 512;
1895                 rdev->config.evergreen.sx_num_of_sets = 4;
1896                 rdev->config.evergreen.sx_max_export_size = 256;
1897                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1898                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1899                 rdev->config.evergreen.max_hw_contexts = 8;
1900                 rdev->config.evergreen.sq_num_cf_insts = 2;
1901
1902                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1903                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1904                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1905                 break;
1906         case CHIP_TURKS:
1907                 rdev->config.evergreen.num_ses = 1;
1908                 rdev->config.evergreen.max_pipes = 4;
1909                 rdev->config.evergreen.max_tile_pipes = 4;
1910                 rdev->config.evergreen.max_simds = 6;
1911                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1912                 rdev->config.evergreen.max_gprs = 256;
1913                 rdev->config.evergreen.max_threads = 248;
1914                 rdev->config.evergreen.max_gs_threads = 32;
1915                 rdev->config.evergreen.max_stack_entries = 256;
1916                 rdev->config.evergreen.sx_num_of_sets = 4;
1917                 rdev->config.evergreen.sx_max_export_size = 256;
1918                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1919                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1920                 rdev->config.evergreen.max_hw_contexts = 8;
1921                 rdev->config.evergreen.sq_num_cf_insts = 2;
1922
1923                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1924                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1925                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1926                 break;
1927         case CHIP_CAICOS:
1928                 rdev->config.evergreen.num_ses = 1;
1929                 rdev->config.evergreen.max_pipes = 4;
1930                 rdev->config.evergreen.max_tile_pipes = 2;
1931                 rdev->config.evergreen.max_simds = 2;
1932                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1933                 rdev->config.evergreen.max_gprs = 256;
1934                 rdev->config.evergreen.max_threads = 192;
1935                 rdev->config.evergreen.max_gs_threads = 16;
1936                 rdev->config.evergreen.max_stack_entries = 256;
1937                 rdev->config.evergreen.sx_num_of_sets = 4;
1938                 rdev->config.evergreen.sx_max_export_size = 128;
1939                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1940                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1941                 rdev->config.evergreen.max_hw_contexts = 4;
1942                 rdev->config.evergreen.sq_num_cf_insts = 1;
1943
1944                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1945                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1946                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1947                 break;
1948         }
1949
1950         /* Initialize HDP */
1951         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1952                 WREG32((0x2c14 + j), 0x00000000);
1953                 WREG32((0x2c18 + j), 0x00000000);
1954                 WREG32((0x2c1c + j), 0x00000000);
1955                 WREG32((0x2c20 + j), 0x00000000);
1956                 WREG32((0x2c24 + j), 0x00000000);
1957         }
1958
1959         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1960
1961         evergreen_fix_pci_max_read_req_size(rdev);
1962
1963         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
1964
1965         cc_gc_shader_pipe_config |=
1966                 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
1967                                   & EVERGREEN_MAX_PIPES_MASK);
1968         cc_gc_shader_pipe_config |=
1969                 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
1970                                & EVERGREEN_MAX_SIMDS_MASK);
1971
1972         cc_rb_backend_disable =
1973                 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
1974                                 & EVERGREEN_MAX_BACKENDS_MASK);
1975
1976
1977         mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1978         if ((rdev->family == CHIP_PALM) ||
1979             (rdev->family == CHIP_SUMO) ||
1980             (rdev->family == CHIP_SUMO2))
1981                 mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);
1982         else
1983                 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1984
1985         switch (rdev->config.evergreen.max_tile_pipes) {
1986         case 1:
1987         default:
1988                 gb_addr_config |= NUM_PIPES(0);
1989                 break;
1990         case 2:
1991                 gb_addr_config |= NUM_PIPES(1);
1992                 break;
1993         case 4:
1994                 gb_addr_config |= NUM_PIPES(2);
1995                 break;
1996         case 8:
1997                 gb_addr_config |= NUM_PIPES(3);
1998                 break;
1999         }
2000
2001         gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
2002         gb_addr_config |= BANK_INTERLEAVE_SIZE(0);
2003         gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1);
2004         gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1);
2005         gb_addr_config |= NUM_GPUS(0); /* Hemlock? */
2006         gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
2007
2008         if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2)
2009                 gb_addr_config |= ROW_SIZE(2);
2010         else
2011                 gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT);
2012
2013         if (rdev->ddev->pdev->device == 0x689e) {
2014                 u32 efuse_straps_4;
2015                 u32 efuse_straps_3;
2016                 u8 efuse_box_bit_131_124;
2017
2018                 WREG32(RCU_IND_INDEX, 0x204);
2019                 efuse_straps_4 = RREG32(RCU_IND_DATA);
2020                 WREG32(RCU_IND_INDEX, 0x203);
2021                 efuse_straps_3 = RREG32(RCU_IND_DATA);
2022                 efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28));
2023
2024                 switch(efuse_box_bit_131_124) {
2025                 case 0x00:
2026                         gb_backend_map = 0x76543210;
2027                         break;
2028                 case 0x55:
2029                         gb_backend_map = 0x77553311;
2030                         break;
2031                 case 0x56:
2032                         gb_backend_map = 0x77553300;
2033                         break;
2034                 case 0x59:
2035                         gb_backend_map = 0x77552211;
2036                         break;
2037                 case 0x66:
2038                         gb_backend_map = 0x77443300;
2039                         break;
2040                 case 0x99:
2041                         gb_backend_map = 0x66552211;
2042                         break;
2043                 case 0x5a:
2044                         gb_backend_map = 0x77552200;
2045                         break;
2046                 case 0xaa:
2047                         gb_backend_map = 0x66442200;
2048                         break;
2049                 case 0x95:
2050                         gb_backend_map = 0x66553311;
2051                         break;
2052                 default:
2053                         DRM_ERROR("bad backend map, using default\n");
2054                         gb_backend_map =
2055                                 evergreen_get_tile_pipe_to_backend_map(rdev,
2056                                                                        rdev->config.evergreen.max_tile_pipes,
2057                                                                        rdev->config.evergreen.max_backends,
2058                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
2059                                                                    rdev->config.evergreen.max_backends) &
2060                                                                         EVERGREEN_MAX_BACKENDS_MASK));
2061                         break;
2062                 }
2063         } else if (rdev->ddev->pdev->device == 0x68b9) {
2064                 u32 efuse_straps_3;
2065                 u8 efuse_box_bit_127_124;
2066
2067                 WREG32(RCU_IND_INDEX, 0x203);
2068                 efuse_straps_3 = RREG32(RCU_IND_DATA);
2069                 efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28);
2070
2071                 switch(efuse_box_bit_127_124) {
2072                 case 0x0:
2073                         gb_backend_map = 0x00003210;
2074                         break;
2075                 case 0x5:
2076                 case 0x6:
2077                 case 0x9:
2078                 case 0xa:
2079                         gb_backend_map = 0x00003311;
2080                         break;
2081                 default:
2082                         DRM_ERROR("bad backend map, using default\n");
2083                         gb_backend_map =
2084                                 evergreen_get_tile_pipe_to_backend_map(rdev,
2085                                                                        rdev->config.evergreen.max_tile_pipes,
2086                                                                        rdev->config.evergreen.max_backends,
2087                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
2088                                                                    rdev->config.evergreen.max_backends) &
2089                                                                         EVERGREEN_MAX_BACKENDS_MASK));
2090                         break;
2091                 }
2092         } else {
2093                 switch (rdev->family) {
2094                 case CHIP_CYPRESS:
2095                 case CHIP_HEMLOCK:
2096                 case CHIP_BARTS:
2097                         gb_backend_map = 0x66442200;
2098                         break;
2099                 case CHIP_JUNIPER:
2100                         gb_backend_map = 0x00002200;
2101                         break;
2102                 default:
2103                         gb_backend_map =
2104                                 evergreen_get_tile_pipe_to_backend_map(rdev,
2105                                                                        rdev->config.evergreen.max_tile_pipes,
2106                                                                        rdev->config.evergreen.max_backends,
2107                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
2108                                                                          rdev->config.evergreen.max_backends) &
2109                                                                         EVERGREEN_MAX_BACKENDS_MASK));
2110                 }
2111         }
2112
2113         /* setup tiling info dword.  gb_addr_config is not adequate since it does
2114          * not have bank info, so create a custom tiling dword.
2115          * bits 3:0   num_pipes
2116          * bits 7:4   num_banks
2117          * bits 11:8  group_size
2118          * bits 15:12 row_size
2119          */
2120         rdev->config.evergreen.tile_config = 0;
2121         switch (rdev->config.evergreen.max_tile_pipes) {
2122         case 1:
2123         default:
2124                 rdev->config.evergreen.tile_config |= (0 << 0);
2125                 break;
2126         case 2:
2127                 rdev->config.evergreen.tile_config |= (1 << 0);
2128                 break;
2129         case 4:
2130                 rdev->config.evergreen.tile_config |= (2 << 0);
2131                 break;
2132         case 8:
2133                 rdev->config.evergreen.tile_config |= (3 << 0);
2134                 break;
2135         }
2136         /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
2137         if (rdev->flags & RADEON_IS_IGP)
2138                 rdev->config.evergreen.tile_config |= 1 << 4;
2139         else
2140                 rdev->config.evergreen.tile_config |=
2141                         ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
2142         rdev->config.evergreen.tile_config |=
2143                 ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;
2144         rdev->config.evergreen.tile_config |=
2145                 ((gb_addr_config & 0x30000000) >> 28) << 12;
2146
2147         rdev->config.evergreen.backend_map = gb_backend_map;
2148         WREG32(GB_BACKEND_MAP, gb_backend_map);
2149         WREG32(GB_ADDR_CONFIG, gb_addr_config);
2150         WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
2151         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
2152
2153         num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
2154         grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
2155
2156         for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
2157                 u32 rb = cc_rb_backend_disable | (0xf0 << 16);
2158                 u32 sp = cc_gc_shader_pipe_config;
2159                 u32 gfx = grbm_gfx_index | SE_INDEX(i);
2160
2161                 if (i == num_shader_engines) {
2162                         rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK);
2163                         sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK);
2164                 }
2165
2166                 WREG32(GRBM_GFX_INDEX, gfx);
2167                 WREG32(RLC_GFX_INDEX, gfx);
2168
2169                 WREG32(CC_RB_BACKEND_DISABLE, rb);
2170                 WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
2171                 WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
2172                 WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
2173         }
2174
2175         grbm_gfx_index |= SE_BROADCAST_WRITES;
2176         WREG32(GRBM_GFX_INDEX, grbm_gfx_index);
2177         WREG32(RLC_GFX_INDEX, grbm_gfx_index);
2178
2179         WREG32(CGTS_SYS_TCC_DISABLE, 0);
2180         WREG32(CGTS_TCC_DISABLE, 0);
2181         WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
2182         WREG32(CGTS_USER_TCC_DISABLE, 0);
2183
2184         /* set HW defaults for 3D engine */
2185         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
2186                                      ROQ_IB2_START(0x2b)));
2187
2188         WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
2189
2190         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
2191                              SYNC_GRADIENT |
2192                              SYNC_WALKER |
2193                              SYNC_ALIGNER));
2194
2195         sx_debug_1 = RREG32(SX_DEBUG_1);
2196         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
2197         WREG32(SX_DEBUG_1, sx_debug_1);
2198
2199
2200         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
2201         smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
2202         smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
2203         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
2204
2205         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
2206                                         POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
2207                                         SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
2208
2209         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
2210                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
2211                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
2212
2213         WREG32(VGT_NUM_INSTANCES, 1);
2214         WREG32(SPI_CONFIG_CNTL, 0);
2215         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
2216         WREG32(CP_PERFMON_CNTL, 0);
2217
2218         WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
2219                                   FETCH_FIFO_HIWATER(0x4) |
2220                                   DONE_FIFO_HIWATER(0xe0) |
2221                                   ALU_UPDATE_FIFO_HIWATER(0x8)));
2222
2223         sq_config = RREG32(SQ_CONFIG);
2224         sq_config &= ~(PS_PRIO(3) |
2225                        VS_PRIO(3) |
2226                        GS_PRIO(3) |
2227                        ES_PRIO(3));
2228         sq_config |= (VC_ENABLE |
2229                       EXPORT_SRC_C |
2230                       PS_PRIO(0) |
2231                       VS_PRIO(1) |
2232                       GS_PRIO(2) |
2233                       ES_PRIO(3));
2234
2235         switch (rdev->family) {
2236         case CHIP_CEDAR:
2237         case CHIP_PALM:
2238         case CHIP_SUMO:
2239         case CHIP_SUMO2:
2240         case CHIP_CAICOS:
2241                 /* no vertex cache */
2242                 sq_config &= ~VC_ENABLE;
2243                 break;
2244         default:
2245                 break;
2246         }
2247
2248         sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
2249
2250         sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
2251         sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
2252         sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
2253         sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2254         sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2255         sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2256         sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2257
2258         switch (rdev->family) {
2259         case CHIP_CEDAR:
2260         case CHIP_PALM:
2261         case CHIP_SUMO:
2262         case CHIP_SUMO2:
2263                 ps_thread_count = 96;
2264                 break;
2265         default:
2266                 ps_thread_count = 128;
2267                 break;
2268         }
2269
2270         sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
2271         sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2272         sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2273         sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2274         sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2275         sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2276
2277         sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2278         sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2279         sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2280         sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2281         sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2282         sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2283
2284         WREG32(SQ_CONFIG, sq_config);
2285         WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2286         WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2287         WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
2288         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2289         WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
2290         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2291         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2292         WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
2293         WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2294         WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
2295
2296         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
2297                                           FORCE_EOV_MAX_REZ_CNT(255)));
2298
2299         switch (rdev->family) {
2300         case CHIP_CEDAR:
2301         case CHIP_PALM:
2302         case CHIP_SUMO:
2303         case CHIP_SUMO2:
2304         case CHIP_CAICOS:
2305                 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
2306                 break;
2307         default:
2308                 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
2309                 break;
2310         }
2311         vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
2312         WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
2313
2314         WREG32(VGT_GS_VERTEX_REUSE, 16);
2315         WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
2316         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2317
2318         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
2319         WREG32(VGT_OUT_DEALLOC_CNTL, 16);
2320
2321         WREG32(CB_PERF_CTR0_SEL_0, 0);
2322         WREG32(CB_PERF_CTR0_SEL_1, 0);
2323         WREG32(CB_PERF_CTR1_SEL_0, 0);
2324         WREG32(CB_PERF_CTR1_SEL_1, 0);
2325         WREG32(CB_PERF_CTR2_SEL_0, 0);
2326         WREG32(CB_PERF_CTR2_SEL_1, 0);
2327         WREG32(CB_PERF_CTR3_SEL_0, 0);
2328         WREG32(CB_PERF_CTR3_SEL_1, 0);
2329
2330         /* clear render buffer base addresses */
2331         WREG32(CB_COLOR0_BASE, 0);
2332         WREG32(CB_COLOR1_BASE, 0);
2333         WREG32(CB_COLOR2_BASE, 0);
2334         WREG32(CB_COLOR3_BASE, 0);
2335         WREG32(CB_COLOR4_BASE, 0);
2336         WREG32(CB_COLOR5_BASE, 0);
2337         WREG32(CB_COLOR6_BASE, 0);
2338         WREG32(CB_COLOR7_BASE, 0);
2339         WREG32(CB_COLOR8_BASE, 0);
2340         WREG32(CB_COLOR9_BASE, 0);
2341         WREG32(CB_COLOR10_BASE, 0);
2342         WREG32(CB_COLOR11_BASE, 0);
2343
2344         /* set the shader const cache sizes to 0 */
2345         for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
2346                 WREG32(i, 0);
2347         for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2348                 WREG32(i, 0);
2349
2350         tmp = RREG32(HDP_MISC_CNTL);
2351         tmp |= HDP_FLUSH_INVALIDATE_CACHE;
2352         WREG32(HDP_MISC_CNTL, tmp);
2353
2354         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2355         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2356
2357         WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2358
2359         udelay(50);
2360
2361 }
2362
2363 int evergreen_mc_init(struct radeon_device *rdev)
2364 {
2365         u32 tmp;
2366         int chansize, numchan;
2367
2368         /* Get VRAM informations */
2369         rdev->mc.vram_is_ddr = true;
2370         if ((rdev->family == CHIP_PALM) ||
2371             (rdev->family == CHIP_SUMO) ||
2372             (rdev->family == CHIP_SUMO2))
2373                 tmp = RREG32(FUS_MC_ARB_RAMCFG);
2374         else
2375                 tmp = RREG32(MC_ARB_RAMCFG);
2376         if (tmp & CHANSIZE_OVERRIDE) {
2377                 chansize = 16;
2378         } else if (tmp & CHANSIZE_MASK) {
2379                 chansize = 64;
2380         } else {
2381                 chansize = 32;
2382         }
2383         tmp = RREG32(MC_SHARED_CHMAP);
2384         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2385         case 0:
2386         default:
2387                 numchan = 1;
2388                 break;
2389         case 1:
2390                 numchan = 2;
2391                 break;
2392         case 2:
2393                 numchan = 4;
2394                 break;
2395         case 3:
2396                 numchan = 8;
2397                 break;
2398         }
2399         rdev->mc.vram_width = numchan * chansize;
2400         /* Could aper size report 0 ? */
2401         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2402         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2403         /* Setup GPU memory space */
2404         if ((rdev->family == CHIP_PALM) ||
2405             (rdev->family == CHIP_SUMO) ||
2406             (rdev->family == CHIP_SUMO2)) {
2407                 /* size in bytes on fusion */
2408                 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2409                 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2410         } else {
2411                 /* size in MB on evergreen/cayman/tn */
2412                 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2413                 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2414         }
2415         rdev->mc.visible_vram_size = rdev->mc.aper_size;
2416         r700_vram_gtt_location(rdev, &rdev->mc);
2417         radeon_update_bandwidth_info(rdev);
2418
2419         return 0;
2420 }
2421
2422 bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2423 {
2424         u32 srbm_status;
2425         u32 grbm_status;
2426         u32 grbm_status_se0, grbm_status_se1;
2427         struct r100_gpu_lockup *lockup = &rdev->config.evergreen.lockup;
2428         int r;
2429
2430         srbm_status = RREG32(SRBM_STATUS);
2431         grbm_status = RREG32(GRBM_STATUS);
2432         grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2433         grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2434         if (!(grbm_status & GUI_ACTIVE)) {
2435                 r100_gpu_lockup_update(lockup, ring);
2436                 return false;
2437         }
2438         /* force CP activities */
2439         r = radeon_ring_lock(rdev, ring, 2);
2440         if (!r) {
2441                 /* PACKET2 NOP */
2442                 radeon_ring_write(ring, 0x80000000);
2443                 radeon_ring_write(ring, 0x80000000);
2444                 radeon_ring_unlock_commit(rdev, ring);
2445         }
2446         ring->rptr = RREG32(CP_RB_RPTR);
2447         return r100_gpu_cp_is_lockup(rdev, lockup, ring);
2448 }
2449
2450 static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
2451 {
2452         struct evergreen_mc_save save;
2453         u32 grbm_reset = 0;
2454
2455         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2456                 return 0;
2457
2458         dev_info(rdev->dev, "GPU softreset \n");
2459         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
2460                 RREG32(GRBM_STATUS));
2461         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
2462                 RREG32(GRBM_STATUS_SE0));
2463         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
2464                 RREG32(GRBM_STATUS_SE1));
2465         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
2466                 RREG32(SRBM_STATUS));
2467         evergreen_mc_stop(rdev, &save);
2468         if (evergreen_mc_wait_for_idle(rdev)) {
2469                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2470         }
2471         /* Disable CP parsing/prefetching */
2472         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2473
2474         /* reset all the gfx blocks */
2475         grbm_reset = (SOFT_RESET_CP |
2476                       SOFT_RESET_CB |
2477                       SOFT_RESET_DB |
2478                       SOFT_RESET_PA |
2479                       SOFT_RESET_SC |
2480                       SOFT_RESET_SPI |
2481                       SOFT_RESET_SH |
2482                       SOFT_RESET_SX |
2483                       SOFT_RESET_TC |
2484                       SOFT_RESET_TA |
2485                       SOFT_RESET_VC |
2486                       SOFT_RESET_VGT);
2487
2488         dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2489         WREG32(GRBM_SOFT_RESET, grbm_reset);
2490         (void)RREG32(GRBM_SOFT_RESET);
2491         udelay(50);
2492         WREG32(GRBM_SOFT_RESET, 0);
2493         (void)RREG32(GRBM_SOFT_RESET);
2494         /* Wait a little for things to settle down */
2495         udelay(50);
2496         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
2497                 RREG32(GRBM_STATUS));
2498         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
2499                 RREG32(GRBM_STATUS_SE0));
2500         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
2501                 RREG32(GRBM_STATUS_SE1));
2502         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
2503                 RREG32(SRBM_STATUS));
2504         evergreen_mc_resume(rdev, &save);
2505         return 0;
2506 }
2507
2508 int evergreen_asic_reset(struct radeon_device *rdev)
2509 {
2510         return evergreen_gpu_soft_reset(rdev);
2511 }
2512
2513 /* Interrupts */
2514
2515 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2516 {
2517         switch (crtc) {
2518         case 0:
2519                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
2520         case 1:
2521                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
2522         case 2:
2523                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
2524         case 3:
2525                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
2526         case 4:
2527                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
2528         case 5:
2529                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
2530         default:
2531                 return 0;
2532         }
2533 }
2534
2535 void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2536 {
2537         u32 tmp;
2538
2539         if (rdev->family >= CHIP_CAYMAN) {
2540                 cayman_cp_int_cntl_setup(rdev, 0,
2541                                          CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2542                 cayman_cp_int_cntl_setup(rdev, 1, 0);
2543                 cayman_cp_int_cntl_setup(rdev, 2, 0);
2544         } else
2545                 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2546         WREG32(GRBM_INT_CNTL, 0);
2547         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2548         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2549         if (rdev->num_crtc >= 4) {
2550                 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2551                 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2552         }
2553         if (rdev->num_crtc >= 6) {
2554                 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2555                 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2556         }
2557
2558         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2559         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2560         if (rdev->num_crtc >= 4) {
2561                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2562                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2563         }
2564         if (rdev->num_crtc >= 6) {
2565                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2566                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2567         }
2568
2569         /* only one DAC on DCE6 */
2570         if (!ASIC_IS_DCE6(rdev))
2571                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2572         WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2573
2574         tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2575         WREG32(DC_HPD1_INT_CONTROL, tmp);
2576         tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2577         WREG32(DC_HPD2_INT_CONTROL, tmp);
2578         tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2579         WREG32(DC_HPD3_INT_CONTROL, tmp);
2580         tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2581         WREG32(DC_HPD4_INT_CONTROL, tmp);
2582         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2583         WREG32(DC_HPD5_INT_CONTROL, tmp);
2584         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2585         WREG32(DC_HPD6_INT_CONTROL, tmp);
2586
2587 }
2588
2589 int evergreen_irq_set(struct radeon_device *rdev)
2590 {
2591         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2592         u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
2593         u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2594         u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2595         u32 grbm_int_cntl = 0;
2596         u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
2597
2598         if (!rdev->irq.installed) {
2599                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
2600                 return -EINVAL;
2601         }
2602         /* don't enable anything if the ih is disabled */
2603         if (!rdev->ih.enabled) {
2604                 r600_disable_interrupts(rdev);
2605                 /* force the active interrupt state to all disabled */
2606                 evergreen_disable_interrupt_state(rdev);
2607                 return 0;
2608         }
2609
2610         hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2611         hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2612         hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2613         hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2614         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2615         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2616
2617         if (rdev->family >= CHIP_CAYMAN) {
2618                 /* enable CP interrupts on all rings */
2619                 if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
2620                         DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2621                         cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2622                 }
2623                 if (rdev->irq.sw_int[CAYMAN_RING_TYPE_CP1_INDEX]) {
2624                         DRM_DEBUG("evergreen_irq_set: sw int cp1\n");
2625                         cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
2626                 }
2627                 if (rdev->irq.sw_int[CAYMAN_RING_TYPE_CP2_INDEX]) {
2628                         DRM_DEBUG("evergreen_irq_set: sw int cp2\n");
2629                         cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
2630                 }
2631         } else {
2632                 if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
2633                         DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2634                         cp_int_cntl |= RB_INT_ENABLE;
2635                         cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2636                 }
2637         }
2638
2639         if (rdev->irq.crtc_vblank_int[0] ||
2640             rdev->irq.pflip[0]) {
2641                 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2642                 crtc1 |= VBLANK_INT_MASK;
2643         }
2644         if (rdev->irq.crtc_vblank_int[1] ||
2645             rdev->irq.pflip[1]) {
2646                 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2647                 crtc2 |= VBLANK_INT_MASK;
2648         }
2649         if (rdev->irq.crtc_vblank_int[2] ||
2650             rdev->irq.pflip[2]) {
2651                 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2652                 crtc3 |= VBLANK_INT_MASK;
2653         }
2654         if (rdev->irq.crtc_vblank_int[3] ||
2655             rdev->irq.pflip[3]) {
2656                 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2657                 crtc4 |= VBLANK_INT_MASK;
2658         }
2659         if (rdev->irq.crtc_vblank_int[4] ||
2660             rdev->irq.pflip[4]) {
2661                 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2662                 crtc5 |= VBLANK_INT_MASK;
2663         }
2664         if (rdev->irq.crtc_vblank_int[5] ||
2665             rdev->irq.pflip[5]) {
2666                 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2667                 crtc6 |= VBLANK_INT_MASK;
2668         }
2669         if (rdev->irq.hpd[0]) {
2670                 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2671                 hpd1 |= DC_HPDx_INT_EN;
2672         }
2673         if (rdev->irq.hpd[1]) {
2674                 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2675                 hpd2 |= DC_HPDx_INT_EN;
2676         }
2677         if (rdev->irq.hpd[2]) {
2678                 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2679                 hpd3 |= DC_HPDx_INT_EN;
2680         }
2681         if (rdev->irq.hpd[3]) {
2682                 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2683                 hpd4 |= DC_HPDx_INT_EN;
2684         }
2685         if (rdev->irq.hpd[4]) {
2686                 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2687                 hpd5 |= DC_HPDx_INT_EN;
2688         }
2689         if (rdev->irq.hpd[5]) {
2690                 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2691                 hpd6 |= DC_HPDx_INT_EN;
2692         }
2693         if (rdev->irq.gui_idle) {
2694                 DRM_DEBUG("gui idle\n");
2695                 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2696         }
2697
2698         if (rdev->family >= CHIP_CAYMAN) {
2699                 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl);
2700                 cayman_cp_int_cntl_setup(rdev, 1, cp_int_cntl1);
2701                 cayman_cp_int_cntl_setup(rdev, 2, cp_int_cntl2);
2702         } else
2703                 WREG32(CP_INT_CNTL, cp_int_cntl);
2704         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
2705
2706         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2707         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2708         if (rdev->num_crtc >= 4) {
2709                 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2710                 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2711         }
2712         if (rdev->num_crtc >= 6) {
2713                 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2714                 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2715         }
2716
2717         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2718         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
2719         if (rdev->num_crtc >= 4) {
2720                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2721                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2722         }
2723         if (rdev->num_crtc >= 6) {
2724                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2725                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2726         }
2727
2728         WREG32(DC_HPD1_INT_CONTROL, hpd1);
2729         WREG32(DC_HPD2_INT_CONTROL, hpd2);
2730         WREG32(DC_HPD3_INT_CONTROL, hpd3);
2731         WREG32(DC_HPD4_INT_CONTROL, hpd4);
2732         WREG32(DC_HPD5_INT_CONTROL, hpd5);
2733         WREG32(DC_HPD6_INT_CONTROL, hpd6);
2734
2735         return 0;
2736 }
2737
2738 static void evergreen_irq_ack(struct radeon_device *rdev)
2739 {
2740         u32 tmp;
2741
2742         rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2743         rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2744         rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2745         rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2746         rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2747         rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2748         rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2749         rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2750         if (rdev->num_crtc >= 4) {
2751                 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2752                 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2753         }
2754         if (rdev->num_crtc >= 6) {
2755                 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2756                 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2757         }
2758
2759         if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2760                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2761         if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2762                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2763         if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
2764                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
2765         if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
2766                 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2767         if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
2768                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
2769         if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
2770                 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2771
2772         if (rdev->num_crtc >= 4) {
2773                 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2774                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2775                 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2776                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2777                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2778                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2779                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2780                         WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2781                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2782                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2783                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2784                         WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2785         }
2786
2787         if (rdev->num_crtc >= 6) {
2788                 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2789                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2790                 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2791                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2792                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2793                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2794                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2795                         WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2796                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2797                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2798                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2799                         WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2800         }
2801
2802         if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2803                 tmp = RREG32(DC_HPD1_INT_CONTROL);
2804                 tmp |= DC_HPDx_INT_ACK;
2805                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2806         }
2807         if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2808                 tmp = RREG32(DC_HPD2_INT_CONTROL);
2809                 tmp |= DC_HPDx_INT_ACK;
2810                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2811         }
2812         if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2813                 tmp = RREG32(DC_HPD3_INT_CONTROL);
2814                 tmp |= DC_HPDx_INT_ACK;
2815                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2816         }
2817         if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2818                 tmp = RREG32(DC_HPD4_INT_CONTROL);
2819                 tmp |= DC_HPDx_INT_ACK;
2820                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2821         }
2822         if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2823                 tmp = RREG32(DC_HPD5_INT_CONTROL);
2824                 tmp |= DC_HPDx_INT_ACK;
2825                 WREG32(DC_HPD5_INT_CONTROL, tmp);
2826         }
2827         if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2828                 tmp = RREG32(DC_HPD5_INT_CONTROL);
2829                 tmp |= DC_HPDx_INT_ACK;
2830                 WREG32(DC_HPD6_INT_CONTROL, tmp);
2831         }
2832 }
2833
2834 void evergreen_irq_disable(struct radeon_device *rdev)
2835 {
2836         r600_disable_interrupts(rdev);
2837         /* Wait and acknowledge irq */
2838         mdelay(1);
2839         evergreen_irq_ack(rdev);
2840         evergreen_disable_interrupt_state(rdev);
2841 }
2842
2843 void evergreen_irq_suspend(struct radeon_device *rdev)
2844 {
2845         evergreen_irq_disable(rdev);
2846         r600_rlc_stop(rdev);
2847 }
2848
2849 static u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2850 {
2851         u32 wptr, tmp;
2852
2853         if (rdev->wb.enabled)
2854                 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
2855         else
2856                 wptr = RREG32(IH_RB_WPTR);
2857
2858         if (wptr & RB_OVERFLOW) {
2859                 /* When a ring buffer overflow happen start parsing interrupt
2860                  * from the last not overwritten vector (wptr + 16). Hopefully
2861                  * this should allow us to catchup.
2862                  */
2863                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2864                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2865                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2866                 tmp = RREG32(IH_RB_CNTL);
2867                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2868                 WREG32(IH_RB_CNTL, tmp);
2869         }
2870         return (wptr & rdev->ih.ptr_mask);
2871 }
2872
2873 int evergreen_irq_process(struct radeon_device *rdev)
2874 {
2875         u32 wptr;
2876         u32 rptr;
2877         u32 src_id, src_data;
2878         u32 ring_index;
2879         unsigned long flags;
2880         bool queue_hotplug = false;
2881
2882         if (!rdev->ih.enabled || rdev->shutdown)
2883                 return IRQ_NONE;
2884
2885         wptr = evergreen_get_ih_wptr(rdev);
2886         rptr = rdev->ih.rptr;
2887         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2888
2889         spin_lock_irqsave(&rdev->ih.lock, flags);
2890         if (rptr == wptr) {
2891                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2892                 return IRQ_NONE;
2893         }
2894 restart_ih:
2895         /* Order reading of wptr vs. reading of IH ring data */
2896         rmb();
2897
2898         /* display interrupts */
2899         evergreen_irq_ack(rdev);
2900
2901         rdev->ih.wptr = wptr;
2902         while (rptr != wptr) {
2903                 /* wptr/rptr are in bytes! */
2904                 ring_index = rptr / 4;
2905                 src_id =  le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
2906                 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
2907
2908                 switch (src_id) {
2909                 case 1: /* D1 vblank/vline */
2910                         switch (src_data) {
2911                         case 0: /* D1 vblank */
2912                                 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
2913                                         if (rdev->irq.crtc_vblank_int[0]) {
2914                                                 drm_handle_vblank(rdev->ddev, 0);
2915                                                 rdev->pm.vblank_sync = true;
2916                                                 wake_up(&rdev->irq.vblank_queue);
2917                                         }
2918                                         if (rdev->irq.pflip[0])
2919                                                 radeon_crtc_handle_flip(rdev, 0);
2920                                         rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2921                                         DRM_DEBUG("IH: D1 vblank\n");
2922                                 }
2923                                 break;
2924                         case 1: /* D1 vline */
2925                                 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
2926                                         rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
2927                                         DRM_DEBUG("IH: D1 vline\n");
2928                                 }
2929                                 break;
2930                         default:
2931                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2932                                 break;
2933                         }
2934                         break;
2935                 case 2: /* D2 vblank/vline */
2936                         switch (src_data) {
2937                         case 0: /* D2 vblank */
2938                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
2939                                         if (rdev->irq.crtc_vblank_int[1]) {
2940                                                 drm_handle_vblank(rdev->ddev, 1);
2941                                                 rdev->pm.vblank_sync = true;
2942                                                 wake_up(&rdev->irq.vblank_queue);
2943                                         }
2944                                         if (rdev->irq.pflip[1])
2945                                                 radeon_crtc_handle_flip(rdev, 1);
2946                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
2947                                         DRM_DEBUG("IH: D2 vblank\n");
2948                                 }
2949                                 break;
2950                         case 1: /* D2 vline */
2951                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2952                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
2953                                         DRM_DEBUG("IH: D2 vline\n");
2954                                 }
2955                                 break;
2956                         default:
2957                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2958                                 break;
2959                         }
2960                         break;
2961                 case 3: /* D3 vblank/vline */
2962                         switch (src_data) {
2963                         case 0: /* D3 vblank */
2964                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
2965                                         if (rdev->irq.crtc_vblank_int[2]) {
2966                                                 drm_handle_vblank(rdev->ddev, 2);
2967                                                 rdev->pm.vblank_sync = true;
2968                                                 wake_up(&rdev->irq.vblank_queue);
2969                                         }
2970                                         if (rdev->irq.pflip[2])
2971                                                 radeon_crtc_handle_flip(rdev, 2);
2972                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
2973                                         DRM_DEBUG("IH: D3 vblank\n");
2974                                 }
2975                                 break;
2976                         case 1: /* D3 vline */
2977                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
2978                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
2979                                         DRM_DEBUG("IH: D3 vline\n");
2980                                 }
2981                                 break;
2982                         default:
2983                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2984                                 break;
2985                         }
2986                         break;
2987                 case 4: /* D4 vblank/vline */
2988                         switch (src_data) {
2989                         case 0: /* D4 vblank */
2990                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
2991                                         if (rdev->irq.crtc_vblank_int[3]) {
2992                                                 drm_handle_vblank(rdev->ddev, 3);
2993                                                 rdev->pm.vblank_sync = true;
2994                                                 wake_up(&rdev->irq.vblank_queue);
2995                                         }
2996                                         if (rdev->irq.pflip[3])
2997                                                 radeon_crtc_handle_flip(rdev, 3);
2998                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
2999                                         DRM_DEBUG("IH: D4 vblank\n");
3000                                 }
3001                                 break;
3002                         case 1: /* D4 vline */
3003                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
3004                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
3005                                         DRM_DEBUG("IH: D4 vline\n");
3006                                 }
3007                                 break;
3008                         default:
3009                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3010                                 break;
3011                         }
3012                         break;
3013                 case 5: /* D5 vblank/vline */
3014                         switch (src_data) {
3015                         case 0: /* D5 vblank */
3016                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
3017                                         if (rdev->irq.crtc_vblank_int[4]) {
3018                                                 drm_handle_vblank(rdev->ddev, 4);
3019                                                 rdev->pm.vblank_sync = true;
3020                                                 wake_up(&rdev->irq.vblank_queue);
3021                                         }
3022                                         if (rdev->irq.pflip[4])
3023                                                 radeon_crtc_handle_flip(rdev, 4);
3024                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
3025                                         DRM_DEBUG("IH: D5 vblank\n");
3026                                 }
3027                                 break;
3028                         case 1: /* D5 vline */
3029                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
3030                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
3031                                         DRM_DEBUG("IH: D5 vline\n");
3032                                 }
3033                                 break;
3034                         default:
3035                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3036                                 break;
3037                         }
3038                         break;
3039                 case 6: /* D6 vblank/vline */
3040                         switch (src_data) {
3041                         case 0: /* D6 vblank */
3042                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
3043                                         if (rdev->irq.crtc_vblank_int[5]) {
3044                                                 drm_handle_vblank(rdev->ddev, 5);
3045                                                 rdev->pm.vblank_sync = true;
3046                                                 wake_up(&rdev->irq.vblank_queue);
3047                                         }
3048                                         if (rdev->irq.pflip[5])
3049                                                 radeon_crtc_handle_flip(rdev, 5);
3050                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
3051                                         DRM_DEBUG("IH: D6 vblank\n");
3052                                 }
3053                                 break;
3054                         case 1: /* D6 vline */
3055                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
3056                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
3057                                         DRM_DEBUG("IH: D6 vline\n");
3058                                 }
3059                                 break;
3060                         default:
3061                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3062                                 break;
3063                         }
3064                         break;
3065                 case 42: /* HPD hotplug */
3066                         switch (src_data) {
3067                         case 0:
3068                                 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
3069                                         rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
3070                                         queue_hotplug = true;
3071                                         DRM_DEBUG("IH: HPD1\n");
3072                                 }
3073                                 break;
3074                         case 1:
3075                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
3076                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
3077                                         queue_hotplug = true;
3078                                         DRM_DEBUG("IH: HPD2\n");
3079                                 }
3080                                 break;
3081                         case 2:
3082                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
3083                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
3084                                         queue_hotplug = true;
3085                                         DRM_DEBUG("IH: HPD3\n");
3086                                 }
3087                                 break;
3088                         case 3:
3089                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
3090                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
3091                                         queue_hotplug = true;
3092                                         DRM_DEBUG("IH: HPD4\n");
3093                                 }
3094                                 break;
3095                         case 4:
3096                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
3097                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
3098                                         queue_hotplug = true;
3099                                         DRM_DEBUG("IH: HPD5\n");
3100                                 }
3101                                 break;
3102                         case 5:
3103                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
3104                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
3105                                         queue_hotplug = true;
3106                                         DRM_DEBUG("IH: HPD6\n");
3107                                 }
3108                                 break;
3109                         default:
3110                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3111                                 break;
3112                         }
3113                         break;
3114                 case 176: /* CP_INT in ring buffer */
3115                 case 177: /* CP_INT in IB1 */
3116                 case 178: /* CP_INT in IB2 */
3117                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3118                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3119                         break;
3120                 case 181: /* CP EOP event */
3121                         DRM_DEBUG("IH: CP EOP\n");
3122                         if (rdev->family >= CHIP_CAYMAN) {
3123                                 switch (src_data) {
3124                                 case 0:
3125                                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3126                                         break;
3127                                 case 1:
3128                                         radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
3129                                         break;
3130                                 case 2:
3131                                         radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
3132                                         break;
3133                                 }
3134                         } else
3135                                 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3136                         break;
3137                 case 233: /* GUI IDLE */
3138                         DRM_DEBUG("IH: GUI idle\n");
3139                         rdev->pm.gui_idle = true;
3140                         wake_up(&rdev->irq.idle_queue);
3141                         break;
3142                 default:
3143                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3144                         break;
3145                 }
3146
3147                 /* wptr/rptr are in bytes! */
3148                 rptr += 16;
3149                 rptr &= rdev->ih.ptr_mask;
3150         }
3151         /* make sure wptr hasn't changed while processing */
3152         wptr = evergreen_get_ih_wptr(rdev);
3153         if (wptr != rdev->ih.wptr)
3154                 goto restart_ih;
3155         if (queue_hotplug)
3156                 schedule_work(&rdev->hotplug_work);
3157         rdev->ih.rptr = rptr;
3158         WREG32(IH_RB_RPTR, rdev->ih.rptr);
3159         spin_unlock_irqrestore(&rdev->ih.lock, flags);
3160         return IRQ_HANDLED;
3161 }
3162
3163 static int evergreen_startup(struct radeon_device *rdev)
3164 {
3165         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3166         int r;
3167
3168         /* enable pcie gen2 link */
3169         evergreen_pcie_gen2_enable(rdev);
3170
3171         if (ASIC_IS_DCE5(rdev)) {
3172                 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
3173                         r = ni_init_microcode(rdev);
3174                         if (r) {
3175                                 DRM_ERROR("Failed to load firmware!\n");
3176                                 return r;
3177                         }
3178                 }
3179                 r = ni_mc_load_microcode(rdev);
3180                 if (r) {
3181                         DRM_ERROR("Failed to load MC firmware!\n");
3182                         return r;
3183                 }
3184         } else {
3185                 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3186                         r = r600_init_microcode(rdev);
3187                         if (r) {
3188                                 DRM_ERROR("Failed to load firmware!\n");
3189                                 return r;
3190                         }
3191                 }
3192         }
3193
3194         r = r600_vram_scratch_init(rdev);
3195         if (r)
3196                 return r;
3197
3198         evergreen_mc_program(rdev);
3199         if (rdev->flags & RADEON_IS_AGP) {
3200                 evergreen_agp_enable(rdev);
3201         } else {
3202                 r = evergreen_pcie_gart_enable(rdev);
3203                 if (r)
3204                         return r;
3205         }
3206         evergreen_gpu_init(rdev);
3207
3208         r = evergreen_blit_init(rdev);
3209         if (r) {
3210                 r600_blit_fini(rdev);
3211                 rdev->asic->copy.copy = NULL;
3212                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
3213         }
3214
3215         /* allocate wb buffer */
3216         r = radeon_wb_init(rdev);
3217         if (r)
3218                 return r;
3219
3220         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3221         if (r) {
3222                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3223                 return r;
3224         }
3225
3226         /* Enable IRQ */
3227         r = r600_irq_init(rdev);
3228         if (r) {
3229                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3230                 radeon_irq_kms_fini(rdev);
3231                 return r;
3232         }
3233         evergreen_irq_set(rdev);
3234
3235         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
3236                              R600_CP_RB_RPTR, R600_CP_RB_WPTR,
3237                              0, 0xfffff, RADEON_CP_PACKET2);
3238         if (r)
3239                 return r;
3240         r = evergreen_cp_load_microcode(rdev);
3241         if (r)
3242                 return r;
3243         r = evergreen_cp_resume(rdev);
3244         if (r)
3245                 return r;
3246
3247         r = radeon_ib_pool_start(rdev);
3248         if (r)
3249                 return r;
3250
3251         r = radeon_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
3252         if (r) {
3253                 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
3254                 rdev->accel_working = false;
3255                 return r;
3256         }
3257
3258         r = r600_audio_init(rdev);
3259         if (r) {
3260                 DRM_ERROR("radeon: audio init failed\n");
3261                 return r;
3262         }
3263
3264         return 0;
3265 }
3266
3267 int evergreen_resume(struct radeon_device *rdev)
3268 {
3269         int r;
3270
3271         /* reset the asic, the gfx blocks are often in a bad state
3272          * after the driver is unloaded or after a resume
3273          */
3274         if (radeon_asic_reset(rdev))
3275                 dev_warn(rdev->dev, "GPU reset failed !\n");
3276         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
3277          * posting will perform necessary task to bring back GPU into good
3278          * shape.
3279          */
3280         /* post card */
3281         atom_asic_init(rdev->mode_info.atom_context);
3282
3283         rdev->accel_working = true;
3284         r = evergreen_startup(rdev);
3285         if (r) {
3286                 DRM_ERROR("evergreen startup failed on resume\n");
3287                 rdev->accel_working = false;
3288                 return r;
3289         }
3290
3291         return r;
3292
3293 }
3294
3295 int evergreen_suspend(struct radeon_device *rdev)
3296 {
3297         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3298
3299         r600_audio_fini(rdev);
3300         /* FIXME: we should wait for ring to be empty */
3301         radeon_ib_pool_suspend(rdev);
3302         r600_blit_suspend(rdev);
3303         r700_cp_stop(rdev);
3304         ring->ready = false;
3305         evergreen_irq_suspend(rdev);
3306         radeon_wb_disable(rdev);
3307         evergreen_pcie_gart_disable(rdev);
3308
3309         return 0;
3310 }
3311
3312 /* Plan is to move initialization in that function and use
3313  * helper function so that radeon_device_init pretty much
3314  * do nothing more than calling asic specific function. This
3315  * should also allow to remove a bunch of callback function
3316  * like vram_info.
3317  */
3318 int evergreen_init(struct radeon_device *rdev)
3319 {
3320         int r;
3321
3322         /* This don't do much */
3323         r = radeon_gem_init(rdev);
3324         if (r)
3325                 return r;
3326         /* Read BIOS */
3327         if (!radeon_get_bios(rdev)) {
3328                 if (ASIC_IS_AVIVO(rdev))
3329                         return -EINVAL;
3330         }
3331         /* Must be an ATOMBIOS */
3332         if (!rdev->is_atom_bios) {
3333                 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");
3334                 return -EINVAL;
3335         }
3336         r = radeon_atombios_init(rdev);
3337         if (r)
3338                 return r;
3339         /* reset the asic, the gfx blocks are often in a bad state
3340          * after the driver is unloaded or after a resume
3341          */
3342         if (radeon_asic_reset(rdev))
3343                 dev_warn(rdev->dev, "GPU reset failed !\n");
3344         /* Post card if necessary */
3345         if (!radeon_card_posted(rdev)) {
3346                 if (!rdev->bios) {
3347                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3348                         return -EINVAL;
3349                 }
3350                 DRM_INFO("GPU not posted. posting now...\n");
3351                 atom_asic_init(rdev->mode_info.atom_context);
3352         }
3353         /* Initialize scratch registers */
3354         r600_scratch_init(rdev);
3355         /* Initialize surface registers */
3356         radeon_surface_init(rdev);
3357         /* Initialize clocks */
3358         radeon_get_clock_info(rdev->ddev);
3359         /* Fence driver */
3360         r = radeon_fence_driver_init(rdev);
3361         if (r)
3362                 return r;
3363         /* initialize AGP */
3364         if (rdev->flags & RADEON_IS_AGP) {
3365                 r = radeon_agp_init(rdev);
3366                 if (r)
3367                         radeon_agp_disable(rdev);
3368         }
3369         /* initialize memory controller */
3370         r = evergreen_mc_init(rdev);
3371         if (r)
3372                 return r;
3373         /* Memory manager */
3374         r = radeon_bo_init(rdev);
3375         if (r)
3376                 return r;
3377
3378         r = radeon_irq_kms_init(rdev);
3379         if (r)
3380                 return r;
3381
3382         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
3383         r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
3384
3385         rdev->ih.ring_obj = NULL;
3386         r600_ih_ring_init(rdev, 64 * 1024);
3387
3388         r = r600_pcie_gart_init(rdev);
3389         if (r)
3390                 return r;
3391
3392         r = radeon_ib_pool_init(rdev);
3393         rdev->accel_working = true;
3394         if (r) {
3395                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3396                 rdev->accel_working = false;
3397         }
3398
3399         r = evergreen_startup(rdev);
3400         if (r) {
3401                 dev_err(rdev->dev, "disabling GPU acceleration\n");
3402                 r700_cp_fini(rdev);
3403                 r600_irq_fini(rdev);
3404                 radeon_wb_fini(rdev);
3405                 r100_ib_fini(rdev);
3406                 radeon_irq_kms_fini(rdev);
3407                 evergreen_pcie_gart_fini(rdev);
3408                 rdev->accel_working = false;
3409         }
3410
3411         /* Don't start up if the MC ucode is missing on BTC parts.
3412          * The default clocks and voltages before the MC ucode
3413          * is loaded are not suffient for advanced operations.
3414          */
3415         if (ASIC_IS_DCE5(rdev)) {
3416                 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
3417                         DRM_ERROR("radeon: MC ucode required for NI+.\n");
3418                         return -EINVAL;
3419                 }
3420         }
3421
3422         return 0;
3423 }
3424
3425 void evergreen_fini(struct radeon_device *rdev)
3426 {
3427         r600_audio_fini(rdev);
3428         r600_blit_fini(rdev);
3429         r700_cp_fini(rdev);
3430         r600_irq_fini(rdev);
3431         radeon_wb_fini(rdev);
3432         r100_ib_fini(rdev);
3433         radeon_irq_kms_fini(rdev);
3434         evergreen_pcie_gart_fini(rdev);
3435         r600_vram_scratch_fini(rdev);
3436         radeon_gem_fini(rdev);
3437         radeon_semaphore_driver_fini(rdev);
3438         radeon_fence_driver_fini(rdev);
3439         radeon_agp_fini(rdev);
3440         radeon_bo_fini(rdev);
3441         radeon_atombios_fini(rdev);
3442         kfree(rdev->bios);
3443         rdev->bios = NULL;
3444 }
3445
3446 void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
3447 {
3448         u32 link_width_cntl, speed_cntl;
3449
3450         if (radeon_pcie_gen2 == 0)
3451                 return;
3452
3453         if (rdev->flags & RADEON_IS_IGP)
3454                 return;
3455
3456         if (!(rdev->flags & RADEON_IS_PCIE))
3457                 return;
3458
3459         /* x2 cards have a special sequence */
3460         if (ASIC_IS_X2(rdev))
3461                 return;
3462
3463         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3464         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3465             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3466
3467                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3468                 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3469                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3470
3471                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3472                 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3473                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3474
3475                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3476                 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3477                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3478
3479                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3480                 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3481                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3482
3483                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3484                 speed_cntl |= LC_GEN2_EN_STRAP;
3485                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3486
3487         } else {
3488                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3489                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3490                 if (1)
3491                         link_width_cntl |= LC_UPCONFIGURE_DIS;
3492                 else
3493                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3494                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3495         }
3496 }