2 * Copyright 2013 Advanced Micro Devices, Inc.
3 * Copyright 2014 Rafał Miłecki
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/hdmi.h>
26 #include "radeon_asic.h"
27 #include "radeon_audio.h"
30 static void dce3_2_afmt_write_speaker_allocation(struct drm_encoder *encoder)
32 struct radeon_device *rdev = encoder->dev->dev_private;
33 struct drm_connector *connector;
34 struct radeon_connector *radeon_connector = NULL;
39 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
40 if (connector->encoder == encoder) {
41 radeon_connector = to_radeon_connector(connector);
46 if (!radeon_connector) {
47 DRM_ERROR("Couldn't find encoder's connector\n");
51 sad_count = drm_edid_to_speaker_allocation(radeon_connector->edid, &sadb);
53 DRM_DEBUG("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
57 /* program the speaker allocation */
58 tmp = RREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
59 tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
61 tmp |= HDMI_CONNECTION;
63 tmp |= SPEAKER_ALLOCATION(sadb[0]);
65 tmp |= SPEAKER_ALLOCATION(5); /* stereo */
66 WREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
71 void dce3_2_afmt_write_sad_regs(struct drm_encoder *encoder,
72 struct cea_sad *sads, int sad_count)
75 struct radeon_device *rdev = encoder->dev->dev_private;
76 static const u16 eld_reg_to_type[][2] = {
77 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
78 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
79 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
80 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
81 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
82 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
83 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
84 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
85 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
86 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
87 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
88 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
91 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
94 int max_channels = -1;
97 for (j = 0; j < sad_count; j++) {
98 struct cea_sad *sad = &sads[j];
100 if (sad->format == eld_reg_to_type[i][1]) {
101 if (sad->channels > max_channels) {
102 value = MAX_CHANNELS(sad->channels) |
103 DESCRIPTOR_BYTE_2(sad->byte2) |
104 SUPPORTED_FREQUENCIES(sad->freq);
105 max_channels = sad->channels;
108 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
109 stereo_freqs |= sad->freq;
115 value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);
117 WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value);
122 * update the info frames with the data from the current display mode
124 void dce3_1_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
126 struct drm_device *dev = encoder->dev;
127 struct radeon_device *rdev = dev->dev_private;
128 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
129 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
130 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
131 struct hdmi_avi_infoframe frame;
135 if (!dig || !dig->afmt)
138 /* Silent, r600_hdmi_enable will raise WARN for us */
139 if (!dig->afmt->enabled)
141 offset = dig->afmt->offset;
143 /* disable audio prior to setting up hw */
144 dig->afmt->pin = r600_audio_get_pin(rdev);
145 r600_audio_enable(rdev, dig->afmt->pin, 0);
147 r600_audio_set_dto(encoder, mode->clock);
149 WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
150 HDMI0_NULL_SEND); /* send null packets when required */
152 WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000);
154 if (ASIC_IS_DCE32(rdev)) {
155 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
156 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
157 HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
158 WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
159 AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */
160 AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
162 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
163 HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */
164 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
165 HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */
166 HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
169 if (ASIC_IS_DCE32(rdev)) {
170 dce3_2_afmt_write_speaker_allocation(encoder);
171 radeon_audio_write_sad_regs(encoder);
174 WREG32(HDMI0_ACR_PACKET_CONTROL + offset,
175 HDMI0_ACR_SOURCE | /* select SW CTS value - XXX verify that hw CTS works on all families */
176 HDMI0_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
178 WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
179 HDMI0_NULL_SEND | /* send null packets when required */
180 HDMI0_GC_SEND | /* send general control packets */
181 HDMI0_GC_CONT); /* send general control packets every frame */
183 /* TODO: HDMI0_AUDIO_INFO_UPDATE */
184 WREG32(HDMI0_INFOFRAME_CONTROL0 + offset,
185 HDMI0_AVI_INFO_SEND | /* enable AVI info frames */
186 HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */
187 HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
188 HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */
190 WREG32(HDMI0_INFOFRAME_CONTROL1 + offset,
191 HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */
192 HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */
194 WREG32(HDMI0_GC + offset, 0); /* unset HDMI0_GC_AVMUTE */
196 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
198 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
202 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
204 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
208 r600_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
209 r600_hdmi_update_ACR(encoder, mode->clock);
211 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
212 WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF);
213 WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF);
214 WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001);
215 WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001);
217 r600_hdmi_audio_workaround(encoder);
219 /* enable audio after to setting up hw */
220 r600_audio_enable(rdev, dig->afmt->pin, 0xf);