drivers/gpu/drm/radeon/cik_sdma.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "radeon.h"
  27 #include "radeon_asic.h"
  28 #include "radeon_trace.h"
  29 #include "cikd.h"
  30
  31 /* sdma */
  32 #define CIK_SDMA_UCODE_SIZE 1050
  33 #define CIK_SDMA_UCODE_VERSION 64
  34
  35 u32 cik_gpu_check_soft_reset(struct radeon_device *rdev);
  36
  37 /*
  38  * sDMA - System DMA
  39  * Starting with CIK, the GPU has new asynchronous
  40  * DMA engines.  These engines are used for compute
  41  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
  42  * and each one supports 1 ring buffer used for gfx
  43  * and 2 queues used for compute.
  44  *
  45  * The programming model is very similar to the CP
  46  * (ring buffer, IBs, etc.), but sDMA has it's own
  47  * packet format that is different from the PM4 format
  48  * used by the CP. sDMA supports copying data, writing
  49  * embedded data, solid fills, and a number of other
  50  * things.  It also has support for tiling/detiling of
  51  * buffers.
  52  */
  53
  54 /**
  55  * cik_sdma_ring_ib_execute - Schedule an IB on the DMA engine
  56  *
  57  * @rdev: radeon_device pointer
  58  * @ib: IB object to schedule
  59  *
  60  * Schedule an IB in the DMA ring (CIK).
  61  */
  62 void cik_sdma_ring_ib_execute(struct radeon_device *rdev,
  63                               struct radeon_ib *ib)
  64 {
  65         struct radeon_ring *ring = &rdev->ring[ib->ring];
  66         u32 extra_bits = (ib->vm ? ib->vm->id : 0) & 0xf;
  67
  68         if (rdev->wb.enabled) {
  69                 u32 next_rptr = ring->wptr + 5;
  70                 while ((next_rptr & 7) != 4)
  71                         next_rptr++;
  72                 next_rptr += 4;
  73                 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
  74                 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
  75                 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
  76                 radeon_ring_write(ring, 1); /* number of DWs to follow */
  77                 radeon_ring_write(ring, next_rptr);
  78         }
  79
  80         /* IB packet must end on a 8 DW boundary */
  81         while ((ring->wptr & 7) != 4)
  82                 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
  83         radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
  84         radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
  85         radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);
  86         radeon_ring_write(ring, ib->length_dw);
  87
  88 }
  89
  90 /**
  91  * cik_sdma_fence_ring_emit - emit a fence on the DMA ring
  92  *
  93  * @rdev: radeon_device pointer
  94  * @fence: radeon fence object
  95  *
  96  * Add a DMA fence packet to the ring to write
  97  * the fence seq number and DMA trap packet to generate
  98  * an interrupt if needed (CIK).
  99  */
 100 void cik_sdma_fence_ring_emit(struct radeon_device *rdev,
 101                               struct radeon_fence *fence)
 102 {
 103         struct radeon_ring *ring = &rdev->ring[fence->ring];
 104         u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
 105
 106         /* write the fence */
 107         radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
 108         radeon_ring_write(ring, addr & 0xffffffff);
 109         radeon_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
 110         radeon_ring_write(ring, fence->seq);
 111         /* generate an interrupt */
 112         radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
 113         /* flush HDP */
 114         /* We should be using the new POLL_REG_MEM special op packet here
 115          * but it causes sDMA to hang sometimes
 116          */
 117         radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
 118         radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
 119         radeon_ring_write(ring, 0);
 120 }
 121
 122 /**
 123  * cik_sdma_semaphore_ring_emit - emit a semaphore on the dma ring
 124  *
 125  * @rdev: radeon_device pointer
 126  * @ring: radeon_ring structure holding ring information
 127  * @semaphore: radeon semaphore object
 128  * @emit_wait: wait or signal semaphore
 129  *
 130  * Add a DMA semaphore packet to the ring wait on or signal
 131  * other rings (CIK).
 132  */
 133 void cik_sdma_semaphore_ring_emit(struct radeon_device *rdev,
 134                                   struct radeon_ring *ring,
 135                                   struct radeon_semaphore *semaphore,
 136                                   bool emit_wait)
 137 {
 138         u64 addr = semaphore->gpu_addr;
 139         u32 extra_bits = emit_wait ? 0 : SDMA_SEMAPHORE_EXTRA_S;
 140
 141         radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits));
 142         radeon_ring_write(ring, addr & 0xfffffff8);
 143         radeon_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
 144 }
 145
 146 /**
 147  * cik_sdma_gfx_stop - stop the gfx async dma engines
 148  *
 149  * @rdev: radeon_device pointer
 150  *
 151  * Stop the gfx async dma ring buffers (CIK).
 152  */
 153 static void cik_sdma_gfx_stop(struct radeon_device *rdev)
 154 {
 155         u32 rb_cntl, reg_offset;
 156         int i;
 157
 158         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
 159
 160         for (i = 0; i < 2; i++) {
 161                 if (i == 0)
 162                         reg_offset = SDMA0_REGISTER_OFFSET;
 163                 else
 164                         reg_offset = SDMA1_REGISTER_OFFSET;
 165                 rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset);
 166                 rb_cntl &= ~SDMA_RB_ENABLE;
 167                 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl);
 168                 WREG32(SDMA0_GFX_IB_CNTL + reg_offset, 0);
 169         }
 170 }
 171
 172 /**
 173  * cik_sdma_rlc_stop - stop the compute async dma engines
 174  *
 175  * @rdev: radeon_device pointer
 176  *
 177  * Stop the compute async dma queues (CIK).
 178  */
 179 static void cik_sdma_rlc_stop(struct radeon_device *rdev)
 180 {
 181         /* XXX todo */
 182 }
 183
 184 /**
 185  * cik_sdma_enable - stop the async dma engines
 186  *
 187  * @rdev: radeon_device pointer
 188  * @enable: enable/disable the DMA MEs.
 189  *
 190  * Halt or unhalt the async dma engines (CIK).
 191  */
 192 void cik_sdma_enable(struct radeon_device *rdev, bool enable)
 193 {
 194         u32 me_cntl, reg_offset;
 195         int i;
 196
 197         for (i = 0; i < 2; i++) {
 198                 if (i == 0)
 199                         reg_offset = SDMA0_REGISTER_OFFSET;
 200                 else
 201                         reg_offset = SDMA1_REGISTER_OFFSET;
 202                 me_cntl = RREG32(SDMA0_ME_CNTL + reg_offset);
 203                 if (enable)
 204                         me_cntl &= ~SDMA_HALT;
 205                 else
 206                         me_cntl |= SDMA_HALT;
 207                 WREG32(SDMA0_ME_CNTL + reg_offset, me_cntl);
 208         }
 209 }
 210
 211 /**
 212  * cik_sdma_gfx_resume - setup and start the async dma engines
 213  *
 214  * @rdev: radeon_device pointer
 215  *
 216  * Set up the gfx DMA ring buffers and enable them (CIK).
 217  * Returns 0 for success, error for failure.
 218  */
 219 static int cik_sdma_gfx_resume(struct radeon_device *rdev)
 220 {
 221         struct radeon_ring *ring;
 222         u32 rb_cntl, ib_cntl;
 223         u32 rb_bufsz;
 224         u32 reg_offset, wb_offset;
 225         int i, r;
 226
 227         for (i = 0; i < 2; i++) {
 228                 if (i == 0) {
 229                         ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
 230                         reg_offset = SDMA0_REGISTER_OFFSET;
 231                         wb_offset = R600_WB_DMA_RPTR_OFFSET;
 232                 } else {
 233                         ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
 234                         reg_offset = SDMA1_REGISTER_OFFSET;
 235                         wb_offset = CAYMAN_WB_DMA1_RPTR_OFFSET;
 236                 }
 237
 238                 WREG32(SDMA0_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0);
 239                 WREG32(SDMA0_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0);
 240
 241                 /* Set ring buffer size in dwords */
 242                 rb_bufsz = order_base_2(ring->ring_size / 4);
 243                 rb_cntl = rb_bufsz << 1;
 244 #ifdef __BIG_ENDIAN
 245                 rb_cntl |= SDMA_RB_SWAP_ENABLE | SDMA_RPTR_WRITEBACK_SWAP_ENABLE;
 246 #endif
 247                 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl);
 248
 249                 /* Initialize the ring buffer's read and write pointers */
 250                 WREG32(SDMA0_GFX_RB_RPTR + reg_offset, 0);
 251                 WREG32(SDMA0_GFX_RB_WPTR + reg_offset, 0);
 252
 253                 /* set the wb address whether it's enabled or not */
 254                 WREG32(SDMA0_GFX_RB_RPTR_ADDR_HI + reg_offset,
 255                        upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 256                 WREG32(SDMA0_GFX_RB_RPTR_ADDR_LO + reg_offset,
 257                        ((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
 258
 259                 if (rdev->wb.enabled)
 260                         rb_cntl |= SDMA_RPTR_WRITEBACK_ENABLE;
 261
 262                 WREG32(SDMA0_GFX_RB_BASE + reg_offset, ring->gpu_addr >> 8);
 263                 WREG32(SDMA0_GFX_RB_BASE_HI + reg_offset, ring->gpu_addr >> 40);
 264
 265                 ring->wptr = 0;
 266                 WREG32(SDMA0_GFX_RB_WPTR + reg_offset, ring->wptr << 2);
 267
 268                 ring->rptr = RREG32(SDMA0_GFX_RB_RPTR + reg_offset) >> 2;
 269
 270                 /* enable DMA RB */
 271                 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl | SDMA_RB_ENABLE);
 272
 273                 ib_cntl = SDMA_IB_ENABLE;
 274 #ifdef __BIG_ENDIAN
 275                 ib_cntl |= SDMA_IB_SWAP_ENABLE;
 276 #endif
 277                 /* enable DMA IBs */
 278                 WREG32(SDMA0_GFX_IB_CNTL + reg_offset, ib_cntl);
 279
 280                 ring->ready = true;
 281
 282                 r = radeon_ring_test(rdev, ring->idx, ring);
 283                 if (r) {
 284                         ring->ready = false;
 285                         return r;
 286                 }
 287         }
 288
 289         radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
 290
 291         return 0;
 292 }
 293
 294 /**
 295  * cik_sdma_rlc_resume - setup and start the async dma engines
 296  *
 297  * @rdev: radeon_device pointer
 298  *
 299  * Set up the compute DMA queues and enable them (CIK).
 300  * Returns 0 for success, error for failure.
 301  */
 302 static int cik_sdma_rlc_resume(struct radeon_device *rdev)
 303 {
 304         /* XXX todo */
 305         return 0;
 306 }
 307
 308 /**
 309  * cik_sdma_load_microcode - load the sDMA ME ucode
 310  *
 311  * @rdev: radeon_device pointer
 312  *
 313  * Loads the sDMA0/1 ucode.
 314  * Returns 0 for success, -EINVAL if the ucode is not available.
 315  */
 316 static int cik_sdma_load_microcode(struct radeon_device *rdev)
 317 {
 318         const __be32 *fw_data;
 319         int i;
 320
 321         if (!rdev->sdma_fw)
 322                 return -EINVAL;
 323
 324         /* stop the gfx rings and rlc compute queues */
 325         cik_sdma_gfx_stop(rdev);
 326         cik_sdma_rlc_stop(rdev);
 327
 328         /* halt the MEs */
 329         cik_sdma_enable(rdev, false);
 330
 331         /* sdma0 */
 332         fw_data = (const __be32 *)rdev->sdma_fw->data;
 333         WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);
 334         for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++)
 335                 WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, be32_to_cpup(fw_data++));
 336         WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);
 337
 338         /* sdma1 */
 339         fw_data = (const __be32 *)rdev->sdma_fw->data;
 340         WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);
 341         for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++)
 342                 WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, be32_to_cpup(fw_data++));
 343         WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);
 344
 345         WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);
 346         WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);
 347         return 0;
 348 }
 349
 350 /**
 351  * cik_sdma_resume - setup and start the async dma engines
 352  *
 353  * @rdev: radeon_device pointer
 354  *
 355  * Set up the DMA engines and enable them (CIK).
 356  * Returns 0 for success, error for failure.
 357  */
 358 int cik_sdma_resume(struct radeon_device *rdev)
 359 {
 360         int r;
 361
 362         /* Reset dma */
 363         WREG32(SRBM_SOFT_RESET, SOFT_RESET_SDMA | SOFT_RESET_SDMA1);
 364         RREG32(SRBM_SOFT_RESET);
 365         udelay(50);
 366         WREG32(SRBM_SOFT_RESET, 0);
 367         RREG32(SRBM_SOFT_RESET);
 368
 369         r = cik_sdma_load_microcode(rdev);
 370         if (r)
 371                 return r;
 372
 373         /* unhalt the MEs */
 374         cik_sdma_enable(rdev, true);
 375
 376         /* start the gfx rings and rlc compute queues */
 377         r = cik_sdma_gfx_resume(rdev);
 378         if (r)
 379                 return r;
 380         r = cik_sdma_rlc_resume(rdev);
 381         if (r)
 382                 return r;
 383
 384         return 0;
 385 }
 386
 387 /**
 388  * cik_sdma_fini - tear down the async dma engines
 389  *
 390  * @rdev: radeon_device pointer
 391  *
 392  * Stop the async dma engines and free the rings (CIK).
 393  */
 394 void cik_sdma_fini(struct radeon_device *rdev)
 395 {
 396         /* stop the gfx rings and rlc compute queues */
 397         cik_sdma_gfx_stop(rdev);
 398         cik_sdma_rlc_stop(rdev);
 399         /* halt the MEs */
 400         cik_sdma_enable(rdev, false);
 401         radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);
 402         radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]);
 403         /* XXX - compute dma queue tear down */
 404 }
 405
 406 /**
 407  * cik_copy_dma - copy pages using the DMA engine
 408  *
 409  * @rdev: radeon_device pointer
 410  * @src_offset: src GPU address
 411  * @dst_offset: dst GPU address
 412  * @num_gpu_pages: number of GPU pages to xfer
 413  * @fence: radeon fence object
 414  *
 415  * Copy GPU paging using the DMA engine (CIK).
 416  * Used by the radeon ttm implementation to move pages if
 417  * registered as the asic copy callback.
 418  */
 419 int cik_copy_dma(struct radeon_device *rdev,
 420                  uint64_t src_offset, uint64_t dst_offset,
 421                  unsigned num_gpu_pages,
 422                  struct radeon_fence **fence)
 423 {
 424         struct radeon_semaphore *sem = NULL;
 425         int ring_index = rdev->asic->copy.dma_ring_index;
 426         struct radeon_ring *ring = &rdev->ring[ring_index];
 427         u32 size_in_bytes, cur_size_in_bytes;
 428         int i, num_loops;
 429         int r = 0;
 430
 431         r = radeon_semaphore_create(rdev, &sem);
 432         if (r) {
 433                 DRM_ERROR("radeon: moving bo (%d).\n", r);
 434                 return r;
 435         }
 436
 437         size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
 438         num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff);
 439         r = radeon_ring_lock(rdev, ring, num_loops * 7 + 14);
 440         if (r) {
 441                 DRM_ERROR("radeon: moving bo (%d).\n", r);
 442                 radeon_semaphore_free(rdev, &sem, NULL);
 443                 return r;
 444         }
 445
 446         if (radeon_fence_need_sync(*fence, ring->idx)) {
 447                 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
 448                                             ring->idx);
 449                 radeon_fence_note_sync(*fence, ring->idx);
 450         } else {
 451                 radeon_semaphore_free(rdev, &sem, NULL);
 452         }
 453
 454         for (i = 0; i < num_loops; i++) {
 455                 cur_size_in_bytes = size_in_bytes;
 456                 if (cur_size_in_bytes > 0x1fffff)
 457                         cur_size_in_bytes = 0x1fffff;
 458                 size_in_bytes -= cur_size_in_bytes;
 459                 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0));
 460                 radeon_ring_write(ring, cur_size_in_bytes);
 461                 radeon_ring_write(ring, 0); /* src/dst endian swap */
 462                 radeon_ring_write(ring, src_offset & 0xffffffff);
 463                 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xffffffff);
 464                 radeon_ring_write(ring, dst_offset & 0xfffffffc);
 465                 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xffffffff);
 466                 src_offset += cur_size_in_bytes;
 467                 dst_offset += cur_size_in_bytes;
 468         }
 469
 470         r = radeon_fence_emit(rdev, fence, ring->idx);
 471         if (r) {
 472                 radeon_ring_unlock_undo(rdev, ring);
 473                 return r;
 474         }
 475
 476         radeon_ring_unlock_commit(rdev, ring);
 477         radeon_semaphore_free(rdev, &sem, *fence);
 478
 479         return r;
 480 }
 481
 482 /**
 483  * cik_sdma_ring_test - simple async dma engine test
 484  *
 485  * @rdev: radeon_device pointer
 486  * @ring: radeon_ring structure holding ring information
 487  *
 488  * Test the DMA engine by writing using it to write an
 489  * value to memory. (CIK).
 490  * Returns 0 for success, error for failure.
 491  */
 492 int cik_sdma_ring_test(struct radeon_device *rdev,
 493                        struct radeon_ring *ring)
 494 {
 495         unsigned i;
 496         int r;
 497         void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
 498         u32 tmp;
 499
 500         if (!ptr) {
 501                 DRM_ERROR("invalid vram scratch pointer\n");
 502                 return -EINVAL;
 503         }
 504
 505         tmp = 0xCAFEDEAD;
 506         writel(tmp, ptr);
 507
 508         r = radeon_ring_lock(rdev, ring, 4);
 509         if (r) {
 510                 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r);
 511                 return r;
 512         }
 513         radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
 514         radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc);
 515         radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xffffffff);
 516         radeon_ring_write(ring, 1); /* number of DWs to follow */
 517         radeon_ring_write(ring, 0xDEADBEEF);
 518         radeon_ring_unlock_commit(rdev, ring);
 519
 520         for (i = 0; i < rdev->usec_timeout; i++) {
 521                 tmp = readl(ptr);
 522                 if (tmp == 0xDEADBEEF)
 523                         break;
 524                 DRM_UDELAY(1);
 525         }
 526
 527         if (i < rdev->usec_timeout) {
 528                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 529         } else {
 530                 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
 531                           ring->idx, tmp);
 532                 r = -EINVAL;
 533         }
 534         return r;
 535 }
 536
 537 /**
 538  * cik_sdma_ib_test - test an IB on the DMA engine
 539  *
 540  * @rdev: radeon_device pointer
 541  * @ring: radeon_ring structure holding ring information
 542  *
 543  * Test a simple IB in the DMA ring (CIK).
 544  * Returns 0 on success, error on failure.
 545  */
 546 int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
 547 {
 548         struct radeon_ib ib;
 549         unsigned i;
 550         int r;
 551         void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
 552         u32 tmp = 0;
 553
 554         if (!ptr) {
 555                 DRM_ERROR("invalid vram scratch pointer\n");
 556                 return -EINVAL;
 557         }
 558
 559         tmp = 0xCAFEDEAD;
 560         writel(tmp, ptr);
 561
 562         r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
 563         if (r) {
 564                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
 565                 return r;
 566         }
 567
 568         ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 569         ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc;
 570         ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xffffffff;
 571         ib.ptr[3] = 1;
 572         ib.ptr[4] = 0xDEADBEEF;
 573         ib.length_dw = 5;
 574
 575         r = radeon_ib_schedule(rdev, &ib, NULL);
 576         if (r) {
 577                 radeon_ib_free(rdev, &ib);
 578                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
 579                 return r;
 580         }
 581         r = radeon_fence_wait(ib.fence, false);
 582         if (r) {
 583                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
 584                 return r;
 585         }
 586         for (i = 0; i < rdev->usec_timeout; i++) {
 587                 tmp = readl(ptr);
 588                 if (tmp == 0xDEADBEEF)
 589                         break;
 590                 DRM_UDELAY(1);
 591         }
 592         if (i < rdev->usec_timeout) {
 593                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
 594         } else {
 595                 DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp);
 596                 r = -EINVAL;
 597         }
 598         radeon_ib_free(rdev, &ib);
 599         return r;
 600 }
 601
 602 /**
 603  * cik_sdma_is_lockup - Check if the DMA engine is locked up
 604  *
 605  * @rdev: radeon_device pointer
 606  * @ring: radeon_ring structure holding ring information
 607  *
 608  * Check if the async DMA engine is locked up (CIK).
 609  * Returns true if the engine appears to be locked up, false if not.
 610  */
 611 bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
 612 {
 613         u32 reset_mask = cik_gpu_check_soft_reset(rdev);
 614         u32 mask;
 615
 616         if (ring->idx == R600_RING_TYPE_DMA_INDEX)
 617                 mask = RADEON_RESET_DMA;
 618         else
 619                 mask = RADEON_RESET_DMA1;
 620
 621         if (!(reset_mask & mask)) {
 622                 radeon_ring_lockup_update(ring);
 623                 return false;
 624         }
 625         /* force ring activities */
 626         radeon_ring_force_activity(rdev, ring);
 627         return radeon_ring_test_lockup(rdev, ring);
 628 }
 629
 630 /**
 631  * cik_sdma_vm_set_page - update the page tables using sDMA
 632  *
 633  * @rdev: radeon_device pointer
 634  * @ib: indirect buffer to fill with commands
 635  * @pe: addr of the page entry
 636  * @addr: dst addr to write into pe
 637  * @count: number of page entries to update
 638  * @incr: increase next addr by incr bytes
 639  * @flags: access flags
 640  *
 641  * Update the page tables using sDMA (CIK).
 642  */
 643 void cik_sdma_vm_set_page(struct radeon_device *rdev,
 644                           struct radeon_ib *ib,
 645                           uint64_t pe,
 646                           uint64_t addr, unsigned count,
 647                           uint32_t incr, uint32_t flags)
 648 {
 649         uint64_t value;
 650         unsigned ndw;
 651
 652         trace_radeon_vm_set_page(pe, addr, count, incr, flags);
 653
 654         if (flags & R600_PTE_SYSTEM) {
 655                 while (count) {
 656                         ndw = count * 2;
 657                         if (ndw > 0xFFFFE)
 658                                 ndw = 0xFFFFE;
 659
 660                         /* for non-physically contiguous pages (system) */
 661                         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 662                         ib->ptr[ib->length_dw++] = pe;
 663                         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 664                         ib->ptr[ib->length_dw++] = ndw;
 665                         for (; ndw > 0; ndw -= 2, --count, pe += 8) {
 666                                 value = radeon_vm_map_gart(rdev, addr);
 667                                 value &= 0xFFFFFFFFFFFFF000ULL;
 668                                 addr += incr;
 669                                 value |= flags;
 670                                 ib->ptr[ib->length_dw++] = value;
 671                                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
 672                         }
 673                 }
 674         } else {
 675                 while (count) {
 676                         ndw = count;
 677                         if (ndw > 0x7FFFF)
 678                                 ndw = 0x7FFFF;
 679
 680                         if (flags & R600_PTE_VALID)
 681                                 value = addr;
 682                         else
 683                                 value = 0;
 684                         /* for physically contiguous pages (vram) */
 685                         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
 686                         ib->ptr[ib->length_dw++] = pe; /* dst addr */
 687                         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 688                         ib->ptr[ib->length_dw++] = flags; /* mask */
 689                         ib->ptr[ib->length_dw++] = 0;
 690                         ib->ptr[ib->length_dw++] = value; /* value */
 691                         ib->ptr[ib->length_dw++] = upper_32_bits(value);
 692                         ib->ptr[ib->length_dw++] = incr; /* increment size */
 693                         ib->ptr[ib->length_dw++] = 0;
 694                         ib->ptr[ib->length_dw++] = ndw; /* number of entries */
 695                         pe += ndw * 8;
 696                         addr += ndw * incr;
 697                         count -= ndw;
 698                 }
 699         }
 700         while (ib->length_dw & 0x7)
 701                 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0);
 702 }
 703
 704 /**
 705  * cik_dma_vm_flush - cik vm flush using sDMA
 706  *
 707  * @rdev: radeon_device pointer
 708  *
 709  * Update the page table base and flush the VM TLB
 710  * using sDMA (CIK).
 711  */
 712 void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
 713 {
 714         struct radeon_ring *ring = &rdev->ring[ridx];
 715
 716         if (vm == NULL)
 717                 return;
 718
 719         radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
 720         if (vm->id < 8) {
 721                 radeon_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2);
 722         } else {
 723                 radeon_ring_write(ring, (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2);
 724         }
 725         radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
 726
 727         /* update SH_MEM_* regs */
 728         radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
 729         radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
 730         radeon_ring_write(ring, VMID(vm->id));
 731
 732         radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
 733         radeon_ring_write(ring, SH_MEM_BASES >> 2);
 734         radeon_ring_write(ring, 0);
 735
 736         radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
 737         radeon_ring_write(ring, SH_MEM_CONFIG >> 2);
 738         radeon_ring_write(ring, 0);
 739
 740         radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
 741         radeon_ring_write(ring, SH_MEM_APE1_BASE >> 2);
 742         radeon_ring_write(ring, 1);
 743
 744         radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
 745         radeon_ring_write(ring, SH_MEM_APE1_LIMIT >> 2);
 746         radeon_ring_write(ring, 0);
 747
 748         radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
 749         radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
 750         radeon_ring_write(ring, VMID(0));
 751
 752         /* flush HDP */
 753         /* We should be using the new POLL_REG_MEM special op packet here
 754          * but it causes sDMA to hang sometimes
 755          */
 756         radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
 757         radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
 758         radeon_ring_write(ring, 0);
 759
 760         /* flush TLB */
 761         radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
 762         radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
 763         radeon_ring_write(ring, 1 << vm->id);
 764 }
 765