2 * Copyright 2007-11 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
31 #include <linux/backlight.h>
33 extern int atom_debug;
36 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
41 if (rdev->family >= CHIP_R600)
42 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
44 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
46 backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
47 ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
49 return backlight_level;
53 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
58 if (rdev->family >= CHIP_R600)
59 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
61 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
63 bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
64 bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
65 ATOM_S2_CURRENT_BL_LEVEL_MASK);
67 if (rdev->family >= CHIP_R600)
68 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
70 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
74 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
76 struct drm_device *dev = radeon_encoder->base.dev;
77 struct radeon_device *rdev = dev->dev_private;
79 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
82 return radeon_atom_get_backlight_level_from_reg(rdev);
86 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
88 struct drm_encoder *encoder = &radeon_encoder->base;
89 struct drm_device *dev = radeon_encoder->base.dev;
90 struct radeon_device *rdev = dev->dev_private;
91 struct radeon_encoder_atom_dig *dig;
92 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
95 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
98 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
99 radeon_encoder->enc_priv) {
100 dig = radeon_encoder->enc_priv;
101 dig->backlight_level = level;
102 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
104 switch (radeon_encoder->encoder_id) {
105 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
106 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
107 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
108 if (dig->backlight_level == 0) {
109 args.ucAction = ATOM_LCD_BLOFF;
110 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
112 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
113 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
114 args.ucAction = ATOM_LCD_BLON;
115 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
118 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
119 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
120 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
121 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
122 if (dig->backlight_level == 0)
123 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
125 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
126 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
135 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
137 static u8 radeon_atom_bl_level(struct backlight_device *bd)
141 /* Convert brightness to hardware level */
142 if (bd->props.brightness < 0)
144 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
145 level = RADEON_MAX_BL_LEVEL;
147 level = bd->props.brightness;
152 static int radeon_atom_backlight_update_status(struct backlight_device *bd)
154 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
155 struct radeon_encoder *radeon_encoder = pdata->encoder;
157 atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
162 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
164 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
165 struct radeon_encoder *radeon_encoder = pdata->encoder;
166 struct drm_device *dev = radeon_encoder->base.dev;
167 struct radeon_device *rdev = dev->dev_private;
169 return radeon_atom_get_backlight_level_from_reg(rdev);
172 static const struct backlight_ops radeon_atom_backlight_ops = {
173 .get_brightness = radeon_atom_backlight_get_brightness,
174 .update_status = radeon_atom_backlight_update_status,
177 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
178 struct drm_connector *drm_connector)
180 struct drm_device *dev = radeon_encoder->base.dev;
181 struct radeon_device *rdev = dev->dev_private;
182 struct backlight_device *bd;
183 struct backlight_properties props;
184 struct radeon_backlight_privdata *pdata;
185 struct radeon_encoder_atom_dig *dig;
189 /* Mac laptops with multiple GPUs use the gmux driver for backlight
190 * so don't register a backlight device
192 if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
193 (rdev->pdev->device == 0x6741))
196 if (!radeon_encoder->enc_priv)
199 if (!rdev->is_atom_bios)
202 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
205 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
207 DRM_ERROR("Memory allocation failed\n");
211 memset(&props, 0, sizeof(props));
212 props.max_brightness = RADEON_MAX_BL_LEVEL;
213 props.type = BACKLIGHT_RAW;
214 snprintf(bl_name, sizeof(bl_name),
215 "radeon_bl%d", dev->primary->index);
216 bd = backlight_device_register(bl_name, &drm_connector->kdev,
217 pdata, &radeon_atom_backlight_ops, &props);
219 DRM_ERROR("Backlight registration failed\n");
223 pdata->encoder = radeon_encoder;
225 backlight_level = radeon_atom_get_backlight_level_from_reg(rdev);
227 dig = radeon_encoder->enc_priv;
230 bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
231 bd->props.power = FB_BLANK_UNBLANK;
232 backlight_update_status(bd);
234 DRM_INFO("radeon atom DIG backlight initialized\n");
243 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
245 struct drm_device *dev = radeon_encoder->base.dev;
246 struct radeon_device *rdev = dev->dev_private;
247 struct backlight_device *bd = NULL;
248 struct radeon_encoder_atom_dig *dig;
250 if (!radeon_encoder->enc_priv)
253 if (!rdev->is_atom_bios)
256 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
259 dig = radeon_encoder->enc_priv;
264 struct radeon_legacy_backlight_privdata *pdata;
266 pdata = bl_get_data(bd);
267 backlight_device_unregister(bd);
270 DRM_INFO("radeon atom LVDS backlight unloaded\n");
274 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
276 void radeon_atom_backlight_init(struct radeon_encoder *encoder)
280 static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
286 /* evil but including atombios.h is much worse */
287 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
288 struct drm_display_mode *mode);
291 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
293 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
294 switch (radeon_encoder->encoder_id) {
295 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
296 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
297 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
298 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
299 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
300 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
301 case ENCODER_OBJECT_ID_INTERNAL_DDI:
302 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
303 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
304 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
305 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
312 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
313 const struct drm_display_mode *mode,
314 struct drm_display_mode *adjusted_mode)
316 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
317 struct drm_device *dev = encoder->dev;
318 struct radeon_device *rdev = dev->dev_private;
320 /* set the active encoder to connector routing */
321 radeon_encoder_set_active_device(encoder);
322 drm_mode_set_crtcinfo(adjusted_mode, 0);
325 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
326 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
327 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
329 /* get the native mode for LVDS */
330 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
331 radeon_panel_mode_fixup(encoder, adjusted_mode);
333 /* get the native mode for TV */
334 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
335 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
337 if (tv_dac->tv_std == TV_STD_NTSC ||
338 tv_dac->tv_std == TV_STD_NTSC_J ||
339 tv_dac->tv_std == TV_STD_PAL_M)
340 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
342 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
346 if (ASIC_IS_DCE3(rdev) &&
347 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
348 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
349 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
350 radeon_dp_set_link_config(connector, adjusted_mode);
357 atombios_dac_setup(struct drm_encoder *encoder, int action)
359 struct drm_device *dev = encoder->dev;
360 struct radeon_device *rdev = dev->dev_private;
361 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
362 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
364 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
366 memset(&args, 0, sizeof(args));
368 switch (radeon_encoder->encoder_id) {
369 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
370 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
371 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
373 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
374 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
375 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
379 args.ucAction = action;
381 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
382 args.ucDacStandard = ATOM_DAC1_PS2;
383 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
384 args.ucDacStandard = ATOM_DAC1_CV;
386 switch (dac_info->tv_std) {
389 case TV_STD_SCART_PAL:
392 args.ucDacStandard = ATOM_DAC1_PAL;
398 args.ucDacStandard = ATOM_DAC1_NTSC;
402 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
404 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
409 atombios_tv_setup(struct drm_encoder *encoder, int action)
411 struct drm_device *dev = encoder->dev;
412 struct radeon_device *rdev = dev->dev_private;
413 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
414 TV_ENCODER_CONTROL_PS_ALLOCATION args;
416 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
418 memset(&args, 0, sizeof(args));
420 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
422 args.sTVEncoder.ucAction = action;
424 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
425 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
427 switch (dac_info->tv_std) {
429 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
432 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
435 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
438 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
441 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
443 case TV_STD_SCART_PAL:
444 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
447 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
450 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
453 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
458 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
460 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
464 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
466 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
470 bpc = radeon_get_monitor_bpc(connector);
474 return PANEL_BPC_UNDEFINE;
476 return PANEL_6BIT_PER_COLOR;
479 return PANEL_8BIT_PER_COLOR;
481 return PANEL_10BIT_PER_COLOR;
483 return PANEL_12BIT_PER_COLOR;
485 return PANEL_16BIT_PER_COLOR;
490 union dvo_encoder_control {
491 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
492 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
493 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
497 atombios_dvo_setup(struct drm_encoder *encoder, int action)
499 struct drm_device *dev = encoder->dev;
500 struct radeon_device *rdev = dev->dev_private;
501 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
502 union dvo_encoder_control args;
503 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
506 memset(&args, 0, sizeof(args));
508 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
511 /* some R4xx chips have the wrong frev */
512 if (rdev->family <= CHIP_RV410)
520 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
522 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
523 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
525 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
529 args.dvo.sDVOEncoder.ucAction = action;
530 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
531 /* DFP1, CRT1, TV1 depending on the type of port */
532 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
534 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
535 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
539 args.dvo_v3.ucAction = action;
540 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
541 args.dvo_v3.ucDVOConfig = 0; /* XXX */
544 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
549 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
553 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
556 union lvds_encoder_control {
557 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
558 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
562 atombios_digital_setup(struct drm_encoder *encoder, int action)
564 struct drm_device *dev = encoder->dev;
565 struct radeon_device *rdev = dev->dev_private;
566 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
567 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
568 union lvds_encoder_control args;
570 int hdmi_detected = 0;
576 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
579 memset(&args, 0, sizeof(args));
581 switch (radeon_encoder->encoder_id) {
582 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
583 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
585 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
586 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
587 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
589 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
590 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
591 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
593 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
597 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
606 args.v1.ucAction = action;
608 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
609 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
610 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
611 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
612 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
613 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
614 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
617 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
618 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
619 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
620 /*if (pScrn->rgbBits == 8) */
621 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
627 args.v2.ucAction = action;
629 if (dig->coherent_mode)
630 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
633 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
634 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
635 args.v2.ucTruncate = 0;
636 args.v2.ucSpatial = 0;
637 args.v2.ucTemporal = 0;
639 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
640 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
641 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
642 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
643 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
644 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
645 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
647 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
648 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
649 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
650 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
651 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
652 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
656 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
657 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
658 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
662 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
667 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
671 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
675 atombios_get_encoder_mode(struct drm_encoder *encoder)
677 struct drm_device *dev = encoder->dev;
678 struct radeon_device *rdev = dev->dev_private;
679 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
680 struct drm_connector *connector;
681 struct radeon_connector *radeon_connector;
682 struct radeon_connector_atom_dig *dig_connector;
684 /* dp bridges are always DP */
685 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
686 return ATOM_ENCODER_MODE_DP;
688 /* DVO is always DVO */
689 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
690 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
691 return ATOM_ENCODER_MODE_DVO;
693 connector = radeon_get_connector_for_encoder(encoder);
694 /* if we don't have an active device yet, just use one of
695 * the connectors tied to the encoder.
698 connector = radeon_get_connector_for_encoder_init(encoder);
699 radeon_connector = to_radeon_connector(connector);
701 switch (connector->connector_type) {
702 case DRM_MODE_CONNECTOR_DVII:
703 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
704 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
706 !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
707 return ATOM_ENCODER_MODE_HDMI;
708 else if (radeon_connector->use_digital)
709 return ATOM_ENCODER_MODE_DVI;
711 return ATOM_ENCODER_MODE_CRT;
713 case DRM_MODE_CONNECTOR_DVID:
714 case DRM_MODE_CONNECTOR_HDMIA:
716 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
718 !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
719 return ATOM_ENCODER_MODE_HDMI;
721 return ATOM_ENCODER_MODE_DVI;
723 case DRM_MODE_CONNECTOR_LVDS:
724 return ATOM_ENCODER_MODE_LVDS;
726 case DRM_MODE_CONNECTOR_DisplayPort:
727 dig_connector = radeon_connector->con_priv;
728 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
729 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
730 return ATOM_ENCODER_MODE_DP;
731 else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
733 !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
734 return ATOM_ENCODER_MODE_HDMI;
736 return ATOM_ENCODER_MODE_DVI;
738 case DRM_MODE_CONNECTOR_eDP:
739 return ATOM_ENCODER_MODE_DP;
740 case DRM_MODE_CONNECTOR_DVIA:
741 case DRM_MODE_CONNECTOR_VGA:
742 return ATOM_ENCODER_MODE_CRT;
744 case DRM_MODE_CONNECTOR_Composite:
745 case DRM_MODE_CONNECTOR_SVIDEO:
746 case DRM_MODE_CONNECTOR_9PinDIN:
748 return ATOM_ENCODER_MODE_TV;
749 /*return ATOM_ENCODER_MODE_CV;*/
755 * DIG Encoder/Transmitter Setup
758 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
759 * Supports up to 3 digital outputs
760 * - 2 DIG encoder blocks.
761 * DIG1 can drive UNIPHY link A or link B
762 * DIG2 can drive UNIPHY link B or LVTMA
765 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
766 * Supports up to 5 digital outputs
767 * - 2 DIG encoder blocks.
768 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
771 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
772 * Supports up to 6 digital outputs
773 * - 6 DIG encoder blocks.
774 * - DIG to PHY mapping is hardcoded
775 * DIG1 drives UNIPHY0 link A, A+B
776 * DIG2 drives UNIPHY0 link B
777 * DIG3 drives UNIPHY1 link A, A+B
778 * DIG4 drives UNIPHY1 link B
779 * DIG5 drives UNIPHY2 link A, A+B
780 * DIG6 drives UNIPHY2 link B
783 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
784 * Supports up to 6 digital outputs
785 * - 2 DIG encoder blocks.
787 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
789 * DIG1 drives UNIPHY0/1/2 link A
790 * DIG2 drives UNIPHY0/1/2 link B
793 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
795 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
796 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
797 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
798 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
801 union dig_encoder_control {
802 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
803 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
804 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
805 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
809 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
811 struct drm_device *dev = encoder->dev;
812 struct radeon_device *rdev = dev->dev_private;
813 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
814 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
815 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
816 union dig_encoder_control args;
820 int dp_lane_count = 0;
821 int hpd_id = RADEON_HPD_NONE;
824 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
825 struct radeon_connector_atom_dig *dig_connector =
826 radeon_connector->con_priv;
828 dp_clock = dig_connector->dp_clock;
829 dp_lane_count = dig_connector->dp_lane_count;
830 hpd_id = radeon_connector->hpd.hpd;
833 /* no dig encoder assigned */
834 if (dig->dig_encoder == -1)
837 memset(&args, 0, sizeof(args));
839 if (ASIC_IS_DCE4(rdev))
840 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
842 if (dig->dig_encoder)
843 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
845 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
848 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
855 args.v1.ucAction = action;
856 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
857 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
858 args.v3.ucPanelMode = panel_mode;
860 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
862 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
863 args.v1.ucLaneNum = dp_lane_count;
864 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
865 args.v1.ucLaneNum = 8;
867 args.v1.ucLaneNum = 4;
869 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
870 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
871 switch (radeon_encoder->encoder_id) {
872 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
873 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
875 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
876 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
877 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
879 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
880 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
884 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
886 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
890 args.v3.ucAction = action;
891 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
892 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
893 args.v3.ucPanelMode = panel_mode;
895 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
897 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
898 args.v3.ucLaneNum = dp_lane_count;
899 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
900 args.v3.ucLaneNum = 8;
902 args.v3.ucLaneNum = 4;
904 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
905 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
906 args.v3.acConfig.ucDigSel = dig->dig_encoder;
907 args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
910 args.v4.ucAction = action;
911 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
912 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
913 args.v4.ucPanelMode = panel_mode;
915 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
917 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
918 args.v4.ucLaneNum = dp_lane_count;
919 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
920 args.v4.ucLaneNum = 8;
922 args.v4.ucLaneNum = 4;
924 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
925 if (dp_clock == 270000)
926 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
927 else if (dp_clock == 540000)
928 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
930 args.v4.acConfig.ucDigSel = dig->dig_encoder;
931 args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
932 if (hpd_id == RADEON_HPD_NONE)
933 args.v4.ucHPD_ID = 0;
935 args.v4.ucHPD_ID = hpd_id + 1;
938 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
943 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
947 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
951 union dig_transmitter_control {
952 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
953 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
954 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
955 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
956 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
960 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
962 struct drm_device *dev = encoder->dev;
963 struct radeon_device *rdev = dev->dev_private;
964 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
965 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
966 struct drm_connector *connector;
967 union dig_transmitter_control args;
973 int dp_lane_count = 0;
974 int connector_object_id = 0;
975 int igp_lane_info = 0;
976 int dig_encoder = dig->dig_encoder;
977 int hpd_id = RADEON_HPD_NONE;
979 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
980 connector = radeon_get_connector_for_encoder_init(encoder);
981 /* just needed to avoid bailing in the encoder check. the encoder
982 * isn't used for init
986 connector = radeon_get_connector_for_encoder(encoder);
989 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
990 struct radeon_connector_atom_dig *dig_connector =
991 radeon_connector->con_priv;
993 hpd_id = radeon_connector->hpd.hpd;
994 dp_clock = dig_connector->dp_clock;
995 dp_lane_count = dig_connector->dp_lane_count;
996 connector_object_id =
997 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
998 igp_lane_info = dig_connector->igp_lane_info;
1001 if (encoder->crtc) {
1002 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1003 pll_id = radeon_crtc->pll_id;
1006 /* no dig encoder assigned */
1007 if (dig_encoder == -1)
1010 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
1013 memset(&args, 0, sizeof(args));
1015 switch (radeon_encoder->encoder_id) {
1016 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1017 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1019 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1020 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1021 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1022 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1024 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1025 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1029 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1036 args.v1.ucAction = action;
1037 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1038 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1039 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1040 args.v1.asMode.ucLaneSel = lane_num;
1041 args.v1.asMode.ucLaneSet = lane_set;
1044 args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
1045 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1046 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1048 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1051 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1054 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1056 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1058 if ((rdev->flags & RADEON_IS_IGP) &&
1059 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1061 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
1062 if (igp_lane_info & 0x1)
1063 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1064 else if (igp_lane_info & 0x2)
1065 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1066 else if (igp_lane_info & 0x4)
1067 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1068 else if (igp_lane_info & 0x8)
1069 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1071 if (igp_lane_info & 0x3)
1072 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1073 else if (igp_lane_info & 0xc)
1074 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1079 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1081 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1084 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1085 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1086 if (dig->coherent_mode)
1087 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1088 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1089 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1093 args.v2.ucAction = action;
1094 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1095 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1096 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1097 args.v2.asMode.ucLaneSel = lane_num;
1098 args.v2.asMode.ucLaneSet = lane_set;
1101 args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
1102 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1103 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1105 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1108 args.v2.acConfig.ucEncoderSel = dig_encoder;
1110 args.v2.acConfig.ucLinkSel = 1;
1112 switch (radeon_encoder->encoder_id) {
1113 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1114 args.v2.acConfig.ucTransmitterSel = 0;
1116 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1117 args.v2.acConfig.ucTransmitterSel = 1;
1119 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1120 args.v2.acConfig.ucTransmitterSel = 2;
1125 args.v2.acConfig.fCoherentMode = 1;
1126 args.v2.acConfig.fDPConnector = 1;
1127 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1128 if (dig->coherent_mode)
1129 args.v2.acConfig.fCoherentMode = 1;
1130 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1131 args.v2.acConfig.fDualLinkConnector = 1;
1135 args.v3.ucAction = action;
1136 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1137 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1138 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1139 args.v3.asMode.ucLaneSel = lane_num;
1140 args.v3.asMode.ucLaneSet = lane_set;
1143 args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
1144 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1145 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1147 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1151 args.v3.ucLaneNum = dp_lane_count;
1152 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1153 args.v3.ucLaneNum = 8;
1155 args.v3.ucLaneNum = 4;
1158 args.v3.acConfig.ucLinkSel = 1;
1159 if (dig_encoder & 1)
1160 args.v3.acConfig.ucEncoderSel = 1;
1162 /* Select the PLL for the PHY
1163 * DP PHY should be clocked from external src if there is
1166 /* On DCE4, if there is an external clock, it generates the DP ref clock */
1167 if (is_dp && rdev->clock.dp_extclk)
1168 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1170 args.v3.acConfig.ucRefClkSource = pll_id;
1172 switch (radeon_encoder->encoder_id) {
1173 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1174 args.v3.acConfig.ucTransmitterSel = 0;
1176 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1177 args.v3.acConfig.ucTransmitterSel = 1;
1179 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1180 args.v3.acConfig.ucTransmitterSel = 2;
1185 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1186 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1187 if (dig->coherent_mode)
1188 args.v3.acConfig.fCoherentMode = 1;
1189 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1190 args.v3.acConfig.fDualLinkConnector = 1;
1194 args.v4.ucAction = action;
1195 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1196 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1197 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1198 args.v4.asMode.ucLaneSel = lane_num;
1199 args.v4.asMode.ucLaneSet = lane_set;
1202 args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
1203 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1204 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1206 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1210 args.v4.ucLaneNum = dp_lane_count;
1211 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1212 args.v4.ucLaneNum = 8;
1214 args.v4.ucLaneNum = 4;
1217 args.v4.acConfig.ucLinkSel = 1;
1218 if (dig_encoder & 1)
1219 args.v4.acConfig.ucEncoderSel = 1;
1221 /* Select the PLL for the PHY
1222 * DP PHY should be clocked from external src if there is
1225 /* On DCE5 DCPLL usually generates the DP ref clock */
1227 if (rdev->clock.dp_extclk)
1228 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1230 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1232 args.v4.acConfig.ucRefClkSource = pll_id;
1234 switch (radeon_encoder->encoder_id) {
1235 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1236 args.v4.acConfig.ucTransmitterSel = 0;
1238 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1239 args.v4.acConfig.ucTransmitterSel = 1;
1241 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1242 args.v4.acConfig.ucTransmitterSel = 2;
1247 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1248 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1249 if (dig->coherent_mode)
1250 args.v4.acConfig.fCoherentMode = 1;
1251 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1252 args.v4.acConfig.fDualLinkConnector = 1;
1256 args.v5.ucAction = action;
1258 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1260 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1262 switch (radeon_encoder->encoder_id) {
1263 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1265 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1267 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1269 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1271 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1273 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1275 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1277 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1279 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1283 args.v5.ucLaneNum = dp_lane_count;
1284 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1285 args.v5.ucLaneNum = 8;
1287 args.v5.ucLaneNum = 4;
1288 args.v5.ucConnObjId = connector_object_id;
1289 args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1291 if (is_dp && rdev->clock.dp_extclk)
1292 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1294 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1297 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1298 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1299 if (dig->coherent_mode)
1300 args.v5.asConfig.ucCoherentMode = 1;
1302 if (hpd_id == RADEON_HPD_NONE)
1303 args.v5.asConfig.ucHPDSel = 0;
1305 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1306 args.v5.ucDigEncoderSel = 1 << dig_encoder;
1307 args.v5.ucDPLaneSet = lane_set;
1310 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1315 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1319 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1323 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1325 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1326 struct drm_device *dev = radeon_connector->base.dev;
1327 struct radeon_device *rdev = dev->dev_private;
1328 union dig_transmitter_control args;
1329 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1332 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1335 if (!ASIC_IS_DCE4(rdev))
1338 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1339 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1342 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1345 memset(&args, 0, sizeof(args));
1347 args.v1.ucAction = action;
1349 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1351 /* wait for the panel to power up */
1352 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1355 for (i = 0; i < 300; i++) {
1356 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1366 union external_encoder_control {
1367 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1368 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1372 atombios_external_encoder_setup(struct drm_encoder *encoder,
1373 struct drm_encoder *ext_encoder,
1376 struct drm_device *dev = encoder->dev;
1377 struct radeon_device *rdev = dev->dev_private;
1378 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1379 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1380 union external_encoder_control args;
1381 struct drm_connector *connector;
1382 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1385 int dp_lane_count = 0;
1386 int connector_object_id = 0;
1387 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1389 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1390 connector = radeon_get_connector_for_encoder_init(encoder);
1392 connector = radeon_get_connector_for_encoder(encoder);
1395 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1396 struct radeon_connector_atom_dig *dig_connector =
1397 radeon_connector->con_priv;
1399 dp_clock = dig_connector->dp_clock;
1400 dp_lane_count = dig_connector->dp_lane_count;
1401 connector_object_id =
1402 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1405 memset(&args, 0, sizeof(args));
1407 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1412 /* no params on frev 1 */
1418 args.v1.sDigEncoder.ucAction = action;
1419 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1420 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1422 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1423 if (dp_clock == 270000)
1424 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1425 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1426 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1427 args.v1.sDigEncoder.ucLaneNum = 8;
1429 args.v1.sDigEncoder.ucLaneNum = 4;
1432 args.v3.sExtEncoder.ucAction = action;
1433 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1434 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1436 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1437 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1439 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1440 if (dp_clock == 270000)
1441 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1442 else if (dp_clock == 540000)
1443 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1444 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1445 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1446 args.v3.sExtEncoder.ucLaneNum = 8;
1448 args.v3.sExtEncoder.ucLaneNum = 4;
1450 case GRAPH_OBJECT_ENUM_ID1:
1451 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1453 case GRAPH_OBJECT_ENUM_ID2:
1454 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1456 case GRAPH_OBJECT_ENUM_ID3:
1457 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1460 args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
1463 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1468 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1471 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1475 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1477 struct drm_device *dev = encoder->dev;
1478 struct radeon_device *rdev = dev->dev_private;
1479 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1480 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1481 ENABLE_YUV_PS_ALLOCATION args;
1482 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1485 memset(&args, 0, sizeof(args));
1487 if (rdev->family >= CHIP_R600)
1488 reg = R600_BIOS_3_SCRATCH;
1490 reg = RADEON_BIOS_3_SCRATCH;
1492 /* XXX: fix up scratch reg handling */
1494 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1495 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1496 (radeon_crtc->crtc_id << 18)));
1497 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1498 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1503 args.ucEnable = ATOM_ENABLE;
1504 args.ucCRTC = radeon_crtc->crtc_id;
1506 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1512 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1514 struct drm_device *dev = encoder->dev;
1515 struct radeon_device *rdev = dev->dev_private;
1516 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1517 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1520 memset(&args, 0, sizeof(args));
1522 switch (radeon_encoder->encoder_id) {
1523 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1524 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1525 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1527 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1528 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1529 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1530 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1532 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1533 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1535 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1536 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1537 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1539 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1541 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1542 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1543 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1544 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1545 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1546 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1548 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1550 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1551 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1552 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1553 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1554 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1555 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1557 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1564 case DRM_MODE_DPMS_ON:
1565 args.ucAction = ATOM_ENABLE;
1566 /* workaround for DVOOutputControl on some RS690 systems */
1567 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1568 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1569 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1570 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1571 WREG32(RADEON_BIOS_3_SCRATCH, reg);
1573 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1574 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1575 args.ucAction = ATOM_LCD_BLON;
1576 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1579 case DRM_MODE_DPMS_STANDBY:
1580 case DRM_MODE_DPMS_SUSPEND:
1581 case DRM_MODE_DPMS_OFF:
1582 args.ucAction = ATOM_DISABLE;
1583 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1584 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1585 args.ucAction = ATOM_LCD_BLOFF;
1586 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1593 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1595 struct drm_device *dev = encoder->dev;
1596 struct radeon_device *rdev = dev->dev_private;
1597 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1598 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1599 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1600 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1601 struct radeon_connector *radeon_connector = NULL;
1602 struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1605 radeon_connector = to_radeon_connector(connector);
1606 radeon_dig_connector = radeon_connector->con_priv;
1610 case DRM_MODE_DPMS_ON:
1611 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1613 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1615 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1617 /* setup and enable the encoder */
1618 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1619 atombios_dig_encoder_setup(encoder,
1620 ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1623 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1624 atombios_external_encoder_setup(encoder, ext_encoder,
1625 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1627 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1628 } else if (ASIC_IS_DCE4(rdev)) {
1629 /* setup and enable the encoder */
1630 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1631 /* enable the transmitter */
1632 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1633 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1635 /* setup and enable the encoder and transmitter */
1636 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1637 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1638 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1639 /* some dce3.x boards have a bug in their transmitter control table.
1640 * ACTION_ENABLE_OUTPUT can probably be dropped since ACTION_ENABLE
1641 * does the same thing and more.
1643 if ((rdev->family != CHIP_RV710) && (rdev->family != CHIP_RV730) &&
1644 (rdev->family != CHIP_RS780) && (rdev->family != CHIP_RS880))
1645 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1647 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1648 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1649 atombios_set_edp_panel_power(connector,
1650 ATOM_TRANSMITTER_ACTION_POWER_ON);
1651 radeon_dig_connector->edp_on = true;
1653 radeon_dp_link_train(encoder, connector);
1654 if (ASIC_IS_DCE4(rdev))
1655 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1657 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1658 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1660 case DRM_MODE_DPMS_STANDBY:
1661 case DRM_MODE_DPMS_SUSPEND:
1662 case DRM_MODE_DPMS_OFF:
1663 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1664 /* disable the transmitter */
1665 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1666 } else if (ASIC_IS_DCE4(rdev)) {
1667 /* disable the transmitter */
1668 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1669 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1671 /* disable the encoder and transmitter */
1672 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1673 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1674 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1676 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1677 if (ASIC_IS_DCE4(rdev))
1678 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1679 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1680 atombios_set_edp_panel_power(connector,
1681 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1682 radeon_dig_connector->edp_on = false;
1685 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1686 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1692 radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
1693 struct drm_encoder *ext_encoder,
1696 struct drm_device *dev = encoder->dev;
1697 struct radeon_device *rdev = dev->dev_private;
1700 case DRM_MODE_DPMS_ON:
1702 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
1703 atombios_external_encoder_setup(encoder, ext_encoder,
1704 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1705 atombios_external_encoder_setup(encoder, ext_encoder,
1706 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1708 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1710 case DRM_MODE_DPMS_STANDBY:
1711 case DRM_MODE_DPMS_SUSPEND:
1712 case DRM_MODE_DPMS_OFF:
1713 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
1714 atombios_external_encoder_setup(encoder, ext_encoder,
1715 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1716 atombios_external_encoder_setup(encoder, ext_encoder,
1717 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1719 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1725 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1727 struct drm_device *dev = encoder->dev;
1728 struct radeon_device *rdev = dev->dev_private;
1729 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1730 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1732 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1733 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1734 radeon_encoder->active_device);
1735 switch (radeon_encoder->encoder_id) {
1736 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1737 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1738 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1739 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1740 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1741 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1742 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1743 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1744 radeon_atom_encoder_dpms_avivo(encoder, mode);
1746 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1747 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1748 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1749 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1750 radeon_atom_encoder_dpms_dig(encoder, mode);
1752 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1753 if (ASIC_IS_DCE5(rdev)) {
1755 case DRM_MODE_DPMS_ON:
1756 atombios_dvo_setup(encoder, ATOM_ENABLE);
1758 case DRM_MODE_DPMS_STANDBY:
1759 case DRM_MODE_DPMS_SUSPEND:
1760 case DRM_MODE_DPMS_OFF:
1761 atombios_dvo_setup(encoder, ATOM_DISABLE);
1764 } else if (ASIC_IS_DCE3(rdev))
1765 radeon_atom_encoder_dpms_dig(encoder, mode);
1767 radeon_atom_encoder_dpms_avivo(encoder, mode);
1769 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1770 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1771 if (ASIC_IS_DCE5(rdev)) {
1773 case DRM_MODE_DPMS_ON:
1774 atombios_dac_setup(encoder, ATOM_ENABLE);
1776 case DRM_MODE_DPMS_STANDBY:
1777 case DRM_MODE_DPMS_SUSPEND:
1778 case DRM_MODE_DPMS_OFF:
1779 atombios_dac_setup(encoder, ATOM_DISABLE);
1783 radeon_atom_encoder_dpms_avivo(encoder, mode);
1790 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);
1792 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1796 union crtc_source_param {
1797 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1798 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1802 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1804 struct drm_device *dev = encoder->dev;
1805 struct radeon_device *rdev = dev->dev_private;
1806 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1807 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1808 union crtc_source_param args;
1809 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1811 struct radeon_encoder_atom_dig *dig;
1813 memset(&args, 0, sizeof(args));
1815 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1823 if (ASIC_IS_AVIVO(rdev))
1824 args.v1.ucCRTC = radeon_crtc->crtc_id;
1826 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1827 args.v1.ucCRTC = radeon_crtc->crtc_id;
1829 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1832 switch (radeon_encoder->encoder_id) {
1833 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1834 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1835 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1837 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1838 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1839 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1840 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1842 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1844 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1845 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1846 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1847 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1849 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1850 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1851 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1852 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1853 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1854 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1856 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1858 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1859 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1860 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1861 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1862 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1863 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1865 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1870 args.v2.ucCRTC = radeon_crtc->crtc_id;
1871 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1872 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1874 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1875 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1876 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1877 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1879 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1881 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1882 switch (radeon_encoder->encoder_id) {
1883 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1884 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1885 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1886 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1887 dig = radeon_encoder->enc_priv;
1888 switch (dig->dig_encoder) {
1890 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1893 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1896 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1899 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1902 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1905 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1909 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1910 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1912 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1913 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1914 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1915 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1916 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1918 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1920 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1921 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1922 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1923 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1924 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1926 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1933 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1937 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1939 /* update scratch regs with new routing */
1940 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1944 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1945 struct drm_display_mode *mode)
1947 struct drm_device *dev = encoder->dev;
1948 struct radeon_device *rdev = dev->dev_private;
1949 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1950 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1952 /* Funky macbooks */
1953 if ((dev->pdev->device == 0x71C5) &&
1954 (dev->pdev->subsystem_vendor == 0x106b) &&
1955 (dev->pdev->subsystem_device == 0x0080)) {
1956 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1957 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1959 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1960 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1962 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1966 /* set scaler clears this on some chips */
1967 if (ASIC_IS_AVIVO(rdev) &&
1968 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1969 if (ASIC_IS_DCE4(rdev)) {
1970 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1971 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1972 EVERGREEN_INTERLEAVE_EN);
1974 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1976 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1977 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1978 AVIVO_D1MODE_INTERLEAVE_EN);
1980 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1985 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1987 struct drm_device *dev = encoder->dev;
1988 struct radeon_device *rdev = dev->dev_private;
1989 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1990 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1991 struct drm_encoder *test_encoder;
1992 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1993 uint32_t dig_enc_in_use = 0;
1995 if (ASIC_IS_DCE6(rdev)) {
1997 switch (radeon_encoder->encoder_id) {
1998 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2004 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2010 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2017 } else if (ASIC_IS_DCE4(rdev)) {
2019 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
2020 /* ontario follows DCE4 */
2021 if (rdev->family == CHIP_PALM) {
2027 /* llano follows DCE3.2 */
2028 return radeon_crtc->crtc_id;
2030 switch (radeon_encoder->encoder_id) {
2031 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2037 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2043 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2053 /* on DCE32 and encoder can driver any block so just crtc id */
2054 if (ASIC_IS_DCE32(rdev)) {
2055 return radeon_crtc->crtc_id;
2058 /* on DCE3 - LVTMA can only be driven by DIGB */
2059 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2060 struct radeon_encoder *radeon_test_encoder;
2062 if (encoder == test_encoder)
2065 if (!radeon_encoder_is_digital(test_encoder))
2068 radeon_test_encoder = to_radeon_encoder(test_encoder);
2069 dig = radeon_test_encoder->enc_priv;
2071 if (dig->dig_encoder >= 0)
2072 dig_enc_in_use |= (1 << dig->dig_encoder);
2075 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2076 if (dig_enc_in_use & 0x2)
2077 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2080 if (!(dig_enc_in_use & 1))
2085 /* This only needs to be called once at startup */
2087 radeon_atom_encoder_init(struct radeon_device *rdev)
2089 struct drm_device *dev = rdev->ddev;
2090 struct drm_encoder *encoder;
2092 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2093 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2094 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2096 switch (radeon_encoder->encoder_id) {
2097 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2098 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2099 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2100 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2101 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2107 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
2108 atombios_external_encoder_setup(encoder, ext_encoder,
2109 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2114 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2115 struct drm_display_mode *mode,
2116 struct drm_display_mode *adjusted_mode)
2118 struct drm_device *dev = encoder->dev;
2119 struct radeon_device *rdev = dev->dev_private;
2120 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2122 radeon_encoder->pixel_clock = adjusted_mode->clock;
2124 /* need to call this here rather than in prepare() since we need some crtc info */
2125 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2127 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2128 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2129 atombios_yuv_setup(encoder, true);
2131 atombios_yuv_setup(encoder, false);
2134 switch (radeon_encoder->encoder_id) {
2135 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2136 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2137 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2138 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2139 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2141 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2142 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2143 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2144 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2145 /* handled in dpms */
2147 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2148 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2149 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2150 atombios_dvo_setup(encoder, ATOM_ENABLE);
2152 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2153 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2154 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2155 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2156 atombios_dac_setup(encoder, ATOM_ENABLE);
2157 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2158 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2159 atombios_tv_setup(encoder, ATOM_ENABLE);
2161 atombios_tv_setup(encoder, ATOM_DISABLE);
2166 atombios_apply_encoder_quirks(encoder, adjusted_mode);
2168 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2169 if (rdev->asic->display.hdmi_enable)
2170 radeon_hdmi_enable(rdev, encoder, true);
2171 if (rdev->asic->display.hdmi_setmode)
2172 radeon_hdmi_setmode(rdev, encoder, adjusted_mode);
2177 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2179 struct drm_device *dev = encoder->dev;
2180 struct radeon_device *rdev = dev->dev_private;
2181 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2182 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2184 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2185 ATOM_DEVICE_CV_SUPPORT |
2186 ATOM_DEVICE_CRT_SUPPORT)) {
2187 DAC_LOAD_DETECTION_PS_ALLOCATION args;
2188 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2191 memset(&args, 0, sizeof(args));
2193 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2196 args.sDacload.ucMisc = 0;
2198 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2199 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2200 args.sDacload.ucDacType = ATOM_DAC_A;
2202 args.sDacload.ucDacType = ATOM_DAC_B;
2204 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2205 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2206 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2207 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2208 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2209 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2211 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2212 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2213 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2215 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2218 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2225 static enum drm_connector_status
2226 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2228 struct drm_device *dev = encoder->dev;
2229 struct radeon_device *rdev = dev->dev_private;
2230 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2231 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2232 uint32_t bios_0_scratch;
2234 if (!atombios_dac_load_detect(encoder, connector)) {
2235 DRM_DEBUG_KMS("detect returned false \n");
2236 return connector_status_unknown;
2239 if (rdev->family >= CHIP_R600)
2240 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2242 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2244 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2245 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2246 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2247 return connector_status_connected;
2249 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2250 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2251 return connector_status_connected;
2253 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2254 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2255 return connector_status_connected;
2257 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2258 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2259 return connector_status_connected; /* CTV */
2260 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2261 return connector_status_connected; /* STV */
2263 return connector_status_disconnected;
2266 static enum drm_connector_status
2267 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2269 struct drm_device *dev = encoder->dev;
2270 struct radeon_device *rdev = dev->dev_private;
2271 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2272 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2273 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2276 if (!ASIC_IS_DCE4(rdev))
2277 return connector_status_unknown;
2280 return connector_status_unknown;
2282 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2283 return connector_status_unknown;
2285 /* load detect on the dp bridge */
2286 atombios_external_encoder_setup(encoder, ext_encoder,
2287 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2289 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2291 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2292 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2293 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2294 return connector_status_connected;
2296 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2297 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2298 return connector_status_connected;
2300 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2301 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2302 return connector_status_connected;
2304 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2305 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2306 return connector_status_connected; /* CTV */
2307 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2308 return connector_status_connected; /* STV */
2310 return connector_status_disconnected;
2314 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2316 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2319 /* ddc_setup on the dp bridge */
2320 atombios_external_encoder_setup(encoder, ext_encoder,
2321 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2325 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2327 struct radeon_device *rdev = encoder->dev->dev_private;
2328 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2329 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2331 if ((radeon_encoder->active_device &
2332 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2333 (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2334 ENCODER_OBJECT_ID_NONE)) {
2335 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2337 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
2338 if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2339 if (rdev->family >= CHIP_R600)
2340 dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2342 /* RS600/690/740 have only 1 afmt block */
2343 dig->afmt = rdev->mode_info.afmt[0];
2348 radeon_atom_output_lock(encoder, true);
2351 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2353 /* select the clock/data port if it uses a router */
2354 if (radeon_connector->router.cd_valid)
2355 radeon_router_select_cd_port(radeon_connector);
2357 /* turn eDP panel on for mode set */
2358 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2359 atombios_set_edp_panel_power(connector,
2360 ATOM_TRANSMITTER_ACTION_POWER_ON);
2363 /* this is needed for the pll/ss setup to work correctly in some cases */
2364 atombios_set_encoder_crtc_source(encoder);
2367 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2369 /* need to call this here as we need the crtc set up */
2370 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2371 radeon_atom_output_lock(encoder, false);
2374 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2376 struct drm_device *dev = encoder->dev;
2377 struct radeon_device *rdev = dev->dev_private;
2378 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2379 struct radeon_encoder_atom_dig *dig;
2381 /* check for pre-DCE3 cards with shared encoders;
2382 * can't really use the links individually, so don't disable
2383 * the encoder if it's in use by another connector
2385 if (!ASIC_IS_DCE3(rdev)) {
2386 struct drm_encoder *other_encoder;
2387 struct radeon_encoder *other_radeon_encoder;
2389 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2390 other_radeon_encoder = to_radeon_encoder(other_encoder);
2391 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2392 drm_helper_encoder_in_use(other_encoder))
2397 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2399 switch (radeon_encoder->encoder_id) {
2400 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2401 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2402 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2403 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2404 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2406 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2407 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2408 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2409 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2410 /* handled in dpms */
2412 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2413 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2414 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2415 atombios_dvo_setup(encoder, ATOM_DISABLE);
2417 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2418 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2419 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2420 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2421 atombios_dac_setup(encoder, ATOM_DISABLE);
2422 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2423 atombios_tv_setup(encoder, ATOM_DISABLE);
2428 if (radeon_encoder_is_digital(encoder)) {
2429 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2430 if (rdev->asic->display.hdmi_enable)
2431 radeon_hdmi_enable(rdev, encoder, false);
2433 dig = radeon_encoder->enc_priv;
2434 dig->dig_encoder = -1;
2436 radeon_encoder->active_device = 0;
2439 /* these are handled by the primary encoders */
2440 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2445 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2451 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2452 struct drm_display_mode *mode,
2453 struct drm_display_mode *adjusted_mode)
2458 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2464 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2469 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2470 const struct drm_display_mode *mode,
2471 struct drm_display_mode *adjusted_mode)
2476 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2477 .dpms = radeon_atom_ext_dpms,
2478 .mode_fixup = radeon_atom_ext_mode_fixup,
2479 .prepare = radeon_atom_ext_prepare,
2480 .mode_set = radeon_atom_ext_mode_set,
2481 .commit = radeon_atom_ext_commit,
2482 .disable = radeon_atom_ext_disable,
2483 /* no detect for TMDS/LVDS yet */
2486 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2487 .dpms = radeon_atom_encoder_dpms,
2488 .mode_fixup = radeon_atom_mode_fixup,
2489 .prepare = radeon_atom_encoder_prepare,
2490 .mode_set = radeon_atom_encoder_mode_set,
2491 .commit = radeon_atom_encoder_commit,
2492 .disable = radeon_atom_encoder_disable,
2493 .detect = radeon_atom_dig_detect,
2496 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2497 .dpms = radeon_atom_encoder_dpms,
2498 .mode_fixup = radeon_atom_mode_fixup,
2499 .prepare = radeon_atom_encoder_prepare,
2500 .mode_set = radeon_atom_encoder_mode_set,
2501 .commit = radeon_atom_encoder_commit,
2502 .detect = radeon_atom_dac_detect,
2505 void radeon_enc_destroy(struct drm_encoder *encoder)
2507 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2508 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2509 radeon_atom_backlight_exit(radeon_encoder);
2510 kfree(radeon_encoder->enc_priv);
2511 drm_encoder_cleanup(encoder);
2512 kfree(radeon_encoder);
2515 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2516 .destroy = radeon_enc_destroy,
2519 static struct radeon_encoder_atom_dac *
2520 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2522 struct drm_device *dev = radeon_encoder->base.dev;
2523 struct radeon_device *rdev = dev->dev_private;
2524 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2529 dac->tv_std = radeon_atombios_get_tv_info(rdev);
2533 static struct radeon_encoder_atom_dig *
2534 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2536 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2537 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2542 /* coherent mode by default */
2543 dig->coherent_mode = true;
2544 dig->dig_encoder = -1;
2546 if (encoder_enum == 2)
2555 radeon_add_atom_encoder(struct drm_device *dev,
2556 uint32_t encoder_enum,
2557 uint32_t supported_device,
2560 struct radeon_device *rdev = dev->dev_private;
2561 struct drm_encoder *encoder;
2562 struct radeon_encoder *radeon_encoder;
2564 /* see if we already added it */
2565 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2566 radeon_encoder = to_radeon_encoder(encoder);
2567 if (radeon_encoder->encoder_enum == encoder_enum) {
2568 radeon_encoder->devices |= supported_device;
2575 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2576 if (!radeon_encoder)
2579 encoder = &radeon_encoder->base;
2580 switch (rdev->num_crtc) {
2582 encoder->possible_crtcs = 0x1;
2586 encoder->possible_crtcs = 0x3;
2589 encoder->possible_crtcs = 0xf;
2592 encoder->possible_crtcs = 0x3f;
2596 radeon_encoder->enc_priv = NULL;
2598 radeon_encoder->encoder_enum = encoder_enum;
2599 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2600 radeon_encoder->devices = supported_device;
2601 radeon_encoder->rmx_type = RMX_OFF;
2602 radeon_encoder->underscan_type = UNDERSCAN_OFF;
2603 radeon_encoder->is_ext_encoder = false;
2604 radeon_encoder->caps = caps;
2606 switch (radeon_encoder->encoder_id) {
2607 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2608 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2609 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2610 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2611 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2612 radeon_encoder->rmx_type = RMX_FULL;
2613 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2614 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2616 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2617 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2619 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2621 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2622 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2623 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2624 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2626 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2627 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2628 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2629 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2630 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2631 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2633 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2634 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2635 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2636 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2637 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2638 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2639 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2640 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2641 radeon_encoder->rmx_type = RMX_FULL;
2642 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2643 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2644 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2645 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2646 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2648 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2649 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2651 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2653 case ENCODER_OBJECT_ID_SI170B:
2654 case ENCODER_OBJECT_ID_CH7303:
2655 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2656 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2657 case ENCODER_OBJECT_ID_TITFP513:
2658 case ENCODER_OBJECT_ID_VT1623:
2659 case ENCODER_OBJECT_ID_HDMI_SI1930:
2660 case ENCODER_OBJECT_ID_TRAVIS:
2661 case ENCODER_OBJECT_ID_NUTMEG:
2662 /* these are handled by the primary encoders */
2663 radeon_encoder->is_ext_encoder = true;
2664 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2665 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2666 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2667 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2669 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2670 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);