2 * Copyright 2007-11 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
31 #include <linux/backlight.h>
33 extern int atom_debug;
36 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
41 if (rdev->family >= CHIP_R600)
42 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
44 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
46 backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
47 ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
49 return backlight_level;
53 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
58 if (rdev->family >= CHIP_R600)
59 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
61 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
63 bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
64 bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
65 ATOM_S2_CURRENT_BL_LEVEL_MASK);
67 if (rdev->family >= CHIP_R600)
68 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
70 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
74 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
76 struct drm_device *dev = radeon_encoder->base.dev;
77 struct radeon_device *rdev = dev->dev_private;
79 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
82 return radeon_atom_get_backlight_level_from_reg(rdev);
86 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
88 struct drm_encoder *encoder = &radeon_encoder->base;
89 struct drm_device *dev = radeon_encoder->base.dev;
90 struct radeon_device *rdev = dev->dev_private;
91 struct radeon_encoder_atom_dig *dig;
92 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
95 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
98 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
99 radeon_encoder->enc_priv) {
100 dig = radeon_encoder->enc_priv;
101 dig->backlight_level = level;
102 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
104 switch (radeon_encoder->encoder_id) {
105 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
106 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
107 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
108 if (dig->backlight_level == 0) {
109 args.ucAction = ATOM_LCD_BLOFF;
110 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
112 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
113 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
114 args.ucAction = ATOM_LCD_BLON;
115 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
118 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
119 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
120 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
121 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
122 if (dig->backlight_level == 0)
123 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
125 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
126 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
135 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
137 static u8 radeon_atom_bl_level(struct backlight_device *bd)
141 /* Convert brightness to hardware level */
142 if (bd->props.brightness < 0)
144 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
145 level = RADEON_MAX_BL_LEVEL;
147 level = bd->props.brightness;
152 static int radeon_atom_backlight_update_status(struct backlight_device *bd)
154 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
155 struct radeon_encoder *radeon_encoder = pdata->encoder;
157 atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
162 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
164 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
165 struct radeon_encoder *radeon_encoder = pdata->encoder;
166 struct drm_device *dev = radeon_encoder->base.dev;
167 struct radeon_device *rdev = dev->dev_private;
169 return radeon_atom_get_backlight_level_from_reg(rdev);
172 static const struct backlight_ops radeon_atom_backlight_ops = {
173 .get_brightness = radeon_atom_backlight_get_brightness,
174 .update_status = radeon_atom_backlight_update_status,
177 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
178 struct drm_connector *drm_connector)
180 struct drm_device *dev = radeon_encoder->base.dev;
181 struct radeon_device *rdev = dev->dev_private;
182 struct backlight_device *bd;
183 struct backlight_properties props;
184 struct radeon_backlight_privdata *pdata;
185 struct radeon_encoder_atom_dig *dig;
189 /* Mac laptops with multiple GPUs use the gmux driver for backlight
190 * so don't register a backlight device
192 if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
193 (rdev->pdev->device == 0x6741))
196 if (!radeon_encoder->enc_priv)
199 if (!rdev->is_atom_bios)
202 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
205 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
207 DRM_ERROR("Memory allocation failed\n");
211 memset(&props, 0, sizeof(props));
212 props.max_brightness = RADEON_MAX_BL_LEVEL;
213 props.type = BACKLIGHT_RAW;
214 snprintf(bl_name, sizeof(bl_name),
215 "radeon_bl%d", dev->primary->index);
216 bd = backlight_device_register(bl_name, drm_connector->kdev,
217 pdata, &radeon_atom_backlight_ops, &props);
219 DRM_ERROR("Backlight registration failed\n");
223 pdata->encoder = radeon_encoder;
225 backlight_level = radeon_atom_get_backlight_level_from_reg(rdev);
227 dig = radeon_encoder->enc_priv;
230 bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
231 bd->props.power = FB_BLANK_UNBLANK;
232 backlight_update_status(bd);
234 DRM_INFO("radeon atom DIG backlight initialized\n");
243 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
245 struct drm_device *dev = radeon_encoder->base.dev;
246 struct radeon_device *rdev = dev->dev_private;
247 struct backlight_device *bd = NULL;
248 struct radeon_encoder_atom_dig *dig;
250 if (!radeon_encoder->enc_priv)
253 if (!rdev->is_atom_bios)
256 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
259 dig = radeon_encoder->enc_priv;
264 struct radeon_legacy_backlight_privdata *pdata;
266 pdata = bl_get_data(bd);
267 backlight_device_unregister(bd);
270 DRM_INFO("radeon atom LVDS backlight unloaded\n");
274 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
276 void radeon_atom_backlight_init(struct radeon_encoder *encoder)
280 static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
286 /* evil but including atombios.h is much worse */
287 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
288 struct drm_display_mode *mode);
291 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
293 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
294 switch (radeon_encoder->encoder_id) {
295 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
296 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
297 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
298 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
299 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
300 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
301 case ENCODER_OBJECT_ID_INTERNAL_DDI:
302 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
303 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
304 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
305 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
306 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
313 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
314 const struct drm_display_mode *mode,
315 struct drm_display_mode *adjusted_mode)
317 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
318 struct drm_device *dev = encoder->dev;
319 struct radeon_device *rdev = dev->dev_private;
321 /* set the active encoder to connector routing */
322 radeon_encoder_set_active_device(encoder);
323 drm_mode_set_crtcinfo(adjusted_mode, 0);
326 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
327 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
328 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
330 /* get the native mode for LVDS */
331 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
332 radeon_panel_mode_fixup(encoder, adjusted_mode);
334 /* get the native mode for TV */
335 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
336 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
338 if (tv_dac->tv_std == TV_STD_NTSC ||
339 tv_dac->tv_std == TV_STD_NTSC_J ||
340 tv_dac->tv_std == TV_STD_PAL_M)
341 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
343 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
347 if (ASIC_IS_DCE3(rdev) &&
348 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
349 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
350 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
351 radeon_dp_set_link_config(connector, adjusted_mode);
358 atombios_dac_setup(struct drm_encoder *encoder, int action)
360 struct drm_device *dev = encoder->dev;
361 struct radeon_device *rdev = dev->dev_private;
362 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
363 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
365 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
367 memset(&args, 0, sizeof(args));
369 switch (radeon_encoder->encoder_id) {
370 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
371 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
372 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
374 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
375 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
376 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
380 args.ucAction = action;
382 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
383 args.ucDacStandard = ATOM_DAC1_PS2;
384 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
385 args.ucDacStandard = ATOM_DAC1_CV;
387 switch (dac_info->tv_std) {
390 case TV_STD_SCART_PAL:
393 args.ucDacStandard = ATOM_DAC1_PAL;
399 args.ucDacStandard = ATOM_DAC1_NTSC;
403 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
405 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
410 atombios_tv_setup(struct drm_encoder *encoder, int action)
412 struct drm_device *dev = encoder->dev;
413 struct radeon_device *rdev = dev->dev_private;
414 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
415 TV_ENCODER_CONTROL_PS_ALLOCATION args;
417 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
419 memset(&args, 0, sizeof(args));
421 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
423 args.sTVEncoder.ucAction = action;
425 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
426 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
428 switch (dac_info->tv_std) {
430 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
433 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
436 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
439 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
442 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
444 case TV_STD_SCART_PAL:
445 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
448 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
451 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
454 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
459 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
461 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
465 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
467 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
471 bpc = radeon_get_monitor_bpc(connector);
475 return PANEL_BPC_UNDEFINE;
477 return PANEL_6BIT_PER_COLOR;
480 return PANEL_8BIT_PER_COLOR;
482 return PANEL_10BIT_PER_COLOR;
484 return PANEL_12BIT_PER_COLOR;
486 return PANEL_16BIT_PER_COLOR;
490 union dvo_encoder_control {
491 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
492 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
493 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
494 DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4;
498 atombios_dvo_setup(struct drm_encoder *encoder, int action)
500 struct drm_device *dev = encoder->dev;
501 struct radeon_device *rdev = dev->dev_private;
502 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
503 union dvo_encoder_control args;
504 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
507 memset(&args, 0, sizeof(args));
509 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
512 /* some R4xx chips have the wrong frev */
513 if (rdev->family <= CHIP_RV410)
521 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
523 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
524 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
526 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
530 args.dvo.sDVOEncoder.ucAction = action;
531 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
532 /* DFP1, CRT1, TV1 depending on the type of port */
533 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
535 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
536 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
540 args.dvo_v3.ucAction = action;
541 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
542 args.dvo_v3.ucDVOConfig = 0; /* XXX */
546 args.dvo_v4.ucAction = action;
547 args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
548 args.dvo_v4.ucDVOConfig = 0; /* XXX */
549 args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
552 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
557 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
561 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
564 union lvds_encoder_control {
565 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
566 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
570 atombios_digital_setup(struct drm_encoder *encoder, int action)
572 struct drm_device *dev = encoder->dev;
573 struct radeon_device *rdev = dev->dev_private;
574 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
575 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
576 union lvds_encoder_control args;
578 int hdmi_detected = 0;
584 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
587 memset(&args, 0, sizeof(args));
589 switch (radeon_encoder->encoder_id) {
590 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
591 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
593 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
594 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
595 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
597 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
598 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
599 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
601 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
605 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
614 args.v1.ucAction = action;
616 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
617 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
618 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
619 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
620 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
621 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
622 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
625 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
626 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
627 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
628 /*if (pScrn->rgbBits == 8) */
629 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
635 args.v2.ucAction = action;
637 if (dig->coherent_mode)
638 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
641 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
642 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
643 args.v2.ucTruncate = 0;
644 args.v2.ucSpatial = 0;
645 args.v2.ucTemporal = 0;
647 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
648 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
649 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
650 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
651 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
652 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
653 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
655 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
656 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
657 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
658 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
659 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
660 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
664 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
665 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
666 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
670 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
675 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
679 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
683 atombios_get_encoder_mode(struct drm_encoder *encoder)
685 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
686 struct drm_connector *connector;
687 struct radeon_connector *radeon_connector;
688 struct radeon_connector_atom_dig *dig_connector;
690 /* dp bridges are always DP */
691 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
692 return ATOM_ENCODER_MODE_DP;
694 /* DVO is always DVO */
695 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
696 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
697 return ATOM_ENCODER_MODE_DVO;
699 connector = radeon_get_connector_for_encoder(encoder);
700 /* if we don't have an active device yet, just use one of
701 * the connectors tied to the encoder.
704 connector = radeon_get_connector_for_encoder_init(encoder);
705 radeon_connector = to_radeon_connector(connector);
707 switch (connector->connector_type) {
708 case DRM_MODE_CONNECTOR_DVII:
709 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
710 if (radeon_audio != 0) {
711 if (radeon_connector->use_digital &&
712 (radeon_connector->audio == RADEON_AUDIO_ENABLE))
713 return ATOM_ENCODER_MODE_HDMI;
714 else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
715 (radeon_connector->audio == RADEON_AUDIO_AUTO))
716 return ATOM_ENCODER_MODE_HDMI;
717 else if (radeon_connector->use_digital)
718 return ATOM_ENCODER_MODE_DVI;
720 return ATOM_ENCODER_MODE_CRT;
721 } else if (radeon_connector->use_digital) {
722 return ATOM_ENCODER_MODE_DVI;
724 return ATOM_ENCODER_MODE_CRT;
727 case DRM_MODE_CONNECTOR_DVID:
728 case DRM_MODE_CONNECTOR_HDMIA:
730 if (radeon_audio != 0) {
731 if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
732 return ATOM_ENCODER_MODE_HDMI;
733 else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
734 (radeon_connector->audio == RADEON_AUDIO_AUTO))
735 return ATOM_ENCODER_MODE_HDMI;
737 return ATOM_ENCODER_MODE_DVI;
739 return ATOM_ENCODER_MODE_DVI;
742 case DRM_MODE_CONNECTOR_LVDS:
743 return ATOM_ENCODER_MODE_LVDS;
745 case DRM_MODE_CONNECTOR_DisplayPort:
746 dig_connector = radeon_connector->con_priv;
747 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
748 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
749 return ATOM_ENCODER_MODE_DP;
750 } else if (radeon_audio != 0) {
751 if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
752 return ATOM_ENCODER_MODE_HDMI;
753 else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
754 (radeon_connector->audio == RADEON_AUDIO_AUTO))
755 return ATOM_ENCODER_MODE_HDMI;
757 return ATOM_ENCODER_MODE_DVI;
759 return ATOM_ENCODER_MODE_DVI;
762 case DRM_MODE_CONNECTOR_eDP:
763 return ATOM_ENCODER_MODE_DP;
764 case DRM_MODE_CONNECTOR_DVIA:
765 case DRM_MODE_CONNECTOR_VGA:
766 return ATOM_ENCODER_MODE_CRT;
768 case DRM_MODE_CONNECTOR_Composite:
769 case DRM_MODE_CONNECTOR_SVIDEO:
770 case DRM_MODE_CONNECTOR_9PinDIN:
772 return ATOM_ENCODER_MODE_TV;
773 /*return ATOM_ENCODER_MODE_CV;*/
779 * DIG Encoder/Transmitter Setup
782 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
783 * Supports up to 3 digital outputs
784 * - 2 DIG encoder blocks.
785 * DIG1 can drive UNIPHY link A or link B
786 * DIG2 can drive UNIPHY link B or LVTMA
789 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
790 * Supports up to 5 digital outputs
791 * - 2 DIG encoder blocks.
792 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
795 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
796 * Supports up to 6 digital outputs
797 * - 6 DIG encoder blocks.
798 * - DIG to PHY mapping is hardcoded
799 * DIG1 drives UNIPHY0 link A, A+B
800 * DIG2 drives UNIPHY0 link B
801 * DIG3 drives UNIPHY1 link A, A+B
802 * DIG4 drives UNIPHY1 link B
803 * DIG5 drives UNIPHY2 link A, A+B
804 * DIG6 drives UNIPHY2 link B
807 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
808 * Supports up to 6 digital outputs
809 * - 2 DIG encoder blocks.
811 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
813 * DIG1 drives UNIPHY0/1/2 link A
814 * DIG2 drives UNIPHY0/1/2 link B
817 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
819 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
820 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
821 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
822 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
825 union dig_encoder_control {
826 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
827 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
828 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
829 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
833 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
835 struct drm_device *dev = encoder->dev;
836 struct radeon_device *rdev = dev->dev_private;
837 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
838 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
839 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
840 union dig_encoder_control args;
844 int dp_lane_count = 0;
845 int hpd_id = RADEON_HPD_NONE;
848 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
849 struct radeon_connector_atom_dig *dig_connector =
850 radeon_connector->con_priv;
852 dp_clock = dig_connector->dp_clock;
853 dp_lane_count = dig_connector->dp_lane_count;
854 hpd_id = radeon_connector->hpd.hpd;
857 /* no dig encoder assigned */
858 if (dig->dig_encoder == -1)
861 memset(&args, 0, sizeof(args));
863 if (ASIC_IS_DCE4(rdev))
864 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
866 if (dig->dig_encoder)
867 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
869 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
872 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
879 args.v1.ucAction = action;
880 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
881 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
882 args.v3.ucPanelMode = panel_mode;
884 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
886 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
887 args.v1.ucLaneNum = dp_lane_count;
888 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
889 args.v1.ucLaneNum = 8;
891 args.v1.ucLaneNum = 4;
893 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
894 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
895 switch (radeon_encoder->encoder_id) {
896 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
897 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
899 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
900 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
901 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
903 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
904 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
908 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
910 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
914 args.v3.ucAction = action;
915 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
916 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
917 args.v3.ucPanelMode = panel_mode;
919 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
921 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
922 args.v3.ucLaneNum = dp_lane_count;
923 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
924 args.v3.ucLaneNum = 8;
926 args.v3.ucLaneNum = 4;
928 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
929 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
930 args.v3.acConfig.ucDigSel = dig->dig_encoder;
931 args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
934 args.v4.ucAction = action;
935 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
936 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
937 args.v4.ucPanelMode = panel_mode;
939 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
941 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
942 args.v4.ucLaneNum = dp_lane_count;
943 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
944 args.v4.ucLaneNum = 8;
946 args.v4.ucLaneNum = 4;
948 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
949 if (dp_clock == 540000)
950 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
951 else if (dp_clock == 324000)
952 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;
953 else if (dp_clock == 270000)
954 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
956 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
958 args.v4.acConfig.ucDigSel = dig->dig_encoder;
959 args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
960 if (hpd_id == RADEON_HPD_NONE)
961 args.v4.ucHPD_ID = 0;
963 args.v4.ucHPD_ID = hpd_id + 1;
966 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
971 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
975 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
979 union dig_transmitter_control {
980 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
981 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
982 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
983 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
984 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
988 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
990 struct drm_device *dev = encoder->dev;
991 struct radeon_device *rdev = dev->dev_private;
992 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
993 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
994 struct drm_connector *connector;
995 union dig_transmitter_control args;
1001 int dp_lane_count = 0;
1002 int connector_object_id = 0;
1003 int igp_lane_info = 0;
1004 int dig_encoder = dig->dig_encoder;
1005 int hpd_id = RADEON_HPD_NONE;
1007 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1008 connector = radeon_get_connector_for_encoder_init(encoder);
1009 /* just needed to avoid bailing in the encoder check. the encoder
1010 * isn't used for init
1014 connector = radeon_get_connector_for_encoder(encoder);
1017 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1018 struct radeon_connector_atom_dig *dig_connector =
1019 radeon_connector->con_priv;
1021 hpd_id = radeon_connector->hpd.hpd;
1022 dp_clock = dig_connector->dp_clock;
1023 dp_lane_count = dig_connector->dp_lane_count;
1024 connector_object_id =
1025 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1026 igp_lane_info = dig_connector->igp_lane_info;
1029 if (encoder->crtc) {
1030 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1031 pll_id = radeon_crtc->pll_id;
1034 /* no dig encoder assigned */
1035 if (dig_encoder == -1)
1038 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
1041 memset(&args, 0, sizeof(args));
1043 switch (radeon_encoder->encoder_id) {
1044 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1045 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1047 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1048 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1049 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1050 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1051 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1053 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1054 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1058 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1065 args.v1.ucAction = action;
1066 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1067 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1068 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1069 args.v1.asMode.ucLaneSel = lane_num;
1070 args.v1.asMode.ucLaneSet = lane_set;
1073 args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
1074 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1075 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1077 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1080 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1083 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1085 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1087 if ((rdev->flags & RADEON_IS_IGP) &&
1088 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1090 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
1091 if (igp_lane_info & 0x1)
1092 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1093 else if (igp_lane_info & 0x2)
1094 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1095 else if (igp_lane_info & 0x4)
1096 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1097 else if (igp_lane_info & 0x8)
1098 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1100 if (igp_lane_info & 0x3)
1101 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1102 else if (igp_lane_info & 0xc)
1103 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1108 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1110 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1113 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1114 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1115 if (dig->coherent_mode)
1116 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1117 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1118 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1122 args.v2.ucAction = action;
1123 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1124 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1125 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1126 args.v2.asMode.ucLaneSel = lane_num;
1127 args.v2.asMode.ucLaneSet = lane_set;
1130 args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
1131 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1132 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1134 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1137 args.v2.acConfig.ucEncoderSel = dig_encoder;
1139 args.v2.acConfig.ucLinkSel = 1;
1141 switch (radeon_encoder->encoder_id) {
1142 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1143 args.v2.acConfig.ucTransmitterSel = 0;
1145 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1146 args.v2.acConfig.ucTransmitterSel = 1;
1148 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1149 args.v2.acConfig.ucTransmitterSel = 2;
1154 args.v2.acConfig.fCoherentMode = 1;
1155 args.v2.acConfig.fDPConnector = 1;
1156 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1157 if (dig->coherent_mode)
1158 args.v2.acConfig.fCoherentMode = 1;
1159 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1160 args.v2.acConfig.fDualLinkConnector = 1;
1164 args.v3.ucAction = action;
1165 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1166 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1167 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1168 args.v3.asMode.ucLaneSel = lane_num;
1169 args.v3.asMode.ucLaneSet = lane_set;
1172 args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
1173 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1174 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1176 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1180 args.v3.ucLaneNum = dp_lane_count;
1181 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1182 args.v3.ucLaneNum = 8;
1184 args.v3.ucLaneNum = 4;
1187 args.v3.acConfig.ucLinkSel = 1;
1188 if (dig_encoder & 1)
1189 args.v3.acConfig.ucEncoderSel = 1;
1191 /* Select the PLL for the PHY
1192 * DP PHY should be clocked from external src if there is
1195 /* On DCE4, if there is an external clock, it generates the DP ref clock */
1196 if (is_dp && rdev->clock.dp_extclk)
1197 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1199 args.v3.acConfig.ucRefClkSource = pll_id;
1201 switch (radeon_encoder->encoder_id) {
1202 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1203 args.v3.acConfig.ucTransmitterSel = 0;
1205 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1206 args.v3.acConfig.ucTransmitterSel = 1;
1208 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1209 args.v3.acConfig.ucTransmitterSel = 2;
1214 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1215 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1216 if (dig->coherent_mode)
1217 args.v3.acConfig.fCoherentMode = 1;
1218 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1219 args.v3.acConfig.fDualLinkConnector = 1;
1223 args.v4.ucAction = action;
1224 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1225 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1226 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1227 args.v4.asMode.ucLaneSel = lane_num;
1228 args.v4.asMode.ucLaneSet = lane_set;
1231 args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
1232 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1233 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1235 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1239 args.v4.ucLaneNum = dp_lane_count;
1240 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1241 args.v4.ucLaneNum = 8;
1243 args.v4.ucLaneNum = 4;
1246 args.v4.acConfig.ucLinkSel = 1;
1247 if (dig_encoder & 1)
1248 args.v4.acConfig.ucEncoderSel = 1;
1250 /* Select the PLL for the PHY
1251 * DP PHY should be clocked from external src if there is
1254 /* On DCE5 DCPLL usually generates the DP ref clock */
1256 if (rdev->clock.dp_extclk)
1257 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1259 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1261 args.v4.acConfig.ucRefClkSource = pll_id;
1263 switch (radeon_encoder->encoder_id) {
1264 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1265 args.v4.acConfig.ucTransmitterSel = 0;
1267 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1268 args.v4.acConfig.ucTransmitterSel = 1;
1270 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1271 args.v4.acConfig.ucTransmitterSel = 2;
1276 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1277 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1278 if (dig->coherent_mode)
1279 args.v4.acConfig.fCoherentMode = 1;
1280 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1281 args.v4.acConfig.fDualLinkConnector = 1;
1285 args.v5.ucAction = action;
1287 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1289 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1291 switch (radeon_encoder->encoder_id) {
1292 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1294 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1296 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1298 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1300 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1302 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1304 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1306 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1308 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1310 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1311 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG;
1315 args.v5.ucLaneNum = dp_lane_count;
1316 else if (radeon_encoder->pixel_clock > 165000)
1317 args.v5.ucLaneNum = 8;
1319 args.v5.ucLaneNum = 4;
1320 args.v5.ucConnObjId = connector_object_id;
1321 args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1323 if (is_dp && rdev->clock.dp_extclk)
1324 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1326 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1329 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1330 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1331 if (dig->coherent_mode)
1332 args.v5.asConfig.ucCoherentMode = 1;
1334 if (hpd_id == RADEON_HPD_NONE)
1335 args.v5.asConfig.ucHPDSel = 0;
1337 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1338 args.v5.ucDigEncoderSel = 1 << dig_encoder;
1339 args.v5.ucDPLaneSet = lane_set;
1342 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1347 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1351 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1355 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1357 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1358 struct drm_device *dev = radeon_connector->base.dev;
1359 struct radeon_device *rdev = dev->dev_private;
1360 union dig_transmitter_control args;
1361 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1364 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1367 if (!ASIC_IS_DCE4(rdev))
1370 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1371 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1374 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1377 memset(&args, 0, sizeof(args));
1379 args.v1.ucAction = action;
1381 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1383 /* wait for the panel to power up */
1384 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1387 for (i = 0; i < 300; i++) {
1388 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1398 union external_encoder_control {
1399 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1400 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1404 atombios_external_encoder_setup(struct drm_encoder *encoder,
1405 struct drm_encoder *ext_encoder,
1408 struct drm_device *dev = encoder->dev;
1409 struct radeon_device *rdev = dev->dev_private;
1410 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1411 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1412 union external_encoder_control args;
1413 struct drm_connector *connector;
1414 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1417 int dp_lane_count = 0;
1418 int connector_object_id = 0;
1419 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1421 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1422 connector = radeon_get_connector_for_encoder_init(encoder);
1424 connector = radeon_get_connector_for_encoder(encoder);
1427 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1428 struct radeon_connector_atom_dig *dig_connector =
1429 radeon_connector->con_priv;
1431 dp_clock = dig_connector->dp_clock;
1432 dp_lane_count = dig_connector->dp_lane_count;
1433 connector_object_id =
1434 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1437 memset(&args, 0, sizeof(args));
1439 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1444 /* no params on frev 1 */
1450 args.v1.sDigEncoder.ucAction = action;
1451 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1452 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1454 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1455 if (dp_clock == 270000)
1456 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1457 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1458 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1459 args.v1.sDigEncoder.ucLaneNum = 8;
1461 args.v1.sDigEncoder.ucLaneNum = 4;
1464 args.v3.sExtEncoder.ucAction = action;
1465 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1466 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1468 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1469 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1471 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1472 if (dp_clock == 270000)
1473 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1474 else if (dp_clock == 540000)
1475 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1476 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1477 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1478 args.v3.sExtEncoder.ucLaneNum = 8;
1480 args.v3.sExtEncoder.ucLaneNum = 4;
1482 case GRAPH_OBJECT_ENUM_ID1:
1483 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1485 case GRAPH_OBJECT_ENUM_ID2:
1486 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1488 case GRAPH_OBJECT_ENUM_ID3:
1489 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1492 args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
1495 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1500 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1503 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1507 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1509 struct drm_device *dev = encoder->dev;
1510 struct radeon_device *rdev = dev->dev_private;
1511 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1512 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1513 ENABLE_YUV_PS_ALLOCATION args;
1514 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1517 memset(&args, 0, sizeof(args));
1519 if (rdev->family >= CHIP_R600)
1520 reg = R600_BIOS_3_SCRATCH;
1522 reg = RADEON_BIOS_3_SCRATCH;
1524 /* XXX: fix up scratch reg handling */
1526 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1527 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1528 (radeon_crtc->crtc_id << 18)));
1529 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1530 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1535 args.ucEnable = ATOM_ENABLE;
1536 args.ucCRTC = radeon_crtc->crtc_id;
1538 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1544 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1546 struct drm_device *dev = encoder->dev;
1547 struct radeon_device *rdev = dev->dev_private;
1548 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1549 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1552 memset(&args, 0, sizeof(args));
1554 switch (radeon_encoder->encoder_id) {
1555 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1556 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1557 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1559 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1560 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1561 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1562 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1564 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1565 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1567 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1568 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1569 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1571 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1573 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1574 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1575 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1576 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1577 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1578 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1580 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1582 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1583 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1584 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1585 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1586 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1587 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1589 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1596 case DRM_MODE_DPMS_ON:
1597 args.ucAction = ATOM_ENABLE;
1598 /* workaround for DVOOutputControl on some RS690 systems */
1599 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1600 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1601 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1602 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1603 WREG32(RADEON_BIOS_3_SCRATCH, reg);
1605 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1606 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1607 args.ucAction = ATOM_LCD_BLON;
1608 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1611 case DRM_MODE_DPMS_STANDBY:
1612 case DRM_MODE_DPMS_SUSPEND:
1613 case DRM_MODE_DPMS_OFF:
1614 args.ucAction = ATOM_DISABLE;
1615 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1616 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1617 args.ucAction = ATOM_LCD_BLOFF;
1618 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1625 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1627 struct drm_device *dev = encoder->dev;
1628 struct radeon_device *rdev = dev->dev_private;
1629 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1630 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1631 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1632 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1633 struct radeon_connector *radeon_connector = NULL;
1634 struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1637 radeon_connector = to_radeon_connector(connector);
1638 radeon_dig_connector = radeon_connector->con_priv;
1642 case DRM_MODE_DPMS_ON:
1643 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1645 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1647 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1649 /* setup and enable the encoder */
1650 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1651 atombios_dig_encoder_setup(encoder,
1652 ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1655 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1656 atombios_external_encoder_setup(encoder, ext_encoder,
1657 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1659 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1660 } else if (ASIC_IS_DCE4(rdev)) {
1661 /* setup and enable the encoder */
1662 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1663 /* enable the transmitter */
1664 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1666 /* setup and enable the encoder and transmitter */
1667 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1668 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1669 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1671 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1672 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1673 atombios_set_edp_panel_power(connector,
1674 ATOM_TRANSMITTER_ACTION_POWER_ON);
1675 radeon_dig_connector->edp_on = true;
1677 radeon_dp_link_train(encoder, connector);
1678 if (ASIC_IS_DCE4(rdev))
1679 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1681 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1682 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1684 case DRM_MODE_DPMS_STANDBY:
1685 case DRM_MODE_DPMS_SUSPEND:
1686 case DRM_MODE_DPMS_OFF:
1687 if (ASIC_IS_DCE4(rdev)) {
1688 /* disable the transmitter */
1689 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1691 /* disable the encoder and transmitter */
1692 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1693 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1695 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1696 if (ASIC_IS_DCE4(rdev))
1697 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1698 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1699 atombios_set_edp_panel_power(connector,
1700 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1701 radeon_dig_connector->edp_on = false;
1704 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1705 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1711 radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
1712 struct drm_encoder *ext_encoder,
1715 struct drm_device *dev = encoder->dev;
1716 struct radeon_device *rdev = dev->dev_private;
1719 case DRM_MODE_DPMS_ON:
1721 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
1722 atombios_external_encoder_setup(encoder, ext_encoder,
1723 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1724 atombios_external_encoder_setup(encoder, ext_encoder,
1725 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1727 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1729 case DRM_MODE_DPMS_STANDBY:
1730 case DRM_MODE_DPMS_SUSPEND:
1731 case DRM_MODE_DPMS_OFF:
1732 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
1733 atombios_external_encoder_setup(encoder, ext_encoder,
1734 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1735 atombios_external_encoder_setup(encoder, ext_encoder,
1736 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1738 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1744 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1746 struct drm_device *dev = encoder->dev;
1747 struct radeon_device *rdev = dev->dev_private;
1748 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1749 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1751 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1752 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1753 radeon_encoder->active_device);
1754 switch (radeon_encoder->encoder_id) {
1755 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1756 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1757 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1758 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1759 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1760 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1761 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1762 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1763 radeon_atom_encoder_dpms_avivo(encoder, mode);
1765 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1766 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1767 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1768 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1769 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1770 radeon_atom_encoder_dpms_dig(encoder, mode);
1772 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1773 if (ASIC_IS_DCE5(rdev)) {
1775 case DRM_MODE_DPMS_ON:
1776 atombios_dvo_setup(encoder, ATOM_ENABLE);
1778 case DRM_MODE_DPMS_STANDBY:
1779 case DRM_MODE_DPMS_SUSPEND:
1780 case DRM_MODE_DPMS_OFF:
1781 atombios_dvo_setup(encoder, ATOM_DISABLE);
1784 } else if (ASIC_IS_DCE3(rdev))
1785 radeon_atom_encoder_dpms_dig(encoder, mode);
1787 radeon_atom_encoder_dpms_avivo(encoder, mode);
1789 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1790 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1791 if (ASIC_IS_DCE5(rdev)) {
1793 case DRM_MODE_DPMS_ON:
1794 atombios_dac_setup(encoder, ATOM_ENABLE);
1796 case DRM_MODE_DPMS_STANDBY:
1797 case DRM_MODE_DPMS_SUSPEND:
1798 case DRM_MODE_DPMS_OFF:
1799 atombios_dac_setup(encoder, ATOM_DISABLE);
1803 radeon_atom_encoder_dpms_avivo(encoder, mode);
1810 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);
1812 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1816 union crtc_source_param {
1817 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1818 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1822 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1824 struct drm_device *dev = encoder->dev;
1825 struct radeon_device *rdev = dev->dev_private;
1826 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1827 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1828 union crtc_source_param args;
1829 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1831 struct radeon_encoder_atom_dig *dig;
1833 memset(&args, 0, sizeof(args));
1835 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1843 if (ASIC_IS_AVIVO(rdev))
1844 args.v1.ucCRTC = radeon_crtc->crtc_id;
1846 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1847 args.v1.ucCRTC = radeon_crtc->crtc_id;
1849 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1852 switch (radeon_encoder->encoder_id) {
1853 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1854 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1855 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1857 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1858 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1859 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1860 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1862 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1864 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1865 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1866 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1867 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1869 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1870 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1871 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1872 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1873 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1874 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1876 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1878 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1879 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1880 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1881 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1882 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1883 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1885 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1890 args.v2.ucCRTC = radeon_crtc->crtc_id;
1891 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1892 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1894 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1895 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1896 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1897 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1899 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1901 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1902 switch (radeon_encoder->encoder_id) {
1903 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1904 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1905 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1906 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1907 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1908 dig = radeon_encoder->enc_priv;
1909 switch (dig->dig_encoder) {
1911 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1914 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1917 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1920 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1923 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1926 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1929 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
1933 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1934 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1936 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1937 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1938 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1939 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1940 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1942 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1944 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1945 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1946 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1947 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1948 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1950 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1957 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1961 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1963 /* update scratch regs with new routing */
1964 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1968 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1969 struct drm_display_mode *mode)
1971 struct drm_device *dev = encoder->dev;
1972 struct radeon_device *rdev = dev->dev_private;
1973 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1974 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1976 /* Funky macbooks */
1977 if ((dev->pdev->device == 0x71C5) &&
1978 (dev->pdev->subsystem_vendor == 0x106b) &&
1979 (dev->pdev->subsystem_device == 0x0080)) {
1980 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1981 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1983 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1984 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1986 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1990 /* set scaler clears this on some chips */
1991 if (ASIC_IS_AVIVO(rdev) &&
1992 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1993 if (ASIC_IS_DCE8(rdev)) {
1994 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1995 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,
1998 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1999 } else if (ASIC_IS_DCE4(rdev)) {
2000 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2001 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
2002 EVERGREEN_INTERLEAVE_EN);
2004 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2006 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2007 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
2008 AVIVO_D1MODE_INTERLEAVE_EN);
2010 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2015 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
2017 struct drm_device *dev = encoder->dev;
2018 struct radeon_device *rdev = dev->dev_private;
2019 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2020 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2021 struct drm_encoder *test_encoder;
2022 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2023 uint32_t dig_enc_in_use = 0;
2025 if (ASIC_IS_DCE6(rdev)) {
2027 switch (radeon_encoder->encoder_id) {
2028 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2034 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2040 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2046 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2050 } else if (ASIC_IS_DCE4(rdev)) {
2052 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
2053 /* ontario follows DCE4 */
2054 if (rdev->family == CHIP_PALM) {
2060 /* llano follows DCE3.2 */
2061 return radeon_crtc->crtc_id;
2063 switch (radeon_encoder->encoder_id) {
2064 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2070 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2076 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2086 /* on DCE32 and encoder can driver any block so just crtc id */
2087 if (ASIC_IS_DCE32(rdev)) {
2088 return radeon_crtc->crtc_id;
2091 /* on DCE3 - LVTMA can only be driven by DIGB */
2092 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2093 struct radeon_encoder *radeon_test_encoder;
2095 if (encoder == test_encoder)
2098 if (!radeon_encoder_is_digital(test_encoder))
2101 radeon_test_encoder = to_radeon_encoder(test_encoder);
2102 dig = radeon_test_encoder->enc_priv;
2104 if (dig->dig_encoder >= 0)
2105 dig_enc_in_use |= (1 << dig->dig_encoder);
2108 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2109 if (dig_enc_in_use & 0x2)
2110 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2113 if (!(dig_enc_in_use & 1))
2118 /* This only needs to be called once at startup */
2120 radeon_atom_encoder_init(struct radeon_device *rdev)
2122 struct drm_device *dev = rdev->ddev;
2123 struct drm_encoder *encoder;
2125 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2126 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2127 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2129 switch (radeon_encoder->encoder_id) {
2130 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2131 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2132 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2133 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2134 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2135 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2141 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
2142 atombios_external_encoder_setup(encoder, ext_encoder,
2143 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2148 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2149 struct drm_display_mode *mode,
2150 struct drm_display_mode *adjusted_mode)
2152 struct drm_device *dev = encoder->dev;
2153 struct radeon_device *rdev = dev->dev_private;
2154 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2156 radeon_encoder->pixel_clock = adjusted_mode->clock;
2158 /* need to call this here rather than in prepare() since we need some crtc info */
2159 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2161 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2162 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2163 atombios_yuv_setup(encoder, true);
2165 atombios_yuv_setup(encoder, false);
2168 switch (radeon_encoder->encoder_id) {
2169 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2170 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2171 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2172 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2173 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2175 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2176 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2177 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2178 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2179 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2180 /* handled in dpms */
2182 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2183 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2184 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2185 atombios_dvo_setup(encoder, ATOM_ENABLE);
2187 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2188 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2189 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2190 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2191 atombios_dac_setup(encoder, ATOM_ENABLE);
2192 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2193 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2194 atombios_tv_setup(encoder, ATOM_ENABLE);
2196 atombios_tv_setup(encoder, ATOM_DISABLE);
2201 atombios_apply_encoder_quirks(encoder, adjusted_mode);
2203 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2204 if (rdev->asic->display.hdmi_enable)
2205 radeon_hdmi_enable(rdev, encoder, true);
2206 if (rdev->asic->display.hdmi_setmode)
2207 radeon_hdmi_setmode(rdev, encoder, adjusted_mode);
2212 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2214 struct drm_device *dev = encoder->dev;
2215 struct radeon_device *rdev = dev->dev_private;
2216 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2217 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2219 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2220 ATOM_DEVICE_CV_SUPPORT |
2221 ATOM_DEVICE_CRT_SUPPORT)) {
2222 DAC_LOAD_DETECTION_PS_ALLOCATION args;
2223 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2226 memset(&args, 0, sizeof(args));
2228 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2231 args.sDacload.ucMisc = 0;
2233 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2234 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2235 args.sDacload.ucDacType = ATOM_DAC_A;
2237 args.sDacload.ucDacType = ATOM_DAC_B;
2239 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2240 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2241 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2242 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2243 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2244 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2246 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2247 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2248 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2250 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2253 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2260 static enum drm_connector_status
2261 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2263 struct drm_device *dev = encoder->dev;
2264 struct radeon_device *rdev = dev->dev_private;
2265 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2266 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2267 uint32_t bios_0_scratch;
2269 if (!atombios_dac_load_detect(encoder, connector)) {
2270 DRM_DEBUG_KMS("detect returned false \n");
2271 return connector_status_unknown;
2274 if (rdev->family >= CHIP_R600)
2275 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2277 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2279 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2280 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2281 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2282 return connector_status_connected;
2284 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2285 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2286 return connector_status_connected;
2288 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2289 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2290 return connector_status_connected;
2292 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2293 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2294 return connector_status_connected; /* CTV */
2295 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2296 return connector_status_connected; /* STV */
2298 return connector_status_disconnected;
2301 static enum drm_connector_status
2302 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2304 struct drm_device *dev = encoder->dev;
2305 struct radeon_device *rdev = dev->dev_private;
2306 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2307 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2308 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2311 if (!ASIC_IS_DCE4(rdev))
2312 return connector_status_unknown;
2315 return connector_status_unknown;
2317 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2318 return connector_status_unknown;
2320 /* load detect on the dp bridge */
2321 atombios_external_encoder_setup(encoder, ext_encoder,
2322 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2324 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2326 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2327 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2328 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2329 return connector_status_connected;
2331 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2332 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2333 return connector_status_connected;
2335 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2336 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2337 return connector_status_connected;
2339 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2340 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2341 return connector_status_connected; /* CTV */
2342 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2343 return connector_status_connected; /* STV */
2345 return connector_status_disconnected;
2349 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2351 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2354 /* ddc_setup on the dp bridge */
2355 atombios_external_encoder_setup(encoder, ext_encoder,
2356 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2360 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2362 struct radeon_device *rdev = encoder->dev->dev_private;
2363 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2364 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2366 if ((radeon_encoder->active_device &
2367 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2368 (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2369 ENCODER_OBJECT_ID_NONE)) {
2370 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2372 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
2373 if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2374 if (rdev->family >= CHIP_R600)
2375 dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2377 /* RS600/690/740 have only 1 afmt block */
2378 dig->afmt = rdev->mode_info.afmt[0];
2383 radeon_atom_output_lock(encoder, true);
2386 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2388 /* select the clock/data port if it uses a router */
2389 if (radeon_connector->router.cd_valid)
2390 radeon_router_select_cd_port(radeon_connector);
2392 /* turn eDP panel on for mode set */
2393 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2394 atombios_set_edp_panel_power(connector,
2395 ATOM_TRANSMITTER_ACTION_POWER_ON);
2398 /* this is needed for the pll/ss setup to work correctly in some cases */
2399 atombios_set_encoder_crtc_source(encoder);
2400 /* set up the FMT blocks */
2401 if (ASIC_IS_DCE8(rdev))
2402 dce8_program_fmt(encoder);
2403 else if (ASIC_IS_DCE4(rdev))
2404 dce4_program_fmt(encoder);
2405 else if (ASIC_IS_DCE3(rdev))
2406 dce3_program_fmt(encoder);
2407 else if (ASIC_IS_AVIVO(rdev))
2408 avivo_program_fmt(encoder);
2411 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2413 /* need to call this here as we need the crtc set up */
2414 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2415 radeon_atom_output_lock(encoder, false);
2418 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2420 struct drm_device *dev = encoder->dev;
2421 struct radeon_device *rdev = dev->dev_private;
2422 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2423 struct radeon_encoder_atom_dig *dig;
2425 /* check for pre-DCE3 cards with shared encoders;
2426 * can't really use the links individually, so don't disable
2427 * the encoder if it's in use by another connector
2429 if (!ASIC_IS_DCE3(rdev)) {
2430 struct drm_encoder *other_encoder;
2431 struct radeon_encoder *other_radeon_encoder;
2433 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2434 other_radeon_encoder = to_radeon_encoder(other_encoder);
2435 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2436 drm_helper_encoder_in_use(other_encoder))
2441 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2443 switch (radeon_encoder->encoder_id) {
2444 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2445 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2446 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2447 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2448 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2450 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2451 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2452 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2453 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2454 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2455 /* handled in dpms */
2457 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2458 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2459 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2460 atombios_dvo_setup(encoder, ATOM_DISABLE);
2462 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2463 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2464 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2465 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2466 atombios_dac_setup(encoder, ATOM_DISABLE);
2467 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2468 atombios_tv_setup(encoder, ATOM_DISABLE);
2473 if (radeon_encoder_is_digital(encoder)) {
2474 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2475 if (rdev->asic->display.hdmi_enable)
2476 radeon_hdmi_enable(rdev, encoder, false);
2478 dig = radeon_encoder->enc_priv;
2479 dig->dig_encoder = -1;
2481 radeon_encoder->active_device = 0;
2484 /* these are handled by the primary encoders */
2485 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2490 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2496 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2497 struct drm_display_mode *mode,
2498 struct drm_display_mode *adjusted_mode)
2503 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2509 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2514 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2515 const struct drm_display_mode *mode,
2516 struct drm_display_mode *adjusted_mode)
2521 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2522 .dpms = radeon_atom_ext_dpms,
2523 .mode_fixup = radeon_atom_ext_mode_fixup,
2524 .prepare = radeon_atom_ext_prepare,
2525 .mode_set = radeon_atom_ext_mode_set,
2526 .commit = radeon_atom_ext_commit,
2527 .disable = radeon_atom_ext_disable,
2528 /* no detect for TMDS/LVDS yet */
2531 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2532 .dpms = radeon_atom_encoder_dpms,
2533 .mode_fixup = radeon_atom_mode_fixup,
2534 .prepare = radeon_atom_encoder_prepare,
2535 .mode_set = radeon_atom_encoder_mode_set,
2536 .commit = radeon_atom_encoder_commit,
2537 .disable = radeon_atom_encoder_disable,
2538 .detect = radeon_atom_dig_detect,
2541 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2542 .dpms = radeon_atom_encoder_dpms,
2543 .mode_fixup = radeon_atom_mode_fixup,
2544 .prepare = radeon_atom_encoder_prepare,
2545 .mode_set = radeon_atom_encoder_mode_set,
2546 .commit = radeon_atom_encoder_commit,
2547 .detect = radeon_atom_dac_detect,
2550 void radeon_enc_destroy(struct drm_encoder *encoder)
2552 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2553 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2554 radeon_atom_backlight_exit(radeon_encoder);
2555 kfree(radeon_encoder->enc_priv);
2556 drm_encoder_cleanup(encoder);
2557 kfree(radeon_encoder);
2560 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2561 .destroy = radeon_enc_destroy,
2564 static struct radeon_encoder_atom_dac *
2565 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2567 struct drm_device *dev = radeon_encoder->base.dev;
2568 struct radeon_device *rdev = dev->dev_private;
2569 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2574 dac->tv_std = radeon_atombios_get_tv_info(rdev);
2578 static struct radeon_encoder_atom_dig *
2579 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2581 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2582 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2587 /* coherent mode by default */
2588 dig->coherent_mode = true;
2589 dig->dig_encoder = -1;
2591 if (encoder_enum == 2)
2600 radeon_add_atom_encoder(struct drm_device *dev,
2601 uint32_t encoder_enum,
2602 uint32_t supported_device,
2605 struct radeon_device *rdev = dev->dev_private;
2606 struct drm_encoder *encoder;
2607 struct radeon_encoder *radeon_encoder;
2609 /* see if we already added it */
2610 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2611 radeon_encoder = to_radeon_encoder(encoder);
2612 if (radeon_encoder->encoder_enum == encoder_enum) {
2613 radeon_encoder->devices |= supported_device;
2620 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2621 if (!radeon_encoder)
2624 encoder = &radeon_encoder->base;
2625 switch (rdev->num_crtc) {
2627 encoder->possible_crtcs = 0x1;
2631 encoder->possible_crtcs = 0x3;
2634 encoder->possible_crtcs = 0xf;
2637 encoder->possible_crtcs = 0x3f;
2641 radeon_encoder->enc_priv = NULL;
2643 radeon_encoder->encoder_enum = encoder_enum;
2644 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2645 radeon_encoder->devices = supported_device;
2646 radeon_encoder->rmx_type = RMX_OFF;
2647 radeon_encoder->underscan_type = UNDERSCAN_OFF;
2648 radeon_encoder->is_ext_encoder = false;
2649 radeon_encoder->caps = caps;
2651 switch (radeon_encoder->encoder_id) {
2652 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2653 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2654 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2655 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2656 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2657 radeon_encoder->rmx_type = RMX_FULL;
2658 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2659 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2661 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2662 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2664 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2666 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2667 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2668 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2669 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2671 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2672 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2673 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2674 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2675 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2676 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2678 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2679 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2680 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2681 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2682 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2683 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2684 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2685 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2686 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2687 radeon_encoder->rmx_type = RMX_FULL;
2688 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2689 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2690 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2691 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2692 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2694 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2695 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2697 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2699 case ENCODER_OBJECT_ID_SI170B:
2700 case ENCODER_OBJECT_ID_CH7303:
2701 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2702 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2703 case ENCODER_OBJECT_ID_TITFP513:
2704 case ENCODER_OBJECT_ID_VT1623:
2705 case ENCODER_OBJECT_ID_HDMI_SI1930:
2706 case ENCODER_OBJECT_ID_TRAVIS:
2707 case ENCODER_OBJECT_ID_NUTMEG:
2708 /* these are handled by the primary encoders */
2709 radeon_encoder->is_ext_encoder = true;
2710 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2711 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2712 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2713 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2715 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2716 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);