drivers/gpu/drm/radeon/atombios_encoders.c

   1 /*
   2  * Copyright 2007-11 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <drm/radeon_drm.h>
  29 #include "radeon.h"
  30 #include "atom.h"
  31 #include <linux/backlight.h>
  32
  33 extern int atom_debug;
  34
  35 static u8
  36 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
  37 {
  38         u8 backlight_level;
  39         u32 bios_2_scratch;
  40
  41         if (rdev->family >= CHIP_R600)
  42                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
  43         else
  44                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
  45
  46         backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
  47                            ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
  48
  49         return backlight_level;
  50 }
  51
  52 static void
  53 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
  54                                        u8 backlight_level)
  55 {
  56         u32 bios_2_scratch;
  57
  58         if (rdev->family >= CHIP_R600)
  59                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
  60         else
  61                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
  62
  63         bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
  64         bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
  65                            ATOM_S2_CURRENT_BL_LEVEL_MASK);
  66
  67         if (rdev->family >= CHIP_R600)
  68                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
  69         else
  70                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
  71 }
  72
  73 u8
  74 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
  75 {
  76         struct drm_device *dev = radeon_encoder->base.dev;
  77         struct radeon_device *rdev = dev->dev_private;
  78
  79         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
  80                 return 0;
  81
  82         return radeon_atom_get_backlight_level_from_reg(rdev);
  83 }
  84
  85 void
  86 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
  87 {
  88         struct drm_encoder *encoder = &radeon_encoder->base;
  89         struct drm_device *dev = radeon_encoder->base.dev;
  90         struct radeon_device *rdev = dev->dev_private;
  91         struct radeon_encoder_atom_dig *dig;
  92         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
  93         int index;
  94
  95         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
  96                 return;
  97
  98         if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
  99             radeon_encoder->enc_priv) {
 100                 dig = radeon_encoder->enc_priv;
 101                 dig->backlight_level = level;
 102                 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
 103
 104                 switch (radeon_encoder->encoder_id) {
 105                 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 106                 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 107                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
 108                         if (dig->backlight_level == 0) {
 109                                 args.ucAction = ATOM_LCD_BLOFF;
 110                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 111                         } else {
 112                                 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
 113                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 114                                 args.ucAction = ATOM_LCD_BLON;
 115                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 116                         }
 117                         break;
 118                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 119                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 120                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 121                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 122                         if (dig->backlight_level == 0)
 123                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
 124                         else {
 125                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
 126                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
 127                         }
 128                         break;
 129                 default:
 130                         break;
 131                 }
 132         }
 133 }
 134
 135 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
 136
 137 static u8 radeon_atom_bl_level(struct backlight_device *bd)
 138 {
 139         u8 level;
 140
 141         /* Convert brightness to hardware level */
 142         if (bd->props.brightness < 0)
 143                 level = 0;
 144         else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
 145                 level = RADEON_MAX_BL_LEVEL;
 146         else
 147                 level = bd->props.brightness;
 148
 149         return level;
 150 }
 151
 152 static int radeon_atom_backlight_update_status(struct backlight_device *bd)
 153 {
 154         struct radeon_backlight_privdata *pdata = bl_get_data(bd);
 155         struct radeon_encoder *radeon_encoder = pdata->encoder;
 156
 157         atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
 158
 159         return 0;
 160 }
 161
 162 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
 163 {
 164         struct radeon_backlight_privdata *pdata = bl_get_data(bd);
 165         struct radeon_encoder *radeon_encoder = pdata->encoder;
 166         struct drm_device *dev = radeon_encoder->base.dev;
 167         struct radeon_device *rdev = dev->dev_private;
 168
 169         return radeon_atom_get_backlight_level_from_reg(rdev);
 170 }
 171
 172 static const struct backlight_ops radeon_atom_backlight_ops = {
 173         .get_brightness = radeon_atom_backlight_get_brightness,
 174         .update_status  = radeon_atom_backlight_update_status,
 175 };
 176
 177 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
 178                                 struct drm_connector *drm_connector)
 179 {
 180         struct drm_device *dev = radeon_encoder->base.dev;
 181         struct radeon_device *rdev = dev->dev_private;
 182         struct backlight_device *bd;
 183         struct backlight_properties props;
 184         struct radeon_backlight_privdata *pdata;
 185         struct radeon_encoder_atom_dig *dig;
 186         u8 backlight_level;
 187         char bl_name[16];
 188
 189         /* Mac laptops with multiple GPUs use the gmux driver for backlight
 190          * so don't register a backlight device
 191          */
 192         if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
 193             (rdev->pdev->device == 0x6741))
 194                 return;
 195
 196         if (!radeon_encoder->enc_priv)
 197                 return;
 198
 199         if (!rdev->is_atom_bios)
 200                 return;
 201
 202         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
 203                 return;
 204
 205         pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
 206         if (!pdata) {
 207                 DRM_ERROR("Memory allocation failed\n");
 208                 goto error;
 209         }
 210
 211         memset(&props, 0, sizeof(props));
 212         props.max_brightness = RADEON_MAX_BL_LEVEL;
 213         props.type = BACKLIGHT_RAW;
 214         snprintf(bl_name, sizeof(bl_name),
 215                  "radeon_bl%d", dev->primary->index);
 216         bd = backlight_device_register(bl_name, &drm_connector->kdev,
 217                                        pdata, &radeon_atom_backlight_ops, &props);
 218         if (IS_ERR(bd)) {
 219                 DRM_ERROR("Backlight registration failed\n");
 220                 goto error;
 221         }
 222
 223         pdata->encoder = radeon_encoder;
 224
 225         backlight_level = radeon_atom_get_backlight_level_from_reg(rdev);
 226
 227         dig = radeon_encoder->enc_priv;
 228         dig->bl_dev = bd;
 229
 230         bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
 231         bd->props.power = FB_BLANK_UNBLANK;
 232         backlight_update_status(bd);
 233
 234         DRM_INFO("radeon atom DIG backlight initialized\n");
 235
 236         return;
 237
 238 error:
 239         kfree(pdata);
 240         return;
 241 }
 242
 243 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
 244 {
 245         struct drm_device *dev = radeon_encoder->base.dev;
 246         struct radeon_device *rdev = dev->dev_private;
 247         struct backlight_device *bd = NULL;
 248         struct radeon_encoder_atom_dig *dig;
 249
 250         if (!radeon_encoder->enc_priv)
 251                 return;
 252
 253         if (!rdev->is_atom_bios)
 254                 return;
 255
 256         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
 257                 return;
 258
 259         dig = radeon_encoder->enc_priv;
 260         bd = dig->bl_dev;
 261         dig->bl_dev = NULL;
 262
 263         if (bd) {
 264                 struct radeon_legacy_backlight_privdata *pdata;
 265
 266                 pdata = bl_get_data(bd);
 267                 backlight_device_unregister(bd);
 268                 kfree(pdata);
 269
 270                 DRM_INFO("radeon atom LVDS backlight unloaded\n");
 271         }
 272 }
 273
 274 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
 275
 276 void radeon_atom_backlight_init(struct radeon_encoder *encoder)
 277 {
 278 }
 279
 280 static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
 281 {
 282 }
 283
 284 #endif
 285
 286 /* evil but including atombios.h is much worse */
 287 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
 288                                 struct drm_display_mode *mode);
 289
 290
 291 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
 292 {
 293         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 294         switch (radeon_encoder->encoder_id) {
 295         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 296         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 297         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 298         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 299         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
 300         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 301         case ENCODER_OBJECT_ID_INTERNAL_DDI:
 302         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 303         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 304         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 305         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 306                 return true;
 307         default:
 308                 return false;
 309         }
 310 }
 311
 312 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
 313                                    const struct drm_display_mode *mode,
 314                                    struct drm_display_mode *adjusted_mode)
 315 {
 316         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 317         struct drm_device *dev = encoder->dev;
 318         struct radeon_device *rdev = dev->dev_private;
 319
 320         /* set the active encoder to connector routing */
 321         radeon_encoder_set_active_device(encoder);
 322         drm_mode_set_crtcinfo(adjusted_mode, 0);
 323
 324         /* hw bug */
 325         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 326             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
 327                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
 328
 329         /* get the native mode for LVDS */
 330         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
 331                 radeon_panel_mode_fixup(encoder, adjusted_mode);
 332
 333         /* get the native mode for TV */
 334         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
 335                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 336                 if (tv_dac) {
 337                         if (tv_dac->tv_std == TV_STD_NTSC ||
 338                             tv_dac->tv_std == TV_STD_NTSC_J ||
 339                             tv_dac->tv_std == TV_STD_PAL_M)
 340                                 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
 341                         else
 342                                 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
 343                 }
 344         }
 345
 346         if (ASIC_IS_DCE3(rdev) &&
 347             ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
 348              (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
 349                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 350                 radeon_dp_set_link_config(connector, adjusted_mode);
 351         }
 352
 353         return true;
 354 }
 355
 356 static void
 357 atombios_dac_setup(struct drm_encoder *encoder, int action)
 358 {
 359         struct drm_device *dev = encoder->dev;
 360         struct radeon_device *rdev = dev->dev_private;
 361         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 362         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 363         int index = 0;
 364         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 365
 366         memset(&args, 0, sizeof(args));
 367
 368         switch (radeon_encoder->encoder_id) {
 369         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 370         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 371                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
 372                 break;
 373         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 374         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 375                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
 376                 break;
 377         }
 378
 379         args.ucAction = action;
 380
 381         if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
 382                 args.ucDacStandard = ATOM_DAC1_PS2;
 383         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 384                 args.ucDacStandard = ATOM_DAC1_CV;
 385         else {
 386                 switch (dac_info->tv_std) {
 387                 case TV_STD_PAL:
 388                 case TV_STD_PAL_M:
 389                 case TV_STD_SCART_PAL:
 390                 case TV_STD_SECAM:
 391                 case TV_STD_PAL_CN:
 392                         args.ucDacStandard = ATOM_DAC1_PAL;
 393                         break;
 394                 case TV_STD_NTSC:
 395                 case TV_STD_NTSC_J:
 396                 case TV_STD_PAL_60:
 397                 default:
 398                         args.ucDacStandard = ATOM_DAC1_NTSC;
 399                         break;
 400                 }
 401         }
 402         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 403
 404         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 405
 406 }
 407
 408 static void
 409 atombios_tv_setup(struct drm_encoder *encoder, int action)
 410 {
 411         struct drm_device *dev = encoder->dev;
 412         struct radeon_device *rdev = dev->dev_private;
 413         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 414         TV_ENCODER_CONTROL_PS_ALLOCATION args;
 415         int index = 0;
 416         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 417
 418         memset(&args, 0, sizeof(args));
 419
 420         index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
 421
 422         args.sTVEncoder.ucAction = action;
 423
 424         if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 425                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 426         else {
 427                 switch (dac_info->tv_std) {
 428                 case TV_STD_NTSC:
 429                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 430                         break;
 431                 case TV_STD_PAL:
 432                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
 433                         break;
 434                 case TV_STD_PAL_M:
 435                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
 436                         break;
 437                 case TV_STD_PAL_60:
 438                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
 439                         break;
 440                 case TV_STD_NTSC_J:
 441                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
 442                         break;
 443                 case TV_STD_SCART_PAL:
 444                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
 445                         break;
 446                 case TV_STD_SECAM:
 447                         args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
 448                         break;
 449                 case TV_STD_PAL_CN:
 450                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
 451                         break;
 452                 default:
 453                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 454                         break;
 455                 }
 456         }
 457
 458         args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 459
 460         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 461
 462 }
 463
 464 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
 465 {
 466         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 467         int bpc = 8;
 468
 469         if (connector)
 470                 bpc = radeon_get_monitor_bpc(connector);
 471
 472         switch (bpc) {
 473         case 0:
 474                 return PANEL_BPC_UNDEFINE;
 475         case 6:
 476                 return PANEL_6BIT_PER_COLOR;
 477         case 8:
 478         default:
 479                 return PANEL_8BIT_PER_COLOR;
 480         case 10:
 481                 return PANEL_10BIT_PER_COLOR;
 482         case 12:
 483                 return PANEL_12BIT_PER_COLOR;
 484         case 16:
 485                 return PANEL_16BIT_PER_COLOR;
 486         }
 487 }
 488
 489
 490 union dvo_encoder_control {
 491         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
 492         DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
 493         DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
 494 };
 495
 496 void
 497 atombios_dvo_setup(struct drm_encoder *encoder, int action)
 498 {
 499         struct drm_device *dev = encoder->dev;
 500         struct radeon_device *rdev = dev->dev_private;
 501         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 502         union dvo_encoder_control args;
 503         int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 504         uint8_t frev, crev;
 505
 506         memset(&args, 0, sizeof(args));
 507
 508         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 509                 return;
 510
 511         /* some R4xx chips have the wrong frev */
 512         if (rdev->family <= CHIP_RV410)
 513                 frev = 1;
 514
 515         switch (frev) {
 516         case 1:
 517                 switch (crev) {
 518                 case 1:
 519                         /* R4xx, R5xx */
 520                         args.ext_tmds.sXTmdsEncoder.ucEnable = action;
 521
 522                         if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 523                                 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 524
 525                         args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
 526                         break;
 527                 case 2:
 528                         /* RS600/690/740 */
 529                         args.dvo.sDVOEncoder.ucAction = action;
 530                         args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 531                         /* DFP1, CRT1, TV1 depending on the type of port */
 532                         args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
 533
 534                         if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 535                                 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
 536                         break;
 537                 case 3:
 538                         /* R6xx */
 539                         args.dvo_v3.ucAction = action;
 540                         args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 541                         args.dvo_v3.ucDVOConfig = 0; /* XXX */
 542                         break;
 543                 default:
 544                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 545                         break;
 546                 }
 547                 break;
 548         default:
 549                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 550                 break;
 551         }
 552
 553         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 554 }
 555
 556 union lvds_encoder_control {
 557         LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
 558         LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
 559 };
 560
 561 void
 562 atombios_digital_setup(struct drm_encoder *encoder, int action)
 563 {
 564         struct drm_device *dev = encoder->dev;
 565         struct radeon_device *rdev = dev->dev_private;
 566         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 567         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 568         union lvds_encoder_control args;
 569         int index = 0;
 570         int hdmi_detected = 0;
 571         uint8_t frev, crev;
 572
 573         if (!dig)
 574                 return;
 575
 576         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
 577                 hdmi_detected = 1;
 578
 579         memset(&args, 0, sizeof(args));
 580
 581         switch (radeon_encoder->encoder_id) {
 582         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 583                 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 584                 break;
 585         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 586         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 587                 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
 588                 break;
 589         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 590                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 591                         index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 592                 else
 593                         index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
 594                 break;
 595         }
 596
 597         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 598                 return;
 599
 600         switch (frev) {
 601         case 1:
 602         case 2:
 603                 switch (crev) {
 604                 case 1:
 605                         args.v1.ucMisc = 0;
 606                         args.v1.ucAction = action;
 607                         if (hdmi_detected)
 608                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 609                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 610                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 611                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 612                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 613                                 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 614                                         args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 615                         } else {
 616                                 if (dig->linkb)
 617                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 618                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 619                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 620                                 /*if (pScrn->rgbBits == 8) */
 621                                 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 622                         }
 623                         break;
 624                 case 2:
 625                 case 3:
 626                         args.v2.ucMisc = 0;
 627                         args.v2.ucAction = action;
 628                         if (crev == 3) {
 629                                 if (dig->coherent_mode)
 630                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
 631                         }
 632                         if (hdmi_detected)
 633                                 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 634                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 635                         args.v2.ucTruncate = 0;
 636                         args.v2.ucSpatial = 0;
 637                         args.v2.ucTemporal = 0;
 638                         args.v2.ucFRC = 0;
 639                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 640                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 641                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 642                                 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
 643                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
 644                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 645                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
 646                                 }
 647                                 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
 648                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
 649                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 650                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
 651                                         if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
 652                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
 653                                 }
 654                         } else {
 655                                 if (dig->linkb)
 656                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 657                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 658                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 659                         }
 660                         break;
 661                 default:
 662                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 663                         break;
 664                 }
 665                 break;
 666         default:
 667                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 668                 break;
 669         }
 670
 671         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 672 }
 673
 674 int
 675 atombios_get_encoder_mode(struct drm_encoder *encoder)
 676 {
 677         struct drm_device *dev = encoder->dev;
 678         struct radeon_device *rdev = dev->dev_private;
 679         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 680         struct drm_connector *connector;
 681         struct radeon_connector *radeon_connector;
 682         struct radeon_connector_atom_dig *dig_connector;
 683
 684         /* dp bridges are always DP */
 685         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
 686                 return ATOM_ENCODER_MODE_DP;
 687
 688         /* DVO is always DVO */
 689         if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
 690             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
 691                 return ATOM_ENCODER_MODE_DVO;
 692
 693         connector = radeon_get_connector_for_encoder(encoder);
 694         /* if we don't have an active device yet, just use one of
 695          * the connectors tied to the encoder.
 696          */
 697         if (!connector)
 698                 connector = radeon_get_connector_for_encoder_init(encoder);
 699         radeon_connector = to_radeon_connector(connector);
 700
 701         switch (connector->connector_type) {
 702         case DRM_MODE_CONNECTOR_DVII:
 703         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
 704                 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
 705                     radeon_audio &&
 706                     !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
 707                         return ATOM_ENCODER_MODE_HDMI;
 708                 else if (radeon_connector->use_digital)
 709                         return ATOM_ENCODER_MODE_DVI;
 710                 else
 711                         return ATOM_ENCODER_MODE_CRT;
 712                 break;
 713         case DRM_MODE_CONNECTOR_DVID:
 714         case DRM_MODE_CONNECTOR_HDMIA:
 715         default:
 716                 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
 717                     radeon_audio &&
 718                     !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
 719                         return ATOM_ENCODER_MODE_HDMI;
 720                 else
 721                         return ATOM_ENCODER_MODE_DVI;
 722                 break;
 723         case DRM_MODE_CONNECTOR_LVDS:
 724                 return ATOM_ENCODER_MODE_LVDS;
 725                 break;
 726         case DRM_MODE_CONNECTOR_DisplayPort:
 727                 dig_connector = radeon_connector->con_priv;
 728                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 729                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
 730                         return ATOM_ENCODER_MODE_DP;
 731                 else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
 732                          radeon_audio &&
 733                          !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
 734                         return ATOM_ENCODER_MODE_HDMI;
 735                 else
 736                         return ATOM_ENCODER_MODE_DVI;
 737                 break;
 738         case DRM_MODE_CONNECTOR_eDP:
 739                 return ATOM_ENCODER_MODE_DP;
 740         case DRM_MODE_CONNECTOR_DVIA:
 741         case DRM_MODE_CONNECTOR_VGA:
 742                 return ATOM_ENCODER_MODE_CRT;
 743                 break;
 744         case DRM_MODE_CONNECTOR_Composite:
 745         case DRM_MODE_CONNECTOR_SVIDEO:
 746         case DRM_MODE_CONNECTOR_9PinDIN:
 747                 /* fix me */
 748                 return ATOM_ENCODER_MODE_TV;
 749                 /*return ATOM_ENCODER_MODE_CV;*/
 750                 break;
 751         }
 752 }
 753
 754 /*
 755  * DIG Encoder/Transmitter Setup
 756  *
 757  * DCE 3.0/3.1
 758  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
 759  * Supports up to 3 digital outputs
 760  * - 2 DIG encoder blocks.
 761  * DIG1 can drive UNIPHY link A or link B
 762  * DIG2 can drive UNIPHY link B or LVTMA
 763  *
 764  * DCE 3.2
 765  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
 766  * Supports up to 5 digital outputs
 767  * - 2 DIG encoder blocks.
 768  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 769  *
 770  * DCE 4.0/5.0/6.0
 771  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 772  * Supports up to 6 digital outputs
 773  * - 6 DIG encoder blocks.
 774  * - DIG to PHY mapping is hardcoded
 775  * DIG1 drives UNIPHY0 link A, A+B
 776  * DIG2 drives UNIPHY0 link B
 777  * DIG3 drives UNIPHY1 link A, A+B
 778  * DIG4 drives UNIPHY1 link B
 779  * DIG5 drives UNIPHY2 link A, A+B
 780  * DIG6 drives UNIPHY2 link B
 781  *
 782  * DCE 4.1
 783  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 784  * Supports up to 6 digital outputs
 785  * - 2 DIG encoder blocks.
 786  * llano
 787  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 788  * ontario
 789  * DIG1 drives UNIPHY0/1/2 link A
 790  * DIG2 drives UNIPHY0/1/2 link B
 791  *
 792  * Routing
 793  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
 794  * Examples:
 795  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
 796  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
 797  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
 798  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
 799  */
 800
 801 union dig_encoder_control {
 802         DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
 803         DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
 804         DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
 805         DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
 806 };
 807
 808 void
 809 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
 810 {
 811         struct drm_device *dev = encoder->dev;
 812         struct radeon_device *rdev = dev->dev_private;
 813         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 814         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 815         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 816         union dig_encoder_control args;
 817         int index = 0;
 818         uint8_t frev, crev;
 819         int dp_clock = 0;
 820         int dp_lane_count = 0;
 821         int hpd_id = RADEON_HPD_NONE;
 822
 823         if (connector) {
 824                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 825                 struct radeon_connector_atom_dig *dig_connector =
 826                         radeon_connector->con_priv;
 827
 828                 dp_clock = dig_connector->dp_clock;
 829                 dp_lane_count = dig_connector->dp_lane_count;
 830                 hpd_id = radeon_connector->hpd.hpd;
 831         }
 832
 833         /* no dig encoder assigned */
 834         if (dig->dig_encoder == -1)
 835                 return;
 836
 837         memset(&args, 0, sizeof(args));
 838
 839         if (ASIC_IS_DCE4(rdev))
 840                 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
 841         else {
 842                 if (dig->dig_encoder)
 843                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 844                 else
 845                         index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 846         }
 847
 848         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 849                 return;
 850
 851         switch (frev) {
 852         case 1:
 853                 switch (crev) {
 854                 case 1:
 855                         args.v1.ucAction = action;
 856                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 857                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 858                                 args.v3.ucPanelMode = panel_mode;
 859                         else
 860                                 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
 861
 862                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
 863                                 args.v1.ucLaneNum = dp_lane_count;
 864                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 865                                 args.v1.ucLaneNum = 8;
 866                         else
 867                                 args.v1.ucLaneNum = 4;
 868
 869                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
 870                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
 871                         switch (radeon_encoder->encoder_id) {
 872                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 873                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
 874                                 break;
 875                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 876                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 877                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
 878                                 break;
 879                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 880                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
 881                                 break;
 882                         }
 883                         if (dig->linkb)
 884                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
 885                         else
 886                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
 887                         break;
 888                 case 2:
 889                 case 3:
 890                         args.v3.ucAction = action;
 891                         args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 892                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 893                                 args.v3.ucPanelMode = panel_mode;
 894                         else
 895                                 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
 896
 897                         if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
 898                                 args.v3.ucLaneNum = dp_lane_count;
 899                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 900                                 args.v3.ucLaneNum = 8;
 901                         else
 902                                 args.v3.ucLaneNum = 4;
 903
 904                         if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
 905                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
 906                         args.v3.acConfig.ucDigSel = dig->dig_encoder;
 907                         args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
 908                         break;
 909                 case 4:
 910                         args.v4.ucAction = action;
 911                         args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 912                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 913                                 args.v4.ucPanelMode = panel_mode;
 914                         else
 915                                 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
 916
 917                         if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
 918                                 args.v4.ucLaneNum = dp_lane_count;
 919                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 920                                 args.v4.ucLaneNum = 8;
 921                         else
 922                                 args.v4.ucLaneNum = 4;
 923
 924                         if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
 925                                 if (dp_clock == 270000)
 926                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
 927                                 else if (dp_clock == 540000)
 928                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
 929                         }
 930                         args.v4.acConfig.ucDigSel = dig->dig_encoder;
 931                         args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
 932                         if (hpd_id == RADEON_HPD_NONE)
 933                                 args.v4.ucHPD_ID = 0;
 934                         else
 935                                 args.v4.ucHPD_ID = hpd_id + 1;
 936                         break;
 937                 default:
 938                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 939                         break;
 940                 }
 941                 break;
 942         default:
 943                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 944                 break;
 945         }
 946
 947         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 948
 949 }
 950
 951 union dig_transmitter_control {
 952         DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
 953         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
 954         DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
 955         DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
 956         DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
 957 };
 958
 959 void
 960 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
 961 {
 962         struct drm_device *dev = encoder->dev;
 963         struct radeon_device *rdev = dev->dev_private;
 964         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 965         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 966         struct drm_connector *connector;
 967         union dig_transmitter_control args;
 968         int index = 0;
 969         uint8_t frev, crev;
 970         bool is_dp = false;
 971         int pll_id = 0;
 972         int dp_clock = 0;
 973         int dp_lane_count = 0;
 974         int connector_object_id = 0;
 975         int igp_lane_info = 0;
 976         int dig_encoder = dig->dig_encoder;
 977         int hpd_id = RADEON_HPD_NONE;
 978
 979         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 980                 connector = radeon_get_connector_for_encoder_init(encoder);
 981                 /* just needed to avoid bailing in the encoder check.  the encoder
 982                  * isn't used for init
 983                  */
 984                 dig_encoder = 0;
 985         } else
 986                 connector = radeon_get_connector_for_encoder(encoder);
 987
 988         if (connector) {
 989                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 990                 struct radeon_connector_atom_dig *dig_connector =
 991                         radeon_connector->con_priv;
 992
 993                 hpd_id = radeon_connector->hpd.hpd;
 994                 dp_clock = dig_connector->dp_clock;
 995                 dp_lane_count = dig_connector->dp_lane_count;
 996                 connector_object_id =
 997                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 998                 igp_lane_info = dig_connector->igp_lane_info;
 999         }
1000
1001         if (encoder->crtc) {
1002                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1003                 pll_id = radeon_crtc->pll_id;
1004         }
1005
1006         /* no dig encoder assigned */
1007         if (dig_encoder == -1)
1008                 return;
1009
1010         if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
1011                 is_dp = true;
1012
1013         memset(&args, 0, sizeof(args));
1014
1015         switch (radeon_encoder->encoder_id) {
1016         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1017                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1018                 break;
1019         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1020         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1021         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1022                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1023                 break;
1024         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1025                 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1026                 break;
1027         }
1028
1029         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1030                 return;
1031
1032         switch (frev) {
1033         case 1:
1034                 switch (crev) {
1035                 case 1:
1036                         args.v1.ucAction = action;
1037                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1038                                 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1039                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1040                                 args.v1.asMode.ucLaneSel = lane_num;
1041                                 args.v1.asMode.ucLaneSet = lane_set;
1042                         } else {
1043                                 if (is_dp)
1044                                         args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
1045                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1046                                         args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1047                                 else
1048                                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1049                         }
1050
1051                         args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1052
1053                         if (dig_encoder)
1054                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1055                         else
1056                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1057
1058                         if ((rdev->flags & RADEON_IS_IGP) &&
1059                             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1060                                 if (is_dp ||
1061                                     !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
1062                                         if (igp_lane_info & 0x1)
1063                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1064                                         else if (igp_lane_info & 0x2)
1065                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1066                                         else if (igp_lane_info & 0x4)
1067                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1068                                         else if (igp_lane_info & 0x8)
1069                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1070                                 } else {
1071                                         if (igp_lane_info & 0x3)
1072                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1073                                         else if (igp_lane_info & 0xc)
1074                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1075                                 }
1076                         }
1077
1078                         if (dig->linkb)
1079                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1080                         else
1081                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1082
1083                         if (is_dp)
1084                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1085                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1086                                 if (dig->coherent_mode)
1087                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1088                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1089                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1090                         }
1091                         break;
1092                 case 2:
1093                         args.v2.ucAction = action;
1094                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1095                                 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1096                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1097                                 args.v2.asMode.ucLaneSel = lane_num;
1098                                 args.v2.asMode.ucLaneSet = lane_set;
1099                         } else {
1100                                 if (is_dp)
1101                                         args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
1102                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1103                                         args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1104                                 else
1105                                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1106                         }
1107
1108                         args.v2.acConfig.ucEncoderSel = dig_encoder;
1109                         if (dig->linkb)
1110                                 args.v2.acConfig.ucLinkSel = 1;
1111
1112                         switch (radeon_encoder->encoder_id) {
1113                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1114                                 args.v2.acConfig.ucTransmitterSel = 0;
1115                                 break;
1116                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1117                                 args.v2.acConfig.ucTransmitterSel = 1;
1118                                 break;
1119                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1120                                 args.v2.acConfig.ucTransmitterSel = 2;
1121                                 break;
1122                         }
1123
1124                         if (is_dp) {
1125                                 args.v2.acConfig.fCoherentMode = 1;
1126                                 args.v2.acConfig.fDPConnector = 1;
1127                         } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1128                                 if (dig->coherent_mode)
1129                                         args.v2.acConfig.fCoherentMode = 1;
1130                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1131                                         args.v2.acConfig.fDualLinkConnector = 1;
1132                         }
1133                         break;
1134                 case 3:
1135                         args.v3.ucAction = action;
1136                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1137                                 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1138                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1139                                 args.v3.asMode.ucLaneSel = lane_num;
1140                                 args.v3.asMode.ucLaneSet = lane_set;
1141                         } else {
1142                                 if (is_dp)
1143                                         args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
1144                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1145                                         args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1146                                 else
1147                                         args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1148                         }
1149
1150                         if (is_dp)
1151                                 args.v3.ucLaneNum = dp_lane_count;
1152                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1153                                 args.v3.ucLaneNum = 8;
1154                         else
1155                                 args.v3.ucLaneNum = 4;
1156
1157                         if (dig->linkb)
1158                                 args.v3.acConfig.ucLinkSel = 1;
1159                         if (dig_encoder & 1)
1160                                 args.v3.acConfig.ucEncoderSel = 1;
1161
1162                         /* Select the PLL for the PHY
1163                          * DP PHY should be clocked from external src if there is
1164                          * one.
1165                          */
1166                         /* On DCE4, if there is an external clock, it generates the DP ref clock */
1167                         if (is_dp && rdev->clock.dp_extclk)
1168                                 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1169                         else
1170                                 args.v3.acConfig.ucRefClkSource = pll_id;
1171
1172                         switch (radeon_encoder->encoder_id) {
1173                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1174                                 args.v3.acConfig.ucTransmitterSel = 0;
1175                                 break;
1176                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1177                                 args.v3.acConfig.ucTransmitterSel = 1;
1178                                 break;
1179                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1180                                 args.v3.acConfig.ucTransmitterSel = 2;
1181                                 break;
1182                         }
1183
1184                         if (is_dp)
1185                                 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1186                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1187                                 if (dig->coherent_mode)
1188                                         args.v3.acConfig.fCoherentMode = 1;
1189                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1190                                         args.v3.acConfig.fDualLinkConnector = 1;
1191                         }
1192                         break;
1193                 case 4:
1194                         args.v4.ucAction = action;
1195                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1196                                 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1197                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1198                                 args.v4.asMode.ucLaneSel = lane_num;
1199                                 args.v4.asMode.ucLaneSet = lane_set;
1200                         } else {
1201                                 if (is_dp)
1202                                         args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
1203                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1204                                         args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1205                                 else
1206                                         args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1207                         }
1208
1209                         if (is_dp)
1210                                 args.v4.ucLaneNum = dp_lane_count;
1211                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1212                                 args.v4.ucLaneNum = 8;
1213                         else
1214                                 args.v4.ucLaneNum = 4;
1215
1216                         if (dig->linkb)
1217                                 args.v4.acConfig.ucLinkSel = 1;
1218                         if (dig_encoder & 1)
1219                                 args.v4.acConfig.ucEncoderSel = 1;
1220
1221                         /* Select the PLL for the PHY
1222                          * DP PHY should be clocked from external src if there is
1223                          * one.
1224                          */
1225                         /* On DCE5 DCPLL usually generates the DP ref clock */
1226                         if (is_dp) {
1227                                 if (rdev->clock.dp_extclk)
1228                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1229                                 else
1230                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1231                         } else
1232                                 args.v4.acConfig.ucRefClkSource = pll_id;
1233
1234                         switch (radeon_encoder->encoder_id) {
1235                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1236                                 args.v4.acConfig.ucTransmitterSel = 0;
1237                                 break;
1238                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1239                                 args.v4.acConfig.ucTransmitterSel = 1;
1240                                 break;
1241                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1242                                 args.v4.acConfig.ucTransmitterSel = 2;
1243                                 break;
1244                         }
1245
1246                         if (is_dp)
1247                                 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1248                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1249                                 if (dig->coherent_mode)
1250                                         args.v4.acConfig.fCoherentMode = 1;
1251                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1252                                         args.v4.acConfig.fDualLinkConnector = 1;
1253                         }
1254                         break;
1255                 case 5:
1256                         args.v5.ucAction = action;
1257                         if (is_dp)
1258                                 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1259                         else
1260                                 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1261
1262                         switch (radeon_encoder->encoder_id) {
1263                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1264                                 if (dig->linkb)
1265                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1266                                 else
1267                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1268                                 break;
1269                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1270                                 if (dig->linkb)
1271                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1272                                 else
1273                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1274                                 break;
1275                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1276                                 if (dig->linkb)
1277                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1278                                 else
1279                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1280                                 break;
1281                         }
1282                         if (is_dp)
1283                                 args.v5.ucLaneNum = dp_lane_count;
1284                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1285                                 args.v5.ucLaneNum = 8;
1286                         else
1287                                 args.v5.ucLaneNum = 4;
1288                         args.v5.ucConnObjId = connector_object_id;
1289                         args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1290
1291                         if (is_dp && rdev->clock.dp_extclk)
1292                                 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1293                         else
1294                                 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1295
1296                         if (is_dp)
1297                                 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1298                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1299                                 if (dig->coherent_mode)
1300                                         args.v5.asConfig.ucCoherentMode = 1;
1301                         }
1302                         if (hpd_id == RADEON_HPD_NONE)
1303                                 args.v5.asConfig.ucHPDSel = 0;
1304                         else
1305                                 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1306                         args.v5.ucDigEncoderSel = 1 << dig_encoder;
1307                         args.v5.ucDPLaneSet = lane_set;
1308                         break;
1309                 default:
1310                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1311                         break;
1312                 }
1313                 break;
1314         default:
1315                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1316                 break;
1317         }
1318
1319         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1320 }
1321
1322 bool
1323 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1324 {
1325         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1326         struct drm_device *dev = radeon_connector->base.dev;
1327         struct radeon_device *rdev = dev->dev_private;
1328         union dig_transmitter_control args;
1329         int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1330         uint8_t frev, crev;
1331
1332         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1333                 goto done;
1334
1335         if (!ASIC_IS_DCE4(rdev))
1336                 goto done;
1337
1338         if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1339             (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1340                 goto done;
1341
1342         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1343                 goto done;
1344
1345         memset(&args, 0, sizeof(args));
1346
1347         args.v1.ucAction = action;
1348
1349         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1350
1351         /* wait for the panel to power up */
1352         if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1353                 int i;
1354
1355                 for (i = 0; i < 300; i++) {
1356                         if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1357                                 return true;
1358                         mdelay(1);
1359                 }
1360                 return false;
1361         }
1362 done:
1363         return true;
1364 }
1365
1366 union external_encoder_control {
1367         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1368         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1369 };
1370
1371 static void
1372 atombios_external_encoder_setup(struct drm_encoder *encoder,
1373                                 struct drm_encoder *ext_encoder,
1374                                 int action)
1375 {
1376         struct drm_device *dev = encoder->dev;
1377         struct radeon_device *rdev = dev->dev_private;
1378         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1379         struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1380         union external_encoder_control args;
1381         struct drm_connector *connector;
1382         int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1383         u8 frev, crev;
1384         int dp_clock = 0;
1385         int dp_lane_count = 0;
1386         int connector_object_id = 0;
1387         u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1388
1389         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1390                 connector = radeon_get_connector_for_encoder_init(encoder);
1391         else
1392                 connector = radeon_get_connector_for_encoder(encoder);
1393
1394         if (connector) {
1395                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1396                 struct radeon_connector_atom_dig *dig_connector =
1397                         radeon_connector->con_priv;
1398
1399                 dp_clock = dig_connector->dp_clock;
1400                 dp_lane_count = dig_connector->dp_lane_count;
1401                 connector_object_id =
1402                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1403         }
1404
1405         memset(&args, 0, sizeof(args));
1406
1407         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1408                 return;
1409
1410         switch (frev) {
1411         case 1:
1412                 /* no params on frev 1 */
1413                 break;
1414         case 2:
1415                 switch (crev) {
1416                 case 1:
1417                 case 2:
1418                         args.v1.sDigEncoder.ucAction = action;
1419                         args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1420                         args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1421
1422                         if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1423                                 if (dp_clock == 270000)
1424                                         args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1425                                 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1426                         } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1427                                 args.v1.sDigEncoder.ucLaneNum = 8;
1428                         else
1429                                 args.v1.sDigEncoder.ucLaneNum = 4;
1430                         break;
1431                 case 3:
1432                         args.v3.sExtEncoder.ucAction = action;
1433                         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1434                                 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1435                         else
1436                                 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1437                         args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1438
1439                         if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1440                                 if (dp_clock == 270000)
1441                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1442                                 else if (dp_clock == 540000)
1443                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1444                                 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1445                         } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1446                                 args.v3.sExtEncoder.ucLaneNum = 8;
1447                         else
1448                                 args.v3.sExtEncoder.ucLaneNum = 4;
1449                         switch (ext_enum) {
1450                         case GRAPH_OBJECT_ENUM_ID1:
1451                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1452                                 break;
1453                         case GRAPH_OBJECT_ENUM_ID2:
1454                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1455                                 break;
1456                         case GRAPH_OBJECT_ENUM_ID3:
1457                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1458                                 break;
1459                         }
1460                         args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
1461                         break;
1462                 default:
1463                         DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1464                         return;
1465                 }
1466                 break;
1467         default:
1468                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1469                 return;
1470         }
1471         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1472 }
1473
1474 static void
1475 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1476 {
1477         struct drm_device *dev = encoder->dev;
1478         struct radeon_device *rdev = dev->dev_private;
1479         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1480         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1481         ENABLE_YUV_PS_ALLOCATION args;
1482         int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1483         uint32_t temp, reg;
1484
1485         memset(&args, 0, sizeof(args));
1486
1487         if (rdev->family >= CHIP_R600)
1488                 reg = R600_BIOS_3_SCRATCH;
1489         else
1490                 reg = RADEON_BIOS_3_SCRATCH;
1491
1492         /* XXX: fix up scratch reg handling */
1493         temp = RREG32(reg);
1494         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1495                 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1496                              (radeon_crtc->crtc_id << 18)));
1497         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1498                 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1499         else
1500                 WREG32(reg, 0);
1501
1502         if (enable)
1503                 args.ucEnable = ATOM_ENABLE;
1504         args.ucCRTC = radeon_crtc->crtc_id;
1505
1506         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1507
1508         WREG32(reg, temp);
1509 }
1510
1511 static void
1512 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1513 {
1514         struct drm_device *dev = encoder->dev;
1515         struct radeon_device *rdev = dev->dev_private;
1516         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1517         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1518         int index = 0;
1519
1520         memset(&args, 0, sizeof(args));
1521
1522         switch (radeon_encoder->encoder_id) {
1523         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1524         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1525                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1526                 break;
1527         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1528         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1529         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1530                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1531                 break;
1532         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1533                 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1534                 break;
1535         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1536                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1537                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1538                 else
1539                         index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1540                 break;
1541         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1542         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1543                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1544                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1545                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1546                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1547                 else
1548                         index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1549                 break;
1550         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1551         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1552                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1553                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1554                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1555                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1556                 else
1557                         index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1558                 break;
1559         default:
1560                 return;
1561         }
1562
1563         switch (mode) {
1564         case DRM_MODE_DPMS_ON:
1565                 args.ucAction = ATOM_ENABLE;
1566                 /* workaround for DVOOutputControl on some RS690 systems */
1567                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1568                         u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1569                         WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1570                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1571                         WREG32(RADEON_BIOS_3_SCRATCH, reg);
1572                 } else
1573                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1574                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1575                         args.ucAction = ATOM_LCD_BLON;
1576                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1577                 }
1578                 break;
1579         case DRM_MODE_DPMS_STANDBY:
1580         case DRM_MODE_DPMS_SUSPEND:
1581         case DRM_MODE_DPMS_OFF:
1582                 args.ucAction = ATOM_DISABLE;
1583                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1584                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1585                         args.ucAction = ATOM_LCD_BLOFF;
1586                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1587                 }
1588                 break;
1589         }
1590 }
1591
1592 static void
1593 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1594 {
1595         struct drm_device *dev = encoder->dev;
1596         struct radeon_device *rdev = dev->dev_private;
1597         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1598         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1599         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1600         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1601         struct radeon_connector *radeon_connector = NULL;
1602         struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1603
1604         if (connector) {
1605                 radeon_connector = to_radeon_connector(connector);
1606                 radeon_dig_connector = radeon_connector->con_priv;
1607         }
1608
1609         switch (mode) {
1610         case DRM_MODE_DPMS_ON:
1611                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1612                         if (!connector)
1613                                 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1614                         else
1615                                 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1616
1617                         /* setup and enable the encoder */
1618                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1619                         atombios_dig_encoder_setup(encoder,
1620                                                    ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1621                                                    dig->panel_mode);
1622                         if (ext_encoder) {
1623                                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1624                                         atombios_external_encoder_setup(encoder, ext_encoder,
1625                                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1626                         }
1627                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1628                 } else if (ASIC_IS_DCE4(rdev)) {
1629                         /* setup and enable the encoder */
1630                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1631                         /* enable the transmitter */
1632                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1633                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1634                 } else {
1635                         /* setup and enable the encoder and transmitter */
1636                         atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1637                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1638                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1639                         /* some dce3.x boards have a bug in their transmitter control table.
1640                          * ACTION_ENABLE_OUTPUT can probably be dropped since ACTION_ENABLE
1641                          * does the same thing and more.
1642                          */
1643                         if ((rdev->family != CHIP_RV710) && (rdev->family != CHIP_RV730) &&
1644                             (rdev->family != CHIP_RS780) && (rdev->family != CHIP_RS880))
1645                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1646                 }
1647                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1648                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1649                                 atombios_set_edp_panel_power(connector,
1650                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
1651                                 radeon_dig_connector->edp_on = true;
1652                         }
1653                         radeon_dp_link_train(encoder, connector);
1654                         if (ASIC_IS_DCE4(rdev))
1655                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1656                 }
1657                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1658                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1659                 break;
1660         case DRM_MODE_DPMS_STANDBY:
1661         case DRM_MODE_DPMS_SUSPEND:
1662         case DRM_MODE_DPMS_OFF:
1663                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1664                         /* disable the transmitter */
1665                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1666                 } else if (ASIC_IS_DCE4(rdev)) {
1667                         /* disable the transmitter */
1668                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1669                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1670                 } else {
1671                         /* disable the encoder and transmitter */
1672                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1673                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1674                         atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1675                 }
1676                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1677                         if (ASIC_IS_DCE4(rdev))
1678                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1679                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1680                                 atombios_set_edp_panel_power(connector,
1681                                                              ATOM_TRANSMITTER_ACTION_POWER_OFF);
1682                                 radeon_dig_connector->edp_on = false;
1683                         }
1684                 }
1685                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1686                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1687                 break;
1688         }
1689 }
1690
1691 static void
1692 radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
1693                              struct drm_encoder *ext_encoder,
1694                              int mode)
1695 {
1696         struct drm_device *dev = encoder->dev;
1697         struct radeon_device *rdev = dev->dev_private;
1698
1699         switch (mode) {
1700         case DRM_MODE_DPMS_ON:
1701         default:
1702                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
1703                         atombios_external_encoder_setup(encoder, ext_encoder,
1704                                                         EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1705                         atombios_external_encoder_setup(encoder, ext_encoder,
1706                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1707                 } else
1708                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1709                 break;
1710         case DRM_MODE_DPMS_STANDBY:
1711         case DRM_MODE_DPMS_SUSPEND:
1712         case DRM_MODE_DPMS_OFF:
1713                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
1714                         atombios_external_encoder_setup(encoder, ext_encoder,
1715                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1716                         atombios_external_encoder_setup(encoder, ext_encoder,
1717                                                         EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1718                 } else
1719                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1720                 break;
1721         }
1722 }
1723
1724 static void
1725 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1726 {
1727         struct drm_device *dev = encoder->dev;
1728         struct radeon_device *rdev = dev->dev_private;
1729         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1730         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1731
1732         DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1733                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1734                   radeon_encoder->active_device);
1735         switch (radeon_encoder->encoder_id) {
1736         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1737         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1738         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1739         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1740         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1741         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1742         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1743         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1744                 radeon_atom_encoder_dpms_avivo(encoder, mode);
1745                 break;
1746         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1747         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1748         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1749         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1750                 radeon_atom_encoder_dpms_dig(encoder, mode);
1751                 break;
1752         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1753                 if (ASIC_IS_DCE5(rdev)) {
1754                         switch (mode) {
1755                         case DRM_MODE_DPMS_ON:
1756                                 atombios_dvo_setup(encoder, ATOM_ENABLE);
1757                                 break;
1758                         case DRM_MODE_DPMS_STANDBY:
1759                         case DRM_MODE_DPMS_SUSPEND:
1760                         case DRM_MODE_DPMS_OFF:
1761                                 atombios_dvo_setup(encoder, ATOM_DISABLE);
1762                                 break;
1763                         }
1764                 } else if (ASIC_IS_DCE3(rdev))
1765                         radeon_atom_encoder_dpms_dig(encoder, mode);
1766                 else
1767                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1768                 break;
1769         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1770         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1771                 if (ASIC_IS_DCE5(rdev)) {
1772                         switch (mode) {
1773                         case DRM_MODE_DPMS_ON:
1774                                 atombios_dac_setup(encoder, ATOM_ENABLE);
1775                                 break;
1776                         case DRM_MODE_DPMS_STANDBY:
1777                         case DRM_MODE_DPMS_SUSPEND:
1778                         case DRM_MODE_DPMS_OFF:
1779                                 atombios_dac_setup(encoder, ATOM_DISABLE);
1780                                 break;
1781                         }
1782                 } else
1783                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1784                 break;
1785         default:
1786                 return;
1787         }
1788
1789         if (ext_encoder)
1790                 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);
1791
1792         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1793
1794 }
1795
1796 union crtc_source_param {
1797         SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1798         SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1799 };
1800
1801 static void
1802 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1803 {
1804         struct drm_device *dev = encoder->dev;
1805         struct radeon_device *rdev = dev->dev_private;
1806         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1807         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1808         union crtc_source_param args;
1809         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1810         uint8_t frev, crev;
1811         struct radeon_encoder_atom_dig *dig;
1812
1813         memset(&args, 0, sizeof(args));
1814
1815         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1816                 return;
1817
1818         switch (frev) {
1819         case 1:
1820                 switch (crev) {
1821                 case 1:
1822                 default:
1823                         if (ASIC_IS_AVIVO(rdev))
1824                                 args.v1.ucCRTC = radeon_crtc->crtc_id;
1825                         else {
1826                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1827                                         args.v1.ucCRTC = radeon_crtc->crtc_id;
1828                                 } else {
1829                                         args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1830                                 }
1831                         }
1832                         switch (radeon_encoder->encoder_id) {
1833                         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1834                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1835                                 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1836                                 break;
1837                         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1838                         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1839                                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1840                                         args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1841                                 else
1842                                         args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1843                                 break;
1844                         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1845                         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1846                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1847                                 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1848                                 break;
1849                         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1850                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1851                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1852                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1853                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1854                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1855                                 else
1856                                         args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1857                                 break;
1858                         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1859                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1860                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1861                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1862                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1863                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1864                                 else
1865                                         args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1866                                 break;
1867                         }
1868                         break;
1869                 case 2:
1870                         args.v2.ucCRTC = radeon_crtc->crtc_id;
1871                         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1872                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1873
1874                                 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1875                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1876                                 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1877                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1878                                 else
1879                                         args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1880                         } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1881                                 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1882                         } else {
1883                                 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1884                         }
1885                         switch (radeon_encoder->encoder_id) {
1886                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1887                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1888                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1889                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1890                                 dig = radeon_encoder->enc_priv;
1891                                 switch (dig->dig_encoder) {
1892                                 case 0:
1893                                         args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1894                                         break;
1895                                 case 1:
1896                                         args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1897                                         break;
1898                                 case 2:
1899                                         args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1900                                         break;
1901                                 case 3:
1902                                         args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1903                                         break;
1904                                 case 4:
1905                                         args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1906                                         break;
1907                                 case 5:
1908                                         args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1909                                         break;
1910                                 }
1911                                 break;
1912                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1913                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1914                                 break;
1915                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1916                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1917                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1918                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1919                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1920                                 else
1921                                         args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1922                                 break;
1923                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1924                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1925                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1926                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1927                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1928                                 else
1929                                         args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1930                                 break;
1931                         }
1932                         break;
1933                 }
1934                 break;
1935         default:
1936                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1937                 return;
1938         }
1939
1940         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1941
1942         /* update scratch regs with new routing */
1943         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1944 }
1945
1946 static void
1947 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1948                               struct drm_display_mode *mode)
1949 {
1950         struct drm_device *dev = encoder->dev;
1951         struct radeon_device *rdev = dev->dev_private;
1952         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1953         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1954
1955         /* Funky macbooks */
1956         if ((dev->pdev->device == 0x71C5) &&
1957             (dev->pdev->subsystem_vendor == 0x106b) &&
1958             (dev->pdev->subsystem_device == 0x0080)) {
1959                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1960                         uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1961
1962                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1963                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1964
1965                         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1966                 }
1967         }
1968
1969         /* set scaler clears this on some chips */
1970         if (ASIC_IS_AVIVO(rdev) &&
1971             (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1972                 if (ASIC_IS_DCE4(rdev)) {
1973                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1974                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1975                                        EVERGREEN_INTERLEAVE_EN);
1976                         else
1977                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1978                 } else {
1979                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1980                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1981                                        AVIVO_D1MODE_INTERLEAVE_EN);
1982                         else
1983                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1984                 }
1985         }
1986 }
1987
1988 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1989 {
1990         struct drm_device *dev = encoder->dev;
1991         struct radeon_device *rdev = dev->dev_private;
1992         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1993         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1994         struct drm_encoder *test_encoder;
1995         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1996         uint32_t dig_enc_in_use = 0;
1997
1998         if (ASIC_IS_DCE6(rdev)) {
1999                 /* DCE6 */
2000                 switch (radeon_encoder->encoder_id) {
2001                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2002                         if (dig->linkb)
2003                                 return 1;
2004                         else
2005                                 return 0;
2006                         break;
2007                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2008                         if (dig->linkb)
2009                                 return 3;
2010                         else
2011                                 return 2;
2012                         break;
2013                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2014                         if (dig->linkb)
2015                                 return 5;
2016                         else
2017                                 return 4;
2018                         break;
2019                 }
2020         } else if (ASIC_IS_DCE4(rdev)) {
2021                 /* DCE4/5 */
2022                 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
2023                         /* ontario follows DCE4 */
2024                         if (rdev->family == CHIP_PALM) {
2025                                 if (dig->linkb)
2026                                         return 1;
2027                                 else
2028                                         return 0;
2029                         } else
2030                                 /* llano follows DCE3.2 */
2031                                 return radeon_crtc->crtc_id;
2032                 } else {
2033                         switch (radeon_encoder->encoder_id) {
2034                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2035                                 if (dig->linkb)
2036                                         return 1;
2037                                 else
2038                                         return 0;
2039                                 break;
2040                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2041                                 if (dig->linkb)
2042                                         return 3;
2043                                 else
2044                                         return 2;
2045                                 break;
2046                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2047                                 if (dig->linkb)
2048                                         return 5;
2049                                 else
2050                                         return 4;
2051                                 break;
2052                         }
2053                 }
2054         }
2055
2056         /* on DCE32 and encoder can driver any block so just crtc id */
2057         if (ASIC_IS_DCE32(rdev)) {
2058                 return radeon_crtc->crtc_id;
2059         }
2060
2061         /* on DCE3 - LVTMA can only be driven by DIGB */
2062         list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2063                 struct radeon_encoder *radeon_test_encoder;
2064
2065                 if (encoder == test_encoder)
2066                         continue;
2067
2068                 if (!radeon_encoder_is_digital(test_encoder))
2069                         continue;
2070
2071                 radeon_test_encoder = to_radeon_encoder(test_encoder);
2072                 dig = radeon_test_encoder->enc_priv;
2073
2074                 if (dig->dig_encoder >= 0)
2075                         dig_enc_in_use |= (1 << dig->dig_encoder);
2076         }
2077
2078         if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2079                 if (dig_enc_in_use & 0x2)
2080                         DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2081                 return 1;
2082         }
2083         if (!(dig_enc_in_use & 1))
2084                 return 0;
2085         return 1;
2086 }
2087
2088 /* This only needs to be called once at startup */
2089 void
2090 radeon_atom_encoder_init(struct radeon_device *rdev)
2091 {
2092         struct drm_device *dev = rdev->ddev;
2093         struct drm_encoder *encoder;
2094
2095         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2096                 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2097                 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2098
2099                 switch (radeon_encoder->encoder_id) {
2100                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2101                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2102                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2103                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2104                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2105                         break;
2106                 default:
2107                         break;
2108                 }
2109
2110                 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
2111                         atombios_external_encoder_setup(encoder, ext_encoder,
2112                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2113         }
2114 }
2115
2116 static void
2117 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2118                              struct drm_display_mode *mode,
2119                              struct drm_display_mode *adjusted_mode)
2120 {
2121         struct drm_device *dev = encoder->dev;
2122         struct radeon_device *rdev = dev->dev_private;
2123         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2124
2125         radeon_encoder->pixel_clock = adjusted_mode->clock;
2126
2127         /* need to call this here rather than in prepare() since we need some crtc info */
2128         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2129
2130         if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2131                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2132                         atombios_yuv_setup(encoder, true);
2133                 else
2134                         atombios_yuv_setup(encoder, false);
2135         }
2136
2137         switch (radeon_encoder->encoder_id) {
2138         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2139         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2140         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2141         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2142                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2143                 break;
2144         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2145         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2146         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2147         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2148                 /* handled in dpms */
2149                 break;
2150         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2151         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2152         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2153                 atombios_dvo_setup(encoder, ATOM_ENABLE);
2154                 break;
2155         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2156         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2157         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2158         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2159                 atombios_dac_setup(encoder, ATOM_ENABLE);
2160                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2161                         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2162                                 atombios_tv_setup(encoder, ATOM_ENABLE);
2163                         else
2164                                 atombios_tv_setup(encoder, ATOM_DISABLE);
2165                 }
2166                 break;
2167         }
2168
2169         atombios_apply_encoder_quirks(encoder, adjusted_mode);
2170
2171         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2172                 if (rdev->asic->display.hdmi_enable)
2173                         radeon_hdmi_enable(rdev, encoder, true);
2174                 if (rdev->asic->display.hdmi_setmode)
2175                         radeon_hdmi_setmode(rdev, encoder, adjusted_mode);
2176         }
2177 }
2178
2179 static bool
2180 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2181 {
2182         struct drm_device *dev = encoder->dev;
2183         struct radeon_device *rdev = dev->dev_private;
2184         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2185         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2186
2187         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2188                                        ATOM_DEVICE_CV_SUPPORT |
2189                                        ATOM_DEVICE_CRT_SUPPORT)) {
2190                 DAC_LOAD_DETECTION_PS_ALLOCATION args;
2191                 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2192                 uint8_t frev, crev;
2193
2194                 memset(&args, 0, sizeof(args));
2195
2196                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2197                         return false;
2198
2199                 args.sDacload.ucMisc = 0;
2200
2201                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2202                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2203                         args.sDacload.ucDacType = ATOM_DAC_A;
2204                 else
2205                         args.sDacload.ucDacType = ATOM_DAC_B;
2206
2207                 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2208                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2209                 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2210                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2211                 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2212                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2213                         if (crev >= 3)
2214                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2215                 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2216                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2217                         if (crev >= 3)
2218                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2219                 }
2220
2221                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2222
2223                 return true;
2224         } else
2225                 return false;
2226 }
2227
2228 static enum drm_connector_status
2229 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2230 {
2231         struct drm_device *dev = encoder->dev;
2232         struct radeon_device *rdev = dev->dev_private;
2233         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2234         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2235         uint32_t bios_0_scratch;
2236
2237         if (!atombios_dac_load_detect(encoder, connector)) {
2238                 DRM_DEBUG_KMS("detect returned false \n");
2239                 return connector_status_unknown;
2240         }
2241
2242         if (rdev->family >= CHIP_R600)
2243                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2244         else
2245                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2246
2247         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2248         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2249                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2250                         return connector_status_connected;
2251         }
2252         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2253                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2254                         return connector_status_connected;
2255         }
2256         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2257                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2258                         return connector_status_connected;
2259         }
2260         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2261                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2262                         return connector_status_connected; /* CTV */
2263                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2264                         return connector_status_connected; /* STV */
2265         }
2266         return connector_status_disconnected;
2267 }
2268
2269 static enum drm_connector_status
2270 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2271 {
2272         struct drm_device *dev = encoder->dev;
2273         struct radeon_device *rdev = dev->dev_private;
2274         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2275         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2276         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2277         u32 bios_0_scratch;
2278
2279         if (!ASIC_IS_DCE4(rdev))
2280                 return connector_status_unknown;
2281
2282         if (!ext_encoder)
2283                 return connector_status_unknown;
2284
2285         if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2286                 return connector_status_unknown;
2287
2288         /* load detect on the dp bridge */
2289         atombios_external_encoder_setup(encoder, ext_encoder,
2290                                         EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2291
2292         bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2293
2294         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2295         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2296                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2297                         return connector_status_connected;
2298         }
2299         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2300                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2301                         return connector_status_connected;
2302         }
2303         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2304                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2305                         return connector_status_connected;
2306         }
2307         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2308                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2309                         return connector_status_connected; /* CTV */
2310                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2311                         return connector_status_connected; /* STV */
2312         }
2313         return connector_status_disconnected;
2314 }
2315
2316 void
2317 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2318 {
2319         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2320
2321         if (ext_encoder)
2322                 /* ddc_setup on the dp bridge */
2323                 atombios_external_encoder_setup(encoder, ext_encoder,
2324                                                 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2325
2326 }
2327
2328 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2329 {
2330         struct radeon_device *rdev = encoder->dev->dev_private;
2331         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2332         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2333
2334         if ((radeon_encoder->active_device &
2335              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2336             (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2337              ENCODER_OBJECT_ID_NONE)) {
2338                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2339                 if (dig) {
2340                         dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
2341                         if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2342                                 if (rdev->family >= CHIP_R600)
2343                                         dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2344                                 else
2345                                         /* RS600/690/740 have only 1 afmt block */
2346                                         dig->afmt = rdev->mode_info.afmt[0];
2347                         }
2348                 }
2349         }
2350
2351         radeon_atom_output_lock(encoder, true);
2352
2353         if (connector) {
2354                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2355
2356                 /* select the clock/data port if it uses a router */
2357                 if (radeon_connector->router.cd_valid)
2358                         radeon_router_select_cd_port(radeon_connector);
2359
2360                 /* turn eDP panel on for mode set */
2361                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2362                         atombios_set_edp_panel_power(connector,
2363                                                      ATOM_TRANSMITTER_ACTION_POWER_ON);
2364         }
2365
2366         /* this is needed for the pll/ss setup to work correctly in some cases */
2367         atombios_set_encoder_crtc_source(encoder);
2368 }
2369
2370 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2371 {
2372         /* need to call this here as we need the crtc set up */
2373         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2374         radeon_atom_output_lock(encoder, false);
2375 }
2376
2377 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2378 {
2379         struct drm_device *dev = encoder->dev;
2380         struct radeon_device *rdev = dev->dev_private;
2381         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2382         struct radeon_encoder_atom_dig *dig;
2383
2384         /* check for pre-DCE3 cards with shared encoders;
2385          * can't really use the links individually, so don't disable
2386          * the encoder if it's in use by another connector
2387          */
2388         if (!ASIC_IS_DCE3(rdev)) {
2389                 struct drm_encoder *other_encoder;
2390                 struct radeon_encoder *other_radeon_encoder;
2391
2392                 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2393                         other_radeon_encoder = to_radeon_encoder(other_encoder);
2394                         if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2395                             drm_helper_encoder_in_use(other_encoder))
2396                                 goto disable_done;
2397                 }
2398         }
2399
2400         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2401
2402         switch (radeon_encoder->encoder_id) {
2403         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2404         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2405         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2406         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2407                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2408                 break;
2409         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2410         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2411         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2412         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2413                 /* handled in dpms */
2414                 break;
2415         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2416         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2417         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2418                 atombios_dvo_setup(encoder, ATOM_DISABLE);
2419                 break;
2420         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2421         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2422         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2423         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2424                 atombios_dac_setup(encoder, ATOM_DISABLE);
2425                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2426                         atombios_tv_setup(encoder, ATOM_DISABLE);
2427                 break;
2428         }
2429
2430 disable_done:
2431         if (radeon_encoder_is_digital(encoder)) {
2432                 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2433                         if (rdev->asic->display.hdmi_enable)
2434                                 radeon_hdmi_enable(rdev, encoder, false);
2435                 }
2436                 dig = radeon_encoder->enc_priv;
2437                 dig->dig_encoder = -1;
2438         }
2439         radeon_encoder->active_device = 0;
2440 }
2441
2442 /* these are handled by the primary encoders */
2443 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2444 {
2445
2446 }
2447
2448 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2449 {
2450
2451 }
2452
2453 static void
2454 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2455                          struct drm_display_mode *mode,
2456                          struct drm_display_mode *adjusted_mode)
2457 {
2458
2459 }
2460
2461 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2462 {
2463
2464 }
2465
2466 static void
2467 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2468 {
2469
2470 }
2471
2472 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2473                                        const struct drm_display_mode *mode,
2474                                        struct drm_display_mode *adjusted_mode)
2475 {
2476         return true;
2477 }
2478
2479 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2480         .dpms = radeon_atom_ext_dpms,
2481         .mode_fixup = radeon_atom_ext_mode_fixup,
2482         .prepare = radeon_atom_ext_prepare,
2483         .mode_set = radeon_atom_ext_mode_set,
2484         .commit = radeon_atom_ext_commit,
2485         .disable = radeon_atom_ext_disable,
2486         /* no detect for TMDS/LVDS yet */
2487 };
2488
2489 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2490         .dpms = radeon_atom_encoder_dpms,
2491         .mode_fixup = radeon_atom_mode_fixup,
2492         .prepare = radeon_atom_encoder_prepare,
2493         .mode_set = radeon_atom_encoder_mode_set,
2494         .commit = radeon_atom_encoder_commit,
2495         .disable = radeon_atom_encoder_disable,
2496         .detect = radeon_atom_dig_detect,
2497 };
2498
2499 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2500         .dpms = radeon_atom_encoder_dpms,
2501         .mode_fixup = radeon_atom_mode_fixup,
2502         .prepare = radeon_atom_encoder_prepare,
2503         .mode_set = radeon_atom_encoder_mode_set,
2504         .commit = radeon_atom_encoder_commit,
2505         .detect = radeon_atom_dac_detect,
2506 };
2507
2508 void radeon_enc_destroy(struct drm_encoder *encoder)
2509 {
2510         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2511         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2512                 radeon_atom_backlight_exit(radeon_encoder);
2513         kfree(radeon_encoder->enc_priv);
2514         drm_encoder_cleanup(encoder);
2515         kfree(radeon_encoder);
2516 }
2517
2518 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2519         .destroy = radeon_enc_destroy,
2520 };
2521
2522 static struct radeon_encoder_atom_dac *
2523 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2524 {
2525         struct drm_device *dev = radeon_encoder->base.dev;
2526         struct radeon_device *rdev = dev->dev_private;
2527         struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2528
2529         if (!dac)
2530                 return NULL;
2531
2532         dac->tv_std = radeon_atombios_get_tv_info(rdev);
2533         return dac;
2534 }
2535
2536 static struct radeon_encoder_atom_dig *
2537 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2538 {
2539         int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2540         struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2541
2542         if (!dig)
2543                 return NULL;
2544
2545         /* coherent mode by default */
2546         dig->coherent_mode = true;
2547         dig->dig_encoder = -1;
2548
2549         if (encoder_enum == 2)
2550                 dig->linkb = true;
2551         else
2552                 dig->linkb = false;
2553
2554         return dig;
2555 }
2556
2557 void
2558 radeon_add_atom_encoder(struct drm_device *dev,
2559                         uint32_t encoder_enum,
2560                         uint32_t supported_device,
2561                         u16 caps)
2562 {
2563         struct radeon_device *rdev = dev->dev_private;
2564         struct drm_encoder *encoder;
2565         struct radeon_encoder *radeon_encoder;
2566
2567         /* see if we already added it */
2568         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2569                 radeon_encoder = to_radeon_encoder(encoder);
2570                 if (radeon_encoder->encoder_enum == encoder_enum) {
2571                         radeon_encoder->devices |= supported_device;
2572                         return;
2573                 }
2574
2575         }
2576
2577         /* add a new one */
2578         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2579         if (!radeon_encoder)
2580                 return;
2581
2582         encoder = &radeon_encoder->base;
2583         switch (rdev->num_crtc) {
2584         case 1:
2585                 encoder->possible_crtcs = 0x1;
2586                 break;
2587         case 2:
2588         default:
2589                 encoder->possible_crtcs = 0x3;
2590                 break;
2591         case 4:
2592                 encoder->possible_crtcs = 0xf;
2593                 break;
2594         case 6:
2595                 encoder->possible_crtcs = 0x3f;
2596                 break;
2597         }
2598
2599         radeon_encoder->enc_priv = NULL;
2600
2601         radeon_encoder->encoder_enum = encoder_enum;
2602         radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2603         radeon_encoder->devices = supported_device;
2604         radeon_encoder->rmx_type = RMX_OFF;
2605         radeon_encoder->underscan_type = UNDERSCAN_OFF;
2606         radeon_encoder->is_ext_encoder = false;
2607         radeon_encoder->caps = caps;
2608
2609         switch (radeon_encoder->encoder_id) {
2610         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2611         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2612         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2613         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2614                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2615                         radeon_encoder->rmx_type = RMX_FULL;
2616                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2617                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2618                 } else {
2619                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2620                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2621                 }
2622                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2623                 break;
2624         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2625                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2626                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2627                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2628                 break;
2629         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2630         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2631         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2632                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2633                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2634                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2635                 break;
2636         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2637         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2638         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2639         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2640         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2641         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2642         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2643                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2644                         radeon_encoder->rmx_type = RMX_FULL;
2645                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2646                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2647                 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2648                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2649                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2650                 } else {
2651                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2652                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2653                 }
2654                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2655                 break;
2656         case ENCODER_OBJECT_ID_SI170B:
2657         case ENCODER_OBJECT_ID_CH7303:
2658         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2659         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2660         case ENCODER_OBJECT_ID_TITFP513:
2661         case ENCODER_OBJECT_ID_VT1623:
2662         case ENCODER_OBJECT_ID_HDMI_SI1930:
2663         case ENCODER_OBJECT_ID_TRAVIS:
2664         case ENCODER_OBJECT_ID_NUTMEG:
2665                 /* these are handled by the primary encoders */
2666                 radeon_encoder->is_ext_encoder = true;
2667                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2668                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2669                 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2670                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2671                 else
2672                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2673                 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2674                 break;
2675         }
2676 }