2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
28 #include <drm/radeon_drm.h>
32 #include "atom-bits.h"
33 #include <drm/drm_dp_helper.h>
35 /* move these to drm_dp_helper.c/h */
36 #define DP_LINK_CONFIGURATION_SIZE 9
37 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
39 static char *voltage_names[] = {
40 "0.4V", "0.6V", "0.8V", "1.2V"
42 static char *pre_emph_names[] = {
43 "0dB", "3.5dB", "6dB", "9.5dB"
46 /***** radeon AUX functions *****/
48 /* Atom needs data in little endian format
49 * so swap as appropriate when copying data to
50 * or from atom. Note that atom operates on
53 void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
56 u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */
60 memcpy(src_tmp, src, num_bytes);
61 src32 = (u32 *)src_tmp;
62 dst32 = (u32 *)dst_tmp;
64 for (i = 0; i < ((num_bytes + 3) / 4); i++)
65 dst32[i] = cpu_to_le32(src32[i]);
66 memcpy(dst, dst_tmp, num_bytes);
68 u8 dws = num_bytes & ~3;
69 for (i = 0; i < ((num_bytes + 3) / 4); i++)
70 dst32[i] = le32_to_cpu(src32[i]);
71 memcpy(dst, dst_tmp, dws);
73 for (i = 0; i < (num_bytes % 4); i++)
74 dst[dws+i] = dst_tmp[dws+i];
78 memcpy(dst, src, num_bytes);
82 union aux_channel_transaction {
83 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
84 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
87 static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
88 u8 *send, int send_bytes,
89 u8 *recv, int recv_size,
92 struct drm_device *dev = chan->dev;
93 struct radeon_device *rdev = dev->dev_private;
94 union aux_channel_transaction args;
95 int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
99 memset(&args, 0, sizeof(args));
101 base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1);
103 radeon_atom_copy_swap(base, send, send_bytes, true);
105 args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4));
106 args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4));
107 args.v1.ucDataOutLen = 0;
108 args.v1.ucChannelID = chan->rec.i2c_id;
109 args.v1.ucDelay = delay / 10;
110 if (ASIC_IS_DCE4(rdev))
111 args.v2.ucHPD_ID = chan->rec.hpd;
113 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
115 *ack = args.v1.ucReplyStatus;
118 if (args.v1.ucReplyStatus == 1) {
119 DRM_DEBUG_KMS("dp_aux_ch timeout\n");
124 if (args.v1.ucReplyStatus == 2) {
125 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
130 if (args.v1.ucReplyStatus == 3) {
131 DRM_DEBUG_KMS("dp_aux_ch error\n");
135 recv_bytes = args.v1.ucDataOutLen;
136 if (recv_bytes > recv_size)
137 recv_bytes = recv_size;
139 if (recv && recv_size)
140 radeon_atom_copy_swap(recv, base + 16, recv_bytes, false);
145 static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector,
146 u16 address, u8 *send, u8 send_bytes, u8 delay)
148 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
151 int msg_bytes = send_bytes + 4;
159 msg[1] = address >> 8;
160 msg[2] = AUX_NATIVE_WRITE << 4;
161 msg[3] = (msg_bytes << 4) | (send_bytes - 1);
162 memcpy(&msg[4], send, send_bytes);
164 for (retry = 0; retry < 4; retry++) {
165 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
166 msg, msg_bytes, NULL, 0, delay, &ack);
171 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
173 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
182 static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
183 u16 address, u8 *recv, int recv_bytes, u8 delay)
185 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
193 msg[1] = address >> 8;
194 msg[2] = AUX_NATIVE_READ << 4;
195 msg[3] = (msg_bytes << 4) | (recv_bytes - 1);
197 for (retry = 0; retry < 4; retry++) {
198 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
199 msg, msg_bytes, recv, recv_bytes, delay, &ack);
204 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
206 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
217 static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector,
220 radeon_dp_aux_native_write(radeon_connector, reg, &val, 1, 0);
223 static u8 radeon_read_dpcd_reg(struct radeon_connector *radeon_connector,
228 radeon_dp_aux_native_read(radeon_connector, reg, &val, 1, 0);
233 int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
234 u8 write_byte, u8 *read_byte)
236 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
237 struct radeon_i2c_chan *auxch = (struct radeon_i2c_chan *)adapter;
238 u16 address = algo_data->address;
247 /* Set up the command byte */
248 if (mode & MODE_I2C_READ)
249 msg[2] = AUX_I2C_READ << 4;
251 msg[2] = AUX_I2C_WRITE << 4;
253 if (!(mode & MODE_I2C_STOP))
254 msg[2] |= AUX_I2C_MOT << 4;
257 msg[1] = address >> 8;
262 msg[3] = msg_bytes << 4;
267 msg[3] = msg_bytes << 4;
275 for (retry = 0; retry < 4; retry++) {
276 ret = radeon_process_aux_ch(auxch,
277 msg, msg_bytes, reply, reply_bytes, 0, &ack);
281 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
285 switch (ack & AUX_NATIVE_REPLY_MASK) {
286 case AUX_NATIVE_REPLY_ACK:
287 /* I2C-over-AUX Reply field is only valid
288 * when paired with AUX ACK.
291 case AUX_NATIVE_REPLY_NACK:
292 DRM_DEBUG_KMS("aux_ch native nack\n");
294 case AUX_NATIVE_REPLY_DEFER:
295 DRM_DEBUG_KMS("aux_ch native defer\n");
299 DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack);
303 switch (ack & AUX_I2C_REPLY_MASK) {
304 case AUX_I2C_REPLY_ACK:
305 if (mode == MODE_I2C_READ)
306 *read_byte = reply[0];
308 case AUX_I2C_REPLY_NACK:
309 DRM_DEBUG_KMS("aux_i2c nack\n");
311 case AUX_I2C_REPLY_DEFER:
312 DRM_DEBUG_KMS("aux_i2c defer\n");
316 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack);
321 DRM_DEBUG_KMS("aux i2c too many retries, giving up\n");
325 /***** general DP utility functions *****/
327 #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200
328 #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5
330 static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
338 for (lane = 0; lane < lane_count; lane++) {
339 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
340 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
342 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
344 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
345 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
353 if (v >= DP_VOLTAGE_MAX)
354 v |= DP_TRAIN_MAX_SWING_REACHED;
356 if (p >= DP_PRE_EMPHASIS_MAX)
357 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
359 DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
360 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
361 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
363 for (lane = 0; lane < 4; lane++)
364 train_set[lane] = v | p;
367 /* convert bits per color to bits per pixel */
368 /* get bpc from the EDID */
369 static int convert_bpc_to_bpp(int bpc)
377 /* get the max pix clock supported by the link rate and lane num */
378 static int dp_get_max_dp_pix_clock(int link_rate,
382 return (link_rate * lane_num * 8) / bpp;
385 /***** radeon specific DP functions *****/
387 static int radeon_dp_get_max_link_rate(struct drm_connector *connector,
388 u8 dpcd[DP_DPCD_SIZE])
392 if (radeon_connector_is_dp12_capable(connector))
393 max_link_rate = min(drm_dp_max_link_rate(dpcd), 540000);
395 max_link_rate = min(drm_dp_max_link_rate(dpcd), 270000);
397 return max_link_rate;
400 /* First get the min lane# when low rate is used according to pixel clock
401 * (prefer low rate), second check max lane# supported by DP panel,
402 * if the max lane# < low rate lane# then use max lane# instead.
404 static int radeon_dp_get_dp_lane_number(struct drm_connector *connector,
405 u8 dpcd[DP_DPCD_SIZE],
408 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
409 int max_link_rate = radeon_dp_get_max_link_rate(connector, dpcd);
410 int max_lane_num = drm_dp_max_lane_count(dpcd);
412 int max_dp_pix_clock;
414 for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) {
415 max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp);
416 if (pix_clock <= max_dp_pix_clock)
423 static int radeon_dp_get_dp_link_clock(struct drm_connector *connector,
424 u8 dpcd[DP_DPCD_SIZE],
427 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
428 int lane_num, max_pix_clock;
430 if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
431 ENCODER_OBJECT_ID_NUTMEG)
434 lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock);
435 max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp);
436 if (pix_clock <= max_pix_clock)
438 max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp);
439 if (pix_clock <= max_pix_clock)
441 if (radeon_connector_is_dp12_capable(connector)) {
442 max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp);
443 if (pix_clock <= max_pix_clock)
447 return radeon_dp_get_max_link_rate(connector, dpcd);
450 static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
451 int action, int dp_clock,
452 u8 ucconfig, u8 lane_num)
454 DP_ENCODER_SERVICE_PARAMETERS args;
455 int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
457 memset(&args, 0, sizeof(args));
458 args.ucLinkClock = dp_clock / 10;
459 args.ucConfig = ucconfig;
460 args.ucAction = action;
461 args.ucLaneNum = lane_num;
464 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
465 return args.ucStatus;
468 u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
470 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
471 struct drm_device *dev = radeon_connector->base.dev;
472 struct radeon_device *rdev = dev->dev_private;
474 return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
475 dig_connector->dp_i2c_bus->rec.i2c_id, 0);
478 static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector)
480 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
483 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
486 if (radeon_dp_aux_native_read(radeon_connector, DP_SINK_OUI, buf, 3, 0))
487 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
488 buf[0], buf[1], buf[2]);
490 if (radeon_dp_aux_native_read(radeon_connector, DP_BRANCH_OUI, buf, 3, 0))
491 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
492 buf[0], buf[1], buf[2]);
495 bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
497 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
498 u8 msg[DP_DPCD_SIZE];
501 ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, msg,
504 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
505 DRM_DEBUG_KMS("DPCD: ");
506 for (i = 0; i < DP_DPCD_SIZE; i++)
507 DRM_DEBUG_KMS("%02x ", msg[i]);
510 radeon_dp_probe_oui(radeon_connector);
514 dig_connector->dpcd[0] = 0;
518 int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
519 struct drm_connector *connector)
521 struct drm_device *dev = encoder->dev;
522 struct radeon_device *rdev = dev->dev_private;
523 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
524 int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
525 u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector);
528 if (!ASIC_IS_DCE4(rdev))
531 if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
532 /* DP bridge chips */
533 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);
535 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
536 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
537 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
538 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
540 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
541 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
543 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);
545 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
551 void radeon_dp_set_link_config(struct drm_connector *connector,
552 const struct drm_display_mode *mode)
554 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
555 struct radeon_connector_atom_dig *dig_connector;
557 if (!radeon_connector->con_priv)
559 dig_connector = radeon_connector->con_priv;
561 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
562 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
563 dig_connector->dp_clock =
564 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
565 dig_connector->dp_lane_count =
566 radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock);
570 int radeon_dp_mode_valid_helper(struct drm_connector *connector,
571 struct drm_display_mode *mode)
573 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
574 struct radeon_connector_atom_dig *dig_connector;
577 if ((mode->clock > 340000) &&
578 (!radeon_connector_is_dp12_capable(connector)))
579 return MODE_CLOCK_HIGH;
581 if (!radeon_connector->con_priv)
582 return MODE_CLOCK_HIGH;
583 dig_connector = radeon_connector->con_priv;
586 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
588 if ((dp_clock == 540000) &&
589 (!radeon_connector_is_dp12_capable(connector)))
590 return MODE_CLOCK_HIGH;
595 static bool radeon_dp_get_link_status(struct radeon_connector *radeon_connector,
596 u8 link_status[DP_LINK_STATUS_SIZE])
599 ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS,
600 link_status, DP_LINK_STATUS_SIZE, 100);
605 DRM_DEBUG_KMS("link status %*ph\n", 6, link_status);
609 bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
611 u8 link_status[DP_LINK_STATUS_SIZE];
612 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
614 if (!radeon_dp_get_link_status(radeon_connector, link_status))
616 if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
621 struct radeon_dp_link_train_info {
622 struct radeon_device *rdev;
623 struct drm_encoder *encoder;
624 struct drm_connector *connector;
625 struct radeon_connector *radeon_connector;
630 u8 dpcd[DP_RECEIVER_CAP_SIZE];
632 u8 link_status[DP_LINK_STATUS_SIZE];
637 static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)
639 /* set the initial vs/emph on the source */
640 atombios_dig_transmitter_setup(dp_info->encoder,
641 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
642 0, dp_info->train_set[0]); /* sets all lanes at once */
644 /* set the vs/emph on the sink */
645 radeon_dp_aux_native_write(dp_info->radeon_connector, DP_TRAINING_LANE0_SET,
646 dp_info->train_set, dp_info->dp_lane_count, 0);
649 static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
653 /* set training pattern on the source */
654 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) {
656 case DP_TRAINING_PATTERN_1:
657 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
659 case DP_TRAINING_PATTERN_2:
660 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
662 case DP_TRAINING_PATTERN_3:
663 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
666 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);
669 case DP_TRAINING_PATTERN_1:
672 case DP_TRAINING_PATTERN_2:
676 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
677 dp_info->dp_clock, dp_info->enc_id, rtp);
680 /* enable training pattern on the sink */
681 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_TRAINING_PATTERN_SET, tp);
684 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
686 struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder);
687 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
690 /* power up the sink */
691 if (dp_info->dpcd[0] >= 0x11)
692 radeon_write_dpcd_reg(dp_info->radeon_connector,
693 DP_SET_POWER, DP_SET_POWER_D0);
695 /* possibly enable downspread on the sink */
696 if (dp_info->dpcd[3] & 0x1)
697 radeon_write_dpcd_reg(dp_info->radeon_connector,
698 DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
700 radeon_write_dpcd_reg(dp_info->radeon_connector,
701 DP_DOWNSPREAD_CTRL, 0);
703 if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) &&
704 (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) {
705 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_EDP_CONFIGURATION_SET, 1);
708 /* set the lane count on the sink */
709 tmp = dp_info->dp_lane_count;
710 if (dp_info->dpcd[DP_DPCD_REV] >= 0x11 &&
711 dp_info->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)
712 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
713 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LANE_COUNT_SET, tmp);
715 /* set the link rate on the sink */
716 tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
717 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LINK_BW_SET, tmp);
719 /* start training on the source */
720 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
721 atombios_dig_encoder_setup(dp_info->encoder,
722 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
724 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,
725 dp_info->dp_clock, dp_info->enc_id, 0);
727 /* disable the training pattern on the sink */
728 radeon_write_dpcd_reg(dp_info->radeon_connector,
729 DP_TRAINING_PATTERN_SET,
730 DP_TRAINING_PATTERN_DISABLE);
735 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info)
739 /* disable the training pattern on the sink */
740 radeon_write_dpcd_reg(dp_info->radeon_connector,
741 DP_TRAINING_PATTERN_SET,
742 DP_TRAINING_PATTERN_DISABLE);
744 /* disable the training pattern on the source */
745 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
746 atombios_dig_encoder_setup(dp_info->encoder,
747 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
749 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
750 dp_info->dp_clock, dp_info->enc_id, 0);
755 static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)
761 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
762 memset(dp_info->train_set, 0, 4);
763 radeon_dp_update_vs_emph(dp_info);
767 /* clock recovery loop */
768 clock_recovery = false;
772 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
774 if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) {
775 DRM_ERROR("displayport link status failed\n");
779 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
780 clock_recovery = true;
784 for (i = 0; i < dp_info->dp_lane_count; i++) {
785 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
788 if (i == dp_info->dp_lane_count) {
789 DRM_ERROR("clock recovery reached max voltage\n");
793 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
795 if (dp_info->tries == 5) {
796 DRM_ERROR("clock recovery tried 5 times\n");
802 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
804 /* Compute new train_set as requested by sink */
805 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
807 radeon_dp_update_vs_emph(dp_info);
809 if (!clock_recovery) {
810 DRM_ERROR("clock recovery failed\n");
813 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
814 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
815 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
816 DP_TRAIN_PRE_EMPHASIS_SHIFT);
821 static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info)
825 if (dp_info->tp3_supported)
826 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
828 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
830 /* channel equalization loop */
834 drm_dp_link_train_channel_eq_delay(dp_info->dpcd);
836 if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) {
837 DRM_ERROR("displayport link status failed\n");
841 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
847 if (dp_info->tries > 5) {
848 DRM_ERROR("channel eq failed: 5 tries\n");
852 /* Compute new train_set as requested by sink */
853 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
855 radeon_dp_update_vs_emph(dp_info);
860 DRM_ERROR("channel eq failed\n");
863 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
864 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
865 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
866 >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
871 void radeon_dp_link_train(struct drm_encoder *encoder,
872 struct drm_connector *connector)
874 struct drm_device *dev = encoder->dev;
875 struct radeon_device *rdev = dev->dev_private;
876 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
877 struct radeon_encoder_atom_dig *dig;
878 struct radeon_connector *radeon_connector;
879 struct radeon_connector_atom_dig *dig_connector;
880 struct radeon_dp_link_train_info dp_info;
884 if (!radeon_encoder->enc_priv)
886 dig = radeon_encoder->enc_priv;
888 radeon_connector = to_radeon_connector(connector);
889 if (!radeon_connector->con_priv)
891 dig_connector = radeon_connector->con_priv;
893 if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
894 (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
897 /* DPEncoderService newer than 1.1 can't program properly the
898 * training pattern. When facing such version use the
899 * DIGXEncoderControl (X== 1 | 2)
901 dp_info.use_dpencoder = true;
902 index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
903 if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) {
905 dp_info.use_dpencoder = false;
910 if (dig->dig_encoder)
911 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
913 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
915 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B;
917 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
919 tmp = radeon_read_dpcd_reg(radeon_connector, DP_MAX_LANE_COUNT);
920 if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
921 dp_info.tp3_supported = true;
923 dp_info.tp3_supported = false;
925 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
927 dp_info.encoder = encoder;
928 dp_info.connector = connector;
929 dp_info.radeon_connector = radeon_connector;
930 dp_info.dp_lane_count = dig_connector->dp_lane_count;
931 dp_info.dp_clock = dig_connector->dp_clock;
933 if (radeon_dp_link_train_init(&dp_info))
935 if (radeon_dp_link_train_cr(&dp_info))
937 if (radeon_dp_link_train_ce(&dp_info))
940 if (radeon_dp_link_train_finish(&dp_info))