drivers/gpu/drm/radeon/atombios_dp.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include "atom-bits.h"
  32 #include "drm_dp_helper.h"
  33
  34 /* move these to drm_dp_helper.c/h */
  35 #define DP_LINK_CONFIGURATION_SIZE 9
  36 #define DP_LINK_STATUS_SIZE        6
  37 #define DP_DPCD_SIZE               8
  38
  39 static char *voltage_names[] = {
  40         "0.4V", "0.6V", "0.8V", "1.2V"
  41 };
  42 static char *pre_emph_names[] = {
  43         "0dB", "3.5dB", "6dB", "9.5dB"
  44 };
  45
  46 /***** radeon AUX functions *****/
  47 union aux_channel_transaction {
  48         PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
  49         PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
  50 };
  51
  52 static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
  53                                  u8 *send, int send_bytes,
  54                                  u8 *recv, int recv_size,
  55                                  u8 delay, u8 *ack)
  56 {
  57         struct drm_device *dev = chan->dev;
  58         struct radeon_device *rdev = dev->dev_private;
  59         union aux_channel_transaction args;
  60         int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
  61         unsigned char *base;
  62         int recv_bytes;
  63
  64         memset(&args, 0, sizeof(args));
  65
  66         base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1);
  67
  68         memcpy(base, send, send_bytes);
  69
  70         args.v1.lpAuxRequest = 0 + 4;
  71         args.v1.lpDataOut = 16 + 4;
  72         args.v1.ucDataOutLen = 0;
  73         args.v1.ucChannelID = chan->rec.i2c_id;
  74         args.v1.ucDelay = delay / 10;
  75         if (ASIC_IS_DCE4(rdev))
  76                 args.v2.ucHPD_ID = chan->rec.hpd;
  77
  78         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  79
  80         *ack = args.v1.ucReplyStatus;
  81
  82         /* timeout */
  83         if (args.v1.ucReplyStatus == 1) {
  84                 DRM_DEBUG_KMS("dp_aux_ch timeout\n");
  85                 return -ETIMEDOUT;
  86         }
  87
  88         /* flags not zero */
  89         if (args.v1.ucReplyStatus == 2) {
  90                 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
  91                 return -EBUSY;
  92         }
  93
  94         /* error */
  95         if (args.v1.ucReplyStatus == 3) {
  96                 DRM_DEBUG_KMS("dp_aux_ch error\n");
  97                 return -EIO;
  98         }
  99
 100         recv_bytes = args.v1.ucDataOutLen;
 101         if (recv_bytes > recv_size)
 102                 recv_bytes = recv_size;
 103
 104         if (recv && recv_size)
 105                 memcpy(recv, base + 16, recv_bytes);
 106
 107         return recv_bytes;
 108 }
 109
 110 static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector,
 111                                       u16 address, u8 *send, u8 send_bytes, u8 delay)
 112 {
 113         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 114         int ret;
 115         u8 msg[20];
 116         int msg_bytes = send_bytes + 4;
 117         u8 ack;
 118         unsigned retry;
 119
 120         if (send_bytes > 16)
 121                 return -1;
 122
 123         msg[0] = address;
 124         msg[1] = address >> 8;
 125         msg[2] = AUX_NATIVE_WRITE << 4;
 126         msg[3] = (msg_bytes << 4) | (send_bytes - 1);
 127         memcpy(&msg[4], send, send_bytes);
 128
 129         for (retry = 0; retry < 4; retry++) {
 130                 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
 131                                             msg, msg_bytes, NULL, 0, delay, &ack);
 132                 if (ret == -EBUSY)
 133                         continue;
 134                 else if (ret < 0)
 135                         return ret;
 136                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 137                         return send_bytes;
 138                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 139                         udelay(400);
 140                 else
 141                         return -EIO;
 142         }
 143
 144         return -EIO;
 145 }
 146
 147 static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
 148                                      u16 address, u8 *recv, int recv_bytes, u8 delay)
 149 {
 150         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 151         u8 msg[4];
 152         int msg_bytes = 4;
 153         u8 ack;
 154         int ret;
 155         unsigned retry;
 156
 157         msg[0] = address;
 158         msg[1] = address >> 8;
 159         msg[2] = AUX_NATIVE_READ << 4;
 160         msg[3] = (msg_bytes << 4) | (recv_bytes - 1);
 161
 162         for (retry = 0; retry < 4; retry++) {
 163                 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
 164                                             msg, msg_bytes, recv, recv_bytes, delay, &ack);
 165                 if (ret == -EBUSY)
 166                         continue;
 167                 else if (ret < 0)
 168                         return ret;
 169                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 170                         return ret;
 171                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 172                         udelay(400);
 173                 else if (ret == 0)
 174                         return -EPROTO;
 175                 else
 176                         return -EIO;
 177         }
 178
 179         return -EIO;
 180 }
 181
 182 static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector,
 183                                  u16 reg, u8 val)
 184 {
 185         radeon_dp_aux_native_write(radeon_connector, reg, &val, 1, 0);
 186 }
 187
 188 static u8 radeon_read_dpcd_reg(struct radeon_connector *radeon_connector,
 189                                u16 reg)
 190 {
 191         u8 val = 0;
 192
 193         radeon_dp_aux_native_read(radeon_connector, reg, &val, 1, 0);
 194
 195         return val;
 196 }
 197
 198 int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 199                          u8 write_byte, u8 *read_byte)
 200 {
 201         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 202         struct radeon_i2c_chan *auxch = (struct radeon_i2c_chan *)adapter;
 203         u16 address = algo_data->address;
 204         u8 msg[5];
 205         u8 reply[2];
 206         unsigned retry;
 207         int msg_bytes;
 208         int reply_bytes = 1;
 209         int ret;
 210         u8 ack;
 211
 212         /* Set up the command byte */
 213         if (mode & MODE_I2C_READ)
 214                 msg[2] = AUX_I2C_READ << 4;
 215         else
 216                 msg[2] = AUX_I2C_WRITE << 4;
 217
 218         if (!(mode & MODE_I2C_STOP))
 219                 msg[2] |= AUX_I2C_MOT << 4;
 220
 221         msg[0] = address;
 222         msg[1] = address >> 8;
 223
 224         switch (mode) {
 225         case MODE_I2C_WRITE:
 226                 msg_bytes = 5;
 227                 msg[3] = msg_bytes << 4;
 228                 msg[4] = write_byte;
 229                 break;
 230         case MODE_I2C_READ:
 231                 msg_bytes = 4;
 232                 msg[3] = msg_bytes << 4;
 233                 break;
 234         default:
 235                 msg_bytes = 4;
 236                 msg[3] = 3 << 4;
 237                 break;
 238         }
 239
 240         for (retry = 0; retry < 4; retry++) {
 241                 ret = radeon_process_aux_ch(auxch,
 242                                             msg, msg_bytes, reply, reply_bytes, 0, &ack);
 243                 if (ret == -EBUSY)
 244                         continue;
 245                 else if (ret < 0) {
 246                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 247                         return ret;
 248                 }
 249
 250                 switch (ack & AUX_NATIVE_REPLY_MASK) {
 251                 case AUX_NATIVE_REPLY_ACK:
 252                         /* I2C-over-AUX Reply field is only valid
 253                          * when paired with AUX ACK.
 254                          */
 255                         break;
 256                 case AUX_NATIVE_REPLY_NACK:
 257                         DRM_DEBUG_KMS("aux_ch native nack\n");
 258                         return -EREMOTEIO;
 259                 case AUX_NATIVE_REPLY_DEFER:
 260                         DRM_DEBUG_KMS("aux_ch native defer\n");
 261                         udelay(400);
 262                         continue;
 263                 default:
 264                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack);
 265                         return -EREMOTEIO;
 266                 }
 267
 268                 switch (ack & AUX_I2C_REPLY_MASK) {
 269                 case AUX_I2C_REPLY_ACK:
 270                         if (mode == MODE_I2C_READ)
 271                                 *read_byte = reply[0];
 272                         return ret;
 273                 case AUX_I2C_REPLY_NACK:
 274                         DRM_DEBUG_KMS("aux_i2c nack\n");
 275                         return -EREMOTEIO;
 276                 case AUX_I2C_REPLY_DEFER:
 277                         DRM_DEBUG_KMS("aux_i2c defer\n");
 278                         udelay(400);
 279                         break;
 280                 default:
 281                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack);
 282                         return -EREMOTEIO;
 283                 }
 284         }
 285
 286         DRM_DEBUG_KMS("aux i2c too many retries, giving up\n");
 287         return -EREMOTEIO;
 288 }
 289
 290 /***** general DP utility functions *****/
 291
 292 static u8 dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r)
 293 {
 294         return link_status[r - DP_LANE0_1_STATUS];
 295 }
 296
 297 static u8 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE],
 298                              int lane)
 299 {
 300         int i = DP_LANE0_1_STATUS + (lane >> 1);
 301         int s = (lane & 1) * 4;
 302         u8 l = dp_link_status(link_status, i);
 303         return (l >> s) & 0xf;
 304 }
 305
 306 static bool dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
 307                                  int lane_count)
 308 {
 309         int lane;
 310         u8 lane_status;
 311
 312         for (lane = 0; lane < lane_count; lane++) {
 313                 lane_status = dp_get_lane_status(link_status, lane);
 314                 if ((lane_status & DP_LANE_CR_DONE) == 0)
 315                         return false;
 316         }
 317         return true;
 318 }
 319
 320 static bool dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
 321                              int lane_count)
 322 {
 323         u8 lane_align;
 324         u8 lane_status;
 325         int lane;
 326
 327         lane_align = dp_link_status(link_status,
 328                                     DP_LANE_ALIGN_STATUS_UPDATED);
 329         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
 330                 return false;
 331         for (lane = 0; lane < lane_count; lane++) {
 332                 lane_status = dp_get_lane_status(link_status, lane);
 333                 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
 334                         return false;
 335         }
 336         return true;
 337 }
 338
 339 static u8 dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE],
 340                                         int lane)
 341
 342 {
 343         int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
 344         int s = ((lane & 1) ?
 345                  DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
 346                  DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
 347         u8 l = dp_link_status(link_status, i);
 348
 349         return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
 350 }
 351
 352 static u8 dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],
 353                                              int lane)
 354 {
 355         int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
 356         int s = ((lane & 1) ?
 357                  DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
 358                  DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
 359         u8 l = dp_link_status(link_status, i);
 360
 361         return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
 362 }
 363
 364 #define DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_1200
 365 #define DP_PRE_EMPHASIS_MAX    DP_TRAIN_PRE_EMPHASIS_9_5
 366
 367 static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
 368                                 int lane_count,
 369                                 u8 train_set[4])
 370 {
 371         u8 v = 0;
 372         u8 p = 0;
 373         int lane;
 374
 375         for (lane = 0; lane < lane_count; lane++) {
 376                 u8 this_v = dp_get_adjust_request_voltage(link_status, lane);
 377                 u8 this_p = dp_get_adjust_request_pre_emphasis(link_status, lane);
 378
 379                 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
 380                           lane,
 381                           voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
 382                           pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
 383
 384                 if (this_v > v)
 385                         v = this_v;
 386                 if (this_p > p)
 387                         p = this_p;
 388         }
 389
 390         if (v >= DP_VOLTAGE_MAX)
 391                 v |= DP_TRAIN_MAX_SWING_REACHED;
 392
 393         if (p >= DP_PRE_EMPHASIS_MAX)
 394                 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 395
 396         DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
 397                   voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
 398                   pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
 399
 400         for (lane = 0; lane < 4; lane++)
 401                 train_set[lane] = v | p;
 402 }
 403
 404 /* convert bits per color to bits per pixel */
 405 /* get bpc from the EDID */
 406 static int convert_bpc_to_bpp(int bpc)
 407 {
 408         if (bpc == 0)
 409                 return 24;
 410         else
 411                 return bpc * 3;
 412 }
 413
 414 /* get the max pix clock supported by the link rate and lane num */
 415 static int dp_get_max_dp_pix_clock(int link_rate,
 416                                    int lane_num,
 417                                    int bpp)
 418 {
 419         return (link_rate * lane_num * 8) / bpp;
 420 }
 421
 422 static int dp_get_max_link_rate(u8 dpcd[DP_DPCD_SIZE])
 423 {
 424         switch (dpcd[DP_MAX_LINK_RATE]) {
 425         case DP_LINK_BW_1_62:
 426         default:
 427                 return 162000;
 428         case DP_LINK_BW_2_7:
 429                 return 270000;
 430         case DP_LINK_BW_5_4:
 431                 return 540000;
 432         }
 433 }
 434
 435 static u8 dp_get_max_lane_number(u8 dpcd[DP_DPCD_SIZE])
 436 {
 437         return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
 438 }
 439
 440 static u8 dp_get_dp_link_rate_coded(int link_rate)
 441 {
 442         switch (link_rate) {
 443         case 162000:
 444         default:
 445                 return DP_LINK_BW_1_62;
 446         case 270000:
 447                 return DP_LINK_BW_2_7;
 448         case 540000:
 449                 return DP_LINK_BW_5_4;
 450         }
 451 }
 452
 453 /***** radeon specific DP functions *****/
 454
 455 /* First get the min lane# when low rate is used according to pixel clock
 456  * (prefer low rate), second check max lane# supported by DP panel,
 457  * if the max lane# < low rate lane# then use max lane# instead.
 458  */
 459 static int radeon_dp_get_dp_lane_number(struct drm_connector *connector,
 460                                         u8 dpcd[DP_DPCD_SIZE],
 461                                         int pix_clock)
 462 {
 463         int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
 464         int max_link_rate = dp_get_max_link_rate(dpcd);
 465         int max_lane_num = dp_get_max_lane_number(dpcd);
 466         int lane_num;
 467         int max_dp_pix_clock;
 468
 469         for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) {
 470                 max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp);
 471                 if (pix_clock <= max_dp_pix_clock)
 472                         break;
 473         }
 474
 475         return lane_num;
 476 }
 477
 478 static int radeon_dp_get_dp_link_clock(struct drm_connector *connector,
 479                                        u8 dpcd[DP_DPCD_SIZE],
 480                                        int pix_clock)
 481 {
 482         int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
 483         int lane_num, max_pix_clock;
 484
 485         if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
 486             ENCODER_OBJECT_ID_NUTMEG)
 487                 return 270000;
 488
 489         lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock);
 490         max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp);
 491         if (pix_clock <= max_pix_clock)
 492                 return 162000;
 493         max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp);
 494         if (pix_clock <= max_pix_clock)
 495                 return 270000;
 496         if (radeon_connector_is_dp12_capable(connector)) {
 497                 max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp);
 498                 if (pix_clock <= max_pix_clock)
 499                         return 540000;
 500         }
 501
 502         return dp_get_max_link_rate(dpcd);
 503 }
 504
 505 static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
 506                                     int action, int dp_clock,
 507                                     u8 ucconfig, u8 lane_num)
 508 {
 509         DP_ENCODER_SERVICE_PARAMETERS args;
 510         int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
 511
 512         memset(&args, 0, sizeof(args));
 513         args.ucLinkClock = dp_clock / 10;
 514         args.ucConfig = ucconfig;
 515         args.ucAction = action;
 516         args.ucLaneNum = lane_num;
 517         args.ucStatus = 0;
 518
 519         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 520         return args.ucStatus;
 521 }
 522
 523 u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
 524 {
 525         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 526         struct drm_device *dev = radeon_connector->base.dev;
 527         struct radeon_device *rdev = dev->dev_private;
 528
 529         return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
 530                                          dig_connector->dp_i2c_bus->rec.i2c_id, 0);
 531 }
 532
 533 static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector)
 534 {
 535         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 536         u8 buf[3];
 537
 538         if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
 539                 return;
 540
 541         if (radeon_dp_aux_native_read(radeon_connector, DP_SINK_OUI, buf, 3, 0))
 542                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
 543                               buf[0], buf[1], buf[2]);
 544
 545         if (radeon_dp_aux_native_read(radeon_connector, DP_BRANCH_OUI, buf, 3, 0))
 546                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
 547                               buf[0], buf[1], buf[2]);
 548 }
 549
 550 bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
 551 {
 552         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 553         u8 msg[25];
 554         int ret, i;
 555
 556         ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, msg, 8, 0);
 557         if (ret > 0) {
 558                 memcpy(dig_connector->dpcd, msg, 8);
 559                 DRM_DEBUG_KMS("DPCD: ");
 560                 for (i = 0; i < 8; i++)
 561                         DRM_DEBUG_KMS("%02x ", msg[i]);
 562                 DRM_DEBUG_KMS("\n");
 563
 564                 radeon_dp_probe_oui(radeon_connector);
 565
 566                 return true;
 567         }
 568         dig_connector->dpcd[0] = 0;
 569         return false;
 570 }
 571
 572 int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
 573                              struct drm_connector *connector)
 574 {
 575         struct drm_device *dev = encoder->dev;
 576         struct radeon_device *rdev = dev->dev_private;
 577         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 578         int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
 579
 580         if (!ASIC_IS_DCE4(rdev))
 581                 return panel_mode;
 582
 583         if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
 584             ENCODER_OBJECT_ID_NUTMEG)
 585                 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
 586         else if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
 587                  ENCODER_OBJECT_ID_TRAVIS) {
 588                 u8 id[6];
 589                 int i;
 590                 for (i = 0; i < 6; i++)
 591                         id[i] = radeon_read_dpcd_reg(radeon_connector, 0x503 + i);
 592                 if (id[0] == 0x73 &&
 593                     id[1] == 0x69 &&
 594                     id[2] == 0x76 &&
 595                     id[3] == 0x61 &&
 596                     id[4] == 0x72 &&
 597                     id[5] == 0x54)
 598                         panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
 599                 else
 600                         panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
 601         } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
 602                 u8 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);
 603                 if (tmp & 1)
 604                         panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
 605         }
 606
 607         return panel_mode;
 608 }
 609
 610 void radeon_dp_set_link_config(struct drm_connector *connector,
 611                                struct drm_display_mode *mode)
 612 {
 613         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 614         struct radeon_connector_atom_dig *dig_connector;
 615
 616         if (!radeon_connector->con_priv)
 617                 return;
 618         dig_connector = radeon_connector->con_priv;
 619
 620         if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 621             (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
 622                 dig_connector->dp_clock =
 623                         radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
 624                 dig_connector->dp_lane_count =
 625                         radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock);
 626         }
 627 }
 628
 629 int radeon_dp_mode_valid_helper(struct drm_connector *connector,
 630                                 struct drm_display_mode *mode)
 631 {
 632         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 633         struct radeon_connector_atom_dig *dig_connector;
 634         int dp_clock;
 635
 636         if (!radeon_connector->con_priv)
 637                 return MODE_CLOCK_HIGH;
 638         dig_connector = radeon_connector->con_priv;
 639
 640         dp_clock =
 641                 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
 642
 643         if ((dp_clock == 540000) &&
 644             (!radeon_connector_is_dp12_capable(connector)))
 645                 return MODE_CLOCK_HIGH;
 646
 647         return MODE_OK;
 648 }
 649
 650 static bool radeon_dp_get_link_status(struct radeon_connector *radeon_connector,
 651                                       u8 link_status[DP_LINK_STATUS_SIZE])
 652 {
 653         int ret;
 654         ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS,
 655                                         link_status, DP_LINK_STATUS_SIZE, 100);
 656         if (ret <= 0) {
 657                 DRM_ERROR("displayport link status failed\n");
 658                 return false;
 659         }
 660
 661         DRM_DEBUG_KMS("link status %02x %02x %02x %02x %02x %02x\n",
 662                   link_status[0], link_status[1], link_status[2],
 663                   link_status[3], link_status[4], link_status[5]);
 664         return true;
 665 }
 666
 667 bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
 668 {
 669         u8 link_status[DP_LINK_STATUS_SIZE];
 670         struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 671
 672         if (!radeon_dp_get_link_status(radeon_connector, link_status))
 673                 return false;
 674         if (dp_channel_eq_ok(link_status, dig->dp_lane_count))
 675                 return false;
 676         return true;
 677 }
 678
 679 struct radeon_dp_link_train_info {
 680         struct radeon_device *rdev;
 681         struct drm_encoder *encoder;
 682         struct drm_connector *connector;
 683         struct radeon_connector *radeon_connector;
 684         int enc_id;
 685         int dp_clock;
 686         int dp_lane_count;
 687         int rd_interval;
 688         bool tp3_supported;
 689         u8 dpcd[8];
 690         u8 train_set[4];
 691         u8 link_status[DP_LINK_STATUS_SIZE];
 692         u8 tries;
 693         bool use_dpencoder;
 694 };
 695
 696 static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)
 697 {
 698         /* set the initial vs/emph on the source */
 699         atombios_dig_transmitter_setup(dp_info->encoder,
 700                                        ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
 701                                        0, dp_info->train_set[0]); /* sets all lanes at once */
 702
 703         /* set the vs/emph on the sink */
 704         radeon_dp_aux_native_write(dp_info->radeon_connector, DP_TRAINING_LANE0_SET,
 705                                    dp_info->train_set, dp_info->dp_lane_count, 0);
 706 }
 707
 708 static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
 709 {
 710         int rtp = 0;
 711
 712         /* set training pattern on the source */
 713         if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) {
 714                 switch (tp) {
 715                 case DP_TRAINING_PATTERN_1:
 716                         rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
 717                         break;
 718                 case DP_TRAINING_PATTERN_2:
 719                         rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
 720                         break;
 721                 case DP_TRAINING_PATTERN_3:
 722                         rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
 723                         break;
 724                 }
 725                 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);
 726         } else {
 727                 switch (tp) {
 728                 case DP_TRAINING_PATTERN_1:
 729                         rtp = 0;
 730                         break;
 731                 case DP_TRAINING_PATTERN_2:
 732                         rtp = 1;
 733                         break;
 734                 }
 735                 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
 736                                           dp_info->dp_clock, dp_info->enc_id, rtp);
 737         }
 738
 739         /* enable training pattern on the sink */
 740         radeon_write_dpcd_reg(dp_info->radeon_connector, DP_TRAINING_PATTERN_SET, tp);
 741 }
 742
 743 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
 744 {
 745         struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder);
 746         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 747         u8 tmp;
 748
 749         /* power up the sink */
 750         if (dp_info->dpcd[0] >= 0x11)
 751                 radeon_write_dpcd_reg(dp_info->radeon_connector,
 752                                       DP_SET_POWER, DP_SET_POWER_D0);
 753
 754         /* possibly enable downspread on the sink */
 755         if (dp_info->dpcd[3] & 0x1)
 756                 radeon_write_dpcd_reg(dp_info->radeon_connector,
 757                                       DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
 758         else
 759                 radeon_write_dpcd_reg(dp_info->radeon_connector,
 760                                       DP_DOWNSPREAD_CTRL, 0);
 761
 762         if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) &&
 763             (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) {
 764                 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_EDP_CONFIGURATION_SET, 1);
 765         }
 766
 767         /* set the lane count on the sink */
 768         tmp = dp_info->dp_lane_count;
 769         if (dp_info->dpcd[DP_DPCD_REV] >= 0x11 &&
 770             dp_info->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)
 771                 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 772         radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LANE_COUNT_SET, tmp);
 773
 774         /* set the link rate on the sink */
 775         tmp = dp_get_dp_link_rate_coded(dp_info->dp_clock);
 776         radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LINK_BW_SET, tmp);
 777
 778         /* start training on the source */
 779         if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
 780                 atombios_dig_encoder_setup(dp_info->encoder,
 781                                            ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
 782         else
 783                 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,
 784                                           dp_info->dp_clock, dp_info->enc_id, 0);
 785
 786         /* disable the training pattern on the sink */
 787         radeon_write_dpcd_reg(dp_info->radeon_connector,
 788                               DP_TRAINING_PATTERN_SET,
 789                               DP_TRAINING_PATTERN_DISABLE);
 790
 791         return 0;
 792 }
 793
 794 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info)
 795 {
 796         udelay(400);
 797
 798         /* disable the training pattern on the sink */
 799         radeon_write_dpcd_reg(dp_info->radeon_connector,
 800                               DP_TRAINING_PATTERN_SET,
 801                               DP_TRAINING_PATTERN_DISABLE);
 802
 803         /* disable the training pattern on the source */
 804         if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
 805                 atombios_dig_encoder_setup(dp_info->encoder,
 806                                            ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
 807         else
 808                 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
 809                                           dp_info->dp_clock, dp_info->enc_id, 0);
 810
 811         return 0;
 812 }
 813
 814 static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)
 815 {
 816         bool clock_recovery;
 817         u8 voltage;
 818         int i;
 819
 820         radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
 821         memset(dp_info->train_set, 0, 4);
 822         radeon_dp_update_vs_emph(dp_info);
 823
 824         udelay(400);
 825
 826         /* clock recovery loop */
 827         clock_recovery = false;
 828         dp_info->tries = 0;
 829         voltage = 0xff;
 830         while (1) {
 831                 if (dp_info->rd_interval == 0)
 832                         udelay(100);
 833                 else
 834                         mdelay(dp_info->rd_interval * 4);
 835
 836                 if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status))
 837                         break;
 838
 839                 if (dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
 840                         clock_recovery = true;
 841                         break;
 842                 }
 843
 844                 for (i = 0; i < dp_info->dp_lane_count; i++) {
 845                         if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
 846                                 break;
 847                 }
 848                 if (i == dp_info->dp_lane_count) {
 849                         DRM_ERROR("clock recovery reached max voltage\n");
 850                         break;
 851                 }
 852
 853                 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
 854                         ++dp_info->tries;
 855                         if (dp_info->tries == 5) {
 856                                 DRM_ERROR("clock recovery tried 5 times\n");
 857                                 break;
 858                         }
 859                 } else
 860                         dp_info->tries = 0;
 861
 862                 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 863
 864                 /* Compute new train_set as requested by sink */
 865                 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
 866
 867                 radeon_dp_update_vs_emph(dp_info);
 868         }
 869         if (!clock_recovery) {
 870                 DRM_ERROR("clock recovery failed\n");
 871                 return -1;
 872         } else {
 873                 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
 874                           dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
 875                           (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
 876                           DP_TRAIN_PRE_EMPHASIS_SHIFT);
 877                 return 0;
 878         }
 879 }
 880
 881 static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info)
 882 {
 883         bool channel_eq;
 884
 885         if (dp_info->tp3_supported)
 886                 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
 887         else
 888                 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
 889
 890         /* channel equalization loop */
 891         dp_info->tries = 0;
 892         channel_eq = false;
 893         while (1) {
 894                 if (dp_info->rd_interval == 0)
 895                         udelay(400);
 896                 else
 897                         mdelay(dp_info->rd_interval * 4);
 898
 899                 if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status))
 900                         break;
 901
 902                 if (dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
 903                         channel_eq = true;
 904                         break;
 905                 }
 906
 907                 /* Try 5 times */
 908                 if (dp_info->tries > 5) {
 909                         DRM_ERROR("channel eq failed: 5 tries\n");
 910                         break;
 911                 }
 912
 913                 /* Compute new train_set as requested by sink */
 914                 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
 915
 916                 radeon_dp_update_vs_emph(dp_info);
 917                 dp_info->tries++;
 918         }
 919
 920         if (!channel_eq) {
 921                 DRM_ERROR("channel eq failed\n");
 922                 return -1;
 923         } else {
 924                 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
 925                           dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
 926                           (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
 927                           >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
 928                 return 0;
 929         }
 930 }
 931
 932 void radeon_dp_link_train(struct drm_encoder *encoder,
 933                           struct drm_connector *connector)
 934 {
 935         struct drm_device *dev = encoder->dev;
 936         struct radeon_device *rdev = dev->dev_private;
 937         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 938         struct radeon_encoder_atom_dig *dig;
 939         struct radeon_connector *radeon_connector;
 940         struct radeon_connector_atom_dig *dig_connector;
 941         struct radeon_dp_link_train_info dp_info;
 942         int index;
 943         u8 tmp, frev, crev;
 944
 945         if (!radeon_encoder->enc_priv)
 946                 return;
 947         dig = radeon_encoder->enc_priv;
 948
 949         radeon_connector = to_radeon_connector(connector);
 950         if (!radeon_connector->con_priv)
 951                 return;
 952         dig_connector = radeon_connector->con_priv;
 953
 954         if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
 955             (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
 956                 return;
 957
 958         /* DPEncoderService newer than 1.1 can't program properly the
 959          * training pattern. When facing such version use the
 960          * DIGXEncoderControl (X== 1 | 2)
 961          */
 962         dp_info.use_dpencoder = true;
 963         index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
 964         if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) {
 965                 if (crev > 1) {
 966                         dp_info.use_dpencoder = false;
 967                 }
 968         }
 969
 970         dp_info.enc_id = 0;
 971         if (dig->dig_encoder)
 972                 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
 973         else
 974                 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
 975         if (dig->linkb)
 976                 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B;
 977         else
 978                 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
 979
 980         dp_info.rd_interval = radeon_read_dpcd_reg(radeon_connector, DP_TRAINING_AUX_RD_INTERVAL);
 981         tmp = radeon_read_dpcd_reg(radeon_connector, DP_MAX_LANE_COUNT);
 982         if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
 983                 dp_info.tp3_supported = true;
 984         else
 985                 dp_info.tp3_supported = false;
 986
 987         memcpy(dp_info.dpcd, dig_connector->dpcd, 8);
 988         dp_info.rdev = rdev;
 989         dp_info.encoder = encoder;
 990         dp_info.connector = connector;
 991         dp_info.radeon_connector = radeon_connector;
 992         dp_info.dp_lane_count = dig_connector->dp_lane_count;
 993         dp_info.dp_clock = dig_connector->dp_clock;
 994
 995         if (radeon_dp_link_train_init(&dp_info))
 996                 goto done;
 997         if (radeon_dp_link_train_cr(&dp_info))
 998                 goto done;
 999         if (radeon_dp_link_train_ce(&dp_info))
1000                 goto done;
1001 done:
1002         if (radeon_dp_link_train_finish(&dp_info))
1003                 return;
1004 }