2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/backlight.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/module.h>
27 #include <linux/of_platform.h>
28 #include <linux/platform_device.h>
29 #include <linux/regulator/consumer.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_mipi_dsi.h>
34 #include <drm/drm_panel.h>
36 #include <video/display_timing.h>
37 #include <video/of_display_timing.h>
38 #include <video/videomode.h>
41 const struct drm_display_mode *modes;
42 unsigned int num_modes;
43 const struct display_timing *timings;
44 unsigned int num_timings;
54 * @prepare: the time (in milliseconds) that it takes for the panel to
55 * become ready and start receiving video data
56 * @enable: the time (in milliseconds) that it takes for the panel to
57 * display the first valid frame after starting to receive
59 * @disable: the time (in milliseconds) that it takes for the panel to
60 * turn the display off (no content is visible)
61 * @unprepare: the time (in milliseconds) that it takes for the panel
62 * to power itself down completely
68 unsigned int unprepare;
75 struct drm_panel base;
80 const struct panel_desc *desc;
82 struct backlight_device *backlight;
83 struct regulator *supply;
84 struct i2c_adapter *ddc;
86 struct gpio_desc *enable_gpio;
89 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
91 return container_of(panel, struct panel_simple, base);
94 static int panel_simple_get_fixed_modes(struct panel_simple *panel)
96 struct drm_connector *connector = panel->base.connector;
97 struct drm_device *drm = panel->base.drm;
98 struct drm_display_mode *mode;
99 unsigned int i, num = 0;
104 for (i = 0; i < panel->desc->num_timings; i++) {
105 const struct display_timing *dt = &panel->desc->timings[i];
108 videomode_from_timing(dt, &vm);
109 mode = drm_mode_create(drm);
111 dev_err(drm->dev, "failed to add mode %ux%u\n",
112 dt->hactive.typ, dt->vactive.typ);
116 drm_display_mode_from_videomode(&vm, mode);
117 drm_mode_set_name(mode);
119 drm_mode_probed_add(connector, mode);
123 for (i = 0; i < panel->desc->num_modes; i++) {
124 const struct drm_display_mode *m = &panel->desc->modes[i];
126 mode = drm_mode_duplicate(drm, m);
128 dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
129 m->hdisplay, m->vdisplay, m->vrefresh);
133 drm_mode_set_name(mode);
135 drm_mode_probed_add(connector, mode);
139 connector->display_info.bpc = panel->desc->bpc;
140 connector->display_info.width_mm = panel->desc->size.width;
141 connector->display_info.height_mm = panel->desc->size.height;
142 if (panel->desc->bus_format)
143 drm_display_info_set_bus_formats(&connector->display_info,
144 &panel->desc->bus_format, 1);
149 static int panel_simple_of_get_native_mode(struct panel_simple *panel)
151 struct drm_connector *connector = panel->base.connector;
152 struct drm_device *drm = panel->base.drm;
153 struct drm_display_mode *mode;
154 struct device_node *timings_np;
157 timings_np = of_get_child_by_name(panel->dev->of_node,
160 dev_dbg(panel->dev, "failed to find display-timings node\n");
164 of_node_put(timings_np);
165 mode = drm_mode_create(drm);
169 ret = of_get_drm_display_mode(panel->dev->of_node, mode,
172 dev_dbg(panel->dev, "failed to find dts display timings\n");
173 drm_mode_destroy(drm, mode);
177 drm_mode_set_name(mode);
178 mode->type |= DRM_MODE_TYPE_PREFERRED;
179 drm_mode_probed_add(connector, mode);
184 static int panel_simple_disable(struct drm_panel *panel)
186 struct panel_simple *p = to_panel_simple(panel);
192 p->backlight->props.power = FB_BLANK_POWERDOWN;
193 backlight_update_status(p->backlight);
196 if (p->desc && p->desc->delay.disable)
197 msleep(p->desc->delay.disable);
204 static int panel_simple_unprepare(struct drm_panel *panel)
206 struct panel_simple *p = to_panel_simple(panel);
212 gpiod_direction_output(p->enable_gpio, 0);
214 regulator_disable(p->supply);
216 if (p->desc && p->desc->delay.unprepare)
217 msleep(p->desc->delay.unprepare);
224 static int panel_simple_prepare(struct drm_panel *panel)
226 struct panel_simple *p = to_panel_simple(panel);
232 err = regulator_enable(p->supply);
234 dev_err(panel->dev, "failed to enable supply: %d\n", err);
239 gpiod_direction_output(p->enable_gpio, 1);
241 if (p->desc && p->desc->delay.prepare)
242 msleep(p->desc->delay.prepare);
249 static int panel_simple_enable(struct drm_panel *panel)
251 struct panel_simple *p = to_panel_simple(panel);
256 if (p->desc && p->desc->delay.enable)
257 msleep(p->desc->delay.enable);
260 p->backlight->props.power = FB_BLANK_UNBLANK;
261 backlight_update_status(p->backlight);
269 static int panel_simple_get_modes(struct drm_panel *panel)
271 struct panel_simple *p = to_panel_simple(panel);
274 /* probe EDID if a DDC bus is available */
276 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
277 drm_mode_connector_update_edid_property(panel->connector, edid);
279 num += drm_add_edid_modes(panel->connector, edid);
284 /* add hard-coded panel modes */
285 num += panel_simple_get_fixed_modes(p);
287 /* add device node plane modes */
288 num += panel_simple_of_get_native_mode(p);
293 static int panel_simple_get_timings(struct drm_panel *panel,
294 unsigned int num_timings,
295 struct display_timing *timings)
297 struct panel_simple *p = to_panel_simple(panel);
303 if (p->desc->num_timings < num_timings)
304 num_timings = p->desc->num_timings;
307 for (i = 0; i < num_timings; i++)
308 timings[i] = p->desc->timings[i];
310 return p->desc->num_timings;
313 static const struct drm_panel_funcs panel_simple_funcs = {
314 .disable = panel_simple_disable,
315 .unprepare = panel_simple_unprepare,
316 .prepare = panel_simple_prepare,
317 .enable = panel_simple_enable,
318 .get_modes = panel_simple_get_modes,
319 .get_timings = panel_simple_get_timings,
322 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
324 struct device_node *backlight, *ddc;
325 struct panel_simple *panel;
328 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
332 panel->enabled = false;
333 panel->prepared = false;
337 panel->supply = devm_regulator_get(dev, "power");
338 if (IS_ERR(panel->supply))
339 return PTR_ERR(panel->supply);
341 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 0);
342 if (IS_ERR(panel->enable_gpio)) {
343 err = PTR_ERR(panel->enable_gpio);
344 dev_err(dev, "failed to request GPIO: %d\n", err);
348 backlight = of_parse_phandle(dev->of_node, "backlight", 0);
350 panel->backlight = of_find_backlight_by_node(backlight);
351 of_node_put(backlight);
353 if (!panel->backlight)
354 return -EPROBE_DEFER;
357 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
359 panel->ddc = of_find_i2c_adapter_by_node(ddc);
368 drm_panel_init(&panel->base);
369 panel->base.dev = dev;
370 panel->base.funcs = &panel_simple_funcs;
372 err = drm_panel_add(&panel->base);
376 dev_set_drvdata(dev, panel);
382 put_device(&panel->ddc->dev);
384 if (panel->backlight)
385 put_device(&panel->backlight->dev);
390 static int panel_simple_remove(struct device *dev)
392 struct panel_simple *panel = dev_get_drvdata(dev);
394 drm_panel_detach(&panel->base);
395 drm_panel_remove(&panel->base);
397 panel_simple_disable(&panel->base);
400 put_device(&panel->ddc->dev);
402 if (panel->backlight)
403 put_device(&panel->backlight->dev);
408 static void panel_simple_shutdown(struct device *dev)
410 struct panel_simple *panel = dev_get_drvdata(dev);
412 panel_simple_disable(&panel->base);
415 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
418 .hsync_start = 800 + 0,
419 .hsync_end = 800 + 0 + 255,
420 .htotal = 800 + 0 + 255 + 0,
422 .vsync_start = 480 + 2,
423 .vsync_end = 480 + 2 + 45,
424 .vtotal = 480 + 2 + 45 + 0,
426 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
429 static const struct panel_desc ampire_am800480r3tmqwa1h = {
430 .modes = &ire_am800480r3tmqwa1h_mode,
437 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
440 static const struct drm_display_mode auo_b101aw03_mode = {
443 .hsync_start = 1024 + 156,
444 .hsync_end = 1024 + 156 + 8,
445 .htotal = 1024 + 156 + 8 + 156,
447 .vsync_start = 600 + 16,
448 .vsync_end = 600 + 16 + 6,
449 .vtotal = 600 + 16 + 6 + 16,
453 static const struct panel_desc auo_b101aw03 = {
454 .modes = &auo_b101aw03_mode,
463 static const struct drm_display_mode auo_b101ean01_mode = {
466 .hsync_start = 1280 + 119,
467 .hsync_end = 1280 + 119 + 32,
468 .htotal = 1280 + 119 + 32 + 21,
470 .vsync_start = 800 + 4,
471 .vsync_end = 800 + 4 + 20,
472 .vtotal = 800 + 4 + 20 + 8,
476 static const struct panel_desc auo_b101ean01 = {
477 .modes = &auo_b101ean01_mode,
486 static const struct drm_display_mode auo_b101ew05_mode = {
489 .hsync_start = 1280 + 18,
490 .hsync_end = 1280 + 18 + 10,
491 .htotal = 1280 + 18 + 10 + 100,
493 .vsync_start = 800 + 6,
494 .vsync_end = 800 + 6 + 2,
495 .vtotal = 800 + 6 + 2 + 8,
499 static const struct panel_desc auo_b101ew05 = {
500 .modes = &auo_b101ew05_mode,
509 static const struct drm_display_mode auo_b101xtn01_mode = {
512 .hsync_start = 1366 + 20,
513 .hsync_end = 1366 + 20 + 70,
514 .htotal = 1366 + 20 + 70,
516 .vsync_start = 768 + 14,
517 .vsync_end = 768 + 14 + 42,
518 .vtotal = 768 + 14 + 42,
520 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
523 static const struct panel_desc auo_b101xtn01 = {
524 .modes = &auo_b101xtn01_mode,
533 static const struct drm_display_mode auo_b116xw03_mode = {
536 .hsync_start = 1366 + 40,
537 .hsync_end = 1366 + 40 + 40,
538 .htotal = 1366 + 40 + 40 + 32,
540 .vsync_start = 768 + 10,
541 .vsync_end = 768 + 10 + 12,
542 .vtotal = 768 + 10 + 12 + 6,
546 static const struct panel_desc auo_b116xw03 = {
547 .modes = &auo_b116xw03_mode,
556 static const struct drm_display_mode auo_b125han03_mode = {
559 .hsync_start = 1920 + 88,
560 .hsync_end = 1920 + 88 + 60,
561 .htotal = 1920 + 88 + 60 + 36,
563 .vsync_start = 1080 + 12,
564 .vsync_end = 1080 + 12 + 4,
565 .vtotal = 1080 + 12 + 4 + 20,
567 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
570 static const struct panel_desc auo_b125han03 = {
571 .modes = &auo_b125han03_mode,
578 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
581 static const struct drm_display_mode auo_b133xtn01_mode = {
584 .hsync_start = 1366 + 48,
585 .hsync_end = 1366 + 48 + 32,
586 .htotal = 1366 + 48 + 32 + 20,
588 .vsync_start = 768 + 3,
589 .vsync_end = 768 + 3 + 6,
590 .vtotal = 768 + 3 + 6 + 13,
594 static const struct panel_desc auo_b133xtn01 = {
595 .modes = &auo_b133xtn01_mode,
604 static const struct drm_display_mode auo_b133htn01_mode = {
607 .hsync_start = 1920 + 172,
608 .hsync_end = 1920 + 172 + 80,
609 .htotal = 1920 + 172 + 80 + 60,
611 .vsync_start = 1080 + 25,
612 .vsync_end = 1080 + 25 + 10,
613 .vtotal = 1080 + 25 + 10 + 10,
617 static const struct panel_desc auo_b133htn01 = {
618 .modes = &auo_b133htn01_mode,
632 static const struct drm_display_mode avic_tm070ddh03_mode = {
635 .hsync_start = 1024 + 160,
636 .hsync_end = 1024 + 160 + 4,
637 .htotal = 1024 + 160 + 4 + 156,
639 .vsync_start = 600 + 17,
640 .vsync_end = 600 + 17 + 1,
641 .vtotal = 600 + 17 + 1 + 17,
645 static const struct panel_desc avic_tm070ddh03 = {
646 .modes = &avic_tm070ddh03_mode,
660 static const struct drm_display_mode boe_nv125fhm_n73_mode = {
663 .hsync_start = 1366 + 80,
664 .hsync_end = 1366 + 80 + 20,
665 .htotal = 1366 + 80 + 20 + 60,
667 .vsync_start = 768 + 12,
668 .vsync_end = 768 + 12 + 2,
669 .vtotal = 768 + 12 + 2 + 8,
671 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
674 static const struct panel_desc boe_nv125fhm_n73 = {
675 .modes = &boe_nv125fhm_n73_mode,
685 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
688 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
691 .hsync_start = 800 + 24,
692 .hsync_end = 800 + 24 + 16,
693 .htotal = 800 + 24 + 16 + 24,
695 .vsync_start = 1280 + 2,
696 .vsync_end = 1280 + 2 + 2,
697 .vtotal = 1280 + 2 + 2 + 4,
701 static const struct panel_desc chunghwa_claa070wp03xg = {
702 .modes = &chunghwa_claa070wp03xg_mode,
711 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
714 .hsync_start = 1366 + 58,
715 .hsync_end = 1366 + 58 + 58,
716 .htotal = 1366 + 58 + 58 + 58,
718 .vsync_start = 768 + 4,
719 .vsync_end = 768 + 4 + 4,
720 .vtotal = 768 + 4 + 4 + 4,
724 static const struct panel_desc chunghwa_claa101wa01a = {
725 .modes = &chunghwa_claa101wa01a_mode,
734 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
737 .hsync_start = 1366 + 48,
738 .hsync_end = 1366 + 48 + 32,
739 .htotal = 1366 + 48 + 32 + 20,
741 .vsync_start = 768 + 16,
742 .vsync_end = 768 + 16 + 8,
743 .vtotal = 768 + 16 + 8 + 16,
747 static const struct panel_desc chunghwa_claa101wb01 = {
748 .modes = &chunghwa_claa101wb01_mode,
757 static const struct drm_display_mode edt_et057090dhu_mode = {
760 .hsync_start = 640 + 16,
761 .hsync_end = 640 + 16 + 30,
762 .htotal = 640 + 16 + 30 + 114,
764 .vsync_start = 480 + 10,
765 .vsync_end = 480 + 10 + 3,
766 .vtotal = 480 + 10 + 3 + 32,
768 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
771 static const struct panel_desc edt_et057090dhu = {
772 .modes = &edt_et057090dhu_mode,
781 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
784 .hsync_start = 800 + 40,
785 .hsync_end = 800 + 40 + 128,
786 .htotal = 800 + 40 + 128 + 88,
788 .vsync_start = 480 + 10,
789 .vsync_end = 480 + 10 + 2,
790 .vtotal = 480 + 10 + 2 + 33,
792 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
795 static const struct panel_desc edt_etm0700g0dh6 = {
796 .modes = &edt_etm0700g0dh6_mode,
805 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
808 .hsync_start = 800 + 168,
809 .hsync_end = 800 + 168 + 64,
810 .htotal = 800 + 168 + 64 + 88,
812 .vsync_start = 480 + 37,
813 .vsync_end = 480 + 37 + 2,
814 .vtotal = 480 + 37 + 2 + 8,
818 static const struct panel_desc foxlink_fl500wvr00_a0t = {
819 .modes = &foxlink_fl500wvr00_a0t_mode,
826 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
829 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
832 .hsync_start = 480 + 5,
833 .hsync_end = 480 + 5 + 1,
834 .htotal = 480 + 5 + 1 + 40,
836 .vsync_start = 272 + 8,
837 .vsync_end = 272 + 8 + 1,
838 .vtotal = 272 + 8 + 1 + 8,
842 static const struct panel_desc giantplus_gpg482739qs5 = {
843 .modes = &giantplus_gpg482739qs5_mode,
850 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
853 static const struct display_timing hannstar_hsd070pww1_timing = {
854 .pixelclock = { 64300000, 71100000, 82000000 },
855 .hactive = { 1280, 1280, 1280 },
856 .hfront_porch = { 1, 1, 10 },
857 .hback_porch = { 1, 1, 10 },
859 * According to the data sheet, the minimum horizontal blanking interval
860 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
861 * minimum working horizontal blanking interval to be 60 clocks.
863 .hsync_len = { 58, 158, 661 },
864 .vactive = { 800, 800, 800 },
865 .vfront_porch = { 1, 1, 10 },
866 .vback_porch = { 1, 1, 10 },
867 .vsync_len = { 1, 21, 203 },
868 .flags = DISPLAY_FLAGS_DE_HIGH,
871 static const struct panel_desc hannstar_hsd070pww1 = {
872 .timings = &hannstar_hsd070pww1_timing,
879 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
882 static const struct display_timing hannstar_hsd100pxn1_timing = {
883 .pixelclock = { 55000000, 65000000, 75000000 },
884 .hactive = { 1024, 1024, 1024 },
885 .hfront_porch = { 40, 40, 40 },
886 .hback_porch = { 220, 220, 220 },
887 .hsync_len = { 20, 60, 100 },
888 .vactive = { 768, 768, 768 },
889 .vfront_porch = { 7, 7, 7 },
890 .vback_porch = { 21, 21, 21 },
891 .vsync_len = { 10, 10, 10 },
892 .flags = DISPLAY_FLAGS_DE_HIGH,
895 static const struct panel_desc hannstar_hsd100pxn1 = {
896 .timings = &hannstar_hsd100pxn1_timing,
903 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
906 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
909 .hsync_start = 800 + 85,
910 .hsync_end = 800 + 85 + 86,
911 .htotal = 800 + 85 + 86 + 85,
913 .vsync_start = 480 + 16,
914 .vsync_end = 480 + 16 + 13,
915 .vtotal = 480 + 16 + 13 + 16,
919 static const struct panel_desc hitachi_tx23d38vm0caa = {
920 .modes = &hitachi_tx23d38vm0caa_mode,
929 static const struct drm_display_mode innolux_at043tn24_mode = {
932 .hsync_start = 480 + 2,
933 .hsync_end = 480 + 2 + 41,
934 .htotal = 480 + 2 + 41 + 2,
936 .vsync_start = 272 + 2,
937 .vsync_end = 272 + 2 + 11,
938 .vtotal = 272 + 2 + 11 + 2,
940 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
943 static const struct panel_desc innolux_at043tn24 = {
944 .modes = &innolux_at043tn24_mode,
951 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
954 static const struct drm_display_mode innolux_g121i1_l01_mode = {
957 .hsync_start = 1280 + 64,
958 .hsync_end = 1280 + 64 + 32,
959 .htotal = 1280 + 64 + 32 + 64,
961 .vsync_start = 800 + 9,
962 .vsync_end = 800 + 9 + 6,
963 .vtotal = 800 + 9 + 6 + 9,
967 static const struct panel_desc innolux_g121i1_l01 = {
968 .modes = &innolux_g121i1_l01_mode,
977 static const struct drm_display_mode innolux_n116bge_mode = {
980 .hsync_start = 1366 + 136,
981 .hsync_end = 1366 + 136 + 30,
982 .htotal = 1366 + 136 + 30 + 60,
984 .vsync_start = 768 + 8,
985 .vsync_end = 768 + 8 + 12,
986 .vtotal = 768 + 8 + 12 + 12,
988 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
991 static const struct panel_desc innolux_n116bge = {
992 .modes = &innolux_n116bge_mode,
1001 static const struct drm_display_mode innolux_n125hce_mode = {
1004 .hsync_start = 1920 + 80,
1005 .hsync_end = 1920 + 80 + 30,
1006 .htotal = 1920 + 80 + 30 + 50,
1008 .vsync_start = 1080 + 12,
1009 .vsync_end = 1080 + 12 + 4,
1010 .vtotal = 1080 + 12 + 4 + 16,
1012 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1015 static const struct panel_desc innolux_n125hce = {
1016 .modes = &innolux_n125hce_mode,
1027 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1030 static const struct drm_display_mode innolux_n156bge_l21_mode = {
1033 .hsync_start = 1366 + 16,
1034 .hsync_end = 1366 + 16 + 34,
1035 .htotal = 1366 + 16 + 34 + 50,
1037 .vsync_start = 768 + 2,
1038 .vsync_end = 768 + 2 + 6,
1039 .vtotal = 768 + 2 + 6 + 12,
1043 static const struct panel_desc innolux_n156bge_l21 = {
1044 .modes = &innolux_n156bge_l21_mode,
1053 static const struct drm_display_mode innolux_zj070na_01p_mode = {
1056 .hsync_start = 1024 + 128,
1057 .hsync_end = 1024 + 128 + 64,
1058 .htotal = 1024 + 128 + 64 + 128,
1060 .vsync_start = 600 + 16,
1061 .vsync_end = 600 + 16 + 4,
1062 .vtotal = 600 + 16 + 4 + 16,
1066 static const struct panel_desc innolux_zj070na_01p = {
1067 .modes = &innolux_zj070na_01p_mode,
1076 static const struct drm_display_mode lg_lb070wv8_mode = {
1079 .hsync_start = 800 + 88,
1080 .hsync_end = 800 + 88 + 80,
1081 .htotal = 800 + 88 + 80 + 88,
1083 .vsync_start = 480 + 10,
1084 .vsync_end = 480 + 10 + 25,
1085 .vtotal = 480 + 10 + 25 + 10,
1089 static const struct panel_desc lg_lb070wv8 = {
1090 .modes = &lg_lb070wv8_mode,
1097 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1100 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
1103 .hsync_start = 1536 + 12,
1104 .hsync_end = 1536 + 12 + 16,
1105 .htotal = 1536 + 12 + 16 + 48,
1107 .vsync_start = 2048 + 8,
1108 .vsync_end = 2048 + 8 + 4,
1109 .vtotal = 2048 + 8 + 4 + 8,
1111 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1114 static const struct panel_desc lg_lp079qx1_sp0v = {
1115 .modes = &lg_lp079qx1_sp0v_mode,
1121 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1124 static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
1127 .hsync_start = 2048 + 150,
1128 .hsync_end = 2048 + 150 + 5,
1129 .htotal = 2048 + 150 + 5 + 5,
1131 .vsync_start = 1536 + 3,
1132 .vsync_end = 1536 + 3 + 1,
1133 .vtotal = 1536 + 3 + 1 + 9,
1137 static const struct panel_desc lg_lp097qx1_spa1 = {
1138 .modes = &lg_lp097qx1_spa1_mode,
1146 static const struct drm_display_mode lg_lp129qe_mode = {
1149 .hsync_start = 2560 + 48,
1150 .hsync_end = 2560 + 48 + 32,
1151 .htotal = 2560 + 48 + 32 + 80,
1153 .vsync_start = 1700 + 3,
1154 .vsync_end = 1700 + 3 + 10,
1155 .vtotal = 1700 + 3 + 10 + 36,
1159 static const struct panel_desc lg_lp129qe = {
1160 .modes = &lg_lp129qe_mode,
1169 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
1172 .hsync_start = 480 + 2,
1173 .hsync_end = 480 + 2 + 41,
1174 .htotal = 480 + 2 + 41 + 2,
1176 .vsync_start = 272 + 2,
1177 .vsync_end = 272 + 2 + 4,
1178 .vtotal = 272 + 2 + 4 + 2,
1182 static const struct panel_desc nec_nl4827hc19_05b = {
1183 .modes = &nec_nl4827hc19_05b_mode,
1190 .bus_format = MEDIA_BUS_FMT_RGB888_1X24
1193 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
1194 .pixelclock = { 30000000, 30000000, 40000000 },
1195 .hactive = { 800, 800, 800 },
1196 .hfront_porch = { 40, 40, 40 },
1197 .hback_porch = { 40, 40, 40 },
1198 .hsync_len = { 1, 48, 48 },
1199 .vactive = { 480, 480, 480 },
1200 .vfront_porch = { 13, 13, 13 },
1201 .vback_porch = { 29, 29, 29 },
1202 .vsync_len = { 3, 3, 3 },
1203 .flags = DISPLAY_FLAGS_DE_HIGH,
1206 static const struct panel_desc okaya_rs800480t_7x0gp = {
1207 .timings = &okaya_rs800480t_7x0gp_timing,
1220 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1223 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
1226 .hsync_start = 480 + 10,
1227 .hsync_end = 480 + 10 + 10,
1228 .htotal = 480 + 10 + 10 + 15,
1230 .vsync_start = 800 + 3,
1231 .vsync_end = 800 + 3 + 3,
1232 .vtotal = 800 + 3 + 3 + 3,
1236 static const struct panel_desc ortustech_com43h4m85ulc = {
1237 .modes = &ortustech_com43h4m85ulc_mode,
1244 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1247 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
1250 .hsync_start = 2560 + 48,
1251 .hsync_end = 2560 + 48 + 32,
1252 .htotal = 2560 + 48 + 32 + 80,
1254 .vsync_start = 1600 + 2,
1255 .vsync_end = 1600 + 2 + 5,
1256 .vtotal = 1600 + 2 + 5 + 57,
1260 static const struct panel_desc samsung_lsn122dl01_c01 = {
1261 .modes = &samsung_lsn122dl01_c01_mode,
1269 static const struct drm_display_mode samsung_ltn101nt05_mode = {
1272 .hsync_start = 1024 + 24,
1273 .hsync_end = 1024 + 24 + 136,
1274 .htotal = 1024 + 24 + 136 + 160,
1276 .vsync_start = 600 + 3,
1277 .vsync_end = 600 + 3 + 6,
1278 .vtotal = 600 + 3 + 6 + 61,
1282 static const struct panel_desc samsung_ltn101nt05 = {
1283 .modes = &samsung_ltn101nt05_mode,
1292 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
1295 .hsync_start = 1366 + 64,
1296 .hsync_end = 1366 + 64 + 48,
1297 .htotal = 1366 + 64 + 48 + 128,
1299 .vsync_start = 768 + 2,
1300 .vsync_end = 768 + 2 + 5,
1301 .vtotal = 768 + 2 + 5 + 17,
1305 static const struct panel_desc samsung_ltn140at29_301 = {
1306 .modes = &samsung_ltn140at29_301_mode,
1315 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
1318 .hsync_start = 800 + 1,
1319 .hsync_end = 800 + 1 + 64,
1320 .htotal = 800 + 1 + 64 + 64,
1322 .vsync_start = 480 + 1,
1323 .vsync_end = 480 + 1 + 23,
1324 .vtotal = 480 + 1 + 23 + 22,
1328 static const struct panel_desc shelly_sca07010_bfn_lnn = {
1329 .modes = &shelly_sca07010_bfn_lnn_mode,
1335 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1338 static const struct of_device_id platform_of_match[] = {
1340 .compatible = "simple-panel",
1343 .compatible = "ampire,am800480r3tmqwa1h",
1344 .data = &ire_am800480r3tmqwa1h,
1346 .compatible = "auo,b101aw03",
1347 .data = &auo_b101aw03,
1349 .compatible = "auo,b101ean01",
1350 .data = &auo_b101ean01,
1352 .compatible = "auo,b101ew05",
1353 .data = &auo_b101ew05,
1355 .compatible = "auo,b101xtn01",
1356 .data = &auo_b101xtn01,
1358 .compatible = "auo,b116xw03",
1359 .data = &auo_b116xw03,
1361 .compatible = "auo,b125han03",
1362 .data = &auo_b125han03,
1364 .compatible = "auo,b133htn01",
1365 .data = &auo_b133htn01,
1367 .compatible = "auo,b133xtn01",
1368 .data = &auo_b133xtn01,
1370 .compatible = "avic,tm070ddh03",
1371 .data = &avic_tm070ddh03,
1373 .compatible = "boe,nv125fhm-n73",
1374 .data = &boe_nv125fhm_n73,
1376 .compatible = "chunghwa,claa070wp03xg",
1377 .data = &chunghwa_claa070wp03xg,
1379 .compatible = "chunghwa,claa101wa01a",
1380 .data = &chunghwa_claa101wa01a
1382 .compatible = "chunghwa,claa101wb01",
1383 .data = &chunghwa_claa101wb01
1385 .compatible = "edt,et057090dhu",
1386 .data = &edt_et057090dhu,
1388 .compatible = "edt,et070080dh6",
1389 .data = &edt_etm0700g0dh6,
1391 .compatible = "edt,etm0700g0dh6",
1392 .data = &edt_etm0700g0dh6,
1394 .compatible = "foxlink,fl500wvr00-a0t",
1395 .data = &foxlink_fl500wvr00_a0t,
1397 .compatible = "giantplus,gpg482739qs5",
1398 .data = &giantplus_gpg482739qs5
1400 .compatible = "hannstar,hsd070pww1",
1401 .data = &hannstar_hsd070pww1,
1403 .compatible = "hannstar,hsd100pxn1",
1404 .data = &hannstar_hsd100pxn1,
1406 .compatible = "hit,tx23d38vm0caa",
1407 .data = &hitachi_tx23d38vm0caa
1409 .compatible = "innolux,at043tn24",
1410 .data = &innolux_at043tn24,
1412 .compatible ="innolux,g121i1-l01",
1413 .data = &innolux_g121i1_l01
1415 .compatible = "innolux,n116bge",
1416 .data = &innolux_n116bge,
1418 .compatible = "innolux,n125hce",
1419 .data = &innolux_n125hce,
1421 .compatible = "innolux,n156bge-l21",
1422 .data = &innolux_n156bge_l21,
1424 .compatible = "innolux,zj070na-01p",
1425 .data = &innolux_zj070na_01p,
1427 .compatible = "lg,lb070wv8",
1428 .data = &lg_lb070wv8,
1430 .compatible = "lg,lp079qx1-sp0v",
1431 .data = &lg_lp079qx1_sp0v,
1433 .compatible = "lg,lp097qx1-spa1",
1434 .data = &lg_lp097qx1_spa1,
1436 .compatible = "lg,lp129qe",
1437 .data = &lg_lp129qe,
1439 .compatible = "nec,nl4827hc19-05b",
1440 .data = &nec_nl4827hc19_05b,
1442 .compatible = "okaya,rs800480t-7x0gp",
1443 .data = &okaya_rs800480t_7x0gp,
1445 .compatible = "ortustech,com43h4m85ulc",
1446 .data = &ortustech_com43h4m85ulc,
1448 .compatible = "samsung,lsn122dl01-c01",
1449 .data = &samsung_lsn122dl01_c01,
1451 .compatible = "samsung,ltn101nt05",
1452 .data = &samsung_ltn101nt05,
1454 .compatible = "samsung,ltn140at29-301",
1455 .data = &samsung_ltn140at29_301,
1457 .compatible = "shelly,sca07010-bfn-lnn",
1458 .data = &shelly_sca07010_bfn_lnn,
1463 MODULE_DEVICE_TABLE(of, platform_of_match);
1465 static int panel_simple_platform_probe(struct platform_device *pdev)
1467 const struct of_device_id *id;
1469 id = of_match_node(platform_of_match, pdev->dev.of_node);
1473 return panel_simple_probe(&pdev->dev, id->data);
1476 static int panel_simple_platform_remove(struct platform_device *pdev)
1478 return panel_simple_remove(&pdev->dev);
1481 static void panel_simple_platform_shutdown(struct platform_device *pdev)
1483 panel_simple_shutdown(&pdev->dev);
1486 static struct platform_driver panel_simple_platform_driver = {
1488 .name = "panel-simple",
1489 .of_match_table = platform_of_match,
1491 .probe = panel_simple_platform_probe,
1492 .remove = panel_simple_platform_remove,
1493 .shutdown = panel_simple_platform_shutdown,
1496 struct panel_desc_dsi {
1497 struct panel_desc desc;
1499 unsigned long flags;
1500 enum mipi_dsi_pixel_format format;
1504 static const struct drm_display_mode auo_b080uan01_mode = {
1507 .hsync_start = 1200 + 62,
1508 .hsync_end = 1200 + 62 + 4,
1509 .htotal = 1200 + 62 + 4 + 62,
1511 .vsync_start = 1920 + 9,
1512 .vsync_end = 1920 + 9 + 2,
1513 .vtotal = 1920 + 9 + 2 + 8,
1517 static const struct panel_desc_dsi auo_b080uan01 = {
1519 .modes = &auo_b080uan01_mode,
1527 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1528 .format = MIPI_DSI_FMT_RGB888,
1532 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
1535 .hsync_start = 1200 + 120,
1536 .hsync_end = 1200 + 120 + 20,
1537 .htotal = 1200 + 120 + 20 + 21,
1539 .vsync_start = 1920 + 21,
1540 .vsync_end = 1920 + 21 + 3,
1541 .vtotal = 1920 + 21 + 3 + 18,
1543 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1546 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
1548 .modes = &boe_tv080wum_nl0_mode,
1555 .flags = MIPI_DSI_MODE_VIDEO |
1556 MIPI_DSI_MODE_VIDEO_BURST |
1557 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
1558 .format = MIPI_DSI_FMT_RGB888,
1562 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
1565 .hsync_start = 800 + 32,
1566 .hsync_end = 800 + 32 + 1,
1567 .htotal = 800 + 32 + 1 + 57,
1569 .vsync_start = 1280 + 28,
1570 .vsync_end = 1280 + 28 + 1,
1571 .vtotal = 1280 + 28 + 1 + 14,
1575 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
1577 .modes = &lg_ld070wx3_sl01_mode,
1585 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1586 .format = MIPI_DSI_FMT_RGB888,
1590 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
1593 .hsync_start = 720 + 12,
1594 .hsync_end = 720 + 12 + 4,
1595 .htotal = 720 + 12 + 4 + 112,
1597 .vsync_start = 1280 + 8,
1598 .vsync_end = 1280 + 8 + 4,
1599 .vtotal = 1280 + 8 + 4 + 12,
1603 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
1605 .modes = &lg_lh500wx1_sd03_mode,
1613 .flags = MIPI_DSI_MODE_VIDEO,
1614 .format = MIPI_DSI_FMT_RGB888,
1618 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
1621 .hsync_start = 1920 + 154,
1622 .hsync_end = 1920 + 154 + 16,
1623 .htotal = 1920 + 154 + 16 + 32,
1625 .vsync_start = 1200 + 17,
1626 .vsync_end = 1200 + 17 + 2,
1627 .vtotal = 1200 + 17 + 2 + 16,
1631 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
1633 .modes = &panasonic_vvx10f004b00_mode,
1641 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
1642 MIPI_DSI_CLOCK_NON_CONTINUOUS,
1643 .format = MIPI_DSI_FMT_RGB888,
1648 static const struct of_device_id dsi_of_match[] = {
1650 .compatible = "simple-panel-dsi",
1653 .compatible = "auo,b080uan01",
1654 .data = &auo_b080uan01
1656 .compatible = "boe,tv080wum-nl0",
1657 .data = &boe_tv080wum_nl0
1659 .compatible = "lg,ld070wx3-sl01",
1660 .data = &lg_ld070wx3_sl01
1662 .compatible = "lg,lh500wx1-sd03",
1663 .data = &lg_lh500wx1_sd03
1665 .compatible = "panasonic,vvx10f004b00",
1666 .data = &panasonic_vvx10f004b00
1671 MODULE_DEVICE_TABLE(of, dsi_of_match);
1673 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
1675 const struct panel_desc_dsi *desc;
1676 const struct of_device_id *id;
1677 const struct panel_desc *pdesc;
1681 id = of_match_node(dsi_of_match, dsi->dev.of_node);
1688 dsi->mode_flags = desc->flags;
1689 dsi->format = desc->format;
1690 dsi->lanes = desc->lanes;
1691 pdesc = &desc->desc;
1696 err = panel_simple_probe(&dsi->dev, pdesc);
1700 if (!of_property_read_u32(dsi->dev.of_node, "dsi,flags", &val))
1701 dsi->mode_flags = val;
1703 if (!of_property_read_u32(dsi->dev.of_node, "dsi,format", &val))
1706 if (!of_property_read_u32(dsi->dev.of_node, "dsi,lanes", &val))
1709 return mipi_dsi_attach(dsi);
1712 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
1716 err = mipi_dsi_detach(dsi);
1718 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
1720 return panel_simple_remove(&dsi->dev);
1723 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
1725 panel_simple_shutdown(&dsi->dev);
1728 static struct mipi_dsi_driver panel_simple_dsi_driver = {
1730 .name = "panel-simple-dsi",
1731 .of_match_table = dsi_of_match,
1733 .probe = panel_simple_dsi_probe,
1734 .remove = panel_simple_dsi_remove,
1735 .shutdown = panel_simple_dsi_shutdown,
1738 static int __init panel_simple_init(void)
1742 err = platform_driver_register(&panel_simple_platform_driver);
1746 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
1747 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
1754 module_init(panel_simple_init);
1756 static void __exit panel_simple_exit(void)
1758 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
1759 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
1761 platform_driver_unregister(&panel_simple_platform_driver);
1763 module_exit(panel_simple_exit);
1765 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
1766 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
1767 MODULE_LICENSE("GPL and additional rights");