2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/backlight.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/module.h>
27 #include <linux/of_platform.h>
28 #include <linux/platform_device.h>
29 #include <linux/regulator/consumer.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_mipi_dsi.h>
34 #include <drm/drm_panel.h>
36 #include <video/display_timing.h>
37 #include <video/mipi_display.h>
38 #include <video/of_display_timing.h>
39 #include <video/videomode.h>
42 u8 dtype; /* data type */
44 u16 dlen; /* payload len */
48 struct dsi_ctrl_hdr dchdr;
52 struct dsi_panel_cmds {
55 struct dsi_cmd_desc *cmds;
60 const struct drm_display_mode *modes;
61 unsigned int num_modes;
62 const struct display_timing *timings;
63 unsigned int num_timings;
73 * @prepare: the time (in milliseconds) that it takes for the panel to
74 * become ready and start receiving video data
75 * @enable: the time (in milliseconds) that it takes for the panel to
76 * display the first valid frame after starting to receive
78 * @disable: the time (in milliseconds) that it takes for the panel to
79 * turn the display off (no content is visible)
80 * @unprepare: the time (in milliseconds) that it takes for the panel
81 * to power itself down completely
87 unsigned int unprepare;
94 struct drm_panel base;
95 struct mipi_dsi_device *dsi;
100 const struct panel_desc *desc;
102 struct backlight_device *backlight;
103 struct regulator *supply;
104 struct i2c_adapter *ddc;
106 struct gpio_desc *enable_gpio;
107 struct gpio_desc *reset_gpio;
108 unsigned int reset_delay;
110 struct dsi_panel_cmds *on_cmds;
111 struct dsi_panel_cmds *off_cmds;
114 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
116 return container_of(panel, struct panel_simple, base);
119 static void panel_simple_dsi_cmds_cleanup(struct panel_simple *p)
122 kfree(p->on_cmds->buf);
123 kfree(p->on_cmds->cmds);
127 kfree(p->off_cmds->buf);
128 kfree(p->off_cmds->cmds);
132 static int panel_simple_dsi_parse_dcs_cmds(struct device *dev,
133 const u8 *data, int blen,
134 struct dsi_panel_cmds *pcmds)
138 struct dsi_ctrl_hdr *dchdr;
144 buf = kmemdup(data, blen, GFP_KERNEL);
148 /* scan dcs commands */
152 while (len > sizeof(*dchdr)) {
153 dchdr = (struct dsi_ctrl_hdr *)bp;
154 dchdr->dlen = ntohs(dchdr->dlen);
156 if (dchdr->dlen > len) {
157 dev_err(dev, "%s: error, len=%d", __func__,
162 bp += sizeof(*dchdr);
163 len -= sizeof(*dchdr);
170 dev_err(dev, "%s: dcs_cmd=%x len=%d error!",
171 __func__, buf[0], blen);
176 pcmds->cmds = kcalloc(cnt, sizeof(struct dsi_cmd_desc), GFP_KERNEL);
182 pcmds->cmd_cnt = cnt;
188 for (i = 0; i < cnt; i++) {
189 dchdr = (struct dsi_ctrl_hdr *)bp;
190 len -= sizeof(*dchdr);
191 bp += sizeof(*dchdr);
192 pcmds->cmds[i].dchdr = *dchdr;
193 pcmds->cmds[i].payload = bp;
198 dev_info(dev, "%s: dcs_cmd=%x len=%d, cmd_cnt=%d\n", __func__,
199 pcmds->buf[0], pcmds->blen, pcmds->cmd_cnt);
203 static int panel_simple_dsi_send_cmds(struct panel_simple *panel,
204 struct dsi_panel_cmds *cmds)
206 struct mipi_dsi_device *dsi = panel->dsi;
212 for (i = 0; i < cmds->cmd_cnt; i++) {
213 struct dsi_cmd_desc *cmd = &cmds->cmds[i];
215 switch (cmd->dchdr.dtype) {
216 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
217 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
218 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
219 case MIPI_DSI_GENERIC_LONG_WRITE:
220 err = mipi_dsi_generic_write(dsi, cmd->payload,
223 case MIPI_DSI_DCS_SHORT_WRITE:
224 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
225 case MIPI_DSI_DCS_LONG_WRITE:
226 err = mipi_dsi_dcs_write_buffer(dsi, cmd->payload,
234 dev_err(panel->dev, "failed to write dcs cmd: %d\n",
238 msleep(cmd->dchdr.wait);
244 static int panel_simple_get_fixed_modes(struct panel_simple *panel)
246 struct drm_connector *connector = panel->base.connector;
247 struct drm_device *drm = panel->base.drm;
248 struct drm_display_mode *mode;
249 unsigned int i, num = 0;
254 for (i = 0; i < panel->desc->num_timings; i++) {
255 const struct display_timing *dt = &panel->desc->timings[i];
258 videomode_from_timing(dt, &vm);
259 mode = drm_mode_create(drm);
261 dev_err(drm->dev, "failed to add mode %ux%u\n",
262 dt->hactive.typ, dt->vactive.typ);
266 drm_display_mode_from_videomode(&vm, mode);
267 drm_mode_set_name(mode);
269 drm_mode_probed_add(connector, mode);
273 for (i = 0; i < panel->desc->num_modes; i++) {
274 const struct drm_display_mode *m = &panel->desc->modes[i];
276 mode = drm_mode_duplicate(drm, m);
278 dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
279 m->hdisplay, m->vdisplay, m->vrefresh);
283 drm_mode_set_name(mode);
285 drm_mode_probed_add(connector, mode);
289 connector->display_info.bpc = panel->desc->bpc;
290 connector->display_info.width_mm = panel->desc->size.width;
291 connector->display_info.height_mm = panel->desc->size.height;
292 if (panel->desc->bus_format)
293 drm_display_info_set_bus_formats(&connector->display_info,
294 &panel->desc->bus_format, 1);
299 static int panel_simple_of_get_native_mode(struct panel_simple *panel)
301 struct drm_connector *connector = panel->base.connector;
302 struct drm_device *drm = panel->base.drm;
303 struct drm_display_mode *mode;
304 struct device_node *timings_np;
307 timings_np = of_get_child_by_name(panel->dev->of_node,
310 dev_dbg(panel->dev, "failed to find display-timings node\n");
314 of_node_put(timings_np);
315 mode = drm_mode_create(drm);
319 ret = of_get_drm_display_mode(panel->dev->of_node, mode,
322 dev_dbg(panel->dev, "failed to find dts display timings\n");
323 drm_mode_destroy(drm, mode);
327 drm_mode_set_name(mode);
328 mode->type |= DRM_MODE_TYPE_PREFERRED;
329 drm_mode_probed_add(connector, mode);
334 static int panel_simple_disable(struct drm_panel *panel)
336 struct panel_simple *p = to_panel_simple(panel);
342 p->backlight->props.power = FB_BLANK_POWERDOWN;
343 backlight_update_status(p->backlight);
346 if (p->desc && p->desc->delay.disable)
347 msleep(p->desc->delay.disable);
354 static int panel_simple_unprepare(struct drm_panel *panel)
356 struct panel_simple *p = to_panel_simple(panel);
363 err = panel_simple_dsi_send_cmds(p, p->off_cmds);
365 dev_err(p->dev, "failed to send off cmds\n");
369 gpiod_direction_output(p->reset_gpio, 1);
372 gpiod_direction_output(p->enable_gpio, 0);
374 regulator_disable(p->supply);
376 if (p->desc && p->desc->delay.unprepare)
377 msleep(p->desc->delay.unprepare);
384 static int panel_simple_prepare(struct drm_panel *panel)
386 struct panel_simple *p = to_panel_simple(panel);
392 err = regulator_enable(p->supply);
394 dev_err(panel->dev, "failed to enable supply: %d\n", err);
399 gpiod_direction_output(p->enable_gpio, 1);
401 if (p->desc && p->desc->delay.prepare)
402 msleep(p->desc->delay.prepare);
405 gpiod_direction_output(p->reset_gpio, 1);
408 msleep(p->reset_delay);
411 gpiod_direction_output(p->reset_gpio, 0);
418 static int panel_simple_enable(struct drm_panel *panel)
420 struct panel_simple *p = to_panel_simple(panel);
427 err = panel_simple_dsi_send_cmds(p, p->on_cmds);
429 dev_err(p->dev, "failed to send on cmds\n");
432 if (p->desc && p->desc->delay.enable)
433 msleep(p->desc->delay.enable);
436 p->backlight->props.power = FB_BLANK_UNBLANK;
437 backlight_update_status(p->backlight);
445 static int panel_simple_get_modes(struct drm_panel *panel)
447 struct panel_simple *p = to_panel_simple(panel);
450 /* add device node plane modes */
451 num += panel_simple_of_get_native_mode(p);
453 /* add hard-coded panel modes */
454 num += panel_simple_get_fixed_modes(p);
456 /* probe EDID if a DDC bus is available */
458 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
459 drm_mode_connector_update_edid_property(panel->connector, edid);
461 num += drm_add_edid_modes(panel->connector, edid);
469 static int panel_simple_get_timings(struct drm_panel *panel,
470 unsigned int num_timings,
471 struct display_timing *timings)
473 struct panel_simple *p = to_panel_simple(panel);
479 if (p->desc->num_timings < num_timings)
480 num_timings = p->desc->num_timings;
483 for (i = 0; i < num_timings; i++)
484 timings[i] = p->desc->timings[i];
486 return p->desc->num_timings;
489 static const struct drm_panel_funcs panel_simple_funcs = {
490 .disable = panel_simple_disable,
491 .unprepare = panel_simple_unprepare,
492 .prepare = panel_simple_prepare,
493 .enable = panel_simple_enable,
494 .get_modes = panel_simple_get_modes,
495 .get_timings = panel_simple_get_timings,
498 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
500 struct device_node *backlight, *ddc;
501 struct panel_simple *panel;
502 struct panel_desc *of_desc;
506 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
511 of_desc = devm_kzalloc(dev, sizeof(*of_desc), GFP_KERNEL);
513 of_desc = devm_kmemdup(dev, desc, sizeof(*of_desc), GFP_KERNEL);
515 if (!of_property_read_u32(dev->of_node, "bus-format", &val))
516 of_desc->bus_format = val;
517 if (!of_property_read_u32(dev->of_node, "delay,prepare", &val))
518 of_desc->delay.prepare = val;
519 if (!of_property_read_u32(dev->of_node, "delay,enable", &val))
520 of_desc->delay.enable = val;
521 if (!of_property_read_u32(dev->of_node, "delay,disable", &val))
522 of_desc->delay.disable = val;
523 if (!of_property_read_u32(dev->of_node, "delay,unprepare", &val))
524 of_desc->delay.unprepare = val;
526 panel->enabled = false;
527 panel->prepared = false;
528 panel->desc = of_desc;
531 panel->supply = devm_regulator_get(dev, "power");
532 if (IS_ERR(panel->supply))
533 return PTR_ERR(panel->supply);
535 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 0);
536 if (IS_ERR(panel->enable_gpio)) {
537 err = PTR_ERR(panel->enable_gpio);
538 dev_err(dev, "failed to request enable GPIO: %d\n", err);
542 panel->reset_gpio = devm_gpiod_get_optional(dev, "reset", 0);
543 if (IS_ERR(panel->reset_gpio)) {
544 err = PTR_ERR(panel->reset_gpio);
545 dev_err(dev, "failed to request reset GPIO: %d\n", err);
549 backlight = of_parse_phandle(dev->of_node, "backlight", 0);
551 panel->backlight = of_find_backlight_by_node(backlight);
552 of_node_put(backlight);
554 if (!panel->backlight)
555 return -EPROBE_DEFER;
558 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
560 panel->ddc = of_find_i2c_adapter_by_node(ddc);
569 drm_panel_init(&panel->base);
570 panel->base.dev = dev;
571 panel->base.funcs = &panel_simple_funcs;
573 err = drm_panel_add(&panel->base);
577 dev_set_drvdata(dev, panel);
583 put_device(&panel->ddc->dev);
585 if (panel->backlight)
586 put_device(&panel->backlight->dev);
591 static int panel_simple_remove(struct device *dev)
593 struct panel_simple *panel = dev_get_drvdata(dev);
595 drm_panel_detach(&panel->base);
596 drm_panel_remove(&panel->base);
598 panel_simple_disable(&panel->base);
601 put_device(&panel->ddc->dev);
603 if (panel->backlight)
604 put_device(&panel->backlight->dev);
606 panel_simple_dsi_cmds_cleanup(panel);
611 static void panel_simple_shutdown(struct device *dev)
613 struct panel_simple *panel = dev_get_drvdata(dev);
615 panel_simple_disable(&panel->base);
618 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
621 .hsync_start = 800 + 0,
622 .hsync_end = 800 + 0 + 255,
623 .htotal = 800 + 0 + 255 + 0,
625 .vsync_start = 480 + 2,
626 .vsync_end = 480 + 2 + 45,
627 .vtotal = 480 + 2 + 45 + 0,
629 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
632 static const struct panel_desc ampire_am800480r3tmqwa1h = {
633 .modes = &ire_am800480r3tmqwa1h_mode,
640 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
643 static const struct drm_display_mode auo_b101aw03_mode = {
646 .hsync_start = 1024 + 156,
647 .hsync_end = 1024 + 156 + 8,
648 .htotal = 1024 + 156 + 8 + 156,
650 .vsync_start = 600 + 16,
651 .vsync_end = 600 + 16 + 6,
652 .vtotal = 600 + 16 + 6 + 16,
656 static const struct panel_desc auo_b101aw03 = {
657 .modes = &auo_b101aw03_mode,
666 static const struct drm_display_mode auo_b101ean01_mode = {
669 .hsync_start = 1280 + 119,
670 .hsync_end = 1280 + 119 + 32,
671 .htotal = 1280 + 119 + 32 + 21,
673 .vsync_start = 800 + 4,
674 .vsync_end = 800 + 4 + 20,
675 .vtotal = 800 + 4 + 20 + 8,
679 static const struct panel_desc auo_b101ean01 = {
680 .modes = &auo_b101ean01_mode,
689 static const struct drm_display_mode auo_b101ew05_mode = {
692 .hsync_start = 1280 + 18,
693 .hsync_end = 1280 + 18 + 10,
694 .htotal = 1280 + 18 + 10 + 100,
696 .vsync_start = 800 + 6,
697 .vsync_end = 800 + 6 + 2,
698 .vtotal = 800 + 6 + 2 + 8,
702 static const struct panel_desc auo_b101ew05 = {
703 .modes = &auo_b101ew05_mode,
712 static const struct drm_display_mode auo_b101xtn01_mode = {
715 .hsync_start = 1366 + 20,
716 .hsync_end = 1366 + 20 + 70,
717 .htotal = 1366 + 20 + 70,
719 .vsync_start = 768 + 14,
720 .vsync_end = 768 + 14 + 42,
721 .vtotal = 768 + 14 + 42,
723 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
726 static const struct panel_desc auo_b101xtn01 = {
727 .modes = &auo_b101xtn01_mode,
736 static const struct drm_display_mode auo_b116xw03_mode = {
739 .hsync_start = 1366 + 40,
740 .hsync_end = 1366 + 40 + 40,
741 .htotal = 1366 + 40 + 40 + 32,
743 .vsync_start = 768 + 10,
744 .vsync_end = 768 + 10 + 12,
745 .vtotal = 768 + 10 + 12 + 6,
749 static const struct panel_desc auo_b116xw03 = {
750 .modes = &auo_b116xw03_mode,
759 static const struct drm_display_mode auo_b125han03_mode = {
762 .hsync_start = 1920 + 48,
763 .hsync_end = 1920 + 48 + 32,
764 .htotal = 1920 + 48 + 32 + 140,
766 .vsync_start = 1080 + 2,
767 .vsync_end = 1080 + 2 + 5,
768 .vtotal = 1080 + 2 + 5 + 57,
770 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
773 static const struct panel_desc auo_b125han03 = {
774 .modes = &auo_b125han03_mode,
781 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
784 static const struct drm_display_mode auo_b133xtn01_mode = {
787 .hsync_start = 1366 + 48,
788 .hsync_end = 1366 + 48 + 32,
789 .htotal = 1366 + 48 + 32 + 20,
791 .vsync_start = 768 + 3,
792 .vsync_end = 768 + 3 + 6,
793 .vtotal = 768 + 3 + 6 + 13,
797 static const struct panel_desc auo_b133xtn01 = {
798 .modes = &auo_b133xtn01_mode,
807 static const struct drm_display_mode auo_b133htn01_mode = {
810 .hsync_start = 1920 + 172,
811 .hsync_end = 1920 + 172 + 80,
812 .htotal = 1920 + 172 + 80 + 60,
814 .vsync_start = 1080 + 25,
815 .vsync_end = 1080 + 25 + 10,
816 .vtotal = 1080 + 25 + 10 + 10,
820 static const struct panel_desc auo_b133htn01 = {
821 .modes = &auo_b133htn01_mode,
835 static const struct drm_display_mode avic_tm070ddh03_mode = {
838 .hsync_start = 1024 + 160,
839 .hsync_end = 1024 + 160 + 4,
840 .htotal = 1024 + 160 + 4 + 156,
842 .vsync_start = 600 + 17,
843 .vsync_end = 600 + 17 + 1,
844 .vtotal = 600 + 17 + 1 + 17,
848 static const struct panel_desc avic_tm070ddh03 = {
849 .modes = &avic_tm070ddh03_mode,
863 static const struct drm_display_mode boe_nv125fhm_n73_mode = {
866 .hsync_start = 1366 + 80,
867 .hsync_end = 1366 + 80 + 20,
868 .htotal = 1366 + 80 + 20 + 60,
870 .vsync_start = 768 + 12,
871 .vsync_end = 768 + 12 + 2,
872 .vtotal = 768 + 12 + 2 + 8,
874 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
877 static const struct panel_desc boe_nv125fhm_n73 = {
878 .modes = &boe_nv125fhm_n73_mode,
888 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
891 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
894 .hsync_start = 800 + 24,
895 .hsync_end = 800 + 24 + 16,
896 .htotal = 800 + 24 + 16 + 24,
898 .vsync_start = 1280 + 2,
899 .vsync_end = 1280 + 2 + 2,
900 .vtotal = 1280 + 2 + 2 + 4,
904 static const struct panel_desc chunghwa_claa070wp03xg = {
905 .modes = &chunghwa_claa070wp03xg_mode,
914 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
917 .hsync_start = 1366 + 58,
918 .hsync_end = 1366 + 58 + 58,
919 .htotal = 1366 + 58 + 58 + 58,
921 .vsync_start = 768 + 4,
922 .vsync_end = 768 + 4 + 4,
923 .vtotal = 768 + 4 + 4 + 4,
927 static const struct panel_desc chunghwa_claa101wa01a = {
928 .modes = &chunghwa_claa101wa01a_mode,
937 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
940 .hsync_start = 1366 + 48,
941 .hsync_end = 1366 + 48 + 32,
942 .htotal = 1366 + 48 + 32 + 20,
944 .vsync_start = 768 + 16,
945 .vsync_end = 768 + 16 + 8,
946 .vtotal = 768 + 16 + 8 + 16,
950 static const struct panel_desc chunghwa_claa101wb01 = {
951 .modes = &chunghwa_claa101wb01_mode,
960 static const struct drm_display_mode edt_et057090dhu_mode = {
963 .hsync_start = 640 + 16,
964 .hsync_end = 640 + 16 + 30,
965 .htotal = 640 + 16 + 30 + 114,
967 .vsync_start = 480 + 10,
968 .vsync_end = 480 + 10 + 3,
969 .vtotal = 480 + 10 + 3 + 32,
971 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
974 static const struct panel_desc edt_et057090dhu = {
975 .modes = &edt_et057090dhu_mode,
984 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
987 .hsync_start = 800 + 40,
988 .hsync_end = 800 + 40 + 128,
989 .htotal = 800 + 40 + 128 + 88,
991 .vsync_start = 480 + 10,
992 .vsync_end = 480 + 10 + 2,
993 .vtotal = 480 + 10 + 2 + 33,
995 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
998 static const struct panel_desc edt_etm0700g0dh6 = {
999 .modes = &edt_etm0700g0dh6_mode,
1008 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1011 .hsync_start = 800 + 168,
1012 .hsync_end = 800 + 168 + 64,
1013 .htotal = 800 + 168 + 64 + 88,
1015 .vsync_start = 480 + 37,
1016 .vsync_end = 480 + 37 + 2,
1017 .vtotal = 480 + 37 + 2 + 8,
1021 static const struct panel_desc foxlink_fl500wvr00_a0t = {
1022 .modes = &foxlink_fl500wvr00_a0t_mode,
1029 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1032 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1035 .hsync_start = 480 + 5,
1036 .hsync_end = 480 + 5 + 1,
1037 .htotal = 480 + 5 + 1 + 40,
1039 .vsync_start = 272 + 8,
1040 .vsync_end = 272 + 8 + 1,
1041 .vtotal = 272 + 8 + 1 + 8,
1045 static const struct panel_desc giantplus_gpg482739qs5 = {
1046 .modes = &giantplus_gpg482739qs5_mode,
1053 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1056 static const struct display_timing hannstar_hsd070pww1_timing = {
1057 .pixelclock = { 64300000, 71100000, 82000000 },
1058 .hactive = { 1280, 1280, 1280 },
1059 .hfront_porch = { 1, 1, 10 },
1060 .hback_porch = { 1, 1, 10 },
1062 * According to the data sheet, the minimum horizontal blanking interval
1063 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
1064 * minimum working horizontal blanking interval to be 60 clocks.
1066 .hsync_len = { 58, 158, 661 },
1067 .vactive = { 800, 800, 800 },
1068 .vfront_porch = { 1, 1, 10 },
1069 .vback_porch = { 1, 1, 10 },
1070 .vsync_len = { 1, 21, 203 },
1071 .flags = DISPLAY_FLAGS_DE_HIGH,
1074 static const struct panel_desc hannstar_hsd070pww1 = {
1075 .timings = &hannstar_hsd070pww1_timing,
1082 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1085 static const struct display_timing hannstar_hsd100pxn1_timing = {
1086 .pixelclock = { 55000000, 65000000, 75000000 },
1087 .hactive = { 1024, 1024, 1024 },
1088 .hfront_porch = { 40, 40, 40 },
1089 .hback_porch = { 220, 220, 220 },
1090 .hsync_len = { 20, 60, 100 },
1091 .vactive = { 768, 768, 768 },
1092 .vfront_porch = { 7, 7, 7 },
1093 .vback_porch = { 21, 21, 21 },
1094 .vsync_len = { 10, 10, 10 },
1095 .flags = DISPLAY_FLAGS_DE_HIGH,
1098 static const struct panel_desc hannstar_hsd100pxn1 = {
1099 .timings = &hannstar_hsd100pxn1_timing,
1106 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1109 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
1112 .hsync_start = 800 + 85,
1113 .hsync_end = 800 + 85 + 86,
1114 .htotal = 800 + 85 + 86 + 85,
1116 .vsync_start = 480 + 16,
1117 .vsync_end = 480 + 16 + 13,
1118 .vtotal = 480 + 16 + 13 + 16,
1122 static const struct panel_desc hitachi_tx23d38vm0caa = {
1123 .modes = &hitachi_tx23d38vm0caa_mode,
1132 static const struct drm_display_mode innolux_at043tn24_mode = {
1135 .hsync_start = 480 + 2,
1136 .hsync_end = 480 + 2 + 41,
1137 .htotal = 480 + 2 + 41 + 2,
1139 .vsync_start = 272 + 2,
1140 .vsync_end = 272 + 2 + 11,
1141 .vtotal = 272 + 2 + 11 + 2,
1143 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1146 static const struct panel_desc innolux_at043tn24 = {
1147 .modes = &innolux_at043tn24_mode,
1154 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1157 static const struct drm_display_mode innolux_g121i1_l01_mode = {
1160 .hsync_start = 1280 + 64,
1161 .hsync_end = 1280 + 64 + 32,
1162 .htotal = 1280 + 64 + 32 + 64,
1164 .vsync_start = 800 + 9,
1165 .vsync_end = 800 + 9 + 6,
1166 .vtotal = 800 + 9 + 6 + 9,
1170 static const struct panel_desc innolux_g121i1_l01 = {
1171 .modes = &innolux_g121i1_l01_mode,
1180 static const struct drm_display_mode innolux_n116bge_mode = {
1183 .hsync_start = 1366 + 136,
1184 .hsync_end = 1366 + 136 + 30,
1185 .htotal = 1366 + 136 + 30 + 60,
1187 .vsync_start = 768 + 8,
1188 .vsync_end = 768 + 8 + 12,
1189 .vtotal = 768 + 8 + 12 + 12,
1191 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1194 static const struct panel_desc innolux_n116bge = {
1195 .modes = &innolux_n116bge_mode,
1204 static const struct drm_display_mode innolux_n125hce_mode = {
1207 .hsync_start = 1920 + 80,
1208 .hsync_end = 1920 + 80 + 30,
1209 .htotal = 1920 + 80 + 30 + 50,
1211 .vsync_start = 1080 + 12,
1212 .vsync_end = 1080 + 12 + 4,
1213 .vtotal = 1080 + 12 + 4 + 16,
1215 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1218 static const struct panel_desc innolux_n125hce = {
1219 .modes = &innolux_n125hce_mode,
1230 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1233 static const struct drm_display_mode innolux_n156bge_l21_mode = {
1236 .hsync_start = 1366 + 16,
1237 .hsync_end = 1366 + 16 + 34,
1238 .htotal = 1366 + 16 + 34 + 50,
1240 .vsync_start = 768 + 2,
1241 .vsync_end = 768 + 2 + 6,
1242 .vtotal = 768 + 2 + 6 + 12,
1246 static const struct panel_desc innolux_n156bge_l21 = {
1247 .modes = &innolux_n156bge_l21_mode,
1256 static const struct drm_display_mode innolux_zj070na_01p_mode = {
1259 .hsync_start = 1024 + 128,
1260 .hsync_end = 1024 + 128 + 64,
1261 .htotal = 1024 + 128 + 64 + 128,
1263 .vsync_start = 600 + 16,
1264 .vsync_end = 600 + 16 + 4,
1265 .vtotal = 600 + 16 + 4 + 16,
1269 static const struct panel_desc innolux_zj070na_01p = {
1270 .modes = &innolux_zj070na_01p_mode,
1279 static const struct drm_display_mode lg_lb070wv8_mode = {
1282 .hsync_start = 800 + 88,
1283 .hsync_end = 800 + 88 + 80,
1284 .htotal = 800 + 88 + 80 + 88,
1286 .vsync_start = 480 + 10,
1287 .vsync_end = 480 + 10 + 25,
1288 .vtotal = 480 + 10 + 25 + 10,
1292 static const struct panel_desc lg_lb070wv8 = {
1293 .modes = &lg_lb070wv8_mode,
1300 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1303 static const struct drm_display_mode sharp_lcd_f402_mode = {
1306 .hsync_start = 1536 + 12,
1307 .hsync_end = 1536 + 12 + 48,
1308 .htotal = 1536 + 12 + 48 + 16,
1310 .vsync_start = 2048 + 8,
1311 .vsync_end = 2048 + 8 + 8,
1312 .vtotal = 2048 + 8 + 8 + 4,
1314 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1317 static const struct panel_desc sharp_lcd_f402 = {
1318 .modes = &sharp_lcd_f402_mode,
1325 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1328 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
1331 .hsync_start = 1536 + 12,
1332 .hsync_end = 1536 + 12 + 16,
1333 .htotal = 1536 + 12 + 16 + 48,
1335 .vsync_start = 2048 + 8,
1336 .vsync_end = 2048 + 8 + 4,
1337 .vtotal = 2048 + 8 + 4 + 8,
1339 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1342 static const struct panel_desc lg_lp079qx1_sp0v = {
1343 .modes = &lg_lp079qx1_sp0v_mode,
1349 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1352 static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
1355 .hsync_start = 2048 + 150,
1356 .hsync_end = 2048 + 150 + 5,
1357 .htotal = 2048 + 150 + 5 + 5,
1359 .vsync_start = 1536 + 3,
1360 .vsync_end = 1536 + 3 + 1,
1361 .vtotal = 1536 + 3 + 1 + 9,
1365 static const struct panel_desc lg_lp097qx1_spa1 = {
1366 .modes = &lg_lp097qx1_spa1_mode,
1374 static const struct drm_display_mode lg_lp129qe_mode = {
1377 .hsync_start = 2560 + 48,
1378 .hsync_end = 2560 + 48 + 32,
1379 .htotal = 2560 + 48 + 32 + 80,
1381 .vsync_start = 1700 + 3,
1382 .vsync_end = 1700 + 3 + 10,
1383 .vtotal = 1700 + 3 + 10 + 36,
1387 static const struct panel_desc lg_lp129qe = {
1388 .modes = &lg_lp129qe_mode,
1397 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
1400 .hsync_start = 480 + 2,
1401 .hsync_end = 480 + 2 + 41,
1402 .htotal = 480 + 2 + 41 + 2,
1404 .vsync_start = 272 + 2,
1405 .vsync_end = 272 + 2 + 4,
1406 .vtotal = 272 + 2 + 4 + 2,
1410 static const struct panel_desc nec_nl4827hc19_05b = {
1411 .modes = &nec_nl4827hc19_05b_mode,
1418 .bus_format = MEDIA_BUS_FMT_RGB888_1X24
1421 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
1422 .pixelclock = { 30000000, 30000000, 40000000 },
1423 .hactive = { 800, 800, 800 },
1424 .hfront_porch = { 40, 40, 40 },
1425 .hback_porch = { 40, 40, 40 },
1426 .hsync_len = { 1, 48, 48 },
1427 .vactive = { 480, 480, 480 },
1428 .vfront_porch = { 13, 13, 13 },
1429 .vback_porch = { 29, 29, 29 },
1430 .vsync_len = { 3, 3, 3 },
1431 .flags = DISPLAY_FLAGS_DE_HIGH,
1434 static const struct panel_desc okaya_rs800480t_7x0gp = {
1435 .timings = &okaya_rs800480t_7x0gp_timing,
1448 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1451 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
1454 .hsync_start = 480 + 10,
1455 .hsync_end = 480 + 10 + 10,
1456 .htotal = 480 + 10 + 10 + 15,
1458 .vsync_start = 800 + 3,
1459 .vsync_end = 800 + 3 + 3,
1460 .vtotal = 800 + 3 + 3 + 3,
1464 static const struct panel_desc ortustech_com43h4m85ulc = {
1465 .modes = &ortustech_com43h4m85ulc_mode,
1472 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1475 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
1478 .hsync_start = 2560 + 48,
1479 .hsync_end = 2560 + 48 + 32,
1480 .htotal = 2560 + 48 + 32 + 80,
1482 .vsync_start = 1600 + 2,
1483 .vsync_end = 1600 + 2 + 5,
1484 .vtotal = 1600 + 2 + 5 + 57,
1488 static const struct panel_desc samsung_lsn122dl01_c01 = {
1489 .modes = &samsung_lsn122dl01_c01_mode,
1497 static const struct drm_display_mode samsung_ltn101nt05_mode = {
1500 .hsync_start = 1024 + 24,
1501 .hsync_end = 1024 + 24 + 136,
1502 .htotal = 1024 + 24 + 136 + 160,
1504 .vsync_start = 600 + 3,
1505 .vsync_end = 600 + 3 + 6,
1506 .vtotal = 600 + 3 + 6 + 61,
1510 static const struct panel_desc samsung_ltn101nt05 = {
1511 .modes = &samsung_ltn101nt05_mode,
1520 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
1523 .hsync_start = 1366 + 64,
1524 .hsync_end = 1366 + 64 + 48,
1525 .htotal = 1366 + 64 + 48 + 128,
1527 .vsync_start = 768 + 2,
1528 .vsync_end = 768 + 2 + 5,
1529 .vtotal = 768 + 2 + 5 + 17,
1533 static const struct panel_desc samsung_ltn140at29_301 = {
1534 .modes = &samsung_ltn140at29_301_mode,
1543 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
1546 .hsync_start = 800 + 1,
1547 .hsync_end = 800 + 1 + 64,
1548 .htotal = 800 + 1 + 64 + 64,
1550 .vsync_start = 480 + 1,
1551 .vsync_end = 480 + 1 + 23,
1552 .vtotal = 480 + 1 + 23 + 22,
1556 static const struct panel_desc shelly_sca07010_bfn_lnn = {
1557 .modes = &shelly_sca07010_bfn_lnn_mode,
1563 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1566 static const struct of_device_id platform_of_match[] = {
1568 .compatible = "simple-panel",
1571 .compatible = "ampire,am800480r3tmqwa1h",
1572 .data = &ire_am800480r3tmqwa1h,
1574 .compatible = "auo,b101aw03",
1575 .data = &auo_b101aw03,
1577 .compatible = "auo,b101ean01",
1578 .data = &auo_b101ean01,
1580 .compatible = "auo,b101ew05",
1581 .data = &auo_b101ew05,
1583 .compatible = "auo,b101xtn01",
1584 .data = &auo_b101xtn01,
1586 .compatible = "auo,b116xw03",
1587 .data = &auo_b116xw03,
1589 .compatible = "auo,b125han03",
1590 .data = &auo_b125han03,
1592 .compatible = "auo,b133htn01",
1593 .data = &auo_b133htn01,
1595 .compatible = "auo,b133xtn01",
1596 .data = &auo_b133xtn01,
1598 .compatible = "avic,tm070ddh03",
1599 .data = &avic_tm070ddh03,
1601 .compatible = "boe,nv125fhm-n73",
1602 .data = &boe_nv125fhm_n73,
1604 .compatible = "chunghwa,claa070wp03xg",
1605 .data = &chunghwa_claa070wp03xg,
1607 .compatible = "chunghwa,claa101wa01a",
1608 .data = &chunghwa_claa101wa01a
1610 .compatible = "chunghwa,claa101wb01",
1611 .data = &chunghwa_claa101wb01
1613 .compatible = "edt,et057090dhu",
1614 .data = &edt_et057090dhu,
1616 .compatible = "edt,et070080dh6",
1617 .data = &edt_etm0700g0dh6,
1619 .compatible = "edt,etm0700g0dh6",
1620 .data = &edt_etm0700g0dh6,
1622 .compatible = "foxlink,fl500wvr00-a0t",
1623 .data = &foxlink_fl500wvr00_a0t,
1625 .compatible = "giantplus,gpg482739qs5",
1626 .data = &giantplus_gpg482739qs5
1628 .compatible = "hannstar,hsd070pww1",
1629 .data = &hannstar_hsd070pww1,
1631 .compatible = "hannstar,hsd100pxn1",
1632 .data = &hannstar_hsd100pxn1,
1634 .compatible = "hit,tx23d38vm0caa",
1635 .data = &hitachi_tx23d38vm0caa
1637 .compatible = "innolux,at043tn24",
1638 .data = &innolux_at043tn24,
1640 .compatible ="innolux,g121i1-l01",
1641 .data = &innolux_g121i1_l01
1643 .compatible = "innolux,n116bge",
1644 .data = &innolux_n116bge,
1646 .compatible = "innolux,n125hce",
1647 .data = &innolux_n125hce,
1649 .compatible = "innolux,n156bge-l21",
1650 .data = &innolux_n156bge_l21,
1652 .compatible = "innolux,zj070na-01p",
1653 .data = &innolux_zj070na_01p,
1655 .compatible = "lg,lb070wv8",
1656 .data = &lg_lb070wv8,
1658 .compatible = "lg,lp079qx1-sp0v",
1659 .data = &lg_lp079qx1_sp0v,
1661 .compatible = "lg,lp097qx1-spa1",
1662 .data = &lg_lp097qx1_spa1,
1664 .compatible = "lg,lp129qe",
1665 .data = &lg_lp129qe,
1667 .compatible = "nec,nl4827hc19-05b",
1668 .data = &nec_nl4827hc19_05b,
1670 .compatible = "okaya,rs800480t-7x0gp",
1671 .data = &okaya_rs800480t_7x0gp,
1673 .compatible = "ortustech,com43h4m85ulc",
1674 .data = &ortustech_com43h4m85ulc,
1676 .compatible = "samsung,lsn122dl01-c01",
1677 .data = &samsung_lsn122dl01_c01,
1679 .compatible = "samsung,ltn101nt05",
1680 .data = &samsung_ltn101nt05,
1682 .compatible = "samsung,ltn140at29-301",
1683 .data = &samsung_ltn140at29_301,
1685 .compatible = "sharp,lcd-f402",
1686 .data = &sharp_lcd_f402,
1688 .compatible = "shelly,sca07010-bfn-lnn",
1689 .data = &shelly_sca07010_bfn_lnn,
1694 MODULE_DEVICE_TABLE(of, platform_of_match);
1696 static int panel_simple_platform_probe(struct platform_device *pdev)
1698 const struct of_device_id *id;
1700 id = of_match_node(platform_of_match, pdev->dev.of_node);
1704 return panel_simple_probe(&pdev->dev, id->data);
1707 static int panel_simple_platform_remove(struct platform_device *pdev)
1709 return panel_simple_remove(&pdev->dev);
1712 static void panel_simple_platform_shutdown(struct platform_device *pdev)
1714 panel_simple_shutdown(&pdev->dev);
1717 static struct platform_driver panel_simple_platform_driver = {
1719 .name = "panel-simple",
1720 .of_match_table = platform_of_match,
1722 .probe = panel_simple_platform_probe,
1723 .remove = panel_simple_platform_remove,
1724 .shutdown = panel_simple_platform_shutdown,
1727 struct panel_desc_dsi {
1728 struct panel_desc desc;
1730 unsigned long flags;
1731 enum mipi_dsi_pixel_format format;
1735 static const struct drm_display_mode auo_b080uan01_mode = {
1738 .hsync_start = 1200 + 62,
1739 .hsync_end = 1200 + 62 + 4,
1740 .htotal = 1200 + 62 + 4 + 62,
1742 .vsync_start = 1920 + 9,
1743 .vsync_end = 1920 + 9 + 2,
1744 .vtotal = 1920 + 9 + 2 + 8,
1748 static const struct panel_desc_dsi auo_b080uan01 = {
1750 .modes = &auo_b080uan01_mode,
1758 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1759 .format = MIPI_DSI_FMT_RGB888,
1763 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
1766 .hsync_start = 1200 + 120,
1767 .hsync_end = 1200 + 120 + 20,
1768 .htotal = 1200 + 120 + 20 + 21,
1770 .vsync_start = 1920 + 21,
1771 .vsync_end = 1920 + 21 + 3,
1772 .vtotal = 1920 + 21 + 3 + 18,
1774 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1777 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
1779 .modes = &boe_tv080wum_nl0_mode,
1786 .flags = MIPI_DSI_MODE_VIDEO |
1787 MIPI_DSI_MODE_VIDEO_BURST |
1788 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
1789 .format = MIPI_DSI_FMT_RGB888,
1793 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
1796 .hsync_start = 800 + 32,
1797 .hsync_end = 800 + 32 + 1,
1798 .htotal = 800 + 32 + 1 + 57,
1800 .vsync_start = 1280 + 28,
1801 .vsync_end = 1280 + 28 + 1,
1802 .vtotal = 1280 + 28 + 1 + 14,
1806 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
1808 .modes = &lg_ld070wx3_sl01_mode,
1816 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1817 .format = MIPI_DSI_FMT_RGB888,
1821 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
1824 .hsync_start = 720 + 12,
1825 .hsync_end = 720 + 12 + 4,
1826 .htotal = 720 + 12 + 4 + 112,
1828 .vsync_start = 1280 + 8,
1829 .vsync_end = 1280 + 8 + 4,
1830 .vtotal = 1280 + 8 + 4 + 12,
1834 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
1836 .modes = &lg_lh500wx1_sd03_mode,
1844 .flags = MIPI_DSI_MODE_VIDEO,
1845 .format = MIPI_DSI_FMT_RGB888,
1849 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
1852 .hsync_start = 1920 + 154,
1853 .hsync_end = 1920 + 154 + 16,
1854 .htotal = 1920 + 154 + 16 + 32,
1856 .vsync_start = 1200 + 17,
1857 .vsync_end = 1200 + 17 + 2,
1858 .vtotal = 1200 + 17 + 2 + 16,
1862 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
1864 .modes = &panasonic_vvx10f004b00_mode,
1872 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
1873 MIPI_DSI_CLOCK_NON_CONTINUOUS,
1874 .format = MIPI_DSI_FMT_RGB888,
1879 static const struct of_device_id dsi_of_match[] = {
1881 .compatible = "simple-panel-dsi",
1884 .compatible = "auo,b080uan01",
1885 .data = &auo_b080uan01
1887 .compatible = "boe,tv080wum-nl0",
1888 .data = &boe_tv080wum_nl0
1890 .compatible = "lg,ld070wx3-sl01",
1891 .data = &lg_ld070wx3_sl01
1893 .compatible = "lg,lh500wx1-sd03",
1894 .data = &lg_lh500wx1_sd03
1896 .compatible = "panasonic,vvx10f004b00",
1897 .data = &panasonic_vvx10f004b00
1902 MODULE_DEVICE_TABLE(of, dsi_of_match);
1904 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
1906 struct panel_simple *panel;
1907 const struct panel_desc_dsi *desc;
1908 const struct of_device_id *id;
1909 const struct panel_desc *pdesc;
1915 id = of_match_node(dsi_of_match, dsi->dev.of_node);
1922 dsi->mode_flags = desc->flags;
1923 dsi->format = desc->format;
1924 dsi->lanes = desc->lanes;
1925 pdesc = &desc->desc;
1930 err = panel_simple_probe(&dsi->dev, pdesc);
1934 panel = dev_get_drvdata(&dsi->dev);
1937 if (!of_property_read_u32(dsi->dev.of_node, "dsi,flags", &val))
1938 dsi->mode_flags = val;
1940 if (!of_property_read_u32(dsi->dev.of_node, "dsi,format", &val))
1943 if (!of_property_read_u32(dsi->dev.of_node, "dsi,lanes", &val))
1946 if (!of_property_read_u32(dsi->dev.of_node, "reset-delay-ms", &val))
1947 panel->reset_delay = val;
1949 data = of_get_property(dsi->dev.of_node, "panel-init-sequence", &len);
1951 panel->on_cmds = devm_kzalloc(&dsi->dev,
1952 sizeof(*panel->on_cmds),
1954 if (!panel->on_cmds)
1957 err = panel_simple_dsi_parse_dcs_cmds(&dsi->dev, data, len,
1960 dev_err(&dsi->dev, "failed to parse panel init sequence\n");
1965 data = of_get_property(dsi->dev.of_node, "panel-exit-sequence", &len);
1967 panel->off_cmds = devm_kzalloc(&dsi->dev,
1968 sizeof(*panel->off_cmds),
1970 if (!panel->off_cmds)
1973 err = panel_simple_dsi_parse_dcs_cmds(&dsi->dev, data, len,
1976 dev_err(&dsi->dev, "failed to parse panel exit sequence\n");
1981 return mipi_dsi_attach(dsi);
1984 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
1988 err = mipi_dsi_detach(dsi);
1990 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
1992 return panel_simple_remove(&dsi->dev);
1995 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
1997 panel_simple_shutdown(&dsi->dev);
2000 static struct mipi_dsi_driver panel_simple_dsi_driver = {
2002 .name = "panel-simple-dsi",
2003 .of_match_table = dsi_of_match,
2005 .probe = panel_simple_dsi_probe,
2006 .remove = panel_simple_dsi_remove,
2007 .shutdown = panel_simple_dsi_shutdown,
2010 static int __init panel_simple_init(void)
2014 err = platform_driver_register(&panel_simple_platform_driver);
2018 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
2019 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
2026 module_init(panel_simple_init);
2028 static void __exit panel_simple_exit(void)
2030 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
2031 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
2033 platform_driver_unregister(&panel_simple_platform_driver);
2035 module_exit(panel_simple_exit);
2037 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
2038 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
2039 MODULE_LICENSE("GPL and additional rights");