2 * Copyright 2012 Nouveau Community
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Martin Peres <martin.peres@labri.fr>
29 nvc0_bus_intr(struct nouveau_subdev *subdev)
31 struct nouveau_bus *pbus = nouveau_bus(subdev);
32 u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140);
34 if (stat & 0x0000000e) {
35 u32 addr = nv_rd32(pbus, 0x009084);
36 u32 data = nv_rd32(pbus, 0x009088);
38 nv_error(pbus, "MMIO %s of 0x%08x FAULT at 0x%06x [ %s%s%s]\n",
39 (addr & 0x00000002) ? "write" : "read", data,
41 (stat & 0x00000002) ? "!ENGINE " : "",
42 (stat & 0x00000004) ? "IBUS " : "",
43 (stat & 0x00000008) ? "TIMEOUT " : "");
45 nv_wr32(pbus, 0x009084, 0x00000000);
46 nv_wr32(pbus, 0x001100, (stat & 0x0000000e));
51 nv_error(pbus, "unknown intr 0x%08x\n", stat);
52 nv_mask(pbus, 0x001140, stat, 0x00000000);
57 nvc0_bus_init(struct nouveau_object *object)
59 struct nv04_bus_priv *priv = (void *)object;
62 ret = nouveau_bus_init(&priv->base);
66 nv_wr32(priv, 0x001100, 0xffffffff);
67 nv_wr32(priv, 0x001140, 0x0000000e);
71 struct nouveau_oclass *
72 nvc0_bus_oclass = &(struct nv04_bus_impl) {
73 .base.handle = NV_SUBDEV(BUS, 0xc0),
74 .base.ofuncs = &(struct nouveau_ofuncs) {
75 .ctor = nv04_bus_ctor,
76 .dtor = _nouveau_bus_dtor,
77 .init = nvc0_bus_init,
78 .fini = _nouveau_bus_fini,
80 .intr = nvc0_bus_intr,