2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <subdev/bios.h>
25 #include <subdev/bios/bit.h>
26 #include <subdev/bios/bmp.h>
27 #include <subdev/bios/conn.h>
28 #include <subdev/bios/dcb.h>
29 #include <subdev/bios/dp.h>
30 #include <subdev/bios/gpio.h>
31 #include <subdev/bios/init.h>
32 #include <subdev/bios/ramcfg.h>
34 #include <subdev/devinit.h>
35 #include <subdev/gpio.h>
36 #include <subdev/i2c.h>
37 #include <subdev/vga.h>
39 #define bioslog(lvl, fmt, args...) do { \
40 nvkm_printk(init->subdev, lvl, info, "0x%04x[%c]: "fmt, \
41 init->offset, init_exec(init) ? \
42 '0' + (init->nested - 1) : ' ', ##args); \
44 #define cont(fmt, args...) do { \
45 if (init->subdev->debug >= NV_DBG_TRACE) \
46 printk(fmt, ##args); \
48 #define trace(fmt, args...) bioslog(TRACE, fmt, ##args)
49 #define warn(fmt, args...) bioslog(WARN, fmt, ##args)
50 #define error(fmt, args...) bioslog(ERROR, fmt, ##args)
52 /******************************************************************************
53 * init parser control flow helpers
54 *****************************************************************************/
57 init_exec(struct nvbios_init *init)
59 return (init->execute == 1) || ((init->execute & 5) == 5);
63 init_exec_set(struct nvbios_init *init, bool exec)
65 if (exec) init->execute &= 0xfd;
66 else init->execute |= 0x02;
70 init_exec_inv(struct nvbios_init *init)
72 init->execute ^= 0x02;
76 init_exec_force(struct nvbios_init *init, bool exec)
78 if (exec) init->execute |= 0x04;
79 else init->execute &= 0xfb;
82 /******************************************************************************
83 * init parser wrappers for normal register/i2c/whatever accessors
84 *****************************************************************************/
87 init_or(struct nvbios_init *init)
89 if (init_exec(init)) {
91 return ffs(init->outp->or) - 1;
92 error("script needs OR!!\n");
98 init_link(struct nvbios_init *init)
100 if (init_exec(init)) {
102 return !(init->outp->sorconf.link & 1);
103 error("script needs OR link\n");
109 init_crtc(struct nvbios_init *init)
111 if (init_exec(init)) {
114 error("script needs crtc\n");
120 init_conn(struct nvbios_init *init)
122 struct nvkm_bios *bios = init->bios;
123 struct nvbios_connE connE;
127 if (init_exec(init)) {
129 conn = init->outp->connector;
130 conn = nvbios_connEp(bios, conn, &ver, &hdr, &connE);
135 error("script needs connector type\n");
142 init_nvreg(struct nvbios_init *init, u32 reg)
144 struct nvkm_devinit *devinit = nvkm_devinit(init->bios);
146 /* C51 (at least) sometimes has the lower bits set which the VBIOS
147 * interprets to mean that access needs to go through certain IO
148 * ports instead. The NVIDIA binary driver has been seen to access
149 * these through the NV register address, so lets assume we can
154 /* GF8+ display scripts need register addresses mangled a bit to
155 * select a specific CRTC/OR
157 if (nv_device(init->bios)->card_type >= NV_50) {
158 if (reg & 0x80000000) {
159 reg += init_crtc(init) * 0x800;
163 if (reg & 0x40000000) {
164 reg += init_or(init) * 0x800;
166 if (reg & 0x20000000) {
167 reg += init_link(init) * 0x80;
173 if (reg & ~0x00fffffc)
174 warn("unknown bits in register 0x%08x\n", reg);
177 reg = devinit->mmio(devinit, reg);
182 init_rd32(struct nvbios_init *init, u32 reg)
184 struct nvkm_device *device = init->bios->subdev.device;
185 reg = init_nvreg(init, reg);
186 if (reg != ~0 && init_exec(init))
187 return nvkm_rd32(device, reg);
192 init_wr32(struct nvbios_init *init, u32 reg, u32 val)
194 struct nvkm_device *device = init->bios->subdev.device;
195 reg = init_nvreg(init, reg);
196 if (reg != ~0 && init_exec(init))
197 nvkm_wr32(device, reg, val);
201 init_mask(struct nvbios_init *init, u32 reg, u32 mask, u32 val)
203 struct nvkm_device *device = init->bios->subdev.device;
204 reg = init_nvreg(init, reg);
205 if (reg != ~0 && init_exec(init)) {
206 u32 tmp = nvkm_rd32(device, reg);
207 nvkm_wr32(device, reg, (tmp & ~mask) | val);
214 init_rdport(struct nvbios_init *init, u16 port)
217 return nvkm_rdport(init->subdev->device, init->crtc, port);
222 init_wrport(struct nvbios_init *init, u16 port, u8 value)
225 nvkm_wrport(init->subdev->device, init->crtc, port, value);
229 init_rdvgai(struct nvbios_init *init, u16 port, u8 index)
231 struct nvkm_subdev *subdev = init->subdev;
232 if (init_exec(init)) {
233 int head = init->crtc < 0 ? 0 : init->crtc;
234 return nvkm_rdvgai(subdev->device, head, port, index);
240 init_wrvgai(struct nvbios_init *init, u16 port, u8 index, u8 value)
242 struct nvkm_device *device = init->subdev->device;
244 /* force head 0 for updates to cr44, it only exists on first head */
245 if (device->card_type < NV_50) {
246 if (port == 0x03d4 && index == 0x44)
250 if (init_exec(init)) {
251 int head = init->crtc < 0 ? 0 : init->crtc;
252 nvkm_wrvgai(device, head, port, index, value);
255 /* select head 1 if cr44 write selected it */
256 if (device->card_type < NV_50) {
257 if (port == 0x03d4 && index == 0x44 && value == 3)
262 static struct nvkm_i2c_port *
263 init_i2c(struct nvbios_init *init, int index)
265 struct nvkm_i2c *i2c = nvkm_i2c(init->bios);
268 index = NV_I2C_DEFAULT(0);
269 if (init->outp && init->outp->i2c_upper_default)
270 index = NV_I2C_DEFAULT(1);
275 error("script needs output for i2c\n");
279 if (index == -2 && init->outp->location) {
280 index = NV_I2C_TYPE_EXTAUX(init->outp->extdev);
281 return i2c->find_type(i2c, index);
284 index = init->outp->i2c_index;
285 if (init->outp->type == DCB_OUTPUT_DP)
286 index += NV_I2C_AUX(0);
289 return i2c->find(i2c, index);
293 init_rdi2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg)
295 struct nvkm_i2c_port *port = init_i2c(init, index);
296 if (port && init_exec(init))
297 return nv_rdi2cr(port, addr, reg);
302 init_wri2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg, u8 val)
304 struct nvkm_i2c_port *port = init_i2c(init, index);
305 if (port && init_exec(init))
306 return nv_wri2cr(port, addr, reg, val);
311 init_rdauxr(struct nvbios_init *init, u32 addr)
313 struct nvkm_i2c_port *port = init_i2c(init, -2);
316 if (port && init_exec(init)) {
317 int ret = nv_rdaux(port, addr, &data, 1);
320 trace("auxch read failed with %d\n", ret);
327 init_wrauxr(struct nvbios_init *init, u32 addr, u8 data)
329 struct nvkm_i2c_port *port = init_i2c(init, -2);
330 if (port && init_exec(init)) {
331 int ret = nv_wraux(port, addr, &data, 1);
333 trace("auxch write failed with %d\n", ret);
340 init_prog_pll(struct nvbios_init *init, u32 id, u32 freq)
342 struct nvkm_devinit *devinit = nvkm_devinit(init->bios);
343 if (devinit->pll_set && init_exec(init)) {
344 int ret = devinit->pll_set(devinit, id, freq);
346 warn("failed to prog pll 0x%08x to %dkHz\n", id, freq);
350 /******************************************************************************
351 * parsing of bios structures that are required to execute init tables
352 *****************************************************************************/
355 init_table(struct nvkm_bios *bios, u16 *len)
357 struct bit_entry bit_I;
359 if (!bit_entry(bios, 'I', &bit_I)) {
364 if (bmp_version(bios) >= 0x0510) {
366 return bios->bmp_offset + 75;
373 init_table_(struct nvbios_init *init, u16 offset, const char *name)
375 struct nvkm_bios *bios = init->bios;
376 u16 len, data = init_table(bios, &len);
378 if (len >= offset + 2) {
379 data = nvbios_rd16(bios, data + offset);
383 warn("%s pointer invalid\n", name);
387 warn("init data too short for %s pointer", name);
391 warn("init data not found\n");
395 #define init_script_table(b) init_table_((b), 0x00, "script table")
396 #define init_macro_index_table(b) init_table_((b), 0x02, "macro index table")
397 #define init_macro_table(b) init_table_((b), 0x04, "macro table")
398 #define init_condition_table(b) init_table_((b), 0x06, "condition table")
399 #define init_io_condition_table(b) init_table_((b), 0x08, "io condition table")
400 #define init_io_flag_condition_table(b) init_table_((b), 0x0a, "io flag conditon table")
401 #define init_function_table(b) init_table_((b), 0x0c, "function table")
402 #define init_xlat_table(b) init_table_((b), 0x10, "xlat table");
405 init_script(struct nvkm_bios *bios, int index)
407 struct nvbios_init init = { .bios = bios };
408 u16 bmp_ver = bmp_version(bios), data;
410 if (bmp_ver && bmp_ver < 0x0510) {
411 if (index > 1 || bmp_ver < 0x0100)
414 data = bios->bmp_offset + (bmp_ver < 0x0200 ? 14 : 18);
415 return nvbios_rd16(bios, data + (index * 2));
418 data = init_script_table(&init);
420 return nvbios_rd16(bios, data + (index * 2));
426 init_unknown_script(struct nvkm_bios *bios)
428 u16 len, data = init_table(bios, &len);
429 if (data && len >= 16)
430 return nvbios_rd16(bios, data + 14);
435 init_ram_restrict_group_count(struct nvbios_init *init)
437 return nvbios_ramcfg_count(init->bios);
441 init_ram_restrict(struct nvbios_init *init)
443 /* This appears to be the behaviour of the VBIOS parser, and *is*
444 * important to cache the NV_PEXTDEV_BOOT0 on later chipsets to
445 * avoid fucking up the memory controller (somehow) by reading it
446 * on every INIT_RAM_RESTRICT_ZM_GROUP opcode.
448 * Preserving the non-caching behaviour on earlier chipsets just
449 * in case *not* re-reading the strap causes similar breakage.
451 if (!init->ramcfg || init->bios->version.major < 0x70)
452 init->ramcfg = 0x80000000 | nvbios_ramcfg_index(init->subdev);
453 return (init->ramcfg & 0x7fffffff);
457 init_xlat_(struct nvbios_init *init, u8 index, u8 offset)
459 struct nvkm_bios *bios = init->bios;
460 u16 table = init_xlat_table(init);
462 u16 data = nvbios_rd16(bios, table + (index * 2));
464 return nvbios_rd08(bios, data + offset);
465 warn("xlat table pointer %d invalid\n", index);
470 /******************************************************************************
471 * utility functions used by various init opcode handlers
472 *****************************************************************************/
475 init_condition_met(struct nvbios_init *init, u8 cond)
477 struct nvkm_bios *bios = init->bios;
478 u16 table = init_condition_table(init);
480 u32 reg = nvbios_rd32(bios, table + (cond * 12) + 0);
481 u32 msk = nvbios_rd32(bios, table + (cond * 12) + 4);
482 u32 val = nvbios_rd32(bios, table + (cond * 12) + 8);
483 trace("\t[0x%02x] (R[0x%06x] & 0x%08x) == 0x%08x\n",
484 cond, reg, msk, val);
485 return (init_rd32(init, reg) & msk) == val;
491 init_io_condition_met(struct nvbios_init *init, u8 cond)
493 struct nvkm_bios *bios = init->bios;
494 u16 table = init_io_condition_table(init);
496 u16 port = nvbios_rd16(bios, table + (cond * 5) + 0);
497 u8 index = nvbios_rd08(bios, table + (cond * 5) + 2);
498 u8 mask = nvbios_rd08(bios, table + (cond * 5) + 3);
499 u8 value = nvbios_rd08(bios, table + (cond * 5) + 4);
500 trace("\t[0x%02x] (0x%04x[0x%02x] & 0x%02x) == 0x%02x\n",
501 cond, port, index, mask, value);
502 return (init_rdvgai(init, port, index) & mask) == value;
508 init_io_flag_condition_met(struct nvbios_init *init, u8 cond)
510 struct nvkm_bios *bios = init->bios;
511 u16 table = init_io_flag_condition_table(init);
513 u16 port = nvbios_rd16(bios, table + (cond * 9) + 0);
514 u8 index = nvbios_rd08(bios, table + (cond * 9) + 2);
515 u8 mask = nvbios_rd08(bios, table + (cond * 9) + 3);
516 u8 shift = nvbios_rd08(bios, table + (cond * 9) + 4);
517 u16 data = nvbios_rd16(bios, table + (cond * 9) + 5);
518 u8 dmask = nvbios_rd08(bios, table + (cond * 9) + 7);
519 u8 value = nvbios_rd08(bios, table + (cond * 9) + 8);
520 u8 ioval = (init_rdvgai(init, port, index) & mask) >> shift;
521 return (nvbios_rd08(bios, data + ioval) & dmask) == value;
527 init_shift(u32 data, u8 shift)
530 return data >> shift;
531 return data << (0x100 - shift);
535 init_tmds_reg(struct nvbios_init *init, u8 tmds)
537 /* For mlv < 0x80, it is an index into a table of TMDS base addresses.
538 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
539 * CR58 for CR57 = 0 to index a table of offsets to the basic
541 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
542 * CR58 for CR57 = 0 to index a table of offsets to the basic
543 * 0x6808b0 address, and then flip the offset by 8.
545 const int pramdac_offset[13] = {
546 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
547 const u32 pramdac_table[4] = {
548 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
552 u32 dacoffset = pramdac_offset[init->outp->or];
555 return 0x6808b0 + dacoffset;
559 error("tmds opcodes need dcb\n");
561 if (tmds < ARRAY_SIZE(pramdac_table))
562 return pramdac_table[tmds];
564 error("tmds selector 0x%02x unknown\n", tmds);
570 /******************************************************************************
571 * init opcode handlers
572 *****************************************************************************/
575 * init_reserved - stub for various unknown/unused single-byte opcodes
579 init_reserved(struct nvbios_init *init)
581 u8 opcode = nvbios_rd08(init->bios, init->offset);
593 trace("RESERVED 0x%02x\t", opcode);
594 for (i = 1; i < length; i++)
595 cont(" 0x%02x", nvbios_rd08(init->bios, init->offset + i));
597 init->offset += length;
601 * INIT_DONE - opcode 0x71
605 init_done(struct nvbios_init *init)
608 init->offset = 0x0000;
612 * INIT_IO_RESTRICT_PROG - opcode 0x32
616 init_io_restrict_prog(struct nvbios_init *init)
618 struct nvkm_bios *bios = init->bios;
619 u16 port = nvbios_rd16(bios, init->offset + 1);
620 u8 index = nvbios_rd08(bios, init->offset + 3);
621 u8 mask = nvbios_rd08(bios, init->offset + 4);
622 u8 shift = nvbios_rd08(bios, init->offset + 5);
623 u8 count = nvbios_rd08(bios, init->offset + 6);
624 u32 reg = nvbios_rd32(bios, init->offset + 7);
627 trace("IO_RESTRICT_PROG\tR[0x%06x] = "
628 "((0x%04x[0x%02x] & 0x%02x) >> %d) [{\n",
629 reg, port, index, mask, shift);
632 conf = (init_rdvgai(init, port, index) & mask) >> shift;
633 for (i = 0; i < count; i++) {
634 u32 data = nvbios_rd32(bios, init->offset);
637 trace("\t0x%08x *\n", data);
638 init_wr32(init, reg, data);
640 trace("\t0x%08x\n", data);
649 * INIT_REPEAT - opcode 0x33
653 init_repeat(struct nvbios_init *init)
655 struct nvkm_bios *bios = init->bios;
656 u8 count = nvbios_rd08(bios, init->offset + 1);
657 u16 repeat = init->repeat;
659 trace("REPEAT\t0x%02x\n", count);
662 init->repeat = init->offset;
663 init->repend = init->offset;
665 init->offset = init->repeat;
668 trace("REPEAT\t0x%02x\n", count);
670 init->offset = init->repend;
671 init->repeat = repeat;
675 * INIT_IO_RESTRICT_PLL - opcode 0x34
679 init_io_restrict_pll(struct nvbios_init *init)
681 struct nvkm_bios *bios = init->bios;
682 u16 port = nvbios_rd16(bios, init->offset + 1);
683 u8 index = nvbios_rd08(bios, init->offset + 3);
684 u8 mask = nvbios_rd08(bios, init->offset + 4);
685 u8 shift = nvbios_rd08(bios, init->offset + 5);
686 s8 iofc = nvbios_rd08(bios, init->offset + 6);
687 u8 count = nvbios_rd08(bios, init->offset + 7);
688 u32 reg = nvbios_rd32(bios, init->offset + 8);
691 trace("IO_RESTRICT_PLL\tR[0x%06x] =PLL= "
692 "((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) IOFCOND 0x%02x [{\n",
693 reg, port, index, mask, shift, iofc);
696 conf = (init_rdvgai(init, port, index) & mask) >> shift;
697 for (i = 0; i < count; i++) {
698 u32 freq = nvbios_rd16(bios, init->offset) * 10;
701 trace("\t%dkHz *\n", freq);
702 if (iofc > 0 && init_io_flag_condition_met(init, iofc))
704 init_prog_pll(init, reg, freq);
706 trace("\t%dkHz\n", freq);
715 * INIT_END_REPEAT - opcode 0x36
719 init_end_repeat(struct nvbios_init *init)
721 trace("END_REPEAT\n");
725 init->repend = init->offset;
731 * INIT_COPY - opcode 0x37
735 init_copy(struct nvbios_init *init)
737 struct nvkm_bios *bios = init->bios;
738 u32 reg = nvbios_rd32(bios, init->offset + 1);
739 u8 shift = nvbios_rd08(bios, init->offset + 5);
740 u8 smask = nvbios_rd08(bios, init->offset + 6);
741 u16 port = nvbios_rd16(bios, init->offset + 7);
742 u8 index = nvbios_rd08(bios, init->offset + 9);
743 u8 mask = nvbios_rd08(bios, init->offset + 10);
746 trace("COPY\t0x%04x[0x%02x] &= 0x%02x |= "
747 "((R[0x%06x] %s 0x%02x) & 0x%02x)\n",
748 port, index, mask, reg, (shift & 0x80) ? "<<" : ">>",
749 (shift & 0x80) ? (0x100 - shift) : shift, smask);
752 data = init_rdvgai(init, port, index) & mask;
753 data |= init_shift(init_rd32(init, reg), shift) & smask;
754 init_wrvgai(init, port, index, data);
758 * INIT_NOT - opcode 0x38
762 init_not(struct nvbios_init *init)
770 * INIT_IO_FLAG_CONDITION - opcode 0x39
774 init_io_flag_condition(struct nvbios_init *init)
776 struct nvkm_bios *bios = init->bios;
777 u8 cond = nvbios_rd08(bios, init->offset + 1);
779 trace("IO_FLAG_CONDITION\t0x%02x\n", cond);
782 if (!init_io_flag_condition_met(init, cond))
783 init_exec_set(init, false);
787 * INIT_DP_CONDITION - opcode 0x3a
791 init_dp_condition(struct nvbios_init *init)
793 struct nvkm_bios *bios = init->bios;
794 struct nvbios_dpout info;
795 u8 cond = nvbios_rd08(bios, init->offset + 1);
796 u8 unkn = nvbios_rd08(bios, init->offset + 2);
797 u8 ver, hdr, cnt, len;
800 trace("DP_CONDITION\t0x%02x 0x%02x\n", cond, unkn);
805 if (init_conn(init) != DCB_CONNECTOR_eDP)
806 init_exec_set(init, false);
811 (data = nvbios_dpout_match(bios, DCB_OUTPUT_DP,
812 (init->outp->or << 0) |
813 (init->outp->sorconf.link << 6),
814 &ver, &hdr, &cnt, &len, &info)))
816 if (!(info.flags & cond))
817 init_exec_set(init, false);
822 warn("script needs dp output table data\n");
825 if (!(init_rdauxr(init, 0x0d) & 1))
826 init_exec_set(init, false);
829 warn("unknown dp condition 0x%02x\n", cond);
835 * INIT_IO_MASK_OR - opcode 0x3b
839 init_io_mask_or(struct nvbios_init *init)
841 struct nvkm_bios *bios = init->bios;
842 u8 index = nvbios_rd08(bios, init->offset + 1);
843 u8 or = init_or(init);
846 trace("IO_MASK_OR\t0x03d4[0x%02x] &= ~(1 << 0x%02x)\n", index, or);
849 data = init_rdvgai(init, 0x03d4, index);
850 init_wrvgai(init, 0x03d4, index, data &= ~(1 << or));
854 * INIT_IO_OR - opcode 0x3c
858 init_io_or(struct nvbios_init *init)
860 struct nvkm_bios *bios = init->bios;
861 u8 index = nvbios_rd08(bios, init->offset + 1);
862 u8 or = init_or(init);
865 trace("IO_OR\t0x03d4[0x%02x] |= (1 << 0x%02x)\n", index, or);
868 data = init_rdvgai(init, 0x03d4, index);
869 init_wrvgai(init, 0x03d4, index, data | (1 << or));
873 * INIT_ANDN_REG - opcode 0x47
877 init_andn_reg(struct nvbios_init *init)
879 struct nvkm_bios *bios = init->bios;
880 u32 reg = nvbios_rd32(bios, init->offset + 1);
881 u32 mask = nvbios_rd32(bios, init->offset + 5);
883 trace("ANDN_REG\tR[0x%06x] &= ~0x%08x\n", reg, mask);
886 init_mask(init, reg, mask, 0);
890 * INIT_OR_REG - opcode 0x48
894 init_or_reg(struct nvbios_init *init)
896 struct nvkm_bios *bios = init->bios;
897 u32 reg = nvbios_rd32(bios, init->offset + 1);
898 u32 mask = nvbios_rd32(bios, init->offset + 5);
900 trace("OR_REG\tR[0x%06x] |= 0x%08x\n", reg, mask);
903 init_mask(init, reg, 0, mask);
907 * INIT_INDEX_ADDRESS_LATCHED - opcode 0x49
911 init_idx_addr_latched(struct nvbios_init *init)
913 struct nvkm_bios *bios = init->bios;
914 u32 creg = nvbios_rd32(bios, init->offset + 1);
915 u32 dreg = nvbios_rd32(bios, init->offset + 5);
916 u32 mask = nvbios_rd32(bios, init->offset + 9);
917 u32 data = nvbios_rd32(bios, init->offset + 13);
918 u8 count = nvbios_rd08(bios, init->offset + 17);
920 trace("INDEX_ADDRESS_LATCHED\tR[0x%06x] : R[0x%06x]\n", creg, dreg);
921 trace("\tCTRL &= 0x%08x |= 0x%08x\n", mask, data);
925 u8 iaddr = nvbios_rd08(bios, init->offset + 0);
926 u8 idata = nvbios_rd08(bios, init->offset + 1);
928 trace("\t[0x%02x] = 0x%02x\n", iaddr, idata);
931 init_wr32(init, dreg, idata);
932 init_mask(init, creg, ~mask, data | iaddr);
937 * INIT_IO_RESTRICT_PLL2 - opcode 0x4a
941 init_io_restrict_pll2(struct nvbios_init *init)
943 struct nvkm_bios *bios = init->bios;
944 u16 port = nvbios_rd16(bios, init->offset + 1);
945 u8 index = nvbios_rd08(bios, init->offset + 3);
946 u8 mask = nvbios_rd08(bios, init->offset + 4);
947 u8 shift = nvbios_rd08(bios, init->offset + 5);
948 u8 count = nvbios_rd08(bios, init->offset + 6);
949 u32 reg = nvbios_rd32(bios, init->offset + 7);
952 trace("IO_RESTRICT_PLL2\t"
953 "R[0x%06x] =PLL= ((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) [{\n",
954 reg, port, index, mask, shift);
957 conf = (init_rdvgai(init, port, index) & mask) >> shift;
958 for (i = 0; i < count; i++) {
959 u32 freq = nvbios_rd32(bios, init->offset);
961 trace("\t%dkHz *\n", freq);
962 init_prog_pll(init, reg, freq);
964 trace("\t%dkHz\n", freq);
972 * INIT_PLL2 - opcode 0x4b
976 init_pll2(struct nvbios_init *init)
978 struct nvkm_bios *bios = init->bios;
979 u32 reg = nvbios_rd32(bios, init->offset + 1);
980 u32 freq = nvbios_rd32(bios, init->offset + 5);
982 trace("PLL2\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
985 init_prog_pll(init, reg, freq);
989 * INIT_I2C_BYTE - opcode 0x4c
993 init_i2c_byte(struct nvbios_init *init)
995 struct nvkm_bios *bios = init->bios;
996 u8 index = nvbios_rd08(bios, init->offset + 1);
997 u8 addr = nvbios_rd08(bios, init->offset + 2) >> 1;
998 u8 count = nvbios_rd08(bios, init->offset + 3);
1000 trace("I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
1004 u8 reg = nvbios_rd08(bios, init->offset + 0);
1005 u8 mask = nvbios_rd08(bios, init->offset + 1);
1006 u8 data = nvbios_rd08(bios, init->offset + 2);
1009 trace("\t[0x%02x] &= 0x%02x |= 0x%02x\n", reg, mask, data);
1012 val = init_rdi2cr(init, index, addr, reg);
1015 init_wri2cr(init, index, addr, reg, (val & mask) | data);
1020 * INIT_ZM_I2C_BYTE - opcode 0x4d
1024 init_zm_i2c_byte(struct nvbios_init *init)
1026 struct nvkm_bios *bios = init->bios;
1027 u8 index = nvbios_rd08(bios, init->offset + 1);
1028 u8 addr = nvbios_rd08(bios, init->offset + 2) >> 1;
1029 u8 count = nvbios_rd08(bios, init->offset + 3);
1031 trace("ZM_I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
1035 u8 reg = nvbios_rd08(bios, init->offset + 0);
1036 u8 data = nvbios_rd08(bios, init->offset + 1);
1038 trace("\t[0x%02x] = 0x%02x\n", reg, data);
1041 init_wri2cr(init, index, addr, reg, data);
1046 * INIT_ZM_I2C - opcode 0x4e
1050 init_zm_i2c(struct nvbios_init *init)
1052 struct nvkm_bios *bios = init->bios;
1053 u8 index = nvbios_rd08(bios, init->offset + 1);
1054 u8 addr = nvbios_rd08(bios, init->offset + 2) >> 1;
1055 u8 count = nvbios_rd08(bios, init->offset + 3);
1058 trace("ZM_I2C\tI2C[0x%02x][0x%02x]\n", index, addr);
1061 for (i = 0; i < count; i++) {
1062 data[i] = nvbios_rd08(bios, init->offset);
1063 trace("\t0x%02x\n", data[i]);
1067 if (init_exec(init)) {
1068 struct nvkm_i2c_port *port = init_i2c(init, index);
1069 struct i2c_msg msg = {
1070 .addr = addr, .flags = 0, .len = count, .buf = data,
1074 if (port && (ret = i2c_transfer(&port->adapter, &msg, 1)) != 1)
1075 warn("i2c wr failed, %d\n", ret);
1080 * INIT_TMDS - opcode 0x4f
1084 init_tmds(struct nvbios_init *init)
1086 struct nvkm_bios *bios = init->bios;
1087 u8 tmds = nvbios_rd08(bios, init->offset + 1);
1088 u8 addr = nvbios_rd08(bios, init->offset + 2);
1089 u8 mask = nvbios_rd08(bios, init->offset + 3);
1090 u8 data = nvbios_rd08(bios, init->offset + 4);
1091 u32 reg = init_tmds_reg(init, tmds);
1093 trace("TMDS\tT[0x%02x][0x%02x] &= 0x%02x |= 0x%02x\n",
1094 tmds, addr, mask, data);
1100 init_wr32(init, reg + 0, addr | 0x00010000);
1101 init_wr32(init, reg + 4, data | (init_rd32(init, reg + 4) & mask));
1102 init_wr32(init, reg + 0, addr);
1106 * INIT_ZM_TMDS_GROUP - opcode 0x50
1110 init_zm_tmds_group(struct nvbios_init *init)
1112 struct nvkm_bios *bios = init->bios;
1113 u8 tmds = nvbios_rd08(bios, init->offset + 1);
1114 u8 count = nvbios_rd08(bios, init->offset + 2);
1115 u32 reg = init_tmds_reg(init, tmds);
1117 trace("TMDS_ZM_GROUP\tT[0x%02x]\n", tmds);
1121 u8 addr = nvbios_rd08(bios, init->offset + 0);
1122 u8 data = nvbios_rd08(bios, init->offset + 1);
1124 trace("\t[0x%02x] = 0x%02x\n", addr, data);
1127 init_wr32(init, reg + 4, data);
1128 init_wr32(init, reg + 0, addr);
1133 * INIT_CR_INDEX_ADDRESS_LATCHED - opcode 0x51
1137 init_cr_idx_adr_latch(struct nvbios_init *init)
1139 struct nvkm_bios *bios = init->bios;
1140 u8 addr0 = nvbios_rd08(bios, init->offset + 1);
1141 u8 addr1 = nvbios_rd08(bios, init->offset + 2);
1142 u8 base = nvbios_rd08(bios, init->offset + 3);
1143 u8 count = nvbios_rd08(bios, init->offset + 4);
1146 trace("CR_INDEX_ADDR C[%02x] C[%02x]\n", addr0, addr1);
1149 save0 = init_rdvgai(init, 0x03d4, addr0);
1151 u8 data = nvbios_rd08(bios, init->offset);
1153 trace("\t\t[0x%02x] = 0x%02x\n", base, data);
1156 init_wrvgai(init, 0x03d4, addr0, base++);
1157 init_wrvgai(init, 0x03d4, addr1, data);
1159 init_wrvgai(init, 0x03d4, addr0, save0);
1163 * INIT_CR - opcode 0x52
1167 init_cr(struct nvbios_init *init)
1169 struct nvkm_bios *bios = init->bios;
1170 u8 addr = nvbios_rd08(bios, init->offset + 1);
1171 u8 mask = nvbios_rd08(bios, init->offset + 2);
1172 u8 data = nvbios_rd08(bios, init->offset + 3);
1175 trace("CR\t\tC[0x%02x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
1178 val = init_rdvgai(init, 0x03d4, addr) & mask;
1179 init_wrvgai(init, 0x03d4, addr, val | data);
1183 * INIT_ZM_CR - opcode 0x53
1187 init_zm_cr(struct nvbios_init *init)
1189 struct nvkm_bios *bios = init->bios;
1190 u8 addr = nvbios_rd08(bios, init->offset + 1);
1191 u8 data = nvbios_rd08(bios, init->offset + 2);
1193 trace("ZM_CR\tC[0x%02x] = 0x%02x\n", addr, data);
1196 init_wrvgai(init, 0x03d4, addr, data);
1200 * INIT_ZM_CR_GROUP - opcode 0x54
1204 init_zm_cr_group(struct nvbios_init *init)
1206 struct nvkm_bios *bios = init->bios;
1207 u8 count = nvbios_rd08(bios, init->offset + 1);
1209 trace("ZM_CR_GROUP\n");
1213 u8 addr = nvbios_rd08(bios, init->offset + 0);
1214 u8 data = nvbios_rd08(bios, init->offset + 1);
1216 trace("\t\tC[0x%02x] = 0x%02x\n", addr, data);
1219 init_wrvgai(init, 0x03d4, addr, data);
1224 * INIT_CONDITION_TIME - opcode 0x56
1228 init_condition_time(struct nvbios_init *init)
1230 struct nvkm_bios *bios = init->bios;
1231 u8 cond = nvbios_rd08(bios, init->offset + 1);
1232 u8 retry = nvbios_rd08(bios, init->offset + 2);
1233 u8 wait = min((u16)retry * 50, 100);
1235 trace("CONDITION_TIME\t0x%02x 0x%02x\n", cond, retry);
1238 if (!init_exec(init))
1242 if (init_condition_met(init, cond))
1247 init_exec_set(init, false);
1251 * INIT_LTIME - opcode 0x57
1255 init_ltime(struct nvbios_init *init)
1257 struct nvkm_bios *bios = init->bios;
1258 u16 msec = nvbios_rd16(bios, init->offset + 1);
1260 trace("LTIME\t0x%04x\n", msec);
1263 if (init_exec(init))
1268 * INIT_ZM_REG_SEQUENCE - opcode 0x58
1272 init_zm_reg_sequence(struct nvbios_init *init)
1274 struct nvkm_bios *bios = init->bios;
1275 u32 base = nvbios_rd32(bios, init->offset + 1);
1276 u8 count = nvbios_rd08(bios, init->offset + 5);
1278 trace("ZM_REG_SEQUENCE\t0x%02x\n", count);
1282 u32 data = nvbios_rd32(bios, init->offset);
1284 trace("\t\tR[0x%06x] = 0x%08x\n", base, data);
1287 init_wr32(init, base, data);
1293 * INIT_PLL_INDIRECT - opcode 0x59
1297 init_pll_indirect(struct nvbios_init *init)
1299 struct nvkm_bios *bios = init->bios;
1300 u32 reg = nvbios_rd32(bios, init->offset + 1);
1301 u16 addr = nvbios_rd16(bios, init->offset + 5);
1302 u32 freq = (u32)nvbios_rd16(bios, addr) * 1000;
1304 trace("PLL_INDIRECT\tR[0x%06x] =PLL= VBIOS[%04x] = %dkHz\n",
1308 init_prog_pll(init, reg, freq);
1312 * INIT_ZM_REG_INDIRECT - opcode 0x5a
1316 init_zm_reg_indirect(struct nvbios_init *init)
1318 struct nvkm_bios *bios = init->bios;
1319 u32 reg = nvbios_rd32(bios, init->offset + 1);
1320 u16 addr = nvbios_rd16(bios, init->offset + 5);
1321 u32 data = nvbios_rd32(bios, addr);
1323 trace("ZM_REG_INDIRECT\tR[0x%06x] = VBIOS[0x%04x] = 0x%08x\n",
1327 init_wr32(init, addr, data);
1331 * INIT_SUB_DIRECT - opcode 0x5b
1335 init_sub_direct(struct nvbios_init *init)
1337 struct nvkm_bios *bios = init->bios;
1338 u16 addr = nvbios_rd16(bios, init->offset + 1);
1341 trace("SUB_DIRECT\t0x%04x\n", addr);
1343 if (init_exec(init)) {
1344 save = init->offset;
1345 init->offset = addr;
1346 if (nvbios_exec(init)) {
1347 error("error parsing sub-table\n");
1350 init->offset = save;
1357 * INIT_JUMP - opcode 0x5c
1361 init_jump(struct nvbios_init *init)
1363 struct nvkm_bios *bios = init->bios;
1364 u16 offset = nvbios_rd16(bios, init->offset + 1);
1366 trace("JUMP\t0x%04x\n", offset);
1368 if (init_exec(init))
1369 init->offset = offset;
1375 * INIT_I2C_IF - opcode 0x5e
1379 init_i2c_if(struct nvbios_init *init)
1381 struct nvkm_bios *bios = init->bios;
1382 u8 index = nvbios_rd08(bios, init->offset + 1);
1383 u8 addr = nvbios_rd08(bios, init->offset + 2);
1384 u8 reg = nvbios_rd08(bios, init->offset + 3);
1385 u8 mask = nvbios_rd08(bios, init->offset + 4);
1386 u8 data = nvbios_rd08(bios, init->offset + 5);
1389 trace("I2C_IF\tI2C[0x%02x][0x%02x][0x%02x] & 0x%02x == 0x%02x\n",
1390 index, addr, reg, mask, data);
1392 init_exec_force(init, true);
1394 value = init_rdi2cr(init, index, addr, reg);
1395 if ((value & mask) != data)
1396 init_exec_set(init, false);
1398 init_exec_force(init, false);
1402 * INIT_COPY_NV_REG - opcode 0x5f
1406 init_copy_nv_reg(struct nvbios_init *init)
1408 struct nvkm_bios *bios = init->bios;
1409 u32 sreg = nvbios_rd32(bios, init->offset + 1);
1410 u8 shift = nvbios_rd08(bios, init->offset + 5);
1411 u32 smask = nvbios_rd32(bios, init->offset + 6);
1412 u32 sxor = nvbios_rd32(bios, init->offset + 10);
1413 u32 dreg = nvbios_rd32(bios, init->offset + 14);
1414 u32 dmask = nvbios_rd32(bios, init->offset + 18);
1417 trace("COPY_NV_REG\tR[0x%06x] &= 0x%08x |= "
1418 "((R[0x%06x] %s 0x%02x) & 0x%08x ^ 0x%08x)\n",
1419 dreg, dmask, sreg, (shift & 0x80) ? "<<" : ">>",
1420 (shift & 0x80) ? (0x100 - shift) : shift, smask, sxor);
1423 data = init_shift(init_rd32(init, sreg), shift);
1424 init_mask(init, dreg, ~dmask, (data & smask) ^ sxor);
1428 * INIT_ZM_INDEX_IO - opcode 0x62
1432 init_zm_index_io(struct nvbios_init *init)
1434 struct nvkm_bios *bios = init->bios;
1435 u16 port = nvbios_rd16(bios, init->offset + 1);
1436 u8 index = nvbios_rd08(bios, init->offset + 3);
1437 u8 data = nvbios_rd08(bios, init->offset + 4);
1439 trace("ZM_INDEX_IO\tI[0x%04x][0x%02x] = 0x%02x\n", port, index, data);
1442 init_wrvgai(init, port, index, data);
1446 * INIT_COMPUTE_MEM - opcode 0x63
1450 init_compute_mem(struct nvbios_init *init)
1452 struct nvkm_devinit *devinit = nvkm_devinit(init->bios);
1454 trace("COMPUTE_MEM\n");
1457 init_exec_force(init, true);
1458 if (init_exec(init) && devinit->meminit)
1459 devinit->meminit(devinit);
1460 init_exec_force(init, false);
1464 * INIT_RESET - opcode 0x65
1468 init_reset(struct nvbios_init *init)
1470 struct nvkm_bios *bios = init->bios;
1471 u32 reg = nvbios_rd32(bios, init->offset + 1);
1472 u32 data1 = nvbios_rd32(bios, init->offset + 5);
1473 u32 data2 = nvbios_rd32(bios, init->offset + 9);
1476 trace("RESET\tR[0x%08x] = 0x%08x, 0x%08x", reg, data1, data2);
1478 init_exec_force(init, true);
1480 savepci19 = init_mask(init, 0x00184c, 0x00000f00, 0x00000000);
1481 init_wr32(init, reg, data1);
1483 init_wr32(init, reg, data2);
1484 init_wr32(init, 0x00184c, savepci19);
1485 init_mask(init, 0x001850, 0x00000001, 0x00000000);
1487 init_exec_force(init, false);
1491 * INIT_CONFIGURE_MEM - opcode 0x66
1495 init_configure_mem_clk(struct nvbios_init *init)
1497 u16 mdata = bmp_mem_init_table(init->bios);
1499 mdata += (init_rdvgai(init, 0x03d4, 0x3c) >> 4) * 66;
1504 init_configure_mem(struct nvbios_init *init)
1506 struct nvkm_bios *bios = init->bios;
1510 trace("CONFIGURE_MEM\n");
1513 if (bios->version.major > 2) {
1517 init_exec_force(init, true);
1519 mdata = init_configure_mem_clk(init);
1520 sdata = bmp_sdr_seq_table(bios);
1521 if (nvbios_rd08(bios, mdata) & 0x01)
1522 sdata = bmp_ddr_seq_table(bios);
1523 mdata += 6; /* skip to data */
1525 data = init_rdvgai(init, 0x03c4, 0x01);
1526 init_wrvgai(init, 0x03c4, 0x01, data | 0x20);
1528 for (; (addr = nvbios_rd32(bios, sdata)) != 0xffffffff; sdata += 4) {
1530 case 0x10021c: /* CKE_NORMAL */
1531 case 0x1002d0: /* CMD_REFRESH */
1532 case 0x1002d4: /* CMD_PRECHARGE */
1536 data = nvbios_rd32(bios, mdata);
1538 if (data == 0xffffffff)
1543 init_wr32(init, addr, data);
1546 init_exec_force(init, false);
1550 * INIT_CONFIGURE_CLK - opcode 0x67
1554 init_configure_clk(struct nvbios_init *init)
1556 struct nvkm_bios *bios = init->bios;
1559 trace("CONFIGURE_CLK\n");
1562 if (bios->version.major > 2) {
1566 init_exec_force(init, true);
1568 mdata = init_configure_mem_clk(init);
1571 clock = nvbios_rd16(bios, mdata + 4) * 10;
1572 init_prog_pll(init, 0x680500, clock);
1575 clock = nvbios_rd16(bios, mdata + 2) * 10;
1576 if (nvbios_rd08(bios, mdata) & 0x01)
1578 init_prog_pll(init, 0x680504, clock);
1580 init_exec_force(init, false);
1584 * INIT_CONFIGURE_PREINIT - opcode 0x68
1588 init_configure_preinit(struct nvbios_init *init)
1590 struct nvkm_bios *bios = init->bios;
1593 trace("CONFIGURE_PREINIT\n");
1596 if (bios->version.major > 2) {
1600 init_exec_force(init, true);
1602 strap = init_rd32(init, 0x101000);
1603 strap = ((strap << 2) & 0xf0) | ((strap & 0x40) >> 6);
1604 init_wrvgai(init, 0x03d4, 0x3c, strap);
1606 init_exec_force(init, false);
1610 * INIT_IO - opcode 0x69
1614 init_io(struct nvbios_init *init)
1616 struct nvkm_bios *bios = init->bios;
1617 u16 port = nvbios_rd16(bios, init->offset + 1);
1618 u8 mask = nvbios_rd16(bios, init->offset + 3);
1619 u8 data = nvbios_rd16(bios, init->offset + 4);
1622 trace("IO\t\tI[0x%04x] &= 0x%02x |= 0x%02x\n", port, mask, data);
1625 /* ummm.. yes.. should really figure out wtf this is and why it's
1626 * needed some day.. it's almost certainly wrong, but, it also
1627 * somehow makes things work...
1629 if (nv_device(init->bios)->card_type >= NV_50 &&
1630 port == 0x03c3 && data == 0x01) {
1631 init_mask(init, 0x614100, 0xf0800000, 0x00800000);
1632 init_mask(init, 0x00e18c, 0x00020000, 0x00020000);
1633 init_mask(init, 0x614900, 0xf0800000, 0x00800000);
1634 init_mask(init, 0x000200, 0x40000000, 0x00000000);
1636 init_mask(init, 0x00e18c, 0x00020000, 0x00000000);
1637 init_mask(init, 0x000200, 0x40000000, 0x40000000);
1638 init_wr32(init, 0x614100, 0x00800018);
1639 init_wr32(init, 0x614900, 0x00800018);
1641 init_wr32(init, 0x614100, 0x10000018);
1642 init_wr32(init, 0x614900, 0x10000018);
1645 value = init_rdport(init, port) & mask;
1646 init_wrport(init, port, data | value);
1650 * INIT_SUB - opcode 0x6b
1654 init_sub(struct nvbios_init *init)
1656 struct nvkm_bios *bios = init->bios;
1657 u8 index = nvbios_rd08(bios, init->offset + 1);
1660 trace("SUB\t0x%02x\n", index);
1662 addr = init_script(bios, index);
1663 if (addr && init_exec(init)) {
1664 save = init->offset;
1665 init->offset = addr;
1666 if (nvbios_exec(init)) {
1667 error("error parsing sub-table\n");
1670 init->offset = save;
1677 * INIT_RAM_CONDITION - opcode 0x6d
1681 init_ram_condition(struct nvbios_init *init)
1683 struct nvkm_bios *bios = init->bios;
1684 u8 mask = nvbios_rd08(bios, init->offset + 1);
1685 u8 value = nvbios_rd08(bios, init->offset + 2);
1687 trace("RAM_CONDITION\t"
1688 "(R[0x100000] & 0x%02x) == 0x%02x\n", mask, value);
1691 if ((init_rd32(init, 0x100000) & mask) != value)
1692 init_exec_set(init, false);
1696 * INIT_NV_REG - opcode 0x6e
1700 init_nv_reg(struct nvbios_init *init)
1702 struct nvkm_bios *bios = init->bios;
1703 u32 reg = nvbios_rd32(bios, init->offset + 1);
1704 u32 mask = nvbios_rd32(bios, init->offset + 5);
1705 u32 data = nvbios_rd32(bios, init->offset + 9);
1707 trace("NV_REG\tR[0x%06x] &= 0x%08x |= 0x%08x\n", reg, mask, data);
1710 init_mask(init, reg, ~mask, data);
1714 * INIT_MACRO - opcode 0x6f
1718 init_macro(struct nvbios_init *init)
1720 struct nvkm_bios *bios = init->bios;
1721 u8 macro = nvbios_rd08(bios, init->offset + 1);
1724 trace("MACRO\t0x%02x\n", macro);
1726 table = init_macro_table(init);
1728 u32 addr = nvbios_rd32(bios, table + (macro * 8) + 0);
1729 u32 data = nvbios_rd32(bios, table + (macro * 8) + 4);
1730 trace("\t\tR[0x%06x] = 0x%08x\n", addr, data);
1731 init_wr32(init, addr, data);
1738 * INIT_RESUME - opcode 0x72
1742 init_resume(struct nvbios_init *init)
1746 init_exec_set(init, true);
1750 * INIT_STRAP_CONDITION - opcode 0x73
1754 init_strap_condition(struct nvbios_init *init)
1756 struct nvkm_bios *bios = init->bios;
1757 u32 mask = nvbios_rd32(bios, init->offset + 1);
1758 u32 value = nvbios_rd32(bios, init->offset + 5);
1760 trace("STRAP_CONDITION\t(R[0x101000] & 0x%08x) == 0x%08x\n", mask, value);
1763 if ((init_rd32(init, 0x101000) & mask) != value)
1764 init_exec_set(init, false);
1768 * INIT_TIME - opcode 0x74
1772 init_time(struct nvbios_init *init)
1774 struct nvkm_bios *bios = init->bios;
1775 u16 usec = nvbios_rd16(bios, init->offset + 1);
1777 trace("TIME\t0x%04x\n", usec);
1780 if (init_exec(init)) {
1784 mdelay((usec + 900) / 1000);
1789 * INIT_CONDITION - opcode 0x75
1793 init_condition(struct nvbios_init *init)
1795 struct nvkm_bios *bios = init->bios;
1796 u8 cond = nvbios_rd08(bios, init->offset + 1);
1798 trace("CONDITION\t0x%02x\n", cond);
1801 if (!init_condition_met(init, cond))
1802 init_exec_set(init, false);
1806 * INIT_IO_CONDITION - opcode 0x76
1810 init_io_condition(struct nvbios_init *init)
1812 struct nvkm_bios *bios = init->bios;
1813 u8 cond = nvbios_rd08(bios, init->offset + 1);
1815 trace("IO_CONDITION\t0x%02x\n", cond);
1818 if (!init_io_condition_met(init, cond))
1819 init_exec_set(init, false);
1823 * INIT_ZM_REG16 - opcode 0x77
1827 init_zm_reg16(struct nvbios_init *init)
1829 struct nvkm_bios *bios = init->bios;
1830 u32 addr = nvbios_rd32(bios, init->offset + 1);
1831 u16 data = nvbios_rd16(bios, init->offset + 5);
1833 trace("ZM_REG\tR[0x%06x] = 0x%04x\n", addr, data);
1836 init_wr32(init, addr, data);
1840 * INIT_INDEX_IO - opcode 0x78
1844 init_index_io(struct nvbios_init *init)
1846 struct nvkm_bios *bios = init->bios;
1847 u16 port = nvbios_rd16(bios, init->offset + 1);
1848 u8 index = nvbios_rd16(bios, init->offset + 3);
1849 u8 mask = nvbios_rd08(bios, init->offset + 4);
1850 u8 data = nvbios_rd08(bios, init->offset + 5);
1853 trace("INDEX_IO\tI[0x%04x][0x%02x] &= 0x%02x |= 0x%02x\n",
1854 port, index, mask, data);
1857 value = init_rdvgai(init, port, index) & mask;
1858 init_wrvgai(init, port, index, data | value);
1862 * INIT_PLL - opcode 0x79
1866 init_pll(struct nvbios_init *init)
1868 struct nvkm_bios *bios = init->bios;
1869 u32 reg = nvbios_rd32(bios, init->offset + 1);
1870 u32 freq = nvbios_rd16(bios, init->offset + 5) * 10;
1872 trace("PLL\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
1875 init_prog_pll(init, reg, freq);
1879 * INIT_ZM_REG - opcode 0x7a
1883 init_zm_reg(struct nvbios_init *init)
1885 struct nvkm_bios *bios = init->bios;
1886 u32 addr = nvbios_rd32(bios, init->offset + 1);
1887 u32 data = nvbios_rd32(bios, init->offset + 5);
1889 trace("ZM_REG\tR[0x%06x] = 0x%08x\n", addr, data);
1892 if (addr == 0x000200)
1895 init_wr32(init, addr, data);
1899 * INIT_RAM_RESTRICT_PLL - opcde 0x87
1903 init_ram_restrict_pll(struct nvbios_init *init)
1905 struct nvkm_bios *bios = init->bios;
1906 u8 type = nvbios_rd08(bios, init->offset + 1);
1907 u8 count = init_ram_restrict_group_count(init);
1908 u8 strap = init_ram_restrict(init);
1911 trace("RAM_RESTRICT_PLL\t0x%02x\n", type);
1914 for (cconf = 0; cconf < count; cconf++) {
1915 u32 freq = nvbios_rd32(bios, init->offset);
1917 if (cconf == strap) {
1918 trace("%dkHz *\n", freq);
1919 init_prog_pll(init, type, freq);
1921 trace("%dkHz\n", freq);
1929 * INIT_GPIO - opcode 0x8e
1933 init_gpio(struct nvbios_init *init)
1935 struct nvkm_gpio *gpio = nvkm_gpio(init->bios);
1940 if (init_exec(init) && gpio && gpio->reset)
1941 gpio->reset(gpio, DCB_GPIO_UNUSED);
1945 * INIT_RAM_RESTRICT_ZM_GROUP - opcode 0x8f
1949 init_ram_restrict_zm_reg_group(struct nvbios_init *init)
1951 struct nvkm_bios *bios = init->bios;
1952 u32 addr = nvbios_rd32(bios, init->offset + 1);
1953 u8 incr = nvbios_rd08(bios, init->offset + 5);
1954 u8 num = nvbios_rd08(bios, init->offset + 6);
1955 u8 count = init_ram_restrict_group_count(init);
1956 u8 index = init_ram_restrict(init);
1959 trace("RAM_RESTRICT_ZM_REG_GROUP\t"
1960 "R[0x%08x] 0x%02x 0x%02x\n", addr, incr, num);
1963 for (i = 0; i < num; i++) {
1964 trace("\tR[0x%06x] = {\n", addr);
1965 for (j = 0; j < count; j++) {
1966 u32 data = nvbios_rd32(bios, init->offset);
1969 trace("\t\t0x%08x *\n", data);
1970 init_wr32(init, addr, data);
1972 trace("\t\t0x%08x\n", data);
1983 * INIT_COPY_ZM_REG - opcode 0x90
1987 init_copy_zm_reg(struct nvbios_init *init)
1989 struct nvkm_bios *bios = init->bios;
1990 u32 sreg = nvbios_rd32(bios, init->offset + 1);
1991 u32 dreg = nvbios_rd32(bios, init->offset + 5);
1993 trace("COPY_ZM_REG\tR[0x%06x] = R[0x%06x]\n", dreg, sreg);
1996 init_wr32(init, dreg, init_rd32(init, sreg));
2000 * INIT_ZM_REG_GROUP - opcode 0x91
2004 init_zm_reg_group(struct nvbios_init *init)
2006 struct nvkm_bios *bios = init->bios;
2007 u32 addr = nvbios_rd32(bios, init->offset + 1);
2008 u8 count = nvbios_rd08(bios, init->offset + 5);
2010 trace("ZM_REG_GROUP\tR[0x%06x] =\n", addr);
2014 u32 data = nvbios_rd32(bios, init->offset);
2015 trace("\t0x%08x\n", data);
2016 init_wr32(init, addr, data);
2022 * INIT_XLAT - opcode 0x96
2026 init_xlat(struct nvbios_init *init)
2028 struct nvkm_bios *bios = init->bios;
2029 u32 saddr = nvbios_rd32(bios, init->offset + 1);
2030 u8 sshift = nvbios_rd08(bios, init->offset + 5);
2031 u8 smask = nvbios_rd08(bios, init->offset + 6);
2032 u8 index = nvbios_rd08(bios, init->offset + 7);
2033 u32 daddr = nvbios_rd32(bios, init->offset + 8);
2034 u32 dmask = nvbios_rd32(bios, init->offset + 12);
2035 u8 shift = nvbios_rd08(bios, init->offset + 16);
2038 trace("INIT_XLAT\tR[0x%06x] &= 0x%08x |= "
2039 "(X%02x((R[0x%06x] %s 0x%02x) & 0x%02x) << 0x%02x)\n",
2040 daddr, dmask, index, saddr, (sshift & 0x80) ? "<<" : ">>",
2041 (sshift & 0x80) ? (0x100 - sshift) : sshift, smask, shift);
2044 data = init_shift(init_rd32(init, saddr), sshift) & smask;
2045 data = init_xlat_(init, index, data) << shift;
2046 init_mask(init, daddr, ~dmask, data);
2050 * INIT_ZM_MASK_ADD - opcode 0x97
2054 init_zm_mask_add(struct nvbios_init *init)
2056 struct nvkm_bios *bios = init->bios;
2057 u32 addr = nvbios_rd32(bios, init->offset + 1);
2058 u32 mask = nvbios_rd32(bios, init->offset + 5);
2059 u32 add = nvbios_rd32(bios, init->offset + 9);
2062 trace("ZM_MASK_ADD\tR[0x%06x] &= 0x%08x += 0x%08x\n", addr, mask, add);
2065 data = init_rd32(init, addr);
2066 data = (data & mask) | ((data + add) & ~mask);
2067 init_wr32(init, addr, data);
2071 * INIT_AUXCH - opcode 0x98
2075 init_auxch(struct nvbios_init *init)
2077 struct nvkm_bios *bios = init->bios;
2078 u32 addr = nvbios_rd32(bios, init->offset + 1);
2079 u8 count = nvbios_rd08(bios, init->offset + 5);
2081 trace("AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
2085 u8 mask = nvbios_rd08(bios, init->offset + 0);
2086 u8 data = nvbios_rd08(bios, init->offset + 1);
2087 trace("\tAUX[0x%08x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
2088 mask = init_rdauxr(init, addr) & mask;
2089 init_wrauxr(init, addr, mask | data);
2095 * INIT_AUXCH - opcode 0x99
2099 init_zm_auxch(struct nvbios_init *init)
2101 struct nvkm_bios *bios = init->bios;
2102 u32 addr = nvbios_rd32(bios, init->offset + 1);
2103 u8 count = nvbios_rd08(bios, init->offset + 5);
2105 trace("ZM_AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
2109 u8 data = nvbios_rd08(bios, init->offset + 0);
2110 trace("\tAUX[0x%08x] = 0x%02x\n", addr, data);
2111 init_wrauxr(init, addr, data);
2117 * INIT_I2C_LONG_IF - opcode 0x9a
2121 init_i2c_long_if(struct nvbios_init *init)
2123 struct nvkm_bios *bios = init->bios;
2124 u8 index = nvbios_rd08(bios, init->offset + 1);
2125 u8 addr = nvbios_rd08(bios, init->offset + 2) >> 1;
2126 u8 reglo = nvbios_rd08(bios, init->offset + 3);
2127 u8 reghi = nvbios_rd08(bios, init->offset + 4);
2128 u8 mask = nvbios_rd08(bios, init->offset + 5);
2129 u8 data = nvbios_rd08(bios, init->offset + 6);
2130 struct nvkm_i2c_port *port;
2132 trace("I2C_LONG_IF\t"
2133 "I2C[0x%02x][0x%02x][0x%02x%02x] & 0x%02x == 0x%02x\n",
2134 index, addr, reglo, reghi, mask, data);
2137 port = init_i2c(init, index);
2139 u8 i[2] = { reghi, reglo };
2141 struct i2c_msg msg[] = {
2142 { .addr = addr, .flags = 0, .len = 2, .buf = i },
2143 { .addr = addr, .flags = I2C_M_RD, .len = 1, .buf = o }
2147 ret = i2c_transfer(&port->adapter, msg, 2);
2148 if (ret == 2 && ((o[0] & mask) == data))
2152 init_exec_set(init, false);
2156 * INIT_GPIO_NE - opcode 0xa9
2160 init_gpio_ne(struct nvbios_init *init)
2162 struct nvkm_bios *bios = init->bios;
2163 struct nvkm_gpio *gpio = nvkm_gpio(bios);
2164 struct dcb_gpio_func func;
2165 u8 count = nvbios_rd08(bios, init->offset + 1);
2166 u8 idx = 0, ver, len;
2172 for (i = init->offset; i < init->offset + count; i++)
2173 cont("0x%02x ", nvbios_rd08(bios, i));
2176 while ((data = dcb_gpio_parse(bios, 0, idx++, &ver, &len, &func))) {
2177 if (func.func != DCB_GPIO_UNUSED) {
2178 for (i = init->offset; i < init->offset + count; i++) {
2179 if (func.func == nvbios_rd08(bios, i))
2183 trace("\tFUNC[0x%02x]", func.func);
2184 if (i == (init->offset + count)) {
2186 if (init_exec(init) && gpio && gpio->reset)
2187 gpio->reset(gpio, func.func);
2193 init->offset += count;
2196 static struct nvbios_init_opcode {
2197 void (*exec)(struct nvbios_init *);
2199 [0x32] = { init_io_restrict_prog },
2200 [0x33] = { init_repeat },
2201 [0x34] = { init_io_restrict_pll },
2202 [0x36] = { init_end_repeat },
2203 [0x37] = { init_copy },
2204 [0x38] = { init_not },
2205 [0x39] = { init_io_flag_condition },
2206 [0x3a] = { init_dp_condition },
2207 [0x3b] = { init_io_mask_or },
2208 [0x3c] = { init_io_or },
2209 [0x47] = { init_andn_reg },
2210 [0x48] = { init_or_reg },
2211 [0x49] = { init_idx_addr_latched },
2212 [0x4a] = { init_io_restrict_pll2 },
2213 [0x4b] = { init_pll2 },
2214 [0x4c] = { init_i2c_byte },
2215 [0x4d] = { init_zm_i2c_byte },
2216 [0x4e] = { init_zm_i2c },
2217 [0x4f] = { init_tmds },
2218 [0x50] = { init_zm_tmds_group },
2219 [0x51] = { init_cr_idx_adr_latch },
2220 [0x52] = { init_cr },
2221 [0x53] = { init_zm_cr },
2222 [0x54] = { init_zm_cr_group },
2223 [0x56] = { init_condition_time },
2224 [0x57] = { init_ltime },
2225 [0x58] = { init_zm_reg_sequence },
2226 [0x59] = { init_pll_indirect },
2227 [0x5a] = { init_zm_reg_indirect },
2228 [0x5b] = { init_sub_direct },
2229 [0x5c] = { init_jump },
2230 [0x5e] = { init_i2c_if },
2231 [0x5f] = { init_copy_nv_reg },
2232 [0x62] = { init_zm_index_io },
2233 [0x63] = { init_compute_mem },
2234 [0x65] = { init_reset },
2235 [0x66] = { init_configure_mem },
2236 [0x67] = { init_configure_clk },
2237 [0x68] = { init_configure_preinit },
2238 [0x69] = { init_io },
2239 [0x6b] = { init_sub },
2240 [0x6d] = { init_ram_condition },
2241 [0x6e] = { init_nv_reg },
2242 [0x6f] = { init_macro },
2243 [0x71] = { init_done },
2244 [0x72] = { init_resume },
2245 [0x73] = { init_strap_condition },
2246 [0x74] = { init_time },
2247 [0x75] = { init_condition },
2248 [0x76] = { init_io_condition },
2249 [0x77] = { init_zm_reg16 },
2250 [0x78] = { init_index_io },
2251 [0x79] = { init_pll },
2252 [0x7a] = { init_zm_reg },
2253 [0x87] = { init_ram_restrict_pll },
2254 [0x8c] = { init_reserved },
2255 [0x8d] = { init_reserved },
2256 [0x8e] = { init_gpio },
2257 [0x8f] = { init_ram_restrict_zm_reg_group },
2258 [0x90] = { init_copy_zm_reg },
2259 [0x91] = { init_zm_reg_group },
2260 [0x92] = { init_reserved },
2261 [0x96] = { init_xlat },
2262 [0x97] = { init_zm_mask_add },
2263 [0x98] = { init_auxch },
2264 [0x99] = { init_zm_auxch },
2265 [0x9a] = { init_i2c_long_if },
2266 [0xa9] = { init_gpio_ne },
2267 [0xaa] = { init_reserved },
2270 #define init_opcode_nr (sizeof(init_opcode) / sizeof(init_opcode[0]))
2273 nvbios_exec(struct nvbios_init *init)
2276 while (init->offset) {
2277 u8 opcode = nvbios_rd08(init->bios, init->offset);
2278 if (opcode >= init_opcode_nr || !init_opcode[opcode].exec) {
2279 error("unknown opcode 0x%02x\n", opcode);
2283 init_opcode[opcode].exec(init);
2290 nvbios_init(struct nvkm_subdev *subdev, bool execute)
2292 struct nvkm_bios *bios = nvkm_bios(subdev);
2298 nvkm_debug(subdev, "running init tables\n");
2299 while (!ret && (data = (init_script(bios, ++i)))) {
2300 struct nvbios_init init = {
2306 .execute = execute ? 1 : 0,
2309 ret = nvbios_exec(&init);
2312 /* the vbios parser will run this right after the normal init
2313 * tables, whereas the binary driver appears to run it later.
2315 if (!ret && (data = init_unknown_script(bios))) {
2316 struct nvbios_init init = {
2322 .execute = execute ? 1 : 0,
2325 ret = nvbios_exec(&init);