2 * Copyright 2013 Red Hat Inc.
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
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15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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20 * OTHER DEALINGS IN THE SOFTWARE.
27 /*******************************************************************************
28 * Perfmon object classes
29 ******************************************************************************/
31 /*******************************************************************************
33 ******************************************************************************/
35 /*******************************************************************************
36 * PPM engine/subdev functions
37 ******************************************************************************/
39 static const struct nouveau_specdom
44 static const struct nouveau_specdom
49 static const struct nouveau_specdom
55 nvc0_perfctr_init(struct nouveau_pm *ppm, struct nouveau_perfdom *dom,
56 struct nouveau_perfctr *ctr)
58 struct nvc0_pm_priv *priv = (void *)ppm;
59 struct nvc0_pm_cntr *cntr = (void *)ctr;
60 u32 log = ctr->logic_op;
64 for (i = 0; i < 4 && ctr->signal[i]; i++)
65 src |= (ctr->signal[i] - dom->signal) << (i * 8);
67 nv_wr32(priv, dom->addr + 0x09c, 0x00040002);
68 nv_wr32(priv, dom->addr + 0x100, 0x00000000);
69 nv_wr32(priv, dom->addr + 0x040 + (cntr->base.slot * 0x08), src);
70 nv_wr32(priv, dom->addr + 0x044 + (cntr->base.slot * 0x08), log);
74 nvc0_perfctr_read(struct nouveau_pm *ppm, struct nouveau_perfdom *dom,
75 struct nouveau_perfctr *ctr)
77 struct nvc0_pm_priv *priv = (void *)ppm;
78 struct nvc0_pm_cntr *cntr = (void *)ctr;
80 switch (cntr->base.slot) {
81 case 0: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x08c); break;
82 case 1: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x088); break;
83 case 2: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x080); break;
84 case 3: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x090); break;
86 cntr->base.clk = nv_rd32(priv, dom->addr + 0x070);
90 nvc0_perfctr_next(struct nouveau_pm *ppm, struct nouveau_perfdom *dom)
92 struct nvc0_pm_priv *priv = (void *)ppm;
93 nv_wr32(priv, dom->addr + 0x06c, dom->signal_nr - 0x40 + 0x27);
94 nv_wr32(priv, dom->addr + 0x0ec, 0x00000011);
97 const struct nouveau_funcdom
99 .init = nvc0_perfctr_init,
100 .read = nvc0_perfctr_read,
101 .next = nvc0_perfctr_next,
105 nvc0_pm_fini(struct nouveau_object *object, bool suspend)
107 struct nvc0_pm_priv *priv = (void *)object;
108 nv_mask(priv, 0x000200, 0x10000000, 0x00000000);
109 nv_mask(priv, 0x000200, 0x10000000, 0x10000000);
110 return nouveau_pm_fini(&priv->base, suspend);
114 nvc0_pm_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
115 struct nouveau_oclass *oclass, void *data, u32 size,
116 struct nouveau_object **pobject)
118 struct nvc0_pm_priv *priv;
122 ret = nouveau_pm_create(parent, engine, oclass, &priv);
123 *pobject = nv_object(priv);
127 ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0,
133 ret = nouveau_perfdom_new(&priv->base, "hub", 0, 0x1b0000, 0, 0x200,
139 mask = (1 << nv_rd32(priv, 0x022430)) - 1;
140 mask &= ~nv_rd32(priv, 0x022504);
141 mask &= ~nv_rd32(priv, 0x022584);
143 ret = nouveau_perfdom_new(&priv->base, "gpc", mask, 0x180000,
144 0x1000, 0x200, nvc0_pm_gpc);
149 mask = (1 << nv_rd32(priv, 0x022438)) - 1;
150 mask &= ~nv_rd32(priv, 0x022548);
151 mask &= ~nv_rd32(priv, 0x0225c8);
153 ret = nouveau_perfdom_new(&priv->base, "part", mask, 0x1a0000,
154 0x1000, 0x200, nvc0_pm_part);
158 nv_engine(priv)->cclass = &nouveau_pm_cclass;
159 nv_engine(priv)->sclass = nouveau_pm_sclass;
164 struct nouveau_oclass
166 .handle = NV_ENGINE(PM, 0xc0),
167 .ofuncs = &(struct nouveau_ofuncs) {
168 .ctor = nvc0_pm_ctor,
169 .dtor = _nouveau_pm_dtor,
170 .init = _nouveau_pm_init,
171 .fini = nvc0_pm_fini,