drivers/gpu/drm/nouveau/nvd0_display.c

   1 /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <linux/dma-mapping.h>
  26
  27 #include "drmP.h"
  28 #include "drm_crtc_helper.h"
  29
  30 #include "nouveau_drv.h"
  31 #include "nouveau_connector.h"
  32 #include "nouveau_encoder.h"
  33 #include "nouveau_crtc.h"
  34 #include "nouveau_dma.h"
  35 #include "nouveau_fb.h"
  36 #include "nv50_display.h"
  37
  38 #define EVO_DMA_NR 9
  39
  40 #define EVO_MASTER  (0x00)
  41 #define EVO_FLIP(c) (0x01 + (c))
  42 #define EVO_OVLY(c) (0x05 + (c))
  43 #define EVO_OIMM(c) (0x09 + (c))
  44 #define EVO_CURS(c) (0x0d + (c))
  45
  46 /* offsets in shared sync bo of various structures */
  47 #define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
  48 #define EVO_MAST_NTFY     EVO_SYNC(  0, 0x00)
  49 #define EVO_FLIP_SEM0(c)  EVO_SYNC((c), 0x00)
  50 #define EVO_FLIP_SEM1(c)  EVO_SYNC((c), 0x10)
  51
  52 struct evo {
  53         int idx;
  54         dma_addr_t handle;
  55         u32 *ptr;
  56         struct {
  57                 u32 offset;
  58                 u16 value;
  59         } sem;
  60 };
  61
  62 struct nvd0_display {
  63         struct nouveau_gpuobj *mem;
  64         struct nouveau_bo *sync;
  65         struct evo evo[9];
  66
  67         struct tasklet_struct tasklet;
  68         u32 modeset;
  69 };
  70
  71 static struct nvd0_display *
  72 nvd0_display(struct drm_device *dev)
  73 {
  74         struct drm_nouveau_private *dev_priv = dev->dev_private;
  75         return dev_priv->engine.display.priv;
  76 }
  77
  78 static struct drm_crtc *
  79 nvd0_display_crtc_get(struct drm_encoder *encoder)
  80 {
  81         return nouveau_encoder(encoder)->crtc;
  82 }
  83
  84 /******************************************************************************
  85  * EVO channel helpers
  86  *****************************************************************************/
  87 static inline int
  88 evo_icmd(struct drm_device *dev, int id, u32 mthd, u32 data)
  89 {
  90         int ret = 0;
  91         nv_mask(dev, 0x610700 + (id * 0x10), 0x00000001, 0x00000001);
  92         nv_wr32(dev, 0x610704 + (id * 0x10), data);
  93         nv_mask(dev, 0x610704 + (id * 0x10), 0x80000ffc, 0x80000000 | mthd);
  94         if (!nv_wait(dev, 0x610704 + (id * 0x10), 0x80000000, 0x00000000))
  95                 ret = -EBUSY;
  96         nv_mask(dev, 0x610700 + (id * 0x10), 0x00000001, 0x00000000);
  97         return ret;
  98 }
  99
 100 static u32 *
 101 evo_wait(struct drm_device *dev, int id, int nr)
 102 {
 103         struct nvd0_display *disp = nvd0_display(dev);
 104         u32 put = nv_rd32(dev, 0x640000 + (id * 0x1000)) / 4;
 105
 106         if (put + nr >= (PAGE_SIZE / 4)) {
 107                 disp->evo[id].ptr[put] = 0x20000000;
 108
 109                 nv_wr32(dev, 0x640000 + (id * 0x1000), 0x00000000);
 110                 if (!nv_wait(dev, 0x640004 + (id * 0x1000), ~0, 0x00000000)) {
 111                         NV_ERROR(dev, "evo %d dma stalled\n", id);
 112                         return NULL;
 113                 }
 114
 115                 put = 0;
 116         }
 117
 118         if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO)
 119                 NV_INFO(dev, "Evo%d: %p START\n", id, disp->evo[id].ptr + put);
 120
 121         return disp->evo[id].ptr + put;
 122 }
 123
 124 static void
 125 evo_kick(u32 *push, struct drm_device *dev, int id)
 126 {
 127         struct nvd0_display *disp = nvd0_display(dev);
 128
 129         if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO) {
 130                 u32 curp = nv_rd32(dev, 0x640000 + (id * 0x1000)) >> 2;
 131                 u32 *cur = disp->evo[id].ptr + curp;
 132
 133                 while (cur < push)
 134                         NV_INFO(dev, "Evo%d: 0x%08x\n", id, *cur++);
 135                 NV_INFO(dev, "Evo%d: %p KICK!\n", id, push);
 136         }
 137
 138         nv_wr32(dev, 0x640000 + (id * 0x1000), (push - disp->evo[id].ptr) << 2);
 139 }
 140
 141 #define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m))
 142 #define evo_data(p,d)   *((p)++) = (d)
 143
 144 static int
 145 evo_init_dma(struct drm_device *dev, int ch)
 146 {
 147         struct nvd0_display *disp = nvd0_display(dev);
 148         u32 flags;
 149
 150         flags = 0x00000000;
 151         if (ch == EVO_MASTER)
 152                 flags |= 0x01000000;
 153
 154         nv_wr32(dev, 0x610494 + (ch * 0x0010), (disp->evo[ch].handle >> 8) | 3);
 155         nv_wr32(dev, 0x610498 + (ch * 0x0010), 0x00010000);
 156         nv_wr32(dev, 0x61049c + (ch * 0x0010), 0x00000001);
 157         nv_mask(dev, 0x610490 + (ch * 0x0010), 0x00000010, 0x00000010);
 158         nv_wr32(dev, 0x640000 + (ch * 0x1000), 0x00000000);
 159         nv_wr32(dev, 0x610490 + (ch * 0x0010), 0x00000013 | flags);
 160         if (!nv_wait(dev, 0x610490 + (ch * 0x0010), 0x80000000, 0x00000000)) {
 161                 NV_ERROR(dev, "PDISP: ch%d 0x%08x\n", ch,
 162                               nv_rd32(dev, 0x610490 + (ch * 0x0010)));
 163                 return -EBUSY;
 164         }
 165
 166         nv_mask(dev, 0x610090, (1 << ch), (1 << ch));
 167         nv_mask(dev, 0x6100a0, (1 << ch), (1 << ch));
 168         return 0;
 169 }
 170
 171 static void
 172 evo_fini_dma(struct drm_device *dev, int ch)
 173 {
 174         if (!(nv_rd32(dev, 0x610490 + (ch * 0x0010)) & 0x00000010))
 175                 return;
 176
 177         nv_mask(dev, 0x610490 + (ch * 0x0010), 0x00000010, 0x00000000);
 178         nv_mask(dev, 0x610490 + (ch * 0x0010), 0x00000003, 0x00000000);
 179         nv_wait(dev, 0x610490 + (ch * 0x0010), 0x80000000, 0x00000000);
 180         nv_mask(dev, 0x610090, (1 << ch), 0x00000000);
 181         nv_mask(dev, 0x6100a0, (1 << ch), 0x00000000);
 182 }
 183
 184 static inline void
 185 evo_piow(struct drm_device *dev, int ch, u16 mthd, u32 data)
 186 {
 187         nv_wr32(dev, 0x640000 + (ch * 0x1000) + mthd, data);
 188 }
 189
 190 static int
 191 evo_init_pio(struct drm_device *dev, int ch)
 192 {
 193         nv_wr32(dev, 0x610490 + (ch * 0x0010), 0x00000001);
 194         if (!nv_wait(dev, 0x610490 + (ch * 0x0010), 0x00010000, 0x00010000)) {
 195                 NV_ERROR(dev, "PDISP: ch%d 0x%08x\n", ch,
 196                               nv_rd32(dev, 0x610490 + (ch * 0x0010)));
 197                 return -EBUSY;
 198         }
 199
 200         nv_mask(dev, 0x610090, (1 << ch), (1 << ch));
 201         nv_mask(dev, 0x6100a0, (1 << ch), (1 << ch));
 202         return 0;
 203 }
 204
 205 static void
 206 evo_fini_pio(struct drm_device *dev, int ch)
 207 {
 208         if (!(nv_rd32(dev, 0x610490 + (ch * 0x0010)) & 0x00000001))
 209                 return;
 210
 211         nv_mask(dev, 0x610490 + (ch * 0x0010), 0x00000010, 0x00000010);
 212         nv_mask(dev, 0x610490 + (ch * 0x0010), 0x00000001, 0x00000000);
 213         nv_wait(dev, 0x610490 + (ch * 0x0010), 0x00010000, 0x00000000);
 214         nv_mask(dev, 0x610090, (1 << ch), 0x00000000);
 215         nv_mask(dev, 0x6100a0, (1 << ch), 0x00000000);
 216 }
 217
 218 static bool
 219 evo_sync_wait(void *data)
 220 {
 221         return nouveau_bo_rd32(data, EVO_MAST_NTFY) != 0x00000000;
 222 }
 223
 224 static int
 225 evo_sync(struct drm_device *dev, int ch)
 226 {
 227         struct nvd0_display *disp = nvd0_display(dev);
 228         u32 *push = evo_wait(dev, ch, 8);
 229         if (push) {
 230                 nouveau_bo_wr32(disp->sync, EVO_MAST_NTFY, 0x00000000);
 231                 evo_mthd(push, 0x0084, 1);
 232                 evo_data(push, 0x80000000 | EVO_MAST_NTFY);
 233                 evo_mthd(push, 0x0080, 2);
 234                 evo_data(push, 0x00000000);
 235                 evo_data(push, 0x00000000);
 236                 evo_kick(push, dev, ch);
 237                 if (nv_wait_cb(dev, evo_sync_wait, disp->sync))
 238                         return 0;
 239         }
 240
 241         return -EBUSY;
 242 }
 243
 244 /******************************************************************************
 245  * Page flipping channel
 246  *****************************************************************************/
 247 struct nouveau_bo *
 248 nvd0_display_crtc_sema(struct drm_device *dev, int crtc)
 249 {
 250         return nvd0_display(dev)->sync;
 251 }
 252
 253 void
 254 nvd0_display_flip_stop(struct drm_crtc *crtc)
 255 {
 256         struct nvd0_display *disp = nvd0_display(crtc->dev);
 257         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 258         struct evo *evo = &disp->evo[EVO_FLIP(nv_crtc->index)];
 259         u32 *push;
 260
 261         push = evo_wait(crtc->dev, evo->idx, 8);
 262         if (push) {
 263                 evo_mthd(push, 0x0084, 1);
 264                 evo_data(push, 0x00000000);
 265                 evo_mthd(push, 0x0094, 1);
 266                 evo_data(push, 0x00000000);
 267                 evo_mthd(push, 0x00c0, 1);
 268                 evo_data(push, 0x00000000);
 269                 evo_mthd(push, 0x0080, 1);
 270                 evo_data(push, 0x00000000);
 271                 evo_kick(push, crtc->dev, evo->idx);
 272         }
 273 }
 274
 275 int
 276 nvd0_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 277                        struct nouveau_channel *chan, u32 swap_interval)
 278 {
 279         struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
 280         struct nvd0_display *disp = nvd0_display(crtc->dev);
 281         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 282         struct evo *evo = &disp->evo[EVO_FLIP(nv_crtc->index)];
 283         u64 offset;
 284         u32 *push;
 285         int ret;
 286
 287         evo_sync(crtc->dev, EVO_MASTER);
 288
 289         swap_interval <<= 4;
 290         if (swap_interval == 0)
 291                 swap_interval |= 0x100;
 292
 293         push = evo_wait(crtc->dev, evo->idx, 128);
 294         if (unlikely(push == NULL))
 295                 return -EBUSY;
 296
 297         /* synchronise with the rendering channel, if necessary */
 298         if (likely(chan)) {
 299                 ret = RING_SPACE(chan, 10);
 300                 if (ret)
 301                         return ret;
 302
 303                 offset  = chan->dispc_vma[nv_crtc->index].offset;
 304                 offset += evo->sem.offset;
 305
 306                 BEGIN_NVC0(chan, 2, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 307                 OUT_RING  (chan, upper_32_bits(offset));
 308                 OUT_RING  (chan, lower_32_bits(offset));
 309                 OUT_RING  (chan, 0xf00d0000 | evo->sem.value);
 310                 OUT_RING  (chan, 0x1002);
 311                 BEGIN_NVC0(chan, 2, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 312                 OUT_RING  (chan, upper_32_bits(offset));
 313                 OUT_RING  (chan, lower_32_bits(offset ^ 0x10));
 314                 OUT_RING  (chan, 0x74b1e000);
 315                 OUT_RING  (chan, 0x1001);
 316                 FIRE_RING (chan);
 317         } else {
 318                 nouveau_bo_wr32(disp->sync, evo->sem.offset / 4,
 319                                 0xf00d0000 | evo->sem.value);
 320                 evo_sync(crtc->dev, EVO_MASTER);
 321         }
 322
 323         /* queue the flip */
 324         evo_mthd(push, 0x0100, 1);
 325         evo_data(push, 0xfffe0000);
 326         evo_mthd(push, 0x0084, 1);
 327         evo_data(push, swap_interval);
 328         if (!(swap_interval & 0x00000100)) {
 329                 evo_mthd(push, 0x00e0, 1);
 330                 evo_data(push, 0x40000000);
 331         }
 332         evo_mthd(push, 0x0088, 4);
 333         evo_data(push, evo->sem.offset);
 334         evo_data(push, 0xf00d0000 | evo->sem.value);
 335         evo_data(push, 0x74b1e000);
 336         evo_data(push, NvEvoSync);
 337         evo_mthd(push, 0x00a0, 2);
 338         evo_data(push, 0x00000000);
 339         evo_data(push, 0x00000000);
 340         evo_mthd(push, 0x00c0, 1);
 341         evo_data(push, nv_fb->r_dma);
 342         evo_mthd(push, 0x0110, 2);
 343         evo_data(push, 0x00000000);
 344         evo_data(push, 0x00000000);
 345         evo_mthd(push, 0x0400, 5);
 346         evo_data(push, nv_fb->nvbo->bo.offset >> 8);
 347         evo_data(push, 0);
 348         evo_data(push, (fb->height << 16) | fb->width);
 349         evo_data(push, nv_fb->r_pitch);
 350         evo_data(push, nv_fb->r_format);
 351         evo_mthd(push, 0x0080, 1);
 352         evo_data(push, 0x00000000);
 353         evo_kick(push, crtc->dev, evo->idx);
 354
 355         evo->sem.offset ^= 0x10;
 356         evo->sem.value++;
 357         return 0;
 358 }
 359
 360 /******************************************************************************
 361  * CRTC
 362  *****************************************************************************/
 363 static int
 364 nvd0_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update)
 365 {
 366         struct drm_nouveau_private *dev_priv = nv_crtc->base.dev->dev_private;
 367         struct drm_device *dev = nv_crtc->base.dev;
 368         struct nouveau_connector *nv_connector;
 369         struct drm_connector *connector;
 370         u32 *push, mode = 0x00;
 371         u32 mthd;
 372
 373         nv_connector = nouveau_crtc_connector_get(nv_crtc);
 374         connector = &nv_connector->base;
 375         if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) {
 376                 if (nv_crtc->base.fb->depth > connector->display_info.bpc * 3)
 377                         mode = DITHERING_MODE_DYNAMIC2X2;
 378         } else {
 379                 mode = nv_connector->dithering_mode;
 380         }
 381
 382         if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) {
 383                 if (connector->display_info.bpc >= 8)
 384                         mode |= DITHERING_DEPTH_8BPC;
 385         } else {
 386                 mode |= nv_connector->dithering_depth;
 387         }
 388
 389         if (dev_priv->card_type < NV_E0)
 390                 mthd = 0x0490 + (nv_crtc->index * 0x0300);
 391         else
 392                 mthd = 0x04a0 + (nv_crtc->index * 0x0300);
 393
 394         push = evo_wait(dev, EVO_MASTER, 4);
 395         if (push) {
 396                 evo_mthd(push, mthd, 1);
 397                 evo_data(push, mode);
 398                 if (update) {
 399                         evo_mthd(push, 0x0080, 1);
 400                         evo_data(push, 0x00000000);
 401                 }
 402                 evo_kick(push, dev, EVO_MASTER);
 403         }
 404
 405         return 0;
 406 }
 407
 408 static int
 409 nvd0_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update)
 410 {
 411         struct drm_display_mode *omode, *umode = &nv_crtc->base.mode;
 412         struct drm_device *dev = nv_crtc->base.dev;
 413         struct drm_crtc *crtc = &nv_crtc->base;
 414         struct nouveau_connector *nv_connector;
 415         int mode = DRM_MODE_SCALE_NONE;
 416         u32 oX, oY, *push;
 417
 418         /* start off at the resolution we programmed the crtc for, this
 419          * effectively handles NONE/FULL scaling
 420          */
 421         nv_connector = nouveau_crtc_connector_get(nv_crtc);
 422         if (nv_connector && nv_connector->native_mode)
 423                 mode = nv_connector->scaling_mode;
 424
 425         if (mode != DRM_MODE_SCALE_NONE)
 426                 omode = nv_connector->native_mode;
 427         else
 428                 omode = umode;
 429
 430         oX = omode->hdisplay;
 431         oY = omode->vdisplay;
 432         if (omode->flags & DRM_MODE_FLAG_DBLSCAN)
 433                 oY *= 2;
 434
 435         /* add overscan compensation if necessary, will keep the aspect
 436          * ratio the same as the backend mode unless overridden by the
 437          * user setting both hborder and vborder properties.
 438          */
 439         if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON ||
 440                              (nv_connector->underscan == UNDERSCAN_AUTO &&
 441                               nv_connector->edid &&
 442                               drm_detect_hdmi_monitor(nv_connector->edid)))) {
 443                 u32 bX = nv_connector->underscan_hborder;
 444                 u32 bY = nv_connector->underscan_vborder;
 445                 u32 aspect = (oY << 19) / oX;
 446
 447                 if (bX) {
 448                         oX -= (bX * 2);
 449                         if (bY) oY -= (bY * 2);
 450                         else    oY  = ((oX * aspect) + (aspect / 2)) >> 19;
 451                 } else {
 452                         oX -= (oX >> 4) + 32;
 453                         if (bY) oY -= (bY * 2);
 454                         else    oY  = ((oX * aspect) + (aspect / 2)) >> 19;
 455                 }
 456         }
 457
 458         /* handle CENTER/ASPECT scaling, taking into account the areas
 459          * removed already for overscan compensation
 460          */
 461         switch (mode) {
 462         case DRM_MODE_SCALE_CENTER:
 463                 oX = min((u32)umode->hdisplay, oX);
 464                 oY = min((u32)umode->vdisplay, oY);
 465                 /* fall-through */
 466         case DRM_MODE_SCALE_ASPECT:
 467                 if (oY < oX) {
 468                         u32 aspect = (umode->hdisplay << 19) / umode->vdisplay;
 469                         oX = ((oY * aspect) + (aspect / 2)) >> 19;
 470                 } else {
 471                         u32 aspect = (umode->vdisplay << 19) / umode->hdisplay;
 472                         oY = ((oX * aspect) + (aspect / 2)) >> 19;
 473                 }
 474                 break;
 475         default:
 476                 break;
 477         }
 478
 479         push = evo_wait(dev, EVO_MASTER, 8);
 480         if (push) {
 481                 evo_mthd(push, 0x04c0 + (nv_crtc->index * 0x300), 3);
 482                 evo_data(push, (oY << 16) | oX);
 483                 evo_data(push, (oY << 16) | oX);
 484                 evo_data(push, (oY << 16) | oX);
 485                 evo_mthd(push, 0x0494 + (nv_crtc->index * 0x300), 1);
 486                 evo_data(push, 0x00000000);
 487                 evo_mthd(push, 0x04b8 + (nv_crtc->index * 0x300), 1);
 488                 evo_data(push, (umode->vdisplay << 16) | umode->hdisplay);
 489                 evo_kick(push, dev, EVO_MASTER);
 490                 if (update) {
 491                         nvd0_display_flip_stop(crtc);
 492                         nvd0_display_flip_next(crtc, crtc->fb, NULL, 1);
 493                 }
 494         }
 495
 496         return 0;
 497 }
 498
 499 static int
 500 nvd0_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb,
 501                     int x, int y, bool update)
 502 {
 503         struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb);
 504         u32 *push;
 505
 506         push = evo_wait(fb->dev, EVO_MASTER, 16);
 507         if (push) {
 508                 evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1);
 509                 evo_data(push, nvfb->nvbo->bo.offset >> 8);
 510                 evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4);
 511                 evo_data(push, (fb->height << 16) | fb->width);
 512                 evo_data(push, nvfb->r_pitch);
 513                 evo_data(push, nvfb->r_format);
 514                 evo_data(push, nvfb->r_dma);
 515                 evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1);
 516                 evo_data(push, (y << 16) | x);
 517                 if (update) {
 518                         evo_mthd(push, 0x0080, 1);
 519                         evo_data(push, 0x00000000);
 520                 }
 521                 evo_kick(push, fb->dev, EVO_MASTER);
 522         }
 523
 524         nv_crtc->fb.tile_flags = nvfb->r_dma;
 525         return 0;
 526 }
 527
 528 static void
 529 nvd0_crtc_cursor_show(struct nouveau_crtc *nv_crtc, bool show, bool update)
 530 {
 531         struct drm_device *dev = nv_crtc->base.dev;
 532         u32 *push = evo_wait(dev, EVO_MASTER, 16);
 533         if (push) {
 534                 if (show) {
 535                         evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2);
 536                         evo_data(push, 0x85000000);
 537                         evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
 538                         evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
 539                         evo_data(push, NvEvoVRAM);
 540                 } else {
 541                         evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1);
 542                         evo_data(push, 0x05000000);
 543                         evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
 544                         evo_data(push, 0x00000000);
 545                 }
 546
 547                 if (update) {
 548                         evo_mthd(push, 0x0080, 1);
 549                         evo_data(push, 0x00000000);
 550                 }
 551
 552                 evo_kick(push, dev, EVO_MASTER);
 553         }
 554 }
 555
 556 static void
 557 nvd0_crtc_dpms(struct drm_crtc *crtc, int mode)
 558 {
 559 }
 560
 561 static void
 562 nvd0_crtc_prepare(struct drm_crtc *crtc)
 563 {
 564         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 565         u32 *push;
 566
 567         nvd0_display_flip_stop(crtc);
 568
 569         push = evo_wait(crtc->dev, EVO_MASTER, 2);
 570         if (push) {
 571                 evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
 572                 evo_data(push, 0x00000000);
 573                 evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1);
 574                 evo_data(push, 0x03000000);
 575                 evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
 576                 evo_data(push, 0x00000000);
 577                 evo_kick(push, crtc->dev, EVO_MASTER);
 578         }
 579
 580         nvd0_crtc_cursor_show(nv_crtc, false, false);
 581 }
 582
 583 static void
 584 nvd0_crtc_commit(struct drm_crtc *crtc)
 585 {
 586         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 587         u32 *push;
 588
 589         push = evo_wait(crtc->dev, EVO_MASTER, 32);
 590         if (push) {
 591                 evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
 592                 evo_data(push, nv_crtc->fb.tile_flags);
 593                 evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4);
 594                 evo_data(push, 0x83000000);
 595                 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
 596                 evo_data(push, 0x00000000);
 597                 evo_data(push, 0x00000000);
 598                 evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
 599                 evo_data(push, NvEvoVRAM);
 600                 evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1);
 601                 evo_data(push, 0xffffff00);
 602                 evo_kick(push, crtc->dev, EVO_MASTER);
 603         }
 604
 605         nvd0_crtc_cursor_show(nv_crtc, nv_crtc->cursor.visible, true);
 606         nvd0_display_flip_next(crtc, crtc->fb, NULL, 1);
 607 }
 608
 609 static bool
 610 nvd0_crtc_mode_fixup(struct drm_crtc *crtc, struct drm_display_mode *mode,
 611                      struct drm_display_mode *adjusted_mode)
 612 {
 613         return true;
 614 }
 615
 616 static int
 617 nvd0_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
 618 {
 619         struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->fb);
 620         int ret;
 621
 622         ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM);
 623         if (ret)
 624                 return ret;
 625
 626         if (old_fb) {
 627                 nvfb = nouveau_framebuffer(old_fb);
 628                 nouveau_bo_unpin(nvfb->nvbo);
 629         }
 630
 631         return 0;
 632 }
 633
 634 static int
 635 nvd0_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
 636                    struct drm_display_mode *mode, int x, int y,
 637                    struct drm_framebuffer *old_fb)
 638 {
 639         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 640         struct nouveau_connector *nv_connector;
 641         u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1;
 642         u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1;
 643         u32 hactive, hsynce, hbackp, hfrontp, hblanke, hblanks;
 644         u32 vactive, vsynce, vbackp, vfrontp, vblanke, vblanks;
 645         u32 vblan2e = 0, vblan2s = 1;
 646         u32 *push;
 647         int ret;
 648
 649         hactive = mode->htotal;
 650         hsynce  = mode->hsync_end - mode->hsync_start - 1;
 651         hbackp  = mode->htotal - mode->hsync_end;
 652         hblanke = hsynce + hbackp;
 653         hfrontp = mode->hsync_start - mode->hdisplay;
 654         hblanks = mode->htotal - hfrontp - 1;
 655
 656         vactive = mode->vtotal * vscan / ilace;
 657         vsynce  = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1;
 658         vbackp  = (mode->vtotal - mode->vsync_end) * vscan / ilace;
 659         vblanke = vsynce + vbackp;
 660         vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace;
 661         vblanks = vactive - vfrontp - 1;
 662         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 663                 vblan2e = vactive + vsynce + vbackp;
 664                 vblan2s = vblan2e + (mode->vdisplay * vscan / ilace);
 665                 vactive = (vactive * 2) + 1;
 666         }
 667
 668         ret = nvd0_crtc_swap_fbs(crtc, old_fb);
 669         if (ret)
 670                 return ret;
 671
 672         push = evo_wait(crtc->dev, EVO_MASTER, 64);
 673         if (push) {
 674                 evo_mthd(push, 0x0410 + (nv_crtc->index * 0x300), 6);
 675                 evo_data(push, 0x00000000);
 676                 evo_data(push, (vactive << 16) | hactive);
 677                 evo_data(push, ( vsynce << 16) | hsynce);
 678                 evo_data(push, (vblanke << 16) | hblanke);
 679                 evo_data(push, (vblanks << 16) | hblanks);
 680                 evo_data(push, (vblan2e << 16) | vblan2s);
 681                 evo_mthd(push, 0x042c + (nv_crtc->index * 0x300), 1);
 682                 evo_data(push, 0x00000000); /* ??? */
 683                 evo_mthd(push, 0x0450 + (nv_crtc->index * 0x300), 3);
 684                 evo_data(push, mode->clock * 1000);
 685                 evo_data(push, 0x00200000); /* ??? */
 686                 evo_data(push, mode->clock * 1000);
 687                 evo_mthd(push, 0x04d0 + (nv_crtc->index * 0x300), 2);
 688                 evo_data(push, 0x00000311);
 689                 evo_data(push, 0x00000100);
 690                 evo_kick(push, crtc->dev, EVO_MASTER);
 691         }
 692
 693         nv_connector = nouveau_crtc_connector_get(nv_crtc);
 694         nvd0_crtc_set_dither(nv_crtc, false);
 695         nvd0_crtc_set_scale(nv_crtc, false);
 696         nvd0_crtc_set_image(nv_crtc, crtc->fb, x, y, false);
 697         return 0;
 698 }
 699
 700 static int
 701 nvd0_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
 702                         struct drm_framebuffer *old_fb)
 703 {
 704         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 705         int ret;
 706
 707         if (!crtc->fb) {
 708                 NV_DEBUG_KMS(crtc->dev, "No FB bound\n");
 709                 return 0;
 710         }
 711
 712         ret = nvd0_crtc_swap_fbs(crtc, old_fb);
 713         if (ret)
 714                 return ret;
 715
 716         nvd0_display_flip_stop(crtc);
 717         nvd0_crtc_set_image(nv_crtc, crtc->fb, x, y, true);
 718         nvd0_display_flip_next(crtc, crtc->fb, NULL, 1);
 719         return 0;
 720 }
 721
 722 static int
 723 nvd0_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
 724                                struct drm_framebuffer *fb, int x, int y,
 725                                enum mode_set_atomic state)
 726 {
 727         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 728         nvd0_display_flip_stop(crtc);
 729         nvd0_crtc_set_image(nv_crtc, fb, x, y, true);
 730         return 0;
 731 }
 732
 733 static void
 734 nvd0_crtc_lut_load(struct drm_crtc *crtc)
 735 {
 736         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 737         void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
 738         int i;
 739
 740         for (i = 0; i < 256; i++) {
 741                 writew(0x6000 + (nv_crtc->lut.r[i] >> 2), lut + (i * 0x20) + 0);
 742                 writew(0x6000 + (nv_crtc->lut.g[i] >> 2), lut + (i * 0x20) + 2);
 743                 writew(0x6000 + (nv_crtc->lut.b[i] >> 2), lut + (i * 0x20) + 4);
 744         }
 745 }
 746
 747 static int
 748 nvd0_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
 749                      uint32_t handle, uint32_t width, uint32_t height)
 750 {
 751         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 752         struct drm_device *dev = crtc->dev;
 753         struct drm_gem_object *gem;
 754         struct nouveau_bo *nvbo;
 755         bool visible = (handle != 0);
 756         int i, ret = 0;
 757
 758         if (visible) {
 759                 if (width != 64 || height != 64)
 760                         return -EINVAL;
 761
 762                 gem = drm_gem_object_lookup(dev, file_priv, handle);
 763                 if (unlikely(!gem))
 764                         return -ENOENT;
 765                 nvbo = nouveau_gem_object(gem);
 766
 767                 ret = nouveau_bo_map(nvbo);
 768                 if (ret == 0) {
 769                         for (i = 0; i < 64 * 64; i++) {
 770                                 u32 v = nouveau_bo_rd32(nvbo, i);
 771                                 nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, v);
 772                         }
 773                         nouveau_bo_unmap(nvbo);
 774                 }
 775
 776                 drm_gem_object_unreference_unlocked(gem);
 777         }
 778
 779         if (visible != nv_crtc->cursor.visible) {
 780                 nvd0_crtc_cursor_show(nv_crtc, visible, true);
 781                 nv_crtc->cursor.visible = visible;
 782         }
 783
 784         return ret;
 785 }
 786
 787 static int
 788 nvd0_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
 789 {
 790         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 791         int ch = EVO_CURS(nv_crtc->index);
 792
 793         evo_piow(crtc->dev, ch, 0x0084, (y << 16) | x);
 794         evo_piow(crtc->dev, ch, 0x0080, 0x00000000);
 795         return 0;
 796 }
 797
 798 static void
 799 nvd0_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
 800                     uint32_t start, uint32_t size)
 801 {
 802         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 803         u32 end = max(start + size, (u32)256);
 804         u32 i;
 805
 806         for (i = start; i < end; i++) {
 807                 nv_crtc->lut.r[i] = r[i];
 808                 nv_crtc->lut.g[i] = g[i];
 809                 nv_crtc->lut.b[i] = b[i];
 810         }
 811
 812         nvd0_crtc_lut_load(crtc);
 813 }
 814
 815 static void
 816 nvd0_crtc_destroy(struct drm_crtc *crtc)
 817 {
 818         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 819         nouveau_bo_unmap(nv_crtc->cursor.nvbo);
 820         nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
 821         nouveau_bo_unmap(nv_crtc->lut.nvbo);
 822         nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
 823         drm_crtc_cleanup(crtc);
 824         kfree(crtc);
 825 }
 826
 827 static const struct drm_crtc_helper_funcs nvd0_crtc_hfunc = {
 828         .dpms = nvd0_crtc_dpms,
 829         .prepare = nvd0_crtc_prepare,
 830         .commit = nvd0_crtc_commit,
 831         .mode_fixup = nvd0_crtc_mode_fixup,
 832         .mode_set = nvd0_crtc_mode_set,
 833         .mode_set_base = nvd0_crtc_mode_set_base,
 834         .mode_set_base_atomic = nvd0_crtc_mode_set_base_atomic,
 835         .load_lut = nvd0_crtc_lut_load,
 836 };
 837
 838 static const struct drm_crtc_funcs nvd0_crtc_func = {
 839         .cursor_set = nvd0_crtc_cursor_set,
 840         .cursor_move = nvd0_crtc_cursor_move,
 841         .gamma_set = nvd0_crtc_gamma_set,
 842         .set_config = drm_crtc_helper_set_config,
 843         .destroy = nvd0_crtc_destroy,
 844         .page_flip = nouveau_crtc_page_flip,
 845 };
 846
 847 static void
 848 nvd0_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y)
 849 {
 850 }
 851
 852 static void
 853 nvd0_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset)
 854 {
 855 }
 856
 857 static int
 858 nvd0_crtc_create(struct drm_device *dev, int index)
 859 {
 860         struct nouveau_crtc *nv_crtc;
 861         struct drm_crtc *crtc;
 862         int ret, i;
 863
 864         nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL);
 865         if (!nv_crtc)
 866                 return -ENOMEM;
 867
 868         nv_crtc->index = index;
 869         nv_crtc->set_dither = nvd0_crtc_set_dither;
 870         nv_crtc->set_scale = nvd0_crtc_set_scale;
 871         nv_crtc->cursor.set_offset = nvd0_cursor_set_offset;
 872         nv_crtc->cursor.set_pos = nvd0_cursor_set_pos;
 873         for (i = 0; i < 256; i++) {
 874                 nv_crtc->lut.r[i] = i << 8;
 875                 nv_crtc->lut.g[i] = i << 8;
 876                 nv_crtc->lut.b[i] = i << 8;
 877         }
 878
 879         crtc = &nv_crtc->base;
 880         drm_crtc_init(dev, crtc, &nvd0_crtc_func);
 881         drm_crtc_helper_add(crtc, &nvd0_crtc_hfunc);
 882         drm_mode_crtc_set_gamma_size(crtc, 256);
 883
 884         ret = nouveau_bo_new(dev, 64 * 64 * 4, 0x100, TTM_PL_FLAG_VRAM,
 885                              0, 0x0000, &nv_crtc->cursor.nvbo);
 886         if (!ret) {
 887                 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
 888                 if (!ret)
 889                         ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
 890                 if (ret)
 891                         nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
 892         }
 893
 894         if (ret)
 895                 goto out;
 896
 897         ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM,
 898                              0, 0x0000, &nv_crtc->lut.nvbo);
 899         if (!ret) {
 900                 ret = nouveau_bo_pin(nv_crtc->lut.nvbo, TTM_PL_FLAG_VRAM);
 901                 if (!ret)
 902                         ret = nouveau_bo_map(nv_crtc->lut.nvbo);
 903                 if (ret)
 904                         nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
 905         }
 906
 907         if (ret)
 908                 goto out;
 909
 910         nvd0_crtc_lut_load(crtc);
 911
 912 out:
 913         if (ret)
 914                 nvd0_crtc_destroy(crtc);
 915         return ret;
 916 }
 917
 918 /******************************************************************************
 919  * DAC
 920  *****************************************************************************/
 921 static void
 922 nvd0_dac_dpms(struct drm_encoder *encoder, int mode)
 923 {
 924         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 925         struct drm_device *dev = encoder->dev;
 926         int or = nv_encoder->or;
 927         u32 dpms_ctrl;
 928
 929         dpms_ctrl = 0x80000000;
 930         if (mode == DRM_MODE_DPMS_STANDBY || mode == DRM_MODE_DPMS_OFF)
 931                 dpms_ctrl |= 0x00000001;
 932         if (mode == DRM_MODE_DPMS_SUSPEND || mode == DRM_MODE_DPMS_OFF)
 933                 dpms_ctrl |= 0x00000004;
 934
 935         nv_wait(dev, 0x61a004 + (or * 0x0800), 0x80000000, 0x00000000);
 936         nv_mask(dev, 0x61a004 + (or * 0x0800), 0xc000007f, dpms_ctrl);
 937         nv_wait(dev, 0x61a004 + (or * 0x0800), 0x80000000, 0x00000000);
 938 }
 939
 940 static bool
 941 nvd0_dac_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 942                     struct drm_display_mode *adjusted_mode)
 943 {
 944         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 945         struct nouveau_connector *nv_connector;
 946
 947         nv_connector = nouveau_encoder_connector_get(nv_encoder);
 948         if (nv_connector && nv_connector->native_mode) {
 949                 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
 950                         int id = adjusted_mode->base.id;
 951                         *adjusted_mode = *nv_connector->native_mode;
 952                         adjusted_mode->base.id = id;
 953                 }
 954         }
 955
 956         return true;
 957 }
 958
 959 static void
 960 nvd0_dac_commit(struct drm_encoder *encoder)
 961 {
 962 }
 963
 964 static void
 965 nvd0_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 966                   struct drm_display_mode *adjusted_mode)
 967 {
 968         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 969         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 970         u32 syncs, magic, *push;
 971
 972         syncs = 0x00000001;
 973         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 974                 syncs |= 0x00000008;
 975         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 976                 syncs |= 0x00000010;
 977
 978         magic = 0x31ec6000 | (nv_crtc->index << 25);
 979         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 980                 magic |= 0x00000001;
 981
 982         nvd0_dac_dpms(encoder, DRM_MODE_DPMS_ON);
 983
 984         push = evo_wait(encoder->dev, EVO_MASTER, 8);
 985         if (push) {
 986                 evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
 987                 evo_data(push, syncs);
 988                 evo_data(push, magic);
 989                 evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 2);
 990                 evo_data(push, 1 << nv_crtc->index);
 991                 evo_data(push, 0x00ff);
 992                 evo_kick(push, encoder->dev, EVO_MASTER);
 993         }
 994
 995         nv_encoder->crtc = encoder->crtc;
 996 }
 997
 998 static void
 999 nvd0_dac_disconnect(struct drm_encoder *encoder)
1000 {
1001         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1002         struct drm_device *dev = encoder->dev;
1003         u32 *push;
1004
1005         if (nv_encoder->crtc) {
1006                 nvd0_crtc_prepare(nv_encoder->crtc);
1007
1008                 push = evo_wait(dev, EVO_MASTER, 4);
1009                 if (push) {
1010                         evo_mthd(push, 0x0180 + (nv_encoder->or * 0x20), 1);
1011                         evo_data(push, 0x00000000);
1012                         evo_mthd(push, 0x0080, 1);
1013                         evo_data(push, 0x00000000);
1014                         evo_kick(push, dev, EVO_MASTER);
1015                 }
1016
1017                 nv_encoder->crtc = NULL;
1018         }
1019 }
1020
1021 static enum drm_connector_status
1022 nvd0_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1023 {
1024         enum drm_connector_status status = connector_status_disconnected;
1025         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1026         struct drm_device *dev = encoder->dev;
1027         int or = nv_encoder->or;
1028         u32 load;
1029
1030         nv_wr32(dev, 0x61a00c + (or * 0x800), 0x00100000);
1031         udelay(9500);
1032         nv_wr32(dev, 0x61a00c + (or * 0x800), 0x80000000);
1033
1034         load = nv_rd32(dev, 0x61a00c + (or * 0x800));
1035         if ((load & 0x38000000) == 0x38000000)
1036                 status = connector_status_connected;
1037
1038         nv_wr32(dev, 0x61a00c + (or * 0x800), 0x00000000);
1039         return status;
1040 }
1041
1042 static void
1043 nvd0_dac_destroy(struct drm_encoder *encoder)
1044 {
1045         drm_encoder_cleanup(encoder);
1046         kfree(encoder);
1047 }
1048
1049 static const struct drm_encoder_helper_funcs nvd0_dac_hfunc = {
1050         .dpms = nvd0_dac_dpms,
1051         .mode_fixup = nvd0_dac_mode_fixup,
1052         .prepare = nvd0_dac_disconnect,
1053         .commit = nvd0_dac_commit,
1054         .mode_set = nvd0_dac_mode_set,
1055         .disable = nvd0_dac_disconnect,
1056         .get_crtc = nvd0_display_crtc_get,
1057         .detect = nvd0_dac_detect
1058 };
1059
1060 static const struct drm_encoder_funcs nvd0_dac_func = {
1061         .destroy = nvd0_dac_destroy,
1062 };
1063
1064 static int
1065 nvd0_dac_create(struct drm_connector *connector, struct dcb_entry *dcbe)
1066 {
1067         struct drm_device *dev = connector->dev;
1068         struct nouveau_encoder *nv_encoder;
1069         struct drm_encoder *encoder;
1070
1071         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1072         if (!nv_encoder)
1073                 return -ENOMEM;
1074         nv_encoder->dcb = dcbe;
1075         nv_encoder->or = ffs(dcbe->or) - 1;
1076
1077         encoder = to_drm_encoder(nv_encoder);
1078         encoder->possible_crtcs = dcbe->heads;
1079         encoder->possible_clones = 0;
1080         drm_encoder_init(dev, encoder, &nvd0_dac_func, DRM_MODE_ENCODER_DAC);
1081         drm_encoder_helper_add(encoder, &nvd0_dac_hfunc);
1082
1083         drm_mode_connector_attach_encoder(connector, encoder);
1084         return 0;
1085 }
1086
1087 /******************************************************************************
1088  * Audio
1089  *****************************************************************************/
1090 static void
1091 nvd0_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1092 {
1093         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1094         struct nouveau_connector *nv_connector;
1095         struct drm_device *dev = encoder->dev;
1096         int i, or = nv_encoder->or * 0x30;
1097
1098         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1099         if (!drm_detect_monitor_audio(nv_connector->edid))
1100                 return;
1101
1102         nv_mask(dev, 0x10ec10 + or, 0x80000003, 0x80000001);
1103
1104         drm_edid_to_eld(&nv_connector->base, nv_connector->edid);
1105         if (nv_connector->base.eld[0]) {
1106                 u8 *eld = nv_connector->base.eld;
1107
1108                 for (i = 0; i < eld[2] * 4; i++)
1109                         nv_wr32(dev, 0x10ec00 + or, (i << 8) | eld[i]);
1110                 for (i = eld[2] * 4; i < 0x60; i++)
1111                         nv_wr32(dev, 0x10ec00 + or, (i << 8) | 0x00);
1112
1113                 nv_mask(dev, 0x10ec10 + or, 0x80000002, 0x80000002);
1114         }
1115 }
1116
1117 static void
1118 nvd0_audio_disconnect(struct drm_encoder *encoder)
1119 {
1120         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1121         struct drm_device *dev = encoder->dev;
1122         int or = nv_encoder->or * 0x30;
1123
1124         nv_mask(dev, 0x10ec10 + or, 0x80000003, 0x80000000);
1125 }
1126
1127 /******************************************************************************
1128  * HDMI
1129  *****************************************************************************/
1130 static void
1131 nvd0_hdmi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1132 {
1133         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1134         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1135         struct nouveau_connector *nv_connector;
1136         struct drm_device *dev = encoder->dev;
1137         int head = nv_crtc->index * 0x800;
1138         u32 rekey = 56; /* binary driver, and tegra constant */
1139         u32 max_ac_packet;
1140
1141         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1142         if (!drm_detect_hdmi_monitor(nv_connector->edid))
1143                 return;
1144
1145         max_ac_packet  = mode->htotal - mode->hdisplay;
1146         max_ac_packet -= rekey;
1147         max_ac_packet -= 18; /* constant from tegra */
1148         max_ac_packet /= 32;
1149
1150         /* AVI InfoFrame */
1151         nv_mask(dev, 0x616714 + head, 0x00000001, 0x00000000);
1152         nv_wr32(dev, 0x61671c + head, 0x000d0282);
1153         nv_wr32(dev, 0x616720 + head, 0x0000006f);
1154         nv_wr32(dev, 0x616724 + head, 0x00000000);
1155         nv_wr32(dev, 0x616728 + head, 0x00000000);
1156         nv_wr32(dev, 0x61672c + head, 0x00000000);
1157         nv_mask(dev, 0x616714 + head, 0x00000001, 0x00000001);
1158
1159         /* ??? InfoFrame? */
1160         nv_mask(dev, 0x6167a4 + head, 0x00000001, 0x00000000);
1161         nv_wr32(dev, 0x6167ac + head, 0x00000010);
1162         nv_mask(dev, 0x6167a4 + head, 0x00000001, 0x00000001);
1163
1164         /* HDMI_CTRL */
1165         nv_mask(dev, 0x616798 + head, 0x401f007f, 0x40000000 | rekey |
1166                                                   max_ac_packet << 16);
1167
1168         /* NFI, audio doesn't work without it though.. */
1169         nv_mask(dev, 0x616548 + head, 0x00000070, 0x00000000);
1170
1171         nvd0_audio_mode_set(encoder, mode);
1172 }
1173
1174 static void
1175 nvd0_hdmi_disconnect(struct drm_encoder *encoder)
1176 {
1177         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1178         struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1179         struct drm_device *dev = encoder->dev;
1180         int head = nv_crtc->index * 0x800;
1181
1182         nvd0_audio_disconnect(encoder);
1183
1184         nv_mask(dev, 0x616798 + head, 0x40000000, 0x00000000);
1185         nv_mask(dev, 0x6167a4 + head, 0x00000001, 0x00000000);
1186         nv_mask(dev, 0x616714 + head, 0x00000001, 0x00000000);
1187 }
1188
1189 /******************************************************************************
1190  * SOR
1191  *****************************************************************************/
1192 static inline u32
1193 nvd0_sor_dp_lane_map(struct drm_device *dev, struct dcb_entry *dcb, u8 lane)
1194 {
1195         static const u8 nvd0[] = { 16, 8, 0, 24 };
1196         return nvd0[lane];
1197 }
1198
1199 static void
1200 nvd0_sor_dp_train_set(struct drm_device *dev, struct dcb_entry *dcb, u8 pattern)
1201 {
1202         const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
1203         const u32 loff = (or * 0x800) + (link * 0x80);
1204         nv_mask(dev, 0x61c110 + loff, 0x0f0f0f0f, 0x01010101 * pattern);
1205 }
1206
1207 static void
1208 nvd0_sor_dp_train_adj(struct drm_device *dev, struct dcb_entry *dcb,
1209                       u8 lane, u8 swing, u8 preem)
1210 {
1211         const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
1212         const u32 loff = (or * 0x800) + (link * 0x80);
1213         u32 shift = nvd0_sor_dp_lane_map(dev, dcb, lane);
1214         u32 mask = 0x000000ff << shift;
1215         u8 *table, *entry, *config = NULL;
1216
1217         switch (swing) {
1218         case 0: preem += 0; break;
1219         case 1: preem += 4; break;
1220         case 2: preem += 7; break;
1221         case 3: preem += 9; break;
1222         }
1223
1224         table = nouveau_dp_bios_data(dev, dcb, &entry);
1225         if (table) {
1226                 if (table[0] == 0x30) {
1227                         config  = entry + table[4];
1228                         config += table[5] * preem;
1229                 } else
1230                 if (table[0] == 0x40) {
1231                         config  = table + table[1];
1232                         config += table[2] * table[3];
1233                         config += table[6] * preem;
1234                 }
1235         }
1236
1237         if (!config) {
1238                 NV_ERROR(dev, "PDISP: unsupported DP table for chipset\n");
1239                 return;
1240         }
1241
1242         nv_mask(dev, 0x61c118 + loff, mask, config[1] << shift);
1243         nv_mask(dev, 0x61c120 + loff, mask, config[2] << shift);
1244         nv_mask(dev, 0x61c130 + loff, 0x0000ff00, config[3] << 8);
1245         nv_mask(dev, 0x61c13c + loff, 0x00000000, 0x00000000);
1246 }
1247
1248 static void
1249 nvd0_sor_dp_link_set(struct drm_device *dev, struct dcb_entry *dcb, int crtc,
1250                      int link_nr, u32 link_bw, bool enhframe)
1251 {
1252         const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
1253         const u32 loff = (or * 0x800) + (link * 0x80);
1254         const u32 soff = (or * 0x800);
1255         u32 dpctrl = nv_rd32(dev, 0x61c10c + loff) & ~0x001f4000;
1256         u32 clksor = nv_rd32(dev, 0x612300 + soff) & ~0x007c0000;
1257         u32 script = 0x0000, lane_mask = 0;
1258         u8 *table, *entry;
1259         int i;
1260
1261         link_bw /= 27000;
1262
1263         table = nouveau_dp_bios_data(dev, dcb, &entry);
1264         if (table) {
1265                 if      (table[0] == 0x30) entry = ROMPTR(dev, entry[10]);
1266                 else if (table[0] == 0x40) entry = ROMPTR(dev, entry[9]);
1267                 else                       entry = NULL;
1268
1269                 while (entry) {
1270                         if (entry[0] >= link_bw)
1271                                 break;
1272                         entry += 3;
1273                 }
1274
1275                 nouveau_bios_run_init_table(dev, script, dcb, crtc);
1276         }
1277
1278         clksor |= link_bw << 18;
1279         dpctrl |= ((1 << link_nr) - 1) << 16;
1280         if (enhframe)
1281                 dpctrl |= 0x00004000;
1282
1283         for (i = 0; i < link_nr; i++)
1284                 lane_mask |= 1 << (nvd0_sor_dp_lane_map(dev, dcb, i) >> 3);
1285
1286         nv_wr32(dev, 0x612300 + soff, clksor);
1287         nv_wr32(dev, 0x61c10c + loff, dpctrl);
1288         nv_mask(dev, 0x61c130 + loff, 0x0000000f, lane_mask);
1289 }
1290
1291 static void
1292 nvd0_sor_dp_link_get(struct drm_device *dev, struct dcb_entry *dcb,
1293                      u32 *link_nr, u32 *link_bw)
1294 {
1295         const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
1296         const u32 loff = (or * 0x800) + (link * 0x80);
1297         const u32 soff = (or * 0x800);
1298         u32 dpctrl = nv_rd32(dev, 0x61c10c + loff) & 0x000f0000;
1299         u32 clksor = nv_rd32(dev, 0x612300 + soff);
1300
1301         if      (dpctrl > 0x00030000) *link_nr = 4;
1302         else if (dpctrl > 0x00010000) *link_nr = 2;
1303         else                          *link_nr = 1;
1304
1305         *link_bw  = (clksor & 0x007c0000) >> 18;
1306         *link_bw *= 27000;
1307 }
1308
1309 static void
1310 nvd0_sor_dp_calc_tu(struct drm_device *dev, struct dcb_entry *dcb,
1311                     u32 crtc, u32 datarate)
1312 {
1313         const u32 symbol = 100000;
1314         const u32 TU = 64;
1315         u32 link_nr, link_bw;
1316         u64 ratio, value;
1317
1318         nvd0_sor_dp_link_get(dev, dcb, &link_nr, &link_bw);
1319
1320         ratio  = datarate;
1321         ratio *= symbol;
1322         do_div(ratio, link_nr * link_bw);
1323
1324         value  = (symbol - ratio) * TU;
1325         value *= ratio;
1326         do_div(value, symbol);
1327         do_div(value, symbol);
1328
1329         value += 5;
1330         value |= 0x08000000;
1331
1332         nv_wr32(dev, 0x616610 + (crtc * 0x800), value);
1333 }
1334
1335 static void
1336 nvd0_sor_dpms(struct drm_encoder *encoder, int mode)
1337 {
1338         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1339         struct drm_device *dev = encoder->dev;
1340         struct drm_encoder *partner;
1341         int or = nv_encoder->or;
1342         u32 dpms_ctrl;
1343
1344         nv_encoder->last_dpms = mode;
1345
1346         list_for_each_entry(partner, &dev->mode_config.encoder_list, head) {
1347                 struct nouveau_encoder *nv_partner = nouveau_encoder(partner);
1348
1349                 if (partner->encoder_type != DRM_MODE_ENCODER_TMDS)
1350                         continue;
1351
1352                 if (nv_partner != nv_encoder &&
1353                     nv_partner->dcb->or == nv_encoder->dcb->or) {
1354                         if (nv_partner->last_dpms == DRM_MODE_DPMS_ON)
1355                                 return;
1356                         break;
1357                 }
1358         }
1359
1360         dpms_ctrl  = (mode == DRM_MODE_DPMS_ON);
1361         dpms_ctrl |= 0x80000000;
1362
1363         nv_wait(dev, 0x61c004 + (or * 0x0800), 0x80000000, 0x00000000);
1364         nv_mask(dev, 0x61c004 + (or * 0x0800), 0x80000001, dpms_ctrl);
1365         nv_wait(dev, 0x61c004 + (or * 0x0800), 0x80000000, 0x00000000);
1366         nv_wait(dev, 0x61c030 + (or * 0x0800), 0x10000000, 0x00000000);
1367
1368         if (nv_encoder->dcb->type == OUTPUT_DP) {
1369                 struct dp_train_func func = {
1370                         .link_set = nvd0_sor_dp_link_set,
1371                         .train_set = nvd0_sor_dp_train_set,
1372                         .train_adj = nvd0_sor_dp_train_adj
1373                 };
1374
1375                 nouveau_dp_dpms(encoder, mode, nv_encoder->dp.datarate, &func);
1376         }
1377 }
1378
1379 static bool
1380 nvd0_sor_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
1381                     struct drm_display_mode *adjusted_mode)
1382 {
1383         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1384         struct nouveau_connector *nv_connector;
1385
1386         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1387         if (nv_connector && nv_connector->native_mode) {
1388                 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
1389                         int id = adjusted_mode->base.id;
1390                         *adjusted_mode = *nv_connector->native_mode;
1391                         adjusted_mode->base.id = id;
1392                 }
1393         }
1394
1395         return true;
1396 }
1397
1398 static void
1399 nvd0_sor_disconnect(struct drm_encoder *encoder)
1400 {
1401         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1402         struct drm_device *dev = encoder->dev;
1403         u32 *push;
1404
1405         if (nv_encoder->crtc) {
1406                 nvd0_crtc_prepare(nv_encoder->crtc);
1407
1408                 push = evo_wait(dev, EVO_MASTER, 4);
1409                 if (push) {
1410                         evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1);
1411                         evo_data(push, 0x00000000);
1412                         evo_mthd(push, 0x0080, 1);
1413                         evo_data(push, 0x00000000);
1414                         evo_kick(push, dev, EVO_MASTER);
1415                 }
1416
1417                 nvd0_hdmi_disconnect(encoder);
1418
1419                 nv_encoder->crtc = NULL;
1420                 nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
1421         }
1422 }
1423
1424 static void
1425 nvd0_sor_prepare(struct drm_encoder *encoder)
1426 {
1427         nvd0_sor_disconnect(encoder);
1428         if (nouveau_encoder(encoder)->dcb->type == OUTPUT_DP)
1429                 evo_sync(encoder->dev, EVO_MASTER);
1430 }
1431
1432 static void
1433 nvd0_sor_commit(struct drm_encoder *encoder)
1434 {
1435 }
1436
1437 static void
1438 nvd0_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
1439                   struct drm_display_mode *mode)
1440 {
1441         struct drm_device *dev = encoder->dev;
1442         struct drm_nouveau_private *dev_priv = dev->dev_private;
1443         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1444         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1445         struct nouveau_connector *nv_connector;
1446         struct nvbios *bios = &dev_priv->vbios;
1447         u32 mode_ctrl = (1 << nv_crtc->index);
1448         u32 syncs, magic, *push;
1449         u32 or_config;
1450
1451         syncs = 0x00000001;
1452         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1453                 syncs |= 0x00000008;
1454         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1455                 syncs |= 0x00000010;
1456
1457         magic = 0x31ec6000 | (nv_crtc->index << 25);
1458         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1459                 magic |= 0x00000001;
1460
1461         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1462         switch (nv_encoder->dcb->type) {
1463         case OUTPUT_TMDS:
1464                 if (nv_encoder->dcb->sorconf.link & 1) {
1465                         if (mode->clock < 165000)
1466                                 mode_ctrl |= 0x00000100;
1467                         else
1468                                 mode_ctrl |= 0x00000500;
1469                 } else {
1470                         mode_ctrl |= 0x00000200;
1471                 }
1472
1473                 or_config = (mode_ctrl & 0x00000f00) >> 8;
1474                 if (mode->clock >= 165000)
1475                         or_config |= 0x0100;
1476
1477                 nvd0_hdmi_mode_set(encoder, mode);
1478                 break;
1479         case OUTPUT_LVDS:
1480                 or_config = (mode_ctrl & 0x00000f00) >> 8;
1481                 if (bios->fp_no_ddc) {
1482                         if (bios->fp.dual_link)
1483                                 or_config |= 0x0100;
1484                         if (bios->fp.if_is_24bit)
1485                                 or_config |= 0x0200;
1486                 } else {
1487                         if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1488                                 if (((u8 *)nv_connector->edid)[121] == 2)
1489                                         or_config |= 0x0100;
1490                         } else
1491                         if (mode->clock >= bios->fp.duallink_transition_clk) {
1492                                 or_config |= 0x0100;
1493                         }
1494
1495                         if (or_config & 0x0100) {
1496                                 if (bios->fp.strapless_is_24bit & 2)
1497                                         or_config |= 0x0200;
1498                         } else {
1499                                 if (bios->fp.strapless_is_24bit & 1)
1500                                         or_config |= 0x0200;
1501                         }
1502
1503                         if (nv_connector->base.display_info.bpc == 8)
1504                                 or_config |= 0x0200;
1505
1506                 }
1507                 break;
1508         case OUTPUT_DP:
1509                 if (nv_connector->base.display_info.bpc == 6) {
1510                         nv_encoder->dp.datarate = mode->clock * 18 / 8;
1511                         syncs |= 0x00000140;
1512                 } else {
1513                         nv_encoder->dp.datarate = mode->clock * 24 / 8;
1514                         syncs |= 0x00000180;
1515                 }
1516
1517                 if (nv_encoder->dcb->sorconf.link & 1)
1518                         mode_ctrl |= 0x00000800;
1519                 else
1520                         mode_ctrl |= 0x00000900;
1521
1522                 or_config = (mode_ctrl & 0x00000f00) >> 8;
1523                 break;
1524         default:
1525                 BUG_ON(1);
1526                 break;
1527         }
1528
1529         nvd0_sor_dpms(encoder, DRM_MODE_DPMS_ON);
1530
1531         if (nv_encoder->dcb->type == OUTPUT_DP) {
1532                 nvd0_sor_dp_calc_tu(dev, nv_encoder->dcb, nv_crtc->index,
1533                                          nv_encoder->dp.datarate);
1534         }
1535
1536         push = evo_wait(dev, EVO_MASTER, 8);
1537         if (push) {
1538                 evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
1539                 evo_data(push, syncs);
1540                 evo_data(push, magic);
1541                 evo_mthd(push, 0x0200 + (nv_encoder->or * 0x020), 2);
1542                 evo_data(push, mode_ctrl);
1543                 evo_data(push, or_config);
1544                 evo_kick(push, dev, EVO_MASTER);
1545         }
1546
1547         nv_encoder->crtc = encoder->crtc;
1548 }
1549
1550 static void
1551 nvd0_sor_destroy(struct drm_encoder *encoder)
1552 {
1553         drm_encoder_cleanup(encoder);
1554         kfree(encoder);
1555 }
1556
1557 static const struct drm_encoder_helper_funcs nvd0_sor_hfunc = {
1558         .dpms = nvd0_sor_dpms,
1559         .mode_fixup = nvd0_sor_mode_fixup,
1560         .prepare = nvd0_sor_prepare,
1561         .commit = nvd0_sor_commit,
1562         .mode_set = nvd0_sor_mode_set,
1563         .disable = nvd0_sor_disconnect,
1564         .get_crtc = nvd0_display_crtc_get,
1565 };
1566
1567 static const struct drm_encoder_funcs nvd0_sor_func = {
1568         .destroy = nvd0_sor_destroy,
1569 };
1570
1571 static int
1572 nvd0_sor_create(struct drm_connector *connector, struct dcb_entry *dcbe)
1573 {
1574         struct drm_device *dev = connector->dev;
1575         struct nouveau_encoder *nv_encoder;
1576         struct drm_encoder *encoder;
1577
1578         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1579         if (!nv_encoder)
1580                 return -ENOMEM;
1581         nv_encoder->dcb = dcbe;
1582         nv_encoder->or = ffs(dcbe->or) - 1;
1583         nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
1584
1585         encoder = to_drm_encoder(nv_encoder);
1586         encoder->possible_crtcs = dcbe->heads;
1587         encoder->possible_clones = 0;
1588         drm_encoder_init(dev, encoder, &nvd0_sor_func, DRM_MODE_ENCODER_TMDS);
1589         drm_encoder_helper_add(encoder, &nvd0_sor_hfunc);
1590
1591         drm_mode_connector_attach_encoder(connector, encoder);
1592         return 0;
1593 }
1594
1595 /******************************************************************************
1596  * IRQ
1597  *****************************************************************************/
1598 static struct dcb_entry *
1599 lookup_dcb(struct drm_device *dev, int id, u32 mc)
1600 {
1601         struct drm_nouveau_private *dev_priv = dev->dev_private;
1602         int type, or, i, link = -1;
1603
1604         if (id < 4) {
1605                 type = OUTPUT_ANALOG;
1606                 or   = id;
1607         } else {
1608                 switch (mc & 0x00000f00) {
1609                 case 0x00000000: link = 0; type = OUTPUT_LVDS; break;
1610                 case 0x00000100: link = 0; type = OUTPUT_TMDS; break;
1611                 case 0x00000200: link = 1; type = OUTPUT_TMDS; break;
1612                 case 0x00000500: link = 0; type = OUTPUT_TMDS; break;
1613                 case 0x00000800: link = 0; type = OUTPUT_DP; break;
1614                 case 0x00000900: link = 1; type = OUTPUT_DP; break;
1615                 default:
1616                         NV_ERROR(dev, "PDISP: unknown SOR mc 0x%08x\n", mc);
1617                         return NULL;
1618                 }
1619
1620                 or = id - 4;
1621         }
1622
1623         for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
1624                 struct dcb_entry *dcb = &dev_priv->vbios.dcb.entry[i];
1625                 if (dcb->type == type && (dcb->or & (1 << or)) &&
1626                     (link < 0 || link == !(dcb->sorconf.link & 1)))
1627                         return dcb;
1628         }
1629
1630         NV_ERROR(dev, "PDISP: DCB for %d/0x%08x not found\n", id, mc);
1631         return NULL;
1632 }
1633
1634 static void
1635 nvd0_display_unk1_handler(struct drm_device *dev, u32 crtc, u32 mask)
1636 {
1637         struct dcb_entry *dcb;
1638         int i;
1639
1640         for (i = 0; mask && i < 8; i++) {
1641                 u32 mcc = nv_rd32(dev, 0x640180 + (i * 0x20));
1642                 if (!(mcc & (1 << crtc)))
1643                         continue;
1644
1645                 dcb = lookup_dcb(dev, i, mcc);
1646                 if (!dcb)
1647                         continue;
1648
1649                 nouveau_bios_run_display_table(dev, 0x0000, -1, dcb, crtc);
1650         }
1651
1652         nv_wr32(dev, 0x6101d4, 0x00000000);
1653         nv_wr32(dev, 0x6109d4, 0x00000000);
1654         nv_wr32(dev, 0x6101d0, 0x80000000);
1655 }
1656
1657 static void
1658 nvd0_display_unk2_handler(struct drm_device *dev, u32 crtc, u32 mask)
1659 {
1660         struct dcb_entry *dcb;
1661         u32 or, tmp, pclk;
1662         int i;
1663
1664         for (i = 0; mask && i < 8; i++) {
1665                 u32 mcc = nv_rd32(dev, 0x640180 + (i * 0x20));
1666                 if (!(mcc & (1 << crtc)))
1667                         continue;
1668
1669                 dcb = lookup_dcb(dev, i, mcc);
1670                 if (!dcb)
1671                         continue;
1672
1673                 nouveau_bios_run_display_table(dev, 0x0000, -2, dcb, crtc);
1674         }
1675
1676         pclk = nv_rd32(dev, 0x660450 + (crtc * 0x300)) / 1000;
1677         NV_DEBUG_KMS(dev, "PDISP: crtc %d pclk %d mask 0x%08x\n",
1678                           crtc, pclk, mask);
1679         if (pclk && (mask & 0x00010000)) {
1680                 nv50_crtc_set_clock(dev, crtc, pclk);
1681         }
1682
1683         for (i = 0; mask && i < 8; i++) {
1684                 u32 mcp = nv_rd32(dev, 0x660180 + (i * 0x20));
1685                 u32 cfg = nv_rd32(dev, 0x660184 + (i * 0x20));
1686                 if (!(mcp & (1 << crtc)))
1687                         continue;
1688
1689                 dcb = lookup_dcb(dev, i, mcp);
1690                 if (!dcb)
1691                         continue;
1692                 or = ffs(dcb->or) - 1;
1693
1694                 nouveau_bios_run_display_table(dev, cfg, pclk, dcb, crtc);
1695
1696                 nv_wr32(dev, 0x612200 + (crtc * 0x800), 0x00000000);
1697                 switch (dcb->type) {
1698                 case OUTPUT_ANALOG:
1699                         nv_wr32(dev, 0x612280 + (or * 0x800), 0x00000000);
1700                         break;
1701                 case OUTPUT_TMDS:
1702                 case OUTPUT_LVDS:
1703                 case OUTPUT_DP:
1704                         if (cfg & 0x00000100)
1705                                 tmp = 0x00000101;
1706                         else
1707                                 tmp = 0x00000000;
1708
1709                         nv_mask(dev, 0x612300 + (or * 0x800), 0x00000707, tmp);
1710                         break;
1711                 default:
1712                         break;
1713                 }
1714
1715                 break;
1716         }
1717
1718         nv_wr32(dev, 0x6101d4, 0x00000000);
1719         nv_wr32(dev, 0x6109d4, 0x00000000);
1720         nv_wr32(dev, 0x6101d0, 0x80000000);
1721 }
1722
1723 static void
1724 nvd0_display_unk4_handler(struct drm_device *dev, u32 crtc, u32 mask)
1725 {
1726         struct dcb_entry *dcb;
1727         int pclk, i;
1728
1729         pclk = nv_rd32(dev, 0x660450 + (crtc * 0x300)) / 1000;
1730
1731         for (i = 0; mask && i < 8; i++) {
1732                 u32 mcp = nv_rd32(dev, 0x660180 + (i * 0x20));
1733                 u32 cfg = nv_rd32(dev, 0x660184 + (i * 0x20));
1734                 if (!(mcp & (1 << crtc)))
1735                         continue;
1736
1737                 dcb = lookup_dcb(dev, i, mcp);
1738                 if (!dcb)
1739                         continue;
1740
1741                 nouveau_bios_run_display_table(dev, cfg, -pclk, dcb, crtc);
1742         }
1743
1744         nv_wr32(dev, 0x6101d4, 0x00000000);
1745         nv_wr32(dev, 0x6109d4, 0x00000000);
1746         nv_wr32(dev, 0x6101d0, 0x80000000);
1747 }
1748
1749 static void
1750 nvd0_display_bh(unsigned long data)
1751 {
1752         struct drm_device *dev = (struct drm_device *)data;
1753         struct nvd0_display *disp = nvd0_display(dev);
1754         u32 mask = 0, crtc = ~0;
1755         int i;
1756
1757         if (drm_debug & (DRM_UT_DRIVER | DRM_UT_KMS)) {
1758                 NV_INFO(dev, "PDISP: modeset req %d\n", disp->modeset);
1759                 NV_INFO(dev, " STAT: 0x%08x 0x%08x 0x%08x\n",
1760                          nv_rd32(dev, 0x6101d0),
1761                          nv_rd32(dev, 0x6101d4), nv_rd32(dev, 0x6109d4));
1762                 for (i = 0; i < 8; i++) {
1763                         NV_INFO(dev, " %s%d: 0x%08x 0x%08x\n",
1764                                 i < 4 ? "DAC" : "SOR", i,
1765                                 nv_rd32(dev, 0x640180 + (i * 0x20)),
1766                                 nv_rd32(dev, 0x660180 + (i * 0x20)));
1767                 }
1768         }
1769
1770         while (!mask && ++crtc < dev->mode_config.num_crtc)
1771                 mask = nv_rd32(dev, 0x6101d4 + (crtc * 0x800));
1772
1773         if (disp->modeset & 0x00000001)
1774                 nvd0_display_unk1_handler(dev, crtc, mask);
1775         if (disp->modeset & 0x00000002)
1776                 nvd0_display_unk2_handler(dev, crtc, mask);
1777         if (disp->modeset & 0x00000004)
1778                 nvd0_display_unk4_handler(dev, crtc, mask);
1779 }
1780
1781 static void
1782 nvd0_display_intr(struct drm_device *dev)
1783 {
1784         struct nvd0_display *disp = nvd0_display(dev);
1785         u32 intr = nv_rd32(dev, 0x610088);
1786         int i;
1787
1788         if (intr & 0x00000001) {
1789                 u32 stat = nv_rd32(dev, 0x61008c);
1790                 nv_wr32(dev, 0x61008c, stat);
1791                 intr &= ~0x00000001;
1792         }
1793
1794         if (intr & 0x00000002) {
1795                 u32 stat = nv_rd32(dev, 0x61009c);
1796                 int chid = ffs(stat) - 1;
1797                 if (chid >= 0) {
1798                         u32 mthd = nv_rd32(dev, 0x6101f0 + (chid * 12));
1799                         u32 data = nv_rd32(dev, 0x6101f4 + (chid * 12));
1800                         u32 unkn = nv_rd32(dev, 0x6101f8 + (chid * 12));
1801
1802                         NV_INFO(dev, "EvoCh: chid %d mthd 0x%04x data 0x%08x "
1803                                      "0x%08x 0x%08x\n",
1804                                 chid, (mthd & 0x0000ffc), data, mthd, unkn);
1805                         nv_wr32(dev, 0x61009c, (1 << chid));
1806                         nv_wr32(dev, 0x6101f0 + (chid * 12), 0x90000000);
1807                 }
1808
1809                 intr &= ~0x00000002;
1810         }
1811
1812         if (intr & 0x00100000) {
1813                 u32 stat = nv_rd32(dev, 0x6100ac);
1814
1815                 if (stat & 0x00000007) {
1816                         disp->modeset = stat;
1817                         tasklet_schedule(&disp->tasklet);
1818
1819                         nv_wr32(dev, 0x6100ac, (stat & 0x00000007));
1820                         stat &= ~0x00000007;
1821                 }
1822
1823                 if (stat) {
1824                         NV_INFO(dev, "PDISP: unknown intr24 0x%08x\n", stat);
1825                         nv_wr32(dev, 0x6100ac, stat);
1826                 }
1827
1828                 intr &= ~0x00100000;
1829         }
1830
1831         for (i = 0; i < dev->mode_config.num_crtc; i++) {
1832                 u32 mask = 0x01000000 << i;
1833                 if (intr & mask) {
1834                         u32 stat = nv_rd32(dev, 0x6100bc + (i * 0x800));
1835                         nv_wr32(dev, 0x6100bc + (i * 0x800), stat);
1836                         intr &= ~mask;
1837                 }
1838         }
1839
1840         if (intr)
1841                 NV_INFO(dev, "PDISP: unknown intr 0x%08x\n", intr);
1842 }
1843
1844 /******************************************************************************
1845  * Init
1846  *****************************************************************************/
1847 void
1848 nvd0_display_fini(struct drm_device *dev)
1849 {
1850         int i;
1851
1852         /* fini cursors + overlays + flips */
1853         for (i = 1; i >= 0; i--) {
1854                 evo_fini_pio(dev, EVO_CURS(i));
1855                 evo_fini_pio(dev, EVO_OIMM(i));
1856                 evo_fini_dma(dev, EVO_OVLY(i));
1857                 evo_fini_dma(dev, EVO_FLIP(i));
1858         }
1859
1860         /* fini master */
1861         evo_fini_dma(dev, EVO_MASTER);
1862 }
1863
1864 int
1865 nvd0_display_init(struct drm_device *dev)
1866 {
1867         struct nvd0_display *disp = nvd0_display(dev);
1868         int ret, i;
1869         u32 *push;
1870
1871         if (nv_rd32(dev, 0x6100ac) & 0x00000100) {
1872                 nv_wr32(dev, 0x6100ac, 0x00000100);
1873                 nv_mask(dev, 0x6194e8, 0x00000001, 0x00000000);
1874                 if (!nv_wait(dev, 0x6194e8, 0x00000002, 0x00000000)) {
1875                         NV_ERROR(dev, "PDISP: 0x6194e8 0x%08x\n",
1876                                  nv_rd32(dev, 0x6194e8));
1877                         return -EBUSY;
1878                 }
1879         }
1880
1881         /* nfi what these are exactly, i do know that SOR_MODE_CTRL won't
1882          * work at all unless you do the SOR part below.
1883          */
1884         for (i = 0; i < 3; i++) {
1885                 u32 dac = nv_rd32(dev, 0x61a000 + (i * 0x800));
1886                 nv_wr32(dev, 0x6101c0 + (i * 0x800), dac);
1887         }
1888
1889         for (i = 0; i < 4; i++) {
1890                 u32 sor = nv_rd32(dev, 0x61c000 + (i * 0x800));
1891                 nv_wr32(dev, 0x6301c4 + (i * 0x800), sor);
1892         }
1893
1894         for (i = 0; i < dev->mode_config.num_crtc; i++) {
1895                 u32 crtc0 = nv_rd32(dev, 0x616104 + (i * 0x800));
1896                 u32 crtc1 = nv_rd32(dev, 0x616108 + (i * 0x800));
1897                 u32 crtc2 = nv_rd32(dev, 0x61610c + (i * 0x800));
1898                 nv_wr32(dev, 0x6101b4 + (i * 0x800), crtc0);
1899                 nv_wr32(dev, 0x6101b8 + (i * 0x800), crtc1);
1900                 nv_wr32(dev, 0x6101bc + (i * 0x800), crtc2);
1901         }
1902
1903         /* point at our hash table / objects, enable interrupts */
1904         nv_wr32(dev, 0x610010, (disp->mem->vinst >> 8) | 9);
1905         nv_mask(dev, 0x6100b0, 0x00000307, 0x00000307);
1906
1907         /* init master */
1908         ret = evo_init_dma(dev, EVO_MASTER);
1909         if (ret)
1910                 goto error;
1911
1912         /* init flips + overlays + cursors */
1913         for (i = 0; i < dev->mode_config.num_crtc; i++) {
1914                 if ((ret = evo_init_dma(dev, EVO_FLIP(i))) ||
1915                     (ret = evo_init_dma(dev, EVO_OVLY(i))) ||
1916                     (ret = evo_init_pio(dev, EVO_OIMM(i))) ||
1917                     (ret = evo_init_pio(dev, EVO_CURS(i))))
1918                         goto error;
1919         }
1920
1921         push = evo_wait(dev, EVO_MASTER, 32);
1922         if (!push) {
1923                 ret = -EBUSY;
1924                 goto error;
1925         }
1926         evo_mthd(push, 0x0088, 1);
1927         evo_data(push, NvEvoSync);
1928         evo_mthd(push, 0x0084, 1);
1929         evo_data(push, 0x00000000);
1930         evo_mthd(push, 0x0084, 1);
1931         evo_data(push, 0x80000000);
1932         evo_mthd(push, 0x008c, 1);
1933         evo_data(push, 0x00000000);
1934         evo_kick(push, dev, EVO_MASTER);
1935
1936 error:
1937         if (ret)
1938                 nvd0_display_fini(dev);
1939         return ret;
1940 }
1941
1942 void
1943 nvd0_display_destroy(struct drm_device *dev)
1944 {
1945         struct drm_nouveau_private *dev_priv = dev->dev_private;
1946         struct nvd0_display *disp = nvd0_display(dev);
1947         struct pci_dev *pdev = dev->pdev;
1948         int i;
1949
1950         for (i = 0; i < EVO_DMA_NR; i++) {
1951                 struct evo *evo = &disp->evo[i];
1952                 pci_free_consistent(pdev, PAGE_SIZE, evo->ptr, evo->handle);
1953         }
1954
1955         nouveau_gpuobj_ref(NULL, &disp->mem);
1956         nouveau_bo_unmap(disp->sync);
1957         nouveau_bo_ref(NULL, &disp->sync);
1958         nouveau_irq_unregister(dev, 26);
1959
1960         dev_priv->engine.display.priv = NULL;
1961         kfree(disp);
1962 }
1963
1964 int
1965 nvd0_display_create(struct drm_device *dev)
1966 {
1967         struct drm_nouveau_private *dev_priv = dev->dev_private;
1968         struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
1969         struct dcb_table *dcb = &dev_priv->vbios.dcb;
1970         struct drm_connector *connector, *tmp;
1971         struct pci_dev *pdev = dev->pdev;
1972         struct nvd0_display *disp;
1973         struct dcb_entry *dcbe;
1974         int crtcs, ret, i;
1975
1976         disp = kzalloc(sizeof(*disp), GFP_KERNEL);
1977         if (!disp)
1978                 return -ENOMEM;
1979         dev_priv->engine.display.priv = disp;
1980
1981         /* create crtc objects to represent the hw heads */
1982         crtcs = nv_rd32(dev, 0x022448);
1983         for (i = 0; i < crtcs; i++) {
1984                 ret = nvd0_crtc_create(dev, i);
1985                 if (ret)
1986                         goto out;
1987         }
1988
1989         /* create encoder/connector objects based on VBIOS DCB table */
1990         for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
1991                 connector = nouveau_connector_create(dev, dcbe->connector);
1992                 if (IS_ERR(connector))
1993                         continue;
1994
1995                 if (dcbe->location != DCB_LOC_ON_CHIP) {
1996                         NV_WARN(dev, "skipping off-chip encoder %d/%d\n",
1997                                 dcbe->type, ffs(dcbe->or) - 1);
1998                         continue;
1999                 }
2000
2001                 switch (dcbe->type) {
2002                 case OUTPUT_TMDS:
2003                 case OUTPUT_LVDS:
2004                 case OUTPUT_DP:
2005                         nvd0_sor_create(connector, dcbe);
2006                         break;
2007                 case OUTPUT_ANALOG:
2008                         nvd0_dac_create(connector, dcbe);
2009                         break;
2010                 default:
2011                         NV_WARN(dev, "skipping unsupported encoder %d/%d\n",
2012                                 dcbe->type, ffs(dcbe->or) - 1);
2013                         continue;
2014                 }
2015         }
2016
2017         /* cull any connectors we created that don't have an encoder */
2018         list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2019                 if (connector->encoder_ids[0])
2020                         continue;
2021
2022                 NV_WARN(dev, "%s has no encoders, removing\n",
2023                         drm_get_connector_name(connector));
2024                 connector->funcs->destroy(connector);
2025         }
2026
2027         /* setup interrupt handling */
2028         tasklet_init(&disp->tasklet, nvd0_display_bh, (unsigned long)dev);
2029         nouveau_irq_register(dev, 26, nvd0_display_intr);
2030
2031         /* small shared memory area we use for notifiers and semaphores */
2032         ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2033                              0, 0x0000, &disp->sync);
2034         if (!ret) {
2035                 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM);
2036                 if (!ret)
2037                         ret = nouveau_bo_map(disp->sync);
2038                 if (ret)
2039                         nouveau_bo_ref(NULL, &disp->sync);
2040         }
2041
2042         if (ret)
2043                 goto out;
2044
2045         /* hash table and dma objects for the memory areas we care about */
2046         ret = nouveau_gpuobj_new(dev, NULL, 0x4000, 0x10000,
2047                                  NVOBJ_FLAG_ZERO_ALLOC, &disp->mem);
2048         if (ret)
2049                 goto out;
2050
2051         /* create evo dma channels */
2052         for (i = 0; i < EVO_DMA_NR; i++) {
2053                 struct evo *evo = &disp->evo[i];
2054                 u64 offset = disp->sync->bo.offset;
2055                 u32 dmao = 0x1000 + (i * 0x100);
2056                 u32 hash = 0x0000 + (i * 0x040);
2057
2058                 evo->idx = i;
2059                 evo->sem.offset = EVO_SYNC(evo->idx, 0x00);
2060                 evo->ptr = pci_alloc_consistent(pdev, PAGE_SIZE, &evo->handle);
2061                 if (!evo->ptr) {
2062                         ret = -ENOMEM;
2063                         goto out;
2064                 }
2065
2066                 nv_wo32(disp->mem, dmao + 0x00, 0x00000049);
2067                 nv_wo32(disp->mem, dmao + 0x04, (offset + 0x0000) >> 8);
2068                 nv_wo32(disp->mem, dmao + 0x08, (offset + 0x0fff) >> 8);
2069                 nv_wo32(disp->mem, dmao + 0x0c, 0x00000000);
2070                 nv_wo32(disp->mem, dmao + 0x10, 0x00000000);
2071                 nv_wo32(disp->mem, dmao + 0x14, 0x00000000);
2072                 nv_wo32(disp->mem, hash + 0x00, NvEvoSync);
2073                 nv_wo32(disp->mem, hash + 0x04, 0x00000001 | (i << 27) |
2074                                                 ((dmao + 0x00) << 9));
2075
2076                 nv_wo32(disp->mem, dmao + 0x20, 0x00000049);
2077                 nv_wo32(disp->mem, dmao + 0x24, 0x00000000);
2078                 nv_wo32(disp->mem, dmao + 0x28, (dev_priv->vram_size - 1) >> 8);
2079                 nv_wo32(disp->mem, dmao + 0x2c, 0x00000000);
2080                 nv_wo32(disp->mem, dmao + 0x30, 0x00000000);
2081                 nv_wo32(disp->mem, dmao + 0x34, 0x00000000);
2082                 nv_wo32(disp->mem, hash + 0x08, NvEvoVRAM);
2083                 nv_wo32(disp->mem, hash + 0x0c, 0x00000001 | (i << 27) |
2084                                                 ((dmao + 0x20) << 9));
2085
2086                 nv_wo32(disp->mem, dmao + 0x40, 0x00000009);
2087                 nv_wo32(disp->mem, dmao + 0x44, 0x00000000);
2088                 nv_wo32(disp->mem, dmao + 0x48, (dev_priv->vram_size - 1) >> 8);
2089                 nv_wo32(disp->mem, dmao + 0x4c, 0x00000000);
2090                 nv_wo32(disp->mem, dmao + 0x50, 0x00000000);
2091                 nv_wo32(disp->mem, dmao + 0x54, 0x00000000);
2092                 nv_wo32(disp->mem, hash + 0x10, NvEvoVRAM_LP);
2093                 nv_wo32(disp->mem, hash + 0x14, 0x00000001 | (i << 27) |
2094                                                 ((dmao + 0x40) << 9));
2095
2096                 nv_wo32(disp->mem, dmao + 0x60, 0x0fe00009);
2097                 nv_wo32(disp->mem, dmao + 0x64, 0x00000000);
2098                 nv_wo32(disp->mem, dmao + 0x68, (dev_priv->vram_size - 1) >> 8);
2099                 nv_wo32(disp->mem, dmao + 0x6c, 0x00000000);
2100                 nv_wo32(disp->mem, dmao + 0x70, 0x00000000);
2101                 nv_wo32(disp->mem, dmao + 0x74, 0x00000000);
2102                 nv_wo32(disp->mem, hash + 0x18, NvEvoFB32);
2103                 nv_wo32(disp->mem, hash + 0x1c, 0x00000001 | (i << 27) |
2104                                                 ((dmao + 0x60) << 9));
2105         }
2106
2107         pinstmem->flush(dev);
2108
2109 out:
2110         if (ret)
2111                 nvd0_display_destroy(dev);
2112         return ret;
2113 }