drivers/gpu/drm/nouveau/nv84_fence.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include "nouveau_drm.h"
  26 #include "nouveau_dma.h"
  27 #include "nouveau_fence.h"
  28
  29 #include "nv50_display.h"
  30
  31 u64
  32 nv84_fence_crtc(struct nouveau_channel *chan, int crtc)
  33 {
  34         struct nv84_fence_chan *fctx = chan->fence;
  35         return fctx->dispc_vma[crtc].offset;
  36 }
  37
  38 static int
  39 nv84_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
  40 {
  41         int ret = RING_SPACE(chan, 8);
  42         if (ret == 0) {
  43                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
  44                 OUT_RING  (chan, chan->vram.handle);
  45                 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 5);
  46                 OUT_RING  (chan, upper_32_bits(virtual));
  47                 OUT_RING  (chan, lower_32_bits(virtual));
  48                 OUT_RING  (chan, sequence);
  49                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
  50                 OUT_RING  (chan, 0x00000000);
  51                 FIRE_RING (chan);
  52         }
  53         return ret;
  54 }
  55
  56 static int
  57 nv84_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
  58 {
  59         int ret = RING_SPACE(chan, 7);
  60         if (ret == 0) {
  61                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
  62                 OUT_RING  (chan, chan->vram.handle);
  63                 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
  64                 OUT_RING  (chan, upper_32_bits(virtual));
  65                 OUT_RING  (chan, lower_32_bits(virtual));
  66                 OUT_RING  (chan, sequence);
  67                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL);
  68                 FIRE_RING (chan);
  69         }
  70         return ret;
  71 }
  72
  73 static int
  74 nv84_fence_emit(struct nouveau_fence *fence)
  75 {
  76         struct nouveau_channel *chan = fence->channel;
  77         struct nv84_fence_chan *fctx = chan->fence;
  78         u64 addr = chan->chid * 16;
  79
  80         if (fence->sysmem)
  81                 addr += fctx->vma_gart.offset;
  82         else
  83                 addr += fctx->vma.offset;
  84
  85         return fctx->base.emit32(chan, addr, fence->sequence);
  86 }
  87
  88 static int
  89 nv84_fence_sync(struct nouveau_fence *fence,
  90                 struct nouveau_channel *prev, struct nouveau_channel *chan)
  91 {
  92         struct nv84_fence_chan *fctx = chan->fence;
  93         u64 addr = prev->chid * 16;
  94
  95         if (fence->sysmem)
  96                 addr += fctx->vma_gart.offset;
  97         else
  98                 addr += fctx->vma.offset;
  99
 100         return fctx->base.sync32(chan, addr, fence->sequence);
 101 }
 102
 103 static u32
 104 nv84_fence_read(struct nouveau_channel *chan)
 105 {
 106         struct nv84_fence_priv *priv = chan->drm->fence;
 107         return nouveau_bo_rd32(priv->bo, chan->chid * 16/4);
 108 }
 109
 110 static void
 111 nv84_fence_context_del(struct nouveau_channel *chan)
 112 {
 113         struct drm_device *dev = chan->drm->dev;
 114         struct nv84_fence_priv *priv = chan->drm->fence;
 115         struct nv84_fence_chan *fctx = chan->fence;
 116         int i;
 117
 118         for (i = 0; i < dev->mode_config.num_crtc; i++) {
 119                 struct nouveau_bo *bo = nv50_display_crtc_sema(dev, i);
 120                 nouveau_bo_vma_del(bo, &fctx->dispc_vma[i]);
 121         }
 122
 123         nouveau_bo_vma_del(priv->bo, &fctx->vma_gart);
 124         nouveau_bo_vma_del(priv->bo, &fctx->vma);
 125         nouveau_fence_context_del(&fctx->base);
 126         chan->fence = NULL;
 127         kfree(fctx);
 128 }
 129
 130 int
 131 nv84_fence_context_new(struct nouveau_channel *chan)
 132 {
 133         struct nouveau_cli *cli = (void *)nvif_client(&chan->device->base);
 134         struct nv84_fence_priv *priv = chan->drm->fence;
 135         struct nv84_fence_chan *fctx;
 136         int ret, i;
 137
 138         fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
 139         if (!fctx)
 140                 return -ENOMEM;
 141
 142         nouveau_fence_context_new(&fctx->base);
 143         fctx->base.emit = nv84_fence_emit;
 144         fctx->base.sync = nv84_fence_sync;
 145         fctx->base.read = nv84_fence_read;
 146         fctx->base.emit32 = nv84_fence_emit32;
 147         fctx->base.sync32 = nv84_fence_sync32;
 148
 149         ret = nouveau_bo_vma_add(priv->bo, cli->vm, &fctx->vma);
 150         if (ret == 0) {
 151                 ret = nouveau_bo_vma_add(priv->bo_gart, cli->vm,
 152                                         &fctx->vma_gart);
 153         }
 154
 155         /* map display semaphore buffers into channel's vm */
 156         for (i = 0; !ret && i < chan->drm->dev->mode_config.num_crtc; i++) {
 157                 struct nouveau_bo *bo = nv50_display_crtc_sema(chan->drm->dev, i);
 158                 ret = nouveau_bo_vma_add(bo, cli->vm, &fctx->dispc_vma[i]);
 159         }
 160
 161         nouveau_bo_wr32(priv->bo, chan->chid * 16/4, 0x00000000);
 162
 163         if (ret)
 164                 nv84_fence_context_del(chan);
 165         return ret;
 166 }
 167
 168 static bool
 169 nv84_fence_suspend(struct nouveau_drm *drm)
 170 {
 171         struct nouveau_fifo *pfifo = nvkm_fifo(&drm->device);
 172         struct nv84_fence_priv *priv = drm->fence;
 173         int i;
 174
 175         priv->suspend = vmalloc((pfifo->max + 1) * sizeof(u32));
 176         if (priv->suspend) {
 177                 for (i = 0; i <= pfifo->max; i++)
 178                         priv->suspend[i] = nouveau_bo_rd32(priv->bo, i*4);
 179         }
 180
 181         return priv->suspend != NULL;
 182 }
 183
 184 static void
 185 nv84_fence_resume(struct nouveau_drm *drm)
 186 {
 187         struct nouveau_fifo *pfifo = nvkm_fifo(&drm->device);
 188         struct nv84_fence_priv *priv = drm->fence;
 189         int i;
 190
 191         if (priv->suspend) {
 192                 for (i = 0; i <= pfifo->max; i++)
 193                         nouveau_bo_wr32(priv->bo, i*4, priv->suspend[i]);
 194                 vfree(priv->suspend);
 195                 priv->suspend = NULL;
 196         }
 197 }
 198
 199 static void
 200 nv84_fence_destroy(struct nouveau_drm *drm)
 201 {
 202         struct nv84_fence_priv *priv = drm->fence;
 203         nouveau_bo_unmap(priv->bo_gart);
 204         if (priv->bo_gart)
 205                 nouveau_bo_unpin(priv->bo_gart);
 206         nouveau_bo_ref(NULL, &priv->bo_gart);
 207         nouveau_bo_unmap(priv->bo);
 208         if (priv->bo)
 209                 nouveau_bo_unpin(priv->bo);
 210         nouveau_bo_ref(NULL, &priv->bo);
 211         drm->fence = NULL;
 212         kfree(priv);
 213 }
 214
 215 int
 216 nv84_fence_create(struct nouveau_drm *drm)
 217 {
 218         struct nouveau_fifo *pfifo = nvkm_fifo(&drm->device);
 219         struct nv84_fence_priv *priv;
 220         int ret;
 221
 222         priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
 223         if (!priv)
 224                 return -ENOMEM;
 225
 226         priv->base.dtor = nv84_fence_destroy;
 227         priv->base.suspend = nv84_fence_suspend;
 228         priv->base.resume = nv84_fence_resume;
 229         priv->base.context_new = nv84_fence_context_new;
 230         priv->base.context_del = nv84_fence_context_del;
 231
 232         init_waitqueue_head(&priv->base.waiting);
 233         priv->base.uevent = true;
 234
 235         ret = nouveau_bo_new(drm->dev, 16 * (pfifo->max + 1), 0,
 236                              TTM_PL_FLAG_VRAM, 0, 0, NULL, &priv->bo);
 237         if (ret == 0) {
 238                 ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM);
 239                 if (ret == 0) {
 240                         ret = nouveau_bo_map(priv->bo);
 241                         if (ret)
 242                                 nouveau_bo_unpin(priv->bo);
 243                 }
 244                 if (ret)
 245                         nouveau_bo_ref(NULL, &priv->bo);
 246         }
 247
 248         if (ret == 0)
 249                 ret = nouveau_bo_new(drm->dev, 16 * (pfifo->max + 1), 0,
 250                                      TTM_PL_FLAG_TT, 0, 0, NULL,
 251                                      &priv->bo_gart);
 252         if (ret == 0) {
 253                 ret = nouveau_bo_pin(priv->bo_gart, TTM_PL_FLAG_TT);
 254                 if (ret == 0) {
 255                         ret = nouveau_bo_map(priv->bo_gart);
 256                         if (ret)
 257                                 nouveau_bo_unpin(priv->bo_gart);
 258                 }
 259                 if (ret)
 260                         nouveau_bo_ref(NULL, &priv->bo_gart);
 261         }
 262
 263         if (ret)
 264                 nv84_fence_destroy(drm);
 265         return ret;
 266 }