drivers/gpu/drm/nouveau/nv50_graph.c

   1 /*
   2  * Copyright (C) 2007 Ben Skeggs.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "nouveau_drv.h"
  30 #include "nouveau_fifo.h"
  31 #include "nouveau_ramht.h"
  32 #include "nouveau_dma.h"
  33 #include "nouveau_vm.h"
  34 #include "nv50_evo.h"
  35
  36 struct nv50_graph_engine {
  37         struct nouveau_exec_engine base;
  38         u32 ctxprog[512];
  39         u32 ctxprog_size;
  40         u32 grctx_size;
  41 };
  42
  43 static int
  44 nv50_graph_init(struct drm_device *dev, int engine)
  45 {
  46         struct drm_nouveau_private *dev_priv = dev->dev_private;
  47         struct nv50_graph_engine *pgraph = nv_engine(dev, engine);
  48         u32 units = nv_rd32(dev, 0x001540);
  49         int i;
  50
  51         NV_DEBUG(dev, "\n");
  52
  53         /* master reset */
  54         nv_mask(dev, 0x000200, 0x00201000, 0x00000000);
  55         nv_mask(dev, 0x000200, 0x00201000, 0x00201000);
  56         nv_wr32(dev, 0x40008c, 0x00000004); /* HW_CTX_SWITCH_ENABLED */
  57
  58         /* reset/enable traps and interrupts */
  59         nv_wr32(dev, 0x400804, 0xc0000000);
  60         nv_wr32(dev, 0x406800, 0xc0000000);
  61         nv_wr32(dev, 0x400c04, 0xc0000000);
  62         nv_wr32(dev, 0x401800, 0xc0000000);
  63         nv_wr32(dev, 0x405018, 0xc0000000);
  64         nv_wr32(dev, 0x402000, 0xc0000000);
  65         for (i = 0; i < 16; i++) {
  66                 if (!(units & (1 << i)))
  67                         continue;
  68
  69                 if (dev_priv->chipset < 0xa0) {
  70                         nv_wr32(dev, 0x408900 + (i << 12), 0xc0000000);
  71                         nv_wr32(dev, 0x408e08 + (i << 12), 0xc0000000);
  72                         nv_wr32(dev, 0x408314 + (i << 12), 0xc0000000);
  73                 } else {
  74                         nv_wr32(dev, 0x408600 + (i << 11), 0xc0000000);
  75                         nv_wr32(dev, 0x408708 + (i << 11), 0xc0000000);
  76                         nv_wr32(dev, 0x40831c + (i << 11), 0xc0000000);
  77                 }
  78         }
  79
  80         nv_wr32(dev, 0x400108, 0xffffffff);
  81         nv_wr32(dev, 0x400138, 0xffffffff);
  82         nv_wr32(dev, 0x400100, 0xffffffff);
  83         nv_wr32(dev, 0x40013c, 0xffffffff);
  84         nv_wr32(dev, 0x400500, 0x00010001);
  85
  86         /* upload context program, initialise ctxctl defaults */
  87         nv_wr32(dev, 0x400324, 0x00000000);
  88         for (i = 0; i < pgraph->ctxprog_size; i++)
  89                 nv_wr32(dev, 0x400328, pgraph->ctxprog[i]);
  90         nv_wr32(dev, 0x400824, 0x00000000);
  91         nv_wr32(dev, 0x400828, 0x00000000);
  92         nv_wr32(dev, 0x40082c, 0x00000000);
  93         nv_wr32(dev, 0x400830, 0x00000000);
  94         nv_wr32(dev, 0x400724, 0x00000000);
  95         nv_wr32(dev, 0x40032c, 0x00000000);
  96         nv_wr32(dev, 0x400320, 4);      /* CTXCTL_CMD = NEWCTXDMA */
  97
  98         /* some unknown zcull magic */
  99         switch (dev_priv->chipset & 0xf0) {
 100         case 0x50:
 101         case 0x80:
 102         case 0x90:
 103                 nv_wr32(dev, 0x402ca8, 0x00000800);
 104                 break;
 105         case 0xa0:
 106         default:
 107                 nv_wr32(dev, 0x402cc0, 0x00000000);
 108                 if (dev_priv->chipset == 0xa0 ||
 109                     dev_priv->chipset == 0xaa ||
 110                     dev_priv->chipset == 0xac) {
 111                         nv_wr32(dev, 0x402ca8, 0x00000802);
 112                 } else {
 113                         nv_wr32(dev, 0x402cc0, 0x00000000);
 114                         nv_wr32(dev, 0x402ca8, 0x00000002);
 115                 }
 116
 117                 break;
 118         }
 119
 120         /* zero out zcull regions */
 121         for (i = 0; i < 8; i++) {
 122                 nv_wr32(dev, 0x402c20 + (i * 8), 0x00000000);
 123                 nv_wr32(dev, 0x402c24 + (i * 8), 0x00000000);
 124                 nv_wr32(dev, 0x402c28 + (i * 8), 0x00000000);
 125                 nv_wr32(dev, 0x402c2c + (i * 8), 0x00000000);
 126         }
 127
 128         return 0;
 129 }
 130
 131 static int
 132 nv50_graph_fini(struct drm_device *dev, int engine, bool suspend)
 133 {
 134         nv_wr32(dev, 0x40013c, 0x00000000);
 135         return 0;
 136 }
 137
 138 static int
 139 nv50_graph_context_new(struct nouveau_channel *chan, int engine)
 140 {
 141         struct drm_device *dev = chan->dev;
 142         struct drm_nouveau_private *dev_priv = dev->dev_private;
 143         struct nouveau_gpuobj *ramin = chan->ramin;
 144         struct nouveau_gpuobj *grctx = NULL;
 145         struct nv50_graph_engine *pgraph = nv_engine(dev, engine);
 146         int hdr, ret;
 147
 148         NV_DEBUG(dev, "ch%d\n", chan->id);
 149
 150         ret = nouveau_gpuobj_new(dev, NULL, pgraph->grctx_size, 0,
 151                                  NVOBJ_FLAG_ZERO_ALLOC |
 152                                  NVOBJ_FLAG_ZERO_FREE, &grctx);
 153         if (ret)
 154                 return ret;
 155
 156         hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20;
 157         nv_wo32(ramin, hdr + 0x00, 0x00190002);
 158         nv_wo32(ramin, hdr + 0x04, grctx->vinst + grctx->size - 1);
 159         nv_wo32(ramin, hdr + 0x08, grctx->vinst);
 160         nv_wo32(ramin, hdr + 0x0c, 0);
 161         nv_wo32(ramin, hdr + 0x10, 0);
 162         nv_wo32(ramin, hdr + 0x14, 0x00010000);
 163
 164         nv50_grctx_fill(dev, grctx);
 165         nv_wo32(grctx, 0x00000, chan->ramin->vinst >> 12);
 166
 167         dev_priv->engine.instmem.flush(dev);
 168
 169         atomic_inc(&chan->vm->engref[NVOBJ_ENGINE_GR]);
 170         chan->engctx[NVOBJ_ENGINE_GR] = grctx;
 171         return 0;
 172 }
 173
 174 static void
 175 nv50_graph_context_del(struct nouveau_channel *chan, int engine)
 176 {
 177         struct nouveau_gpuobj *grctx = chan->engctx[engine];
 178         struct drm_device *dev = chan->dev;
 179         struct drm_nouveau_private *dev_priv = dev->dev_private;
 180         int i, hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20;
 181
 182         for (i = hdr; i < hdr + 24; i += 4)
 183                 nv_wo32(chan->ramin, i, 0);
 184         dev_priv->engine.instmem.flush(dev);
 185
 186         atomic_dec(&chan->vm->engref[engine]);
 187         nouveau_gpuobj_ref(NULL, &grctx);
 188         chan->engctx[engine] = NULL;
 189 }
 190
 191 static int
 192 nv50_graph_object_new(struct nouveau_channel *chan, int engine,
 193                       u32 handle, u16 class)
 194 {
 195         struct drm_device *dev = chan->dev;
 196         struct drm_nouveau_private *dev_priv = dev->dev_private;
 197         struct nouveau_gpuobj *obj = NULL;
 198         int ret;
 199
 200         ret = nouveau_gpuobj_new(dev, chan, 16, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
 201         if (ret)
 202                 return ret;
 203         obj->engine = 1;
 204         obj->class  = class;
 205
 206         nv_wo32(obj, 0x00, class);
 207         nv_wo32(obj, 0x04, 0x00000000);
 208         nv_wo32(obj, 0x08, 0x00000000);
 209         nv_wo32(obj, 0x0c, 0x00000000);
 210         dev_priv->engine.instmem.flush(dev);
 211
 212         ret = nouveau_ramht_insert(chan, handle, obj);
 213         nouveau_gpuobj_ref(NULL, &obj);
 214         return ret;
 215 }
 216
 217 static void
 218 nv50_graph_tlb_flush(struct drm_device *dev, int engine)
 219 {
 220         nv50_vm_flush_engine(dev, 0);
 221 }
 222
 223 static void
 224 nv84_graph_tlb_flush(struct drm_device *dev, int engine)
 225 {
 226         struct drm_nouveau_private *dev_priv = dev->dev_private;
 227         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
 228         bool idle, timeout = false;
 229         unsigned long flags;
 230         u64 start;
 231         u32 tmp;
 232
 233         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 234         nv_mask(dev, 0x400500, 0x00000001, 0x00000000);
 235
 236         start = ptimer->read(dev);
 237         do {
 238                 idle = true;
 239
 240                 for (tmp = nv_rd32(dev, 0x400380); tmp && idle; tmp >>= 3) {
 241                         if ((tmp & 7) == 1)
 242                                 idle = false;
 243                 }
 244
 245                 for (tmp = nv_rd32(dev, 0x400384); tmp && idle; tmp >>= 3) {
 246                         if ((tmp & 7) == 1)
 247                                 idle = false;
 248                 }
 249
 250                 for (tmp = nv_rd32(dev, 0x400388); tmp && idle; tmp >>= 3) {
 251                         if ((tmp & 7) == 1)
 252                                 idle = false;
 253                 }
 254         } while (!idle && !(timeout = ptimer->read(dev) - start > 2000000000));
 255
 256         if (timeout) {
 257                 NV_ERROR(dev, "PGRAPH TLB flush idle timeout fail: "
 258                               "0x%08x 0x%08x 0x%08x 0x%08x\n",
 259                          nv_rd32(dev, 0x400700), nv_rd32(dev, 0x400380),
 260                          nv_rd32(dev, 0x400384), nv_rd32(dev, 0x400388));
 261         }
 262
 263         nv50_vm_flush_engine(dev, 0);
 264
 265         nv_mask(dev, 0x400500, 0x00000001, 0x00000001);
 266         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 267 }
 268
 269 static struct nouveau_enum nv50_mp_exec_error_names[] = {
 270         { 3, "STACK_UNDERFLOW", NULL },
 271         { 4, "QUADON_ACTIVE", NULL },
 272         { 8, "TIMEOUT", NULL },
 273         { 0x10, "INVALID_OPCODE", NULL },
 274         { 0x40, "BREAKPOINT", NULL },
 275         {}
 276 };
 277
 278 static struct nouveau_bitfield nv50_graph_trap_m2mf[] = {
 279         { 0x00000001, "NOTIFY" },
 280         { 0x00000002, "IN" },
 281         { 0x00000004, "OUT" },
 282         {}
 283 };
 284
 285 static struct nouveau_bitfield nv50_graph_trap_vfetch[] = {
 286         { 0x00000001, "FAULT" },
 287         {}
 288 };
 289
 290 static struct nouveau_bitfield nv50_graph_trap_strmout[] = {
 291         { 0x00000001, "FAULT" },
 292         {}
 293 };
 294
 295 static struct nouveau_bitfield nv50_graph_trap_ccache[] = {
 296         { 0x00000001, "FAULT" },
 297         {}
 298 };
 299
 300 /* There must be a *lot* of these. Will take some time to gather them up. */
 301 struct nouveau_enum nv50_data_error_names[] = {
 302         { 0x00000003, "INVALID_QUERY_OR_TEXTURE", NULL },
 303         { 0x00000004, "INVALID_VALUE", NULL },
 304         { 0x00000005, "INVALID_ENUM", NULL },
 305         { 0x00000008, "INVALID_OBJECT", NULL },
 306         { 0x00000009, "READ_ONLY_OBJECT", NULL },
 307         { 0x0000000a, "SUPERVISOR_OBJECT", NULL },
 308         { 0x0000000b, "INVALID_ADDRESS_ALIGNMENT", NULL },
 309         { 0x0000000c, "INVALID_BITFIELD", NULL },
 310         { 0x0000000d, "BEGIN_END_ACTIVE", NULL },
 311         { 0x0000000e, "SEMANTIC_COLOR_BACK_OVER_LIMIT", NULL },
 312         { 0x0000000f, "VIEWPORT_ID_NEEDS_GP", NULL },
 313         { 0x00000010, "RT_DOUBLE_BIND", NULL },
 314         { 0x00000011, "RT_TYPES_MISMATCH", NULL },
 315         { 0x00000012, "RT_LINEAR_WITH_ZETA", NULL },
 316         { 0x00000015, "FP_TOO_FEW_REGS", NULL },
 317         { 0x00000016, "ZETA_FORMAT_CSAA_MISMATCH", NULL },
 318         { 0x00000017, "RT_LINEAR_WITH_MSAA", NULL },
 319         { 0x00000018, "FP_INTERPOLANT_START_OVER_LIMIT", NULL },
 320         { 0x00000019, "SEMANTIC_LAYER_OVER_LIMIT", NULL },
 321         { 0x0000001a, "RT_INVALID_ALIGNMENT", NULL },
 322         { 0x0000001b, "SAMPLER_OVER_LIMIT", NULL },
 323         { 0x0000001c, "TEXTURE_OVER_LIMIT", NULL },
 324         { 0x0000001e, "GP_TOO_MANY_OUTPUTS", NULL },
 325         { 0x0000001f, "RT_BPP128_WITH_MS8", NULL },
 326         { 0x00000021, "Z_OUT_OF_BOUNDS", NULL },
 327         { 0x00000023, "XY_OUT_OF_BOUNDS", NULL },
 328         { 0x00000024, "VP_ZERO_INPUTS", NULL },
 329         { 0x00000027, "CP_MORE_PARAMS_THAN_SHARED", NULL },
 330         { 0x00000028, "CP_NO_REG_SPACE_STRIPED", NULL },
 331         { 0x00000029, "CP_NO_REG_SPACE_PACKED", NULL },
 332         { 0x0000002a, "CP_NOT_ENOUGH_WARPS", NULL },
 333         { 0x0000002b, "CP_BLOCK_SIZE_MISMATCH", NULL },
 334         { 0x0000002c, "CP_NOT_ENOUGH_LOCAL_WARPS", NULL },
 335         { 0x0000002d, "CP_NOT_ENOUGH_STACK_WARPS", NULL },
 336         { 0x0000002e, "CP_NO_BLOCKDIM_LATCH", NULL },
 337         { 0x00000031, "ENG2D_FORMAT_MISMATCH", NULL },
 338         { 0x0000003f, "PRIMITIVE_ID_NEEDS_GP", NULL },
 339         { 0x00000044, "SEMANTIC_VIEWPORT_OVER_LIMIT", NULL },
 340         { 0x00000045, "SEMANTIC_COLOR_FRONT_OVER_LIMIT", NULL },
 341         { 0x00000046, "LAYER_ID_NEEDS_GP", NULL },
 342         { 0x00000047, "SEMANTIC_CLIP_OVER_LIMIT", NULL },
 343         { 0x00000048, "SEMANTIC_PTSZ_OVER_LIMIT", NULL },
 344         {}
 345 };
 346
 347 static struct nouveau_bitfield nv50_graph_intr[] = {
 348         { 0x00000001, "NOTIFY" },
 349         { 0x00000002, "COMPUTE_QUERY" },
 350         { 0x00000010, "ILLEGAL_MTHD" },
 351         { 0x00000020, "ILLEGAL_CLASS" },
 352         { 0x00000040, "DOUBLE_NOTIFY" },
 353         { 0x00001000, "CONTEXT_SWITCH" },
 354         { 0x00010000, "BUFFER_NOTIFY" },
 355         { 0x00100000, "DATA_ERROR" },
 356         { 0x00200000, "TRAP" },
 357         { 0x01000000, "SINGLE_STEP" },
 358         {}
 359 };
 360
 361 static void
 362 nv50_pgraph_mp_trap(struct drm_device *dev, int tpid, int display)
 363 {
 364         struct drm_nouveau_private *dev_priv = dev->dev_private;
 365         uint32_t units = nv_rd32(dev, 0x1540);
 366         uint32_t addr, mp10, status, pc, oplow, ophigh;
 367         int i;
 368         int mps = 0;
 369         for (i = 0; i < 4; i++) {
 370                 if (!(units & 1 << (i+24)))
 371                         continue;
 372                 if (dev_priv->chipset < 0xa0)
 373                         addr = 0x408200 + (tpid << 12) + (i << 7);
 374                 else
 375                         addr = 0x408100 + (tpid << 11) + (i << 7);
 376                 mp10 = nv_rd32(dev, addr + 0x10);
 377                 status = nv_rd32(dev, addr + 0x14);
 378                 if (!status)
 379                         continue;
 380                 if (display) {
 381                         nv_rd32(dev, addr + 0x20);
 382                         pc = nv_rd32(dev, addr + 0x24);
 383                         oplow = nv_rd32(dev, addr + 0x70);
 384                         ophigh = nv_rd32(dev, addr + 0x74);
 385                         NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - "
 386                                         "TP %d MP %d: ", tpid, i);
 387                         nouveau_enum_print(nv50_mp_exec_error_names, status);
 388                         printk(" at %06x warp %d, opcode %08x %08x\n",
 389                                         pc&0xffffff, pc >> 24,
 390                                         oplow, ophigh);
 391                 }
 392                 nv_wr32(dev, addr + 0x10, mp10);
 393                 nv_wr32(dev, addr + 0x14, 0);
 394                 mps++;
 395         }
 396         if (!mps && display)
 397                 NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - TP %d: "
 398                                 "No MPs claiming errors?\n", tpid);
 399 }
 400
 401 static void
 402 nv50_pgraph_tp_trap(struct drm_device *dev, int type, uint32_t ustatus_old,
 403                 uint32_t ustatus_new, int display, const char *name)
 404 {
 405         struct drm_nouveau_private *dev_priv = dev->dev_private;
 406         int tps = 0;
 407         uint32_t units = nv_rd32(dev, 0x1540);
 408         int i, r;
 409         uint32_t ustatus_addr, ustatus;
 410         for (i = 0; i < 16; i++) {
 411                 if (!(units & (1 << i)))
 412                         continue;
 413                 if (dev_priv->chipset < 0xa0)
 414                         ustatus_addr = ustatus_old + (i << 12);
 415                 else
 416                         ustatus_addr = ustatus_new + (i << 11);
 417                 ustatus = nv_rd32(dev, ustatus_addr) & 0x7fffffff;
 418                 if (!ustatus)
 419                         continue;
 420                 tps++;
 421                 switch (type) {
 422                 case 6: /* texture error... unknown for now */
 423                         if (display) {
 424                                 NV_ERROR(dev, "magic set %d:\n", i);
 425                                 for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4)
 426                                         NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
 427                                                 nv_rd32(dev, r));
 428                         }
 429                         break;
 430                 case 7: /* MP error */
 431                         if (ustatus & 0x04030000) {
 432                                 nv50_pgraph_mp_trap(dev, i, display);
 433                                 ustatus &= ~0x04030000;
 434                         }
 435                         break;
 436                 case 8: /* TPDMA error */
 437                         {
 438                         uint32_t e0c = nv_rd32(dev, ustatus_addr + 4);
 439                         uint32_t e10 = nv_rd32(dev, ustatus_addr + 8);
 440                         uint32_t e14 = nv_rd32(dev, ustatus_addr + 0xc);
 441                         uint32_t e18 = nv_rd32(dev, ustatus_addr + 0x10);
 442                         uint32_t e1c = nv_rd32(dev, ustatus_addr + 0x14);
 443                         uint32_t e20 = nv_rd32(dev, ustatus_addr + 0x18);
 444                         uint32_t e24 = nv_rd32(dev, ustatus_addr + 0x1c);
 445                         /* 2d engine destination */
 446                         if (ustatus & 0x00000010) {
 447                                 if (display) {
 448                                         NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - Unknown fault at address %02x%08x\n",
 449                                                         i, e14, e10);
 450                                         NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
 451                                                         i, e0c, e18, e1c, e20, e24);
 452                                 }
 453                                 ustatus &= ~0x00000010;
 454                         }
 455                         /* Render target */
 456                         if (ustatus & 0x00000040) {
 457                                 if (display) {
 458                                         NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - Unknown fault at address %02x%08x\n",
 459                                                         i, e14, e10);
 460                                         NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
 461                                                         i, e0c, e18, e1c, e20, e24);
 462                                 }
 463                                 ustatus &= ~0x00000040;
 464                         }
 465                         /* CUDA memory: l[], g[] or stack. */
 466                         if (ustatus & 0x00000080) {
 467                                 if (display) {
 468                                         if (e18 & 0x80000000) {
 469                                                 /* g[] read fault? */
 470                                                 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global read fault at address %02x%08x\n",
 471                                                                 i, e14, e10 | ((e18 >> 24) & 0x1f));
 472                                                 e18 &= ~0x1f000000;
 473                                         } else if (e18 & 0xc) {
 474                                                 /* g[] write fault? */
 475                                                 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global write fault at address %02x%08x\n",
 476                                                                 i, e14, e10 | ((e18 >> 7) & 0x1f));
 477                                                 e18 &= ~0x00000f80;
 478                                         } else {
 479                                                 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Unknown CUDA fault at address %02x%08x\n",
 480                                                                 i, e14, e10);
 481                                         }
 482                                         NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
 483                                                         i, e0c, e18, e1c, e20, e24);
 484                                 }
 485                                 ustatus &= ~0x00000080;
 486                         }
 487                         }
 488                         break;
 489                 }
 490                 if (ustatus) {
 491                         if (display)
 492                                 NV_INFO(dev, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus);
 493                 }
 494                 nv_wr32(dev, ustatus_addr, 0xc0000000);
 495         }
 496
 497         if (!tps && display)
 498                 NV_INFO(dev, "%s - No TPs claiming errors?\n", name);
 499 }
 500
 501 static int
 502 nv50_pgraph_trap_handler(struct drm_device *dev, u32 display, u64 inst, u32 chid)
 503 {
 504         u32 status = nv_rd32(dev, 0x400108);
 505         u32 ustatus;
 506
 507         if (!status && display) {
 508                 NV_INFO(dev, "PGRAPH - TRAP: no units reporting traps?\n");
 509                 return 1;
 510         }
 511
 512         /* DISPATCH: Relays commands to other units and handles NOTIFY,
 513          * COND, QUERY. If you get a trap from it, the command is still stuck
 514          * in DISPATCH and you need to do something about it. */
 515         if (status & 0x001) {
 516                 ustatus = nv_rd32(dev, 0x400804) & 0x7fffffff;
 517                 if (!ustatus && display) {
 518                         NV_INFO(dev, "PGRAPH_TRAP_DISPATCH - no ustatus?\n");
 519                 }
 520
 521                 nv_wr32(dev, 0x400500, 0x00000000);
 522
 523                 /* Known to be triggered by screwed up NOTIFY and COND... */
 524                 if (ustatus & 0x00000001) {
 525                         u32 addr = nv_rd32(dev, 0x400808);
 526                         u32 subc = (addr & 0x00070000) >> 16;
 527                         u32 mthd = (addr & 0x00001ffc);
 528                         u32 datal = nv_rd32(dev, 0x40080c);
 529                         u32 datah = nv_rd32(dev, 0x400810);
 530                         u32 class = nv_rd32(dev, 0x400814);
 531                         u32 r848 = nv_rd32(dev, 0x400848);
 532
 533                         NV_INFO(dev, "PGRAPH - TRAP DISPATCH_FAULT\n");
 534                         if (display && (addr & 0x80000000)) {
 535                                 NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) "
 536                                              "subc %d class 0x%04x mthd 0x%04x "
 537                                              "data 0x%08x%08x "
 538                                              "400808 0x%08x 400848 0x%08x\n",
 539                                         chid, inst, subc, class, mthd, datah,
 540                                         datal, addr, r848);
 541                         } else
 542                         if (display) {
 543                                 NV_INFO(dev, "PGRAPH - no stuck command?\n");
 544                         }
 545
 546                         nv_wr32(dev, 0x400808, 0);
 547                         nv_wr32(dev, 0x4008e8, nv_rd32(dev, 0x4008e8) & 3);
 548                         nv_wr32(dev, 0x400848, 0);
 549                         ustatus &= ~0x00000001;
 550                 }
 551
 552                 if (ustatus & 0x00000002) {
 553                         u32 addr = nv_rd32(dev, 0x40084c);
 554                         u32 subc = (addr & 0x00070000) >> 16;
 555                         u32 mthd = (addr & 0x00001ffc);
 556                         u32 data = nv_rd32(dev, 0x40085c);
 557                         u32 class = nv_rd32(dev, 0x400814);
 558
 559                         NV_INFO(dev, "PGRAPH - TRAP DISPATCH_QUERY\n");
 560                         if (display && (addr & 0x80000000)) {
 561                                 NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) "
 562                                              "subc %d class 0x%04x mthd 0x%04x "
 563                                              "data 0x%08x 40084c 0x%08x\n",
 564                                         chid, inst, subc, class, mthd,
 565                                         data, addr);
 566                         } else
 567                         if (display) {
 568                                 NV_INFO(dev, "PGRAPH - no stuck command?\n");
 569                         }
 570
 571                         nv_wr32(dev, 0x40084c, 0);
 572                         ustatus &= ~0x00000002;
 573                 }
 574
 575                 if (ustatus && display) {
 576                         NV_INFO(dev, "PGRAPH - TRAP_DISPATCH (unknown "
 577                                       "0x%08x)\n", ustatus);
 578                 }
 579
 580                 nv_wr32(dev, 0x400804, 0xc0000000);
 581                 nv_wr32(dev, 0x400108, 0x001);
 582                 status &= ~0x001;
 583                 if (!status)
 584                         return 0;
 585         }
 586
 587         /* M2MF: Memory to memory copy engine. */
 588         if (status & 0x002) {
 589                 u32 ustatus = nv_rd32(dev, 0x406800) & 0x7fffffff;
 590                 if (display) {
 591                         NV_INFO(dev, "PGRAPH - TRAP_M2MF");
 592                         nouveau_bitfield_print(nv50_graph_trap_m2mf, ustatus);
 593                         printk("\n");
 594                         NV_INFO(dev, "PGRAPH - TRAP_M2MF %08x %08x %08x %08x\n",
 595                                 nv_rd32(dev, 0x406804), nv_rd32(dev, 0x406808),
 596                                 nv_rd32(dev, 0x40680c), nv_rd32(dev, 0x406810));
 597
 598                 }
 599
 600                 /* No sane way found yet -- just reset the bugger. */
 601                 nv_wr32(dev, 0x400040, 2);
 602                 nv_wr32(dev, 0x400040, 0);
 603                 nv_wr32(dev, 0x406800, 0xc0000000);
 604                 nv_wr32(dev, 0x400108, 0x002);
 605                 status &= ~0x002;
 606         }
 607
 608         /* VFETCH: Fetches data from vertex buffers. */
 609         if (status & 0x004) {
 610                 u32 ustatus = nv_rd32(dev, 0x400c04) & 0x7fffffff;
 611                 if (display) {
 612                         NV_INFO(dev, "PGRAPH - TRAP_VFETCH");
 613                         nouveau_bitfield_print(nv50_graph_trap_vfetch, ustatus);
 614                         printk("\n");
 615                         NV_INFO(dev, "PGRAPH - TRAP_VFETCH %08x %08x %08x %08x\n",
 616                                 nv_rd32(dev, 0x400c00), nv_rd32(dev, 0x400c08),
 617                                 nv_rd32(dev, 0x400c0c), nv_rd32(dev, 0x400c10));
 618                 }
 619
 620                 nv_wr32(dev, 0x400c04, 0xc0000000);
 621                 nv_wr32(dev, 0x400108, 0x004);
 622                 status &= ~0x004;
 623         }
 624
 625         /* STRMOUT: DirectX streamout / OpenGL transform feedback. */
 626         if (status & 0x008) {
 627                 ustatus = nv_rd32(dev, 0x401800) & 0x7fffffff;
 628                 if (display) {
 629                         NV_INFO(dev, "PGRAPH - TRAP_STRMOUT");
 630                         nouveau_bitfield_print(nv50_graph_trap_strmout, ustatus);
 631                         printk("\n");
 632                         NV_INFO(dev, "PGRAPH - TRAP_STRMOUT %08x %08x %08x %08x\n",
 633                                 nv_rd32(dev, 0x401804), nv_rd32(dev, 0x401808),
 634                                 nv_rd32(dev, 0x40180c), nv_rd32(dev, 0x401810));
 635
 636                 }
 637
 638                 /* No sane way found yet -- just reset the bugger. */
 639                 nv_wr32(dev, 0x400040, 0x80);
 640                 nv_wr32(dev, 0x400040, 0);
 641                 nv_wr32(dev, 0x401800, 0xc0000000);
 642                 nv_wr32(dev, 0x400108, 0x008);
 643                 status &= ~0x008;
 644         }
 645
 646         /* CCACHE: Handles code and c[] caches and fills them. */
 647         if (status & 0x010) {
 648                 ustatus = nv_rd32(dev, 0x405018) & 0x7fffffff;
 649                 if (display) {
 650                         NV_INFO(dev, "PGRAPH - TRAP_CCACHE");
 651                         nouveau_bitfield_print(nv50_graph_trap_ccache, ustatus);
 652                         printk("\n");
 653                         NV_INFO(dev, "PGRAPH - TRAP_CCACHE %08x %08x %08x %08x"
 654                                      " %08x %08x %08x\n",
 655                                 nv_rd32(dev, 0x405000), nv_rd32(dev, 0x405004),
 656                                 nv_rd32(dev, 0x405008), nv_rd32(dev, 0x40500c),
 657                                 nv_rd32(dev, 0x405010), nv_rd32(dev, 0x405014),
 658                                 nv_rd32(dev, 0x40501c));
 659
 660                 }
 661
 662                 nv_wr32(dev, 0x405018, 0xc0000000);
 663                 nv_wr32(dev, 0x400108, 0x010);
 664                 status &= ~0x010;
 665         }
 666
 667         /* Unknown, not seen yet... 0x402000 is the only trap status reg
 668          * remaining, so try to handle it anyway. Perhaps related to that
 669          * unknown DMA slot on tesla? */
 670         if (status & 0x20) {
 671                 ustatus = nv_rd32(dev, 0x402000) & 0x7fffffff;
 672                 if (display)
 673                         NV_INFO(dev, "PGRAPH - TRAP_UNKC04 0x%08x\n", ustatus);
 674                 nv_wr32(dev, 0x402000, 0xc0000000);
 675                 /* no status modifiction on purpose */
 676         }
 677
 678         /* TEXTURE: CUDA texturing units */
 679         if (status & 0x040) {
 680                 nv50_pgraph_tp_trap(dev, 6, 0x408900, 0x408600, display,
 681                                     "PGRAPH - TRAP_TEXTURE");
 682                 nv_wr32(dev, 0x400108, 0x040);
 683                 status &= ~0x040;
 684         }
 685
 686         /* MP: CUDA execution engines. */
 687         if (status & 0x080) {
 688                 nv50_pgraph_tp_trap(dev, 7, 0x408314, 0x40831c, display,
 689                                     "PGRAPH - TRAP_MP");
 690                 nv_wr32(dev, 0x400108, 0x080);
 691                 status &= ~0x080;
 692         }
 693
 694         /* TPDMA:  Handles TP-initiated uncached memory accesses:
 695          * l[], g[], stack, 2d surfaces, render targets. */
 696         if (status & 0x100) {
 697                 nv50_pgraph_tp_trap(dev, 8, 0x408e08, 0x408708, display,
 698                                     "PGRAPH - TRAP_TPDMA");
 699                 nv_wr32(dev, 0x400108, 0x100);
 700                 status &= ~0x100;
 701         }
 702
 703         if (status) {
 704                 if (display)
 705                         NV_INFO(dev, "PGRAPH - TRAP: unknown 0x%08x\n", status);
 706                 nv_wr32(dev, 0x400108, status);
 707         }
 708
 709         return 1;
 710 }
 711
 712 int
 713 nv50_graph_isr_chid(struct drm_device *dev, u64 inst)
 714 {
 715         struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
 716         struct drm_nouveau_private *dev_priv = dev->dev_private;
 717         struct nouveau_channel *chan;
 718         unsigned long flags;
 719         int i;
 720
 721         spin_lock_irqsave(&dev_priv->channels.lock, flags);
 722         for (i = 0; i < pfifo->channels; i++) {
 723                 chan = dev_priv->channels.ptr[i];
 724                 if (!chan || !chan->ramin)
 725                         continue;
 726
 727                 if (inst == chan->ramin->vinst)
 728                         break;
 729         }
 730         spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
 731         return i;
 732 }
 733
 734 static void
 735 nv50_graph_isr(struct drm_device *dev)
 736 {
 737         u32 stat;
 738
 739         while ((stat = nv_rd32(dev, 0x400100))) {
 740                 u64 inst = (u64)(nv_rd32(dev, 0x40032c) & 0x0fffffff) << 12;
 741                 u32 chid = nv50_graph_isr_chid(dev, inst);
 742                 u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
 743                 u32 subc = (addr & 0x00070000) >> 16;
 744                 u32 mthd = (addr & 0x00001ffc);
 745                 u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
 746                 u32 class = nv_rd32(dev, 0x400814);
 747                 u32 show = stat;
 748
 749                 if (stat & 0x00000010) {
 750                         if (!nouveau_gpuobj_mthd_call2(dev, chid, class,
 751                                                        mthd, data))
 752                                 show &= ~0x00000010;
 753                 }
 754
 755                 show = (show && nouveau_ratelimit()) ? show : 0;
 756
 757                 if (show & 0x00100000) {
 758                         u32 ecode = nv_rd32(dev, 0x400110);
 759                         NV_INFO(dev, "PGRAPH - DATA_ERROR ");
 760                         nouveau_enum_print(nv50_data_error_names, ecode);
 761                         printk("\n");
 762                 }
 763
 764                 if (stat & 0x00200000) {
 765                         if (!nv50_pgraph_trap_handler(dev, show, inst, chid))
 766                                 show &= ~0x00200000;
 767                 }
 768
 769                 nv_wr32(dev, 0x400100, stat);
 770                 nv_wr32(dev, 0x400500, 0x00010001);
 771
 772                 if (show) {
 773                         NV_INFO(dev, "PGRAPH -");
 774                         nouveau_bitfield_print(nv50_graph_intr, show);
 775                         printk("\n");
 776                         NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) subc %d "
 777                                      "class 0x%04x mthd 0x%04x data 0x%08x\n",
 778                                 chid, inst, subc, class, mthd, data);
 779                         nv50_fb_vm_trap(dev, 1);
 780                 }
 781         }
 782
 783         if (nv_rd32(dev, 0x400824) & (1 << 31))
 784                 nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) & ~(1 << 31));
 785 }
 786
 787 static void
 788 nv50_graph_destroy(struct drm_device *dev, int engine)
 789 {
 790         struct nv50_graph_engine *pgraph = nv_engine(dev, engine);
 791
 792         NVOBJ_ENGINE_DEL(dev, GR);
 793
 794         nouveau_irq_unregister(dev, 12);
 795         kfree(pgraph);
 796 }
 797
 798 int
 799 nv50_graph_create(struct drm_device *dev)
 800 {
 801         struct drm_nouveau_private *dev_priv = dev->dev_private;
 802         struct nv50_graph_engine *pgraph;
 803         int ret;
 804
 805         pgraph = kzalloc(sizeof(*pgraph),GFP_KERNEL);
 806         if (!pgraph)
 807                 return -ENOMEM;
 808
 809         ret = nv50_grctx_init(dev, pgraph->ctxprog, ARRAY_SIZE(pgraph->ctxprog),
 810                                   &pgraph->ctxprog_size,
 811                                   &pgraph->grctx_size);
 812         if (ret) {
 813                 NV_ERROR(dev, "PGRAPH: ctxprog build failed\n");
 814                 kfree(pgraph);
 815                 return 0;
 816         }
 817
 818         pgraph->base.destroy = nv50_graph_destroy;
 819         pgraph->base.init = nv50_graph_init;
 820         pgraph->base.fini = nv50_graph_fini;
 821         pgraph->base.context_new = nv50_graph_context_new;
 822         pgraph->base.context_del = nv50_graph_context_del;
 823         pgraph->base.object_new = nv50_graph_object_new;
 824         if (dev_priv->chipset == 0x50 || dev_priv->chipset == 0xac)
 825                 pgraph->base.tlb_flush = nv50_graph_tlb_flush;
 826         else
 827                 pgraph->base.tlb_flush = nv84_graph_tlb_flush;
 828
 829         nouveau_irq_register(dev, 12, nv50_graph_isr);
 830
 831         NVOBJ_ENGINE_ADD(dev, GR, &pgraph->base);
 832         NVOBJ_CLASS(dev, 0x0030, GR); /* null */
 833         NVOBJ_CLASS(dev, 0x5039, GR); /* m2mf */
 834         NVOBJ_CLASS(dev, 0x502d, GR); /* 2d */
 835
 836         /* tesla */
 837         if (dev_priv->chipset == 0x50)
 838                 NVOBJ_CLASS(dev, 0x5097, GR); /* tesla (nv50) */
 839         else
 840         if (dev_priv->chipset < 0xa0)
 841                 NVOBJ_CLASS(dev, 0x8297, GR); /* tesla (nv8x/nv9x) */
 842         else {
 843                 switch (dev_priv->chipset) {
 844                 case 0xa0:
 845                 case 0xaa:
 846                 case 0xac:
 847                         NVOBJ_CLASS(dev, 0x8397, GR);
 848                         break;
 849                 case 0xa3:
 850                 case 0xa5:
 851                 case 0xa8:
 852                         NVOBJ_CLASS(dev, 0x8597, GR);
 853                         break;
 854                 case 0xaf:
 855                         NVOBJ_CLASS(dev, 0x8697, GR);
 856                         break;
 857                 }
 858         }
 859
 860         /* compute */
 861         NVOBJ_CLASS(dev, 0x50c0, GR);
 862         if (dev_priv->chipset  > 0xa0 &&
 863             dev_priv->chipset != 0xaa &&
 864             dev_priv->chipset != 0xac)
 865                 NVOBJ_CLASS(dev, 0x85c0, GR);
 866
 867         return 0;
 868 }