2 * Copyright (C) 2007 Ben Skeggs.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "nouveau_drv.h"
30 #include "nouveau_ramht.h"
33 nv50_fifo_playlist_update(struct drm_device *dev)
35 struct drm_nouveau_private *dev_priv = dev->dev_private;
36 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
37 struct nouveau_gpuobj *cur;
42 cur = pfifo->playlist[pfifo->cur_playlist];
43 pfifo->cur_playlist = !pfifo->cur_playlist;
45 /* We never schedule channel 0 or 127 */
46 for (i = 1, nr = 0; i < 127; i++) {
47 if (dev_priv->fifos[i] && dev_priv->fifos[i]->ramfc) {
48 nv_wo32(cur, (nr * 4), i);
52 dev_priv->engine.instmem.flush(dev);
54 nv_wr32(dev, 0x32f4, cur->vinst >> 12);
55 nv_wr32(dev, 0x32ec, nr);
56 nv_wr32(dev, 0x2500, 0x101);
60 nv50_fifo_channel_enable(struct drm_device *dev, int channel)
62 struct drm_nouveau_private *dev_priv = dev->dev_private;
63 struct nouveau_channel *chan = dev_priv->fifos[channel];
66 NV_DEBUG(dev, "ch%d\n", channel);
68 if (dev_priv->chipset == 0x50)
69 inst = chan->ramfc->vinst >> 12;
71 inst = chan->ramfc->vinst >> 8;
73 nv_wr32(dev, NV50_PFIFO_CTX_TABLE(channel), inst |
74 NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED);
78 nv50_fifo_channel_disable(struct drm_device *dev, int channel)
80 struct drm_nouveau_private *dev_priv = dev->dev_private;
83 NV_DEBUG(dev, "ch%d\n", channel);
85 if (dev_priv->chipset == 0x50)
86 inst = NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80;
88 inst = NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84;
89 nv_wr32(dev, NV50_PFIFO_CTX_TABLE(channel), inst);
93 nv50_fifo_init_reset(struct drm_device *dev)
95 uint32_t pmc_e = NV_PMC_ENABLE_PFIFO;
99 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) & ~pmc_e);
100 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) | pmc_e);
104 nv50_fifo_init_intr(struct drm_device *dev)
108 nv_wr32(dev, NV03_PFIFO_INTR_0, 0xFFFFFFFF);
109 nv_wr32(dev, NV03_PFIFO_INTR_EN_0, 0xFFFFFFFF);
113 nv50_fifo_init_context_table(struct drm_device *dev)
115 struct drm_nouveau_private *dev_priv = dev->dev_private;
120 for (i = 0; i < NV50_PFIFO_CTX_TABLE__SIZE; i++) {
121 if (dev_priv->fifos[i])
122 nv50_fifo_channel_enable(dev, i);
124 nv50_fifo_channel_disable(dev, i);
127 nv50_fifo_playlist_update(dev);
131 nv50_fifo_init_regs__nv(struct drm_device *dev)
135 nv_wr32(dev, 0x250c, 0x6f3cfc34);
139 nv50_fifo_init_regs(struct drm_device *dev)
143 nv_wr32(dev, 0x2500, 0);
144 nv_wr32(dev, 0x3250, 0);
145 nv_wr32(dev, 0x3220, 0);
146 nv_wr32(dev, 0x3204, 0);
147 nv_wr32(dev, 0x3210, 0);
148 nv_wr32(dev, 0x3270, 0);
150 /* Enable dummy channels setup by nv50_instmem.c */
151 nv50_fifo_channel_enable(dev, 0);
152 nv50_fifo_channel_enable(dev, 127);
156 nv50_fifo_init(struct drm_device *dev)
158 struct drm_nouveau_private *dev_priv = dev->dev_private;
159 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
164 if (pfifo->playlist[0]) {
165 pfifo->cur_playlist = !pfifo->cur_playlist;
169 ret = nouveau_gpuobj_new(dev, NULL, 128*4, 0x1000,
170 NVOBJ_FLAG_ZERO_ALLOC,
171 &pfifo->playlist[0]);
173 NV_ERROR(dev, "error creating playlist 0: %d\n", ret);
177 ret = nouveau_gpuobj_new(dev, NULL, 128*4, 0x1000,
178 NVOBJ_FLAG_ZERO_ALLOC,
179 &pfifo->playlist[1]);
181 nouveau_gpuobj_ref(NULL, &pfifo->playlist[0]);
182 NV_ERROR(dev, "error creating playlist 1: %d\n", ret);
187 nv50_fifo_init_reset(dev);
188 nv50_fifo_init_intr(dev);
189 nv50_fifo_init_context_table(dev);
190 nv50_fifo_init_regs__nv(dev);
191 nv50_fifo_init_regs(dev);
192 dev_priv->engine.fifo.enable(dev);
193 dev_priv->engine.fifo.reassign(dev, true);
199 nv50_fifo_takedown(struct drm_device *dev)
201 struct drm_nouveau_private *dev_priv = dev->dev_private;
202 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
206 if (!pfifo->playlist[0])
209 nouveau_gpuobj_ref(NULL, &pfifo->playlist[0]);
210 nouveau_gpuobj_ref(NULL, &pfifo->playlist[1]);
214 nv50_fifo_channel_id(struct drm_device *dev)
216 return nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH1) &
217 NV50_PFIFO_CACHE1_PUSH1_CHID_MASK;
221 nv50_fifo_create_context(struct nouveau_channel *chan)
223 struct drm_device *dev = chan->dev;
224 struct drm_nouveau_private *dev_priv = dev->dev_private;
225 struct nouveau_gpuobj *ramfc = NULL;
229 NV_DEBUG(dev, "ch%d\n", chan->id);
231 if (dev_priv->chipset == 0x50) {
232 ret = nouveau_gpuobj_new_fake(dev, chan->ramin->pinst,
233 chan->ramin->vinst, 0x100,
234 NVOBJ_FLAG_ZERO_ALLOC |
235 NVOBJ_FLAG_ZERO_FREE,
240 ret = nouveau_gpuobj_new_fake(dev, chan->ramin->pinst + 0x0400,
241 chan->ramin->vinst + 0x0400,
242 4096, 0, &chan->cache);
246 ret = nouveau_gpuobj_new(dev, chan, 0x100, 256,
247 NVOBJ_FLAG_ZERO_ALLOC |
248 NVOBJ_FLAG_ZERO_FREE, &chan->ramfc);
252 ret = nouveau_gpuobj_new(dev, chan, 4096, 1024,
259 spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
261 nv_wo32(ramfc, 0x48, chan->pushbuf->cinst >> 4);
262 nv_wo32(ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
263 (4 << 24) /* SEARCH_FULL */ |
264 (chan->ramht->gpuobj->cinst >> 4));
265 nv_wo32(ramfc, 0x44, 0x2101ffff);
266 nv_wo32(ramfc, 0x60, 0x7fffffff);
267 nv_wo32(ramfc, 0x40, 0x00000000);
268 nv_wo32(ramfc, 0x7c, 0x30000001);
269 nv_wo32(ramfc, 0x78, 0x00000000);
270 nv_wo32(ramfc, 0x3c, 0x403f6078);
271 nv_wo32(ramfc, 0x50, chan->pushbuf_base + chan->dma.ib_base * 4);
272 nv_wo32(ramfc, 0x54, drm_order(chan->dma.ib_max + 1) << 16);
274 if (dev_priv->chipset != 0x50) {
275 nv_wo32(chan->ramin, 0, chan->id);
276 nv_wo32(chan->ramin, 4, chan->ramfc->vinst >> 8);
278 nv_wo32(ramfc, 0x88, chan->cache->vinst >> 10);
279 nv_wo32(ramfc, 0x98, chan->ramin->vinst >> 12);
282 dev_priv->engine.instmem.flush(dev);
284 nv50_fifo_channel_enable(dev, chan->id);
285 nv50_fifo_playlist_update(dev);
286 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
291 nv50_fifo_destroy_context(struct nouveau_channel *chan)
293 struct drm_device *dev = chan->dev;
294 struct nouveau_gpuobj *ramfc = NULL;
296 NV_DEBUG(dev, "ch%d\n", chan->id);
298 /* This will ensure the channel is seen as disabled. */
299 nouveau_gpuobj_ref(chan->ramfc, &ramfc);
300 nouveau_gpuobj_ref(NULL, &chan->ramfc);
301 nv50_fifo_channel_disable(dev, chan->id);
303 /* Dummy channel, also used on ch 127 */
305 nv50_fifo_channel_disable(dev, 127);
306 nv50_fifo_playlist_update(dev);
308 nouveau_gpuobj_ref(NULL, &ramfc);
309 nouveau_gpuobj_ref(NULL, &chan->cache);
313 nv50_fifo_load_context(struct nouveau_channel *chan)
315 struct drm_device *dev = chan->dev;
316 struct drm_nouveau_private *dev_priv = dev->dev_private;
317 struct nouveau_gpuobj *ramfc = chan->ramfc;
318 struct nouveau_gpuobj *cache = chan->cache;
321 NV_DEBUG(dev, "ch%d\n", chan->id);
323 nv_wr32(dev, 0x3330, nv_ro32(ramfc, 0x00));
324 nv_wr32(dev, 0x3334, nv_ro32(ramfc, 0x04));
325 nv_wr32(dev, 0x3240, nv_ro32(ramfc, 0x08));
326 nv_wr32(dev, 0x3320, nv_ro32(ramfc, 0x0c));
327 nv_wr32(dev, 0x3244, nv_ro32(ramfc, 0x10));
328 nv_wr32(dev, 0x3328, nv_ro32(ramfc, 0x14));
329 nv_wr32(dev, 0x3368, nv_ro32(ramfc, 0x18));
330 nv_wr32(dev, 0x336c, nv_ro32(ramfc, 0x1c));
331 nv_wr32(dev, 0x3370, nv_ro32(ramfc, 0x20));
332 nv_wr32(dev, 0x3374, nv_ro32(ramfc, 0x24));
333 nv_wr32(dev, 0x3378, nv_ro32(ramfc, 0x28));
334 nv_wr32(dev, 0x337c, nv_ro32(ramfc, 0x2c));
335 nv_wr32(dev, 0x3228, nv_ro32(ramfc, 0x30));
336 nv_wr32(dev, 0x3364, nv_ro32(ramfc, 0x34));
337 nv_wr32(dev, 0x32a0, nv_ro32(ramfc, 0x38));
338 nv_wr32(dev, 0x3224, nv_ro32(ramfc, 0x3c));
339 nv_wr32(dev, 0x324c, nv_ro32(ramfc, 0x40));
340 nv_wr32(dev, 0x2044, nv_ro32(ramfc, 0x44));
341 nv_wr32(dev, 0x322c, nv_ro32(ramfc, 0x48));
342 nv_wr32(dev, 0x3234, nv_ro32(ramfc, 0x4c));
343 nv_wr32(dev, 0x3340, nv_ro32(ramfc, 0x50));
344 nv_wr32(dev, 0x3344, nv_ro32(ramfc, 0x54));
345 nv_wr32(dev, 0x3280, nv_ro32(ramfc, 0x58));
346 nv_wr32(dev, 0x3254, nv_ro32(ramfc, 0x5c));
347 nv_wr32(dev, 0x3260, nv_ro32(ramfc, 0x60));
348 nv_wr32(dev, 0x3264, nv_ro32(ramfc, 0x64));
349 nv_wr32(dev, 0x3268, nv_ro32(ramfc, 0x68));
350 nv_wr32(dev, 0x326c, nv_ro32(ramfc, 0x6c));
351 nv_wr32(dev, 0x32e4, nv_ro32(ramfc, 0x70));
352 nv_wr32(dev, 0x3248, nv_ro32(ramfc, 0x74));
353 nv_wr32(dev, 0x2088, nv_ro32(ramfc, 0x78));
354 nv_wr32(dev, 0x2058, nv_ro32(ramfc, 0x7c));
355 nv_wr32(dev, 0x2210, nv_ro32(ramfc, 0x80));
357 cnt = nv_ro32(ramfc, 0x84);
358 for (ptr = 0; ptr < cnt; ptr++) {
359 nv_wr32(dev, NV40_PFIFO_CACHE1_METHOD(ptr),
360 nv_ro32(cache, (ptr * 8) + 0));
361 nv_wr32(dev, NV40_PFIFO_CACHE1_DATA(ptr),
362 nv_ro32(cache, (ptr * 8) + 4));
364 nv_wr32(dev, NV03_PFIFO_CACHE1_PUT, cnt << 2);
365 nv_wr32(dev, NV03_PFIFO_CACHE1_GET, 0);
367 /* guessing that all the 0x34xx regs aren't on NV50 */
368 if (dev_priv->chipset != 0x50) {
369 nv_wr32(dev, 0x340c, nv_ro32(ramfc, 0x88));
370 nv_wr32(dev, 0x3400, nv_ro32(ramfc, 0x8c));
371 nv_wr32(dev, 0x3404, nv_ro32(ramfc, 0x90));
372 nv_wr32(dev, 0x3408, nv_ro32(ramfc, 0x94));
373 nv_wr32(dev, 0x3410, nv_ro32(ramfc, 0x98));
376 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, chan->id | (1<<16));
381 nv50_fifo_unload_context(struct drm_device *dev)
383 struct drm_nouveau_private *dev_priv = dev->dev_private;
384 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
385 struct nouveau_gpuobj *ramfc, *cache;
386 struct nouveau_channel *chan = NULL;
387 int chid, get, put, ptr;
391 chid = pfifo->channel_id(dev);
392 if (chid < 1 || chid >= dev_priv->engine.fifo.channels - 1)
395 chan = dev_priv->fifos[chid];
397 NV_ERROR(dev, "Inactive channel on PFIFO: %d\n", chid);
400 NV_DEBUG(dev, "ch%d\n", chan->id);
404 nv_wo32(ramfc, 0x00, nv_rd32(dev, 0x3330));
405 nv_wo32(ramfc, 0x04, nv_rd32(dev, 0x3334));
406 nv_wo32(ramfc, 0x08, nv_rd32(dev, 0x3240));
407 nv_wo32(ramfc, 0x0c, nv_rd32(dev, 0x3320));
408 nv_wo32(ramfc, 0x10, nv_rd32(dev, 0x3244));
409 nv_wo32(ramfc, 0x14, nv_rd32(dev, 0x3328));
410 nv_wo32(ramfc, 0x18, nv_rd32(dev, 0x3368));
411 nv_wo32(ramfc, 0x1c, nv_rd32(dev, 0x336c));
412 nv_wo32(ramfc, 0x20, nv_rd32(dev, 0x3370));
413 nv_wo32(ramfc, 0x24, nv_rd32(dev, 0x3374));
414 nv_wo32(ramfc, 0x28, nv_rd32(dev, 0x3378));
415 nv_wo32(ramfc, 0x2c, nv_rd32(dev, 0x337c));
416 nv_wo32(ramfc, 0x30, nv_rd32(dev, 0x3228));
417 nv_wo32(ramfc, 0x34, nv_rd32(dev, 0x3364));
418 nv_wo32(ramfc, 0x38, nv_rd32(dev, 0x32a0));
419 nv_wo32(ramfc, 0x3c, nv_rd32(dev, 0x3224));
420 nv_wo32(ramfc, 0x40, nv_rd32(dev, 0x324c));
421 nv_wo32(ramfc, 0x44, nv_rd32(dev, 0x2044));
422 nv_wo32(ramfc, 0x48, nv_rd32(dev, 0x322c));
423 nv_wo32(ramfc, 0x4c, nv_rd32(dev, 0x3234));
424 nv_wo32(ramfc, 0x50, nv_rd32(dev, 0x3340));
425 nv_wo32(ramfc, 0x54, nv_rd32(dev, 0x3344));
426 nv_wo32(ramfc, 0x58, nv_rd32(dev, 0x3280));
427 nv_wo32(ramfc, 0x5c, nv_rd32(dev, 0x3254));
428 nv_wo32(ramfc, 0x60, nv_rd32(dev, 0x3260));
429 nv_wo32(ramfc, 0x64, nv_rd32(dev, 0x3264));
430 nv_wo32(ramfc, 0x68, nv_rd32(dev, 0x3268));
431 nv_wo32(ramfc, 0x6c, nv_rd32(dev, 0x326c));
432 nv_wo32(ramfc, 0x70, nv_rd32(dev, 0x32e4));
433 nv_wo32(ramfc, 0x74, nv_rd32(dev, 0x3248));
434 nv_wo32(ramfc, 0x78, nv_rd32(dev, 0x2088));
435 nv_wo32(ramfc, 0x7c, nv_rd32(dev, 0x2058));
436 nv_wo32(ramfc, 0x80, nv_rd32(dev, 0x2210));
438 put = (nv_rd32(dev, NV03_PFIFO_CACHE1_PUT) & 0x7ff) >> 2;
439 get = (nv_rd32(dev, NV03_PFIFO_CACHE1_GET) & 0x7ff) >> 2;
442 nv_wo32(cache, ptr + 0,
443 nv_rd32(dev, NV40_PFIFO_CACHE1_METHOD(get)));
444 nv_wo32(cache, ptr + 4,
445 nv_rd32(dev, NV40_PFIFO_CACHE1_DATA(get)));
446 get = (get + 1) & 0x1ff;
450 /* guessing that all the 0x34xx regs aren't on NV50 */
451 if (dev_priv->chipset != 0x50) {
452 nv_wo32(ramfc, 0x84, ptr >> 3);
453 nv_wo32(ramfc, 0x88, nv_rd32(dev, 0x340c));
454 nv_wo32(ramfc, 0x8c, nv_rd32(dev, 0x3400));
455 nv_wo32(ramfc, 0x90, nv_rd32(dev, 0x3404));
456 nv_wo32(ramfc, 0x94, nv_rd32(dev, 0x3408));
457 nv_wo32(ramfc, 0x98, nv_rd32(dev, 0x3410));
460 dev_priv->engine.instmem.flush(dev);
462 /*XXX: probably reload ch127 (NULL) state back too */
463 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, 127);
468 nv50_fifo_tlb_flush(struct drm_device *dev)
470 nv50_vm_flush(dev, 5);