2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 #include "nouveau_drv.h"
28 #include "nouveau_ramht.h"
29 #include "nouveau_fence.h"
30 #include "nouveau_software.h"
31 #include "nouveau_hw.h"
33 struct nv04_software_priv {
34 struct nouveau_software_priv base;
37 struct nv04_software_chan {
38 struct nouveau_software_chan base;
42 mthd_flip(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data)
45 struct nouveau_page_flip_state state;
47 if (!nouveau_finish_page_flip(chan, &state)) {
48 nv_set_crtc_base(chan->dev, state.crtc, state.offset +
49 state.y * state.pitch +
50 state.x * state.bpp / 8);
57 nv04_software_context_new(struct nouveau_channel *chan, int engine)
59 struct nv04_software_chan *pch;
61 pch = kzalloc(sizeof(*pch), GFP_KERNEL);
65 nouveau_software_context_new(&pch->base);
66 chan->engctx[engine] = pch;
71 nv04_software_context_del(struct nouveau_channel *chan, int engine)
73 struct nv04_software_chan *pch = chan->engctx[engine];
74 chan->engctx[engine] = NULL;
79 nv04_software_object_new(struct nouveau_channel *chan, int engine,
80 u32 handle, u16 class)
82 struct drm_device *dev = chan->dev;
83 struct nouveau_gpuobj *obj = NULL;
86 ret = nouveau_gpuobj_new(dev, chan, 16, 16, 0, &obj);
92 ret = nouveau_ramht_insert(chan, handle, obj);
93 nouveau_gpuobj_ref(NULL, &obj);
98 nv04_software_init(struct drm_device *dev, int engine)
104 nv04_software_fini(struct drm_device *dev, int engine, bool suspend)
110 nv04_software_destroy(struct drm_device *dev, int engine)
112 struct nv04_software_priv *psw = nv_engine(dev, engine);
114 NVOBJ_ENGINE_DEL(dev, SW);
119 nv04_software_create(struct drm_device *dev)
121 struct drm_nouveau_private *dev_priv = dev->dev_private;
122 struct nv04_software_priv *psw;
124 psw = kzalloc(sizeof(*psw), GFP_KERNEL);
128 psw->base.base.destroy = nv04_software_destroy;
129 psw->base.base.init = nv04_software_init;
130 psw->base.base.fini = nv04_software_fini;
131 psw->base.base.context_new = nv04_software_context_new;
132 psw->base.base.context_del = nv04_software_context_del;
133 psw->base.base.object_new = nv04_software_object_new;
134 nouveau_software_create(&psw->base);
136 NVOBJ_ENGINE_ADD(dev, SW, &psw->base.base);
137 if (dev_priv->card_type <= NV_04) {
138 NVOBJ_CLASS(dev, 0x006e, SW);
139 NVOBJ_MTHD (dev, 0x006e, 0x0150, nv04_fence_mthd);
140 NVOBJ_MTHD (dev, 0x006e, 0x0500, mthd_flip);
142 NVOBJ_CLASS(dev, 0x016e, SW);
143 NVOBJ_MTHD (dev, 0x016e, 0x0500, mthd_flip);