drivers/gpu/drm/nouveau/nouveau_mem.c

   1 /*
   2  * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3  * Copyright 2005 Stephane Marchesin
   4  *
   5  * The Weather Channel (TM) funded Tungsten Graphics to develop the
   6  * initial release of the Radeon 8500 driver under the XFree86 license.
   7  * This notice must be preserved.
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  24  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  25  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  26  * DEALINGS IN THE SOFTWARE.
  27  *
  28  * Authors:
  29  *    Keith Whitwell <keith@tungstengraphics.com>
  30  */
  31
  32
  33 #include "drmP.h"
  34 #include "drm.h"
  35 #include "drm_sarea.h"
  36
  37 #include "nouveau_drv.h"
  38 #include "nouveau_pm.h"
  39 #include "nouveau_mm.h"
  40 #include "nouveau_vm.h"
  41
  42 /*
  43  * NV10-NV40 tiling helpers
  44  */
  45
  46 static void
  47 nv10_mem_update_tile_region(struct drm_device *dev,
  48                             struct nouveau_tile_reg *tile, uint32_t addr,
  49                             uint32_t size, uint32_t pitch, uint32_t flags)
  50 {
  51         struct drm_nouveau_private *dev_priv = dev->dev_private;
  52         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
  53         struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
  54         int i = tile - dev_priv->tile.reg, j;
  55         unsigned long save;
  56
  57         nouveau_fence_unref(&tile->fence);
  58
  59         if (tile->pitch)
  60                 pfb->free_tile_region(dev, i);
  61
  62         if (pitch)
  63                 pfb->init_tile_region(dev, i, addr, size, pitch, flags);
  64
  65         spin_lock_irqsave(&dev_priv->context_switch_lock, save);
  66         pfifo->reassign(dev, false);
  67         pfifo->cache_pull(dev, false);
  68
  69         nouveau_wait_for_idle(dev);
  70
  71         pfb->set_tile_region(dev, i);
  72         for (j = 0; j < NVOBJ_ENGINE_NR; j++) {
  73                 if (dev_priv->eng[j] && dev_priv->eng[j]->set_tile_region)
  74                         dev_priv->eng[j]->set_tile_region(dev, i);
  75         }
  76
  77         pfifo->cache_pull(dev, true);
  78         pfifo->reassign(dev, true);
  79         spin_unlock_irqrestore(&dev_priv->context_switch_lock, save);
  80 }
  81
  82 static struct nouveau_tile_reg *
  83 nv10_mem_get_tile_region(struct drm_device *dev, int i)
  84 {
  85         struct drm_nouveau_private *dev_priv = dev->dev_private;
  86         struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
  87
  88         spin_lock(&dev_priv->tile.lock);
  89
  90         if (!tile->used &&
  91             (!tile->fence || nouveau_fence_signalled(tile->fence)))
  92                 tile->used = true;
  93         else
  94                 tile = NULL;
  95
  96         spin_unlock(&dev_priv->tile.lock);
  97         return tile;
  98 }
  99
 100 void
 101 nv10_mem_put_tile_region(struct drm_device *dev, struct nouveau_tile_reg *tile,
 102                          struct nouveau_fence *fence)
 103 {
 104         struct drm_nouveau_private *dev_priv = dev->dev_private;
 105
 106         if (tile) {
 107                 spin_lock(&dev_priv->tile.lock);
 108                 if (fence) {
 109                         /* Mark it as pending. */
 110                         tile->fence = fence;
 111                         nouveau_fence_ref(fence);
 112                 }
 113
 114                 tile->used = false;
 115                 spin_unlock(&dev_priv->tile.lock);
 116         }
 117 }
 118
 119 struct nouveau_tile_reg *
 120 nv10_mem_set_tiling(struct drm_device *dev, uint32_t addr, uint32_t size,
 121                     uint32_t pitch, uint32_t flags)
 122 {
 123         struct drm_nouveau_private *dev_priv = dev->dev_private;
 124         struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
 125         struct nouveau_tile_reg *tile, *found = NULL;
 126         int i;
 127
 128         for (i = 0; i < pfb->num_tiles; i++) {
 129                 tile = nv10_mem_get_tile_region(dev, i);
 130
 131                 if (pitch && !found) {
 132                         found = tile;
 133                         continue;
 134
 135                 } else if (tile && tile->pitch) {
 136                         /* Kill an unused tile region. */
 137                         nv10_mem_update_tile_region(dev, tile, 0, 0, 0, 0);
 138                 }
 139
 140                 nv10_mem_put_tile_region(dev, tile, NULL);
 141         }
 142
 143         if (found)
 144                 nv10_mem_update_tile_region(dev, found, addr, size,
 145                                             pitch, flags);
 146         return found;
 147 }
 148
 149 /*
 150  * Cleanup everything
 151  */
 152 void
 153 nouveau_mem_vram_fini(struct drm_device *dev)
 154 {
 155         struct drm_nouveau_private *dev_priv = dev->dev_private;
 156
 157         ttm_bo_device_release(&dev_priv->ttm.bdev);
 158
 159         nouveau_ttm_global_release(dev_priv);
 160
 161         if (dev_priv->fb_mtrr >= 0) {
 162                 drm_mtrr_del(dev_priv->fb_mtrr,
 163                              pci_resource_start(dev->pdev, 1),
 164                              pci_resource_len(dev->pdev, 1), DRM_MTRR_WC);
 165                 dev_priv->fb_mtrr = -1;
 166         }
 167 }
 168
 169 void
 170 nouveau_mem_gart_fini(struct drm_device *dev)
 171 {
 172         nouveau_sgdma_takedown(dev);
 173
 174         if (drm_core_has_AGP(dev) && dev->agp) {
 175                 struct drm_agp_mem *entry, *tempe;
 176
 177                 /* Remove AGP resources, but leave dev->agp
 178                    intact until drv_cleanup is called. */
 179                 list_for_each_entry_safe(entry, tempe, &dev->agp->memory, head) {
 180                         if (entry->bound)
 181                                 drm_unbind_agp(entry->memory);
 182                         drm_free_agp(entry->memory, entry->pages);
 183                         kfree(entry);
 184                 }
 185                 INIT_LIST_HEAD(&dev->agp->memory);
 186
 187                 if (dev->agp->acquired)
 188                         drm_agp_release(dev);
 189
 190                 dev->agp->acquired = 0;
 191                 dev->agp->enabled = 0;
 192         }
 193 }
 194
 195 static uint32_t
 196 nouveau_mem_detect_nv04(struct drm_device *dev)
 197 {
 198         uint32_t boot0 = nv_rd32(dev, NV04_PFB_BOOT_0);
 199
 200         if (boot0 & 0x00000100)
 201                 return (((boot0 >> 12) & 0xf) * 2 + 2) * 1024 * 1024;
 202
 203         switch (boot0 & NV04_PFB_BOOT_0_RAM_AMOUNT) {
 204         case NV04_PFB_BOOT_0_RAM_AMOUNT_32MB:
 205                 return 32 * 1024 * 1024;
 206         case NV04_PFB_BOOT_0_RAM_AMOUNT_16MB:
 207                 return 16 * 1024 * 1024;
 208         case NV04_PFB_BOOT_0_RAM_AMOUNT_8MB:
 209                 return 8 * 1024 * 1024;
 210         case NV04_PFB_BOOT_0_RAM_AMOUNT_4MB:
 211                 return 4 * 1024 * 1024;
 212         }
 213
 214         return 0;
 215 }
 216
 217 static uint32_t
 218 nouveau_mem_detect_nforce(struct drm_device *dev)
 219 {
 220         struct drm_nouveau_private *dev_priv = dev->dev_private;
 221         struct pci_dev *bridge;
 222         uint32_t mem;
 223
 224         bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1));
 225         if (!bridge) {
 226                 NV_ERROR(dev, "no bridge device\n");
 227                 return 0;
 228         }
 229
 230         if (dev_priv->flags & NV_NFORCE) {
 231                 pci_read_config_dword(bridge, 0x7C, &mem);
 232                 return (uint64_t)(((mem >> 6) & 31) + 1)*1024*1024;
 233         } else
 234         if (dev_priv->flags & NV_NFORCE2) {
 235                 pci_read_config_dword(bridge, 0x84, &mem);
 236                 return (uint64_t)(((mem >> 4) & 127) + 1)*1024*1024;
 237         }
 238
 239         NV_ERROR(dev, "impossible!\n");
 240         return 0;
 241 }
 242
 243 int
 244 nouveau_mem_detect(struct drm_device *dev)
 245 {
 246         struct drm_nouveau_private *dev_priv = dev->dev_private;
 247
 248         if (dev_priv->card_type == NV_04) {
 249                 dev_priv->vram_size = nouveau_mem_detect_nv04(dev);
 250         } else
 251         if (dev_priv->flags & (NV_NFORCE | NV_NFORCE2)) {
 252                 dev_priv->vram_size = nouveau_mem_detect_nforce(dev);
 253         } else
 254         if (dev_priv->card_type < NV_50) {
 255                 dev_priv->vram_size  = nv_rd32(dev, NV04_PFB_FIFO_DATA);
 256                 dev_priv->vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
 257         }
 258
 259         if (dev_priv->vram_size)
 260                 return 0;
 261         return -ENOMEM;
 262 }
 263
 264 bool
 265 nouveau_mem_flags_valid(struct drm_device *dev, u32 tile_flags)
 266 {
 267         if (!(tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK))
 268                 return true;
 269
 270         return false;
 271 }
 272
 273 #if __OS_HAS_AGP
 274 static unsigned long
 275 get_agp_mode(struct drm_device *dev, unsigned long mode)
 276 {
 277         struct drm_nouveau_private *dev_priv = dev->dev_private;
 278
 279         /*
 280          * FW seems to be broken on nv18, it makes the card lock up
 281          * randomly.
 282          */
 283         if (dev_priv->chipset == 0x18)
 284                 mode &= ~PCI_AGP_COMMAND_FW;
 285
 286         /*
 287          * AGP mode set in the command line.
 288          */
 289         if (nouveau_agpmode > 0) {
 290                 bool agpv3 = mode & 0x8;
 291                 int rate = agpv3 ? nouveau_agpmode / 4 : nouveau_agpmode;
 292
 293                 mode = (mode & ~0x7) | (rate & 0x7);
 294         }
 295
 296         return mode;
 297 }
 298 #endif
 299
 300 int
 301 nouveau_mem_reset_agp(struct drm_device *dev)
 302 {
 303 #if __OS_HAS_AGP
 304         uint32_t saved_pci_nv_1, pmc_enable;
 305         int ret;
 306
 307         /* First of all, disable fast writes, otherwise if it's
 308          * already enabled in the AGP bridge and we disable the card's
 309          * AGP controller we might be locking ourselves out of it. */
 310         if ((nv_rd32(dev, NV04_PBUS_PCI_NV_19) |
 311              dev->agp->mode) & PCI_AGP_COMMAND_FW) {
 312                 struct drm_agp_info info;
 313                 struct drm_agp_mode mode;
 314
 315                 ret = drm_agp_info(dev, &info);
 316                 if (ret)
 317                         return ret;
 318
 319                 mode.mode = get_agp_mode(dev, info.mode) & ~PCI_AGP_COMMAND_FW;
 320                 ret = drm_agp_enable(dev, mode);
 321                 if (ret)
 322                         return ret;
 323         }
 324
 325         saved_pci_nv_1 = nv_rd32(dev, NV04_PBUS_PCI_NV_1);
 326
 327         /* clear busmaster bit */
 328         nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1 & ~0x4);
 329         /* disable AGP */
 330         nv_wr32(dev, NV04_PBUS_PCI_NV_19, 0);
 331
 332         /* power cycle pgraph, if enabled */
 333         pmc_enable = nv_rd32(dev, NV03_PMC_ENABLE);
 334         if (pmc_enable & NV_PMC_ENABLE_PGRAPH) {
 335                 nv_wr32(dev, NV03_PMC_ENABLE,
 336                                 pmc_enable & ~NV_PMC_ENABLE_PGRAPH);
 337                 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
 338                                 NV_PMC_ENABLE_PGRAPH);
 339         }
 340
 341         /* and restore (gives effect of resetting AGP) */
 342         nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1);
 343 #endif
 344
 345         return 0;
 346 }
 347
 348 int
 349 nouveau_mem_init_agp(struct drm_device *dev)
 350 {
 351 #if __OS_HAS_AGP
 352         struct drm_nouveau_private *dev_priv = dev->dev_private;
 353         struct drm_agp_info info;
 354         struct drm_agp_mode mode;
 355         int ret;
 356
 357         if (!dev->agp->acquired) {
 358                 ret = drm_agp_acquire(dev);
 359                 if (ret) {
 360                         NV_ERROR(dev, "Unable to acquire AGP: %d\n", ret);
 361                         return ret;
 362                 }
 363         }
 364
 365         nouveau_mem_reset_agp(dev);
 366
 367         ret = drm_agp_info(dev, &info);
 368         if (ret) {
 369                 NV_ERROR(dev, "Unable to get AGP info: %d\n", ret);
 370                 return ret;
 371         }
 372
 373         /* see agp.h for the AGPSTAT_* modes available */
 374         mode.mode = get_agp_mode(dev, info.mode);
 375         ret = drm_agp_enable(dev, mode);
 376         if (ret) {
 377                 NV_ERROR(dev, "Unable to enable AGP: %d\n", ret);
 378                 return ret;
 379         }
 380
 381         dev_priv->gart_info.type        = NOUVEAU_GART_AGP;
 382         dev_priv->gart_info.aper_base   = info.aperture_base;
 383         dev_priv->gart_info.aper_size   = info.aperture_size;
 384 #endif
 385         return 0;
 386 }
 387
 388 int
 389 nouveau_mem_vram_init(struct drm_device *dev)
 390 {
 391         struct drm_nouveau_private *dev_priv = dev->dev_private;
 392         struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
 393         int ret, dma_bits;
 394
 395         dma_bits = 32;
 396         if (dev_priv->card_type >= NV_50) {
 397                 if (pci_dma_supported(dev->pdev, DMA_BIT_MASK(40)))
 398                         dma_bits = 40;
 399         } else
 400         if (0 && pci_is_pcie(dev->pdev) &&
 401             dev_priv->chipset  > 0x40 &&
 402             dev_priv->chipset != 0x45) {
 403                 if (pci_dma_supported(dev->pdev, DMA_BIT_MASK(39)))
 404                         dma_bits = 39;
 405         }
 406
 407         ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits));
 408         if (ret)
 409                 return ret;
 410         ret = pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits));
 411         if (ret) {
 412                 /* Reset to default value. */
 413                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(32));
 414         }
 415
 416
 417         ret = nouveau_ttm_global_init(dev_priv);
 418         if (ret)
 419                 return ret;
 420
 421         ret = ttm_bo_device_init(&dev_priv->ttm.bdev,
 422                                  dev_priv->ttm.bo_global_ref.ref.object,
 423                                  &nouveau_bo_driver, DRM_FILE_PAGE_OFFSET,
 424                                  dma_bits <= 32 ? true : false);
 425         if (ret) {
 426                 NV_ERROR(dev, "Error initialising bo driver: %d\n", ret);
 427                 return ret;
 428         }
 429
 430         NV_INFO(dev, "Detected %dMiB VRAM\n", (int)(dev_priv->vram_size >> 20));
 431         if (dev_priv->vram_sys_base) {
 432                 NV_INFO(dev, "Stolen system memory at: 0x%010llx\n",
 433                         dev_priv->vram_sys_base);
 434         }
 435
 436         dev_priv->fb_available_size = dev_priv->vram_size;
 437         dev_priv->fb_mappable_pages = dev_priv->fb_available_size;
 438         if (dev_priv->fb_mappable_pages > pci_resource_len(dev->pdev, 1))
 439                 dev_priv->fb_mappable_pages = pci_resource_len(dev->pdev, 1);
 440         dev_priv->fb_mappable_pages >>= PAGE_SHIFT;
 441
 442         dev_priv->fb_available_size -= dev_priv->ramin_rsvd_vram;
 443         dev_priv->fb_aper_free = dev_priv->fb_available_size;
 444
 445         /* mappable vram */
 446         ret = ttm_bo_init_mm(bdev, TTM_PL_VRAM,
 447                              dev_priv->fb_available_size >> PAGE_SHIFT);
 448         if (ret) {
 449                 NV_ERROR(dev, "Failed VRAM mm init: %d\n", ret);
 450                 return ret;
 451         }
 452
 453         if (dev_priv->card_type < NV_50) {
 454                 ret = nouveau_bo_new(dev, 256*1024, 0, TTM_PL_FLAG_VRAM,
 455                                      0, 0, &dev_priv->vga_ram);
 456                 if (ret == 0)
 457                         ret = nouveau_bo_pin(dev_priv->vga_ram,
 458                                              TTM_PL_FLAG_VRAM);
 459
 460                 if (ret) {
 461                         NV_WARN(dev, "failed to reserve VGA memory\n");
 462                         nouveau_bo_ref(NULL, &dev_priv->vga_ram);
 463                 }
 464         }
 465
 466         dev_priv->fb_mtrr = drm_mtrr_add(pci_resource_start(dev->pdev, 1),
 467                                          pci_resource_len(dev->pdev, 1),
 468                                          DRM_MTRR_WC);
 469         return 0;
 470 }
 471
 472 int
 473 nouveau_mem_gart_init(struct drm_device *dev)
 474 {
 475         struct drm_nouveau_private *dev_priv = dev->dev_private;
 476         struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
 477         int ret;
 478
 479         dev_priv->gart_info.type = NOUVEAU_GART_NONE;
 480
 481 #if !defined(__powerpc__) && !defined(__ia64__)
 482         if (drm_pci_device_is_agp(dev) && dev->agp && nouveau_agpmode) {
 483                 ret = nouveau_mem_init_agp(dev);
 484                 if (ret)
 485                         NV_ERROR(dev, "Error initialising AGP: %d\n", ret);
 486         }
 487 #endif
 488
 489         if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) {
 490                 ret = nouveau_sgdma_init(dev);
 491                 if (ret) {
 492                         NV_ERROR(dev, "Error initialising PCI(E): %d\n", ret);
 493                         return ret;
 494                 }
 495         }
 496
 497         NV_INFO(dev, "%d MiB GART (aperture)\n",
 498                 (int)(dev_priv->gart_info.aper_size >> 20));
 499         dev_priv->gart_info.aper_free = dev_priv->gart_info.aper_size;
 500
 501         ret = ttm_bo_init_mm(bdev, TTM_PL_TT,
 502                              dev_priv->gart_info.aper_size >> PAGE_SHIFT);
 503         if (ret) {
 504                 NV_ERROR(dev, "Failed TT mm init: %d\n", ret);
 505                 return ret;
 506         }
 507
 508         return 0;
 509 }
 510
 511 /* XXX: For now a dummy. More samples required, possibly even a card
 512  * Called from nouveau_perf.c */
 513 void nv30_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr,
 514                                                         struct nouveau_pm_tbl_entry *e, uint8_t magic_number,
 515                                                         struct nouveau_pm_memtiming *timing) {
 516
 517         NV_DEBUG(dev,"Timing entry format unknown, please contact nouveau developers");
 518 }
 519
 520 void nv40_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr,
 521                                                         struct nouveau_pm_tbl_entry *e, uint8_t magic_number,
 522                                                         struct nouveau_pm_memtiming *timing) {
 523
 524         timing->reg_0 = (e->tRC << 24 | e->tRFC << 16 | e->tRAS << 8 | e->tRP);
 525
 526         /* XXX: I don't trust the -1's and +1's... they must come
 527          *      from somewhere! */
 528         timing->reg_1 = (e->tWR + 2 + magic_number) << 24 |
 529                                   1 << 16 |
 530                                   (e->tUNK_1 + 2 + magic_number) << 8 |
 531                                   (e->tCL + 2 - magic_number);
 532         timing->reg_2 = (magic_number << 24 | e->tUNK_12 << 16 | e->tUNK_11 << 8 | e->tUNK_10);
 533         timing->reg_2 |= 0x20200000;
 534
 535         NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x\n", timing->id,
 536                  timing->reg_0, timing->reg_1,timing->reg_2);
 537 }
 538
 539 void nv50_mem_timing_entry(struct drm_device *dev, struct bit_entry *P, struct nouveau_pm_tbl_header *hdr,
 540                                                         struct nouveau_pm_tbl_entry *e, uint8_t magic_number,struct nouveau_pm_memtiming *timing) {
 541         struct drm_nouveau_private *dev_priv = dev->dev_private;
 542
 543         uint8_t unk18 = 1,
 544                 unk19 = 1,
 545                 unk20 = 0,
 546                 unk21 = 0;
 547
 548         switch (min(hdr->entry_len, (u8) 22)) {
 549         case 22:
 550                 unk21 = e->tUNK_21;
 551         case 21:
 552                 unk20 = e->tUNK_20;
 553         case 20:
 554                 unk19 = e->tUNK_19;
 555         case 19:
 556                 unk18 = e->tUNK_18;
 557                 break;
 558         }
 559
 560         timing->reg_0 = (e->tRC << 24 | e->tRFC << 16 | e->tRAS << 8 | e->tRP);
 561
 562         /* XXX: I don't trust the -1's and +1's... they must come
 563          *      from somewhere! */
 564         timing->reg_1 = (e->tWR + unk19 + 1 + magic_number) << 24 |
 565                                   max(unk18, (u8) 1) << 16 |
 566                                   (e->tUNK_1 + unk19 + 1 + magic_number) << 8;
 567         if (dev_priv->chipset == 0xa8) {
 568                 timing->reg_1 |= (e->tCL - 1);
 569         } else {
 570                 timing->reg_1 |= (e->tCL + 2 - magic_number);
 571         }
 572         timing->reg_2 = (e->tUNK_12 << 16 | e->tUNK_11 << 8 | e->tUNK_10);
 573
 574         timing->reg_5 = (e->tRAS << 24 | e->tRC);
 575         timing->reg_5 += max(e->tUNK_10, e->tUNK_11) << 16;
 576
 577         if (P->version == 1) {
 578                 timing->reg_2 |= magic_number << 24;
 579                 timing->reg_3 = (0x14 + e->tCL) << 24 |
 580                                                 0x16 << 16 |
 581                                                 (e->tCL - 1) << 8 |
 582                                                 (e->tCL - 1);
 583                 timing->reg_4 = (nv_rd32(dev,0x10022c) & 0xffff0000) | e->tUNK_13 << 8  | e->tUNK_13;
 584                 timing->reg_5 |= (e->tCL + 2) << 8;
 585                 timing->reg_7 = 0x4000202 | (e->tCL - 1) << 16;
 586         } else {
 587                 timing->reg_2 |= (unk19 - 1) << 24;
 588                 /* XXX: reg_10022c for recentish cards pretty much unknown*/
 589                 timing->reg_3 = e->tCL - 1;
 590                 timing->reg_4 = (unk20 << 24 | unk21 << 16 |
 591                                                         e->tUNK_13 << 8  | e->tUNK_13);
 592                 /* XXX: +6? */
 593                 timing->reg_5 |= (unk19 + 6) << 8;
 594
 595                 /* XXX: reg_10023c currently unknown
 596                  * 10023c seen as 06xxxxxx, 0bxxxxxx or 0fxxxxxx */
 597                 timing->reg_7 = 0x202;
 598         }
 599
 600         NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x %08x\n", timing->id,
 601                  timing->reg_0, timing->reg_1,
 602                  timing->reg_2, timing->reg_3);
 603         NV_DEBUG(dev, "         230: %08x %08x %08x %08x\n",
 604                  timing->reg_4, timing->reg_5,
 605                  timing->reg_6, timing->reg_7);
 606         NV_DEBUG(dev, "         240: %08x\n", timing->reg_8);
 607 }
 608
 609 void nvc0_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr,
 610                                                         struct nouveau_pm_tbl_entry *e, struct nouveau_pm_memtiming *timing) {
 611         timing->reg_0 = (e->tRC << 24 | (e->tRFC & 0x7f) << 17 | e->tRAS << 8 | e->tRP);
 612         timing->reg_1 = (nv_rd32(dev,0x10f294) & 0xff000000) | (e->tUNK_11&0x0f) << 20 | (e->tUNK_19 << 7) | (e->tCL & 0x0f);
 613         timing->reg_2 = (nv_rd32(dev,0x10f298) & 0xff0000ff) | e->tWR << 16 | e->tUNK_1 << 8;
 614         timing->reg_3 = e->tUNK_20 << 9 | e->tUNK_13;
 615         timing->reg_4 = (nv_rd32(dev,0x10f2a0) & 0xfff000ff) | e->tUNK_12 << 15;
 616         NV_DEBUG(dev, "Entry %d: 290: %08x %08x %08x %08x\n", timing->id,
 617                  timing->reg_0, timing->reg_1,
 618                  timing->reg_2, timing->reg_3);
 619         NV_DEBUG(dev, "         2a0: %08x %08x %08x %08x\n",
 620                  timing->reg_4, timing->reg_5,
 621                  timing->reg_6, timing->reg_7);
 622 }
 623
 624 /**
 625  * Processes the Memory Timing BIOS table, stores generated
 626  * register values
 627  * @pre init scripts were run, memtiming regs are initialized
 628  */
 629 void
 630 nouveau_mem_timing_init(struct drm_device *dev)
 631 {
 632         struct drm_nouveau_private *dev_priv = dev->dev_private;
 633         struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
 634         struct nouveau_pm_memtimings *memtimings = &pm->memtimings;
 635         struct nvbios *bios = &dev_priv->vbios;
 636         struct bit_entry P;
 637         struct nouveau_pm_tbl_header *hdr = NULL;
 638         uint8_t magic_number;
 639         u8 *entry;
 640         int i;
 641
 642         if (bios->type == NVBIOS_BIT) {
 643                 if (bit_table(dev, 'P', &P))
 644                         return;
 645
 646                 if (P.version == 1)
 647                         hdr = (struct nouveau_pm_tbl_header *) ROMPTR(dev, P.data[4]);
 648                 else
 649                 if (P.version == 2)
 650                         hdr = (struct nouveau_pm_tbl_header *) ROMPTR(dev, P.data[8]);
 651                 else {
 652                         NV_WARN(dev, "unknown mem for BIT P %d\n", P.version);
 653                 }
 654         } else {
 655                 NV_DEBUG(dev, "BMP version too old for memory\n");
 656                 return;
 657         }
 658
 659         if (!hdr) {
 660                 NV_DEBUG(dev, "memory timing table pointer invalid\n");
 661                 return;
 662         }
 663
 664         if (hdr->version != 0x10) {
 665                 NV_WARN(dev, "memory timing table 0x%02x unknown\n", hdr->version);
 666                 return;
 667         }
 668
 669         /* validate record length */
 670         if (hdr->entry_len < 15) {
 671                 NV_ERROR(dev, "mem timing table length unknown: %d\n", hdr->entry_len);
 672                 return;
 673         }
 674
 675         /* parse vbios entries into common format */
 676         memtimings->timing =
 677                 kcalloc(hdr->entry_cnt, sizeof(*memtimings->timing), GFP_KERNEL);
 678         if (!memtimings->timing)
 679                 return;
 680
 681         /* Get "some number" from the timing reg for NV_40 and NV_50
 682          * Used in calculations later... source unknown */
 683         magic_number = 0;
 684         if (P.version == 1) {
 685                 magic_number = (nv_rd32(dev, 0x100228) & 0x0f000000) >> 24;
 686         }
 687
 688         entry = (u8*) hdr + hdr->header_len;
 689         for (i = 0; i < hdr->entry_cnt; i++, entry += hdr->entry_len) {
 690                 struct nouveau_pm_memtiming *timing = &pm->memtimings.timing[i];
 691                 if (entry[0] == 0)
 692                         continue;
 693
 694                 timing->id = i;
 695                 timing->WR = entry[0];
 696                 timing->CL = entry[2];
 697
 698                 if(dev_priv->card_type <= NV_40) {
 699                         nv40_mem_timing_entry(dev,hdr,(struct nouveau_pm_tbl_entry*) entry,magic_number,&pm->memtimings.timing[i]);
 700                 } else if(dev_priv->card_type == NV_50){
 701                         nv50_mem_timing_entry(dev,&P,hdr,(struct nouveau_pm_tbl_entry*) entry,magic_number,&pm->memtimings.timing[i]);
 702                 } else if(dev_priv->card_type == NV_C0) {
 703                         nvc0_mem_timing_entry(dev,hdr,(struct nouveau_pm_tbl_entry*) entry,&pm->memtimings.timing[i]);
 704                 }
 705         }
 706
 707         memtimings->nr_timing = hdr->entry_cnt;
 708         memtimings->supported = P.version == 1;
 709 }
 710
 711 void
 712 nouveau_mem_timing_fini(struct drm_device *dev)
 713 {
 714         struct drm_nouveau_private *dev_priv = dev->dev_private;
 715         struct nouveau_pm_memtimings *mem = &dev_priv->engine.pm.memtimings;
 716
 717         if(mem->timing) {
 718                 kfree(mem->timing);
 719                 mem->timing = NULL;
 720         }
 721 }
 722
 723 static int
 724 nouveau_vram_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
 725 {
 726         /* nothing to do */
 727         return 0;
 728 }
 729
 730 static int
 731 nouveau_vram_manager_fini(struct ttm_mem_type_manager *man)
 732 {
 733         /* nothing to do */
 734         return 0;
 735 }
 736
 737 static inline void
 738 nouveau_mem_node_cleanup(struct nouveau_mem *node)
 739 {
 740         if (node->vma[0].node) {
 741                 nouveau_vm_unmap(&node->vma[0]);
 742                 nouveau_vm_put(&node->vma[0]);
 743         }
 744
 745         if (node->vma[1].node) {
 746                 nouveau_vm_unmap(&node->vma[1]);
 747                 nouveau_vm_put(&node->vma[1]);
 748         }
 749 }
 750
 751 static void
 752 nouveau_vram_manager_del(struct ttm_mem_type_manager *man,
 753                          struct ttm_mem_reg *mem)
 754 {
 755         struct drm_nouveau_private *dev_priv = nouveau_bdev(man->bdev);
 756         struct nouveau_vram_engine *vram = &dev_priv->engine.vram;
 757         struct drm_device *dev = dev_priv->dev;
 758
 759         nouveau_mem_node_cleanup(mem->mm_node);
 760         vram->put(dev, (struct nouveau_mem **)&mem->mm_node);
 761 }
 762
 763 static int
 764 nouveau_vram_manager_new(struct ttm_mem_type_manager *man,
 765                          struct ttm_buffer_object *bo,
 766                          struct ttm_placement *placement,
 767                          struct ttm_mem_reg *mem)
 768 {
 769         struct drm_nouveau_private *dev_priv = nouveau_bdev(man->bdev);
 770         struct nouveau_vram_engine *vram = &dev_priv->engine.vram;
 771         struct drm_device *dev = dev_priv->dev;
 772         struct nouveau_bo *nvbo = nouveau_bo(bo);
 773         struct nouveau_mem *node;
 774         u32 size_nc = 0;
 775         int ret;
 776
 777         if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG)
 778                 size_nc = 1 << nvbo->page_shift;
 779
 780         ret = vram->get(dev, mem->num_pages << PAGE_SHIFT,
 781                         mem->page_alignment << PAGE_SHIFT, size_nc,
 782                         (nvbo->tile_flags >> 8) & 0x3ff, &node);
 783         if (ret) {
 784                 mem->mm_node = NULL;
 785                 return (ret == -ENOSPC) ? 0 : ret;
 786         }
 787
 788         node->page_shift = nvbo->page_shift;
 789
 790         mem->mm_node = node;
 791         mem->start   = node->offset >> PAGE_SHIFT;
 792         return 0;
 793 }
 794
 795 void
 796 nouveau_vram_manager_debug(struct ttm_mem_type_manager *man, const char *prefix)
 797 {
 798         struct nouveau_mm *mm = man->priv;
 799         struct nouveau_mm_node *r;
 800         u32 total = 0, free = 0;
 801
 802         mutex_lock(&mm->mutex);
 803         list_for_each_entry(r, &mm->nodes, nl_entry) {
 804                 printk(KERN_DEBUG "%s %d: 0x%010llx 0x%010llx\n",
 805                        prefix, r->type, ((u64)r->offset << 12),
 806                        (((u64)r->offset + r->length) << 12));
 807
 808                 total += r->length;
 809                 if (!r->type)
 810                         free += r->length;
 811         }
 812         mutex_unlock(&mm->mutex);
 813
 814         printk(KERN_DEBUG "%s  total: 0x%010llx free: 0x%010llx\n",
 815                prefix, (u64)total << 12, (u64)free << 12);
 816         printk(KERN_DEBUG "%s  block: 0x%08x\n",
 817                prefix, mm->block_size << 12);
 818 }
 819
 820 const struct ttm_mem_type_manager_func nouveau_vram_manager = {
 821         nouveau_vram_manager_init,
 822         nouveau_vram_manager_fini,
 823         nouveau_vram_manager_new,
 824         nouveau_vram_manager_del,
 825         nouveau_vram_manager_debug
 826 };
 827
 828 static int
 829 nouveau_gart_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
 830 {
 831         return 0;
 832 }
 833
 834 static int
 835 nouveau_gart_manager_fini(struct ttm_mem_type_manager *man)
 836 {
 837         return 0;
 838 }
 839
 840 static void
 841 nouveau_gart_manager_del(struct ttm_mem_type_manager *man,
 842                          struct ttm_mem_reg *mem)
 843 {
 844         nouveau_mem_node_cleanup(mem->mm_node);
 845         kfree(mem->mm_node);
 846         mem->mm_node = NULL;
 847 }
 848
 849 static int
 850 nouveau_gart_manager_new(struct ttm_mem_type_manager *man,
 851                          struct ttm_buffer_object *bo,
 852                          struct ttm_placement *placement,
 853                          struct ttm_mem_reg *mem)
 854 {
 855         struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
 856         struct nouveau_mem *node;
 857
 858         if (unlikely((mem->num_pages << PAGE_SHIFT) >=
 859                      dev_priv->gart_info.aper_size))
 860                 return -ENOMEM;
 861
 862         node = kzalloc(sizeof(*node), GFP_KERNEL);
 863         if (!node)
 864                 return -ENOMEM;
 865         node->page_shift = 12;
 866
 867         mem->mm_node = node;
 868         mem->start   = 0;
 869         return 0;
 870 }
 871
 872 void
 873 nouveau_gart_manager_debug(struct ttm_mem_type_manager *man, const char *prefix)
 874 {
 875 }
 876
 877 const struct ttm_mem_type_manager_func nouveau_gart_manager = {
 878         nouveau_gart_manager_init,
 879         nouveau_gart_manager_fini,
 880         nouveau_gart_manager_new,
 881         nouveau_gart_manager_del,
 882         nouveau_gart_manager_debug
 883 };