drivers/gpu/drm/nouveau/nouveau_mem.c

   1 /*
   2  * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3  * Copyright 2005 Stephane Marchesin
   4  *
   5  * The Weather Channel (TM) funded Tungsten Graphics to develop the
   6  * initial release of the Radeon 8500 driver under the XFree86 license.
   7  * This notice must be preserved.
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  24  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  25  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  26  * DEALINGS IN THE SOFTWARE.
  27  *
  28  * Authors:
  29  *    Keith Whitwell <keith@tungstengraphics.com>
  30  */
  31
  32
  33 #include "drmP.h"
  34 #include "drm.h"
  35 #include "drm_sarea.h"
  36 #include "nouveau_drv.h"
  37
  38 /*
  39  * NV10-NV40 tiling helpers
  40  */
  41
  42 static void
  43 nv10_mem_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
  44                            uint32_t size, uint32_t pitch)
  45 {
  46         struct drm_nouveau_private *dev_priv = dev->dev_private;
  47         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
  48         struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
  49         struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
  50         struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
  51
  52         tile->addr = addr;
  53         tile->size = size;
  54         tile->used = !!pitch;
  55         nouveau_fence_unref((void **)&tile->fence);
  56
  57         if (!pfifo->cache_flush(dev))
  58                 return;
  59
  60         pfifo->reassign(dev, false);
  61         pfifo->cache_flush(dev);
  62         pfifo->cache_pull(dev, false);
  63
  64         nouveau_wait_for_idle(dev);
  65
  66         pgraph->set_region_tiling(dev, i, addr, size, pitch);
  67         pfb->set_region_tiling(dev, i, addr, size, pitch);
  68
  69         pfifo->cache_pull(dev, true);
  70         pfifo->reassign(dev, true);
  71 }
  72
  73 struct nouveau_tile_reg *
  74 nv10_mem_set_tiling(struct drm_device *dev, uint32_t addr, uint32_t size,
  75                     uint32_t pitch)
  76 {
  77         struct drm_nouveau_private *dev_priv = dev->dev_private;
  78         struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
  79         struct nouveau_tile_reg *tile = dev_priv->tile.reg, *found = NULL;
  80         int i;
  81
  82         spin_lock(&dev_priv->tile.lock);
  83
  84         for (i = 0; i < pfb->num_tiles; i++) {
  85                 if (tile[i].used)
  86                         /* Tile region in use. */
  87                         continue;
  88
  89                 if (tile[i].fence &&
  90                     !nouveau_fence_signalled(tile[i].fence, NULL))
  91                         /* Pending tile region. */
  92                         continue;
  93
  94                 if (max(tile[i].addr, addr) <
  95                     min(tile[i].addr + tile[i].size, addr + size))
  96                         /* Kill an intersecting tile region. */
  97                         nv10_mem_set_region_tiling(dev, i, 0, 0, 0);
  98
  99                 if (pitch && !found) {
 100                         /* Free tile region. */
 101                         nv10_mem_set_region_tiling(dev, i, addr, size, pitch);
 102                         found = &tile[i];
 103                 }
 104         }
 105
 106         spin_unlock(&dev_priv->tile.lock);
 107
 108         return found;
 109 }
 110
 111 void
 112 nv10_mem_expire_tiling(struct drm_device *dev, struct nouveau_tile_reg *tile,
 113                        struct nouveau_fence *fence)
 114 {
 115         if (fence) {
 116                 /* Mark it as pending. */
 117                 tile->fence = fence;
 118                 nouveau_fence_ref(fence);
 119         }
 120
 121         tile->used = false;
 122 }
 123
 124 /*
 125  * NV50 VM helpers
 126  */
 127 int
 128 nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size,
 129                         uint32_t flags, uint64_t phys)
 130 {
 131         struct drm_nouveau_private *dev_priv = dev->dev_private;
 132         struct nouveau_gpuobj *pgt;
 133         unsigned block;
 134         int i;
 135
 136         virt = ((virt - dev_priv->vm_vram_base) >> 16) << 1;
 137         size = (size >> 16) << 1;
 138
 139         phys |= ((uint64_t)flags << 32);
 140         phys |= 1;
 141         if (dev_priv->vram_sys_base) {
 142                 phys += dev_priv->vram_sys_base;
 143                 phys |= 0x30;
 144         }
 145
 146         while (size) {
 147                 unsigned offset_h = upper_32_bits(phys);
 148                 unsigned offset_l = lower_32_bits(phys);
 149                 unsigned pte, end;
 150
 151                 for (i = 7; i >= 0; i--) {
 152                         block = 1 << (i + 1);
 153                         if (size >= block && !(virt & (block - 1)))
 154                                 break;
 155                 }
 156                 offset_l |= (i << 7);
 157
 158                 phys += block << 15;
 159                 size -= block;
 160
 161                 while (block) {
 162                         pgt = dev_priv->vm_vram_pt[virt >> 14];
 163                         pte = virt & 0x3ffe;
 164
 165                         end = pte + block;
 166                         if (end > 16384)
 167                                 end = 16384;
 168                         block -= (end - pte);
 169                         virt  += (end - pte);
 170
 171                         while (pte < end) {
 172                                 nv_wo32(pgt, (pte * 4) + 0, offset_l);
 173                                 nv_wo32(pgt, (pte * 4) + 4, offset_h);
 174                                 pte += 2;
 175                         }
 176                 }
 177         }
 178         dev_priv->engine.instmem.flush(dev);
 179
 180         nv50_vm_flush(dev, 5);
 181         nv50_vm_flush(dev, 0);
 182         nv50_vm_flush(dev, 4);
 183         nv50_vm_flush(dev, 6);
 184         return 0;
 185 }
 186
 187 void
 188 nv50_mem_vm_unbind(struct drm_device *dev, uint64_t virt, uint32_t size)
 189 {
 190         struct drm_nouveau_private *dev_priv = dev->dev_private;
 191         struct nouveau_gpuobj *pgt;
 192         unsigned pages, pte, end;
 193
 194         virt -= dev_priv->vm_vram_base;
 195         pages = (size >> 16) << 1;
 196
 197         while (pages) {
 198                 pgt = dev_priv->vm_vram_pt[virt >> 29];
 199                 pte = (virt & 0x1ffe0000ULL) >> 15;
 200
 201                 end = pte + pages;
 202                 if (end > 16384)
 203                         end = 16384;
 204                 pages -= (end - pte);
 205                 virt  += (end - pte) << 15;
 206
 207                 while (pte < end) {
 208                         nv_wo32(pgt, (pte * 4), 0);
 209                         pte++;
 210                 }
 211         }
 212         dev_priv->engine.instmem.flush(dev);
 213
 214         nv50_vm_flush(dev, 5);
 215         nv50_vm_flush(dev, 0);
 216         nv50_vm_flush(dev, 4);
 217         nv50_vm_flush(dev, 6);
 218 }
 219
 220 /*
 221  * Cleanup everything
 222  */
 223 void
 224 nouveau_mem_vram_fini(struct drm_device *dev)
 225 {
 226         struct drm_nouveau_private *dev_priv = dev->dev_private;
 227
 228         nouveau_bo_unpin(dev_priv->vga_ram);
 229         nouveau_bo_ref(NULL, &dev_priv->vga_ram);
 230
 231         ttm_bo_device_release(&dev_priv->ttm.bdev);
 232
 233         nouveau_ttm_global_release(dev_priv);
 234
 235         if (dev_priv->fb_mtrr >= 0) {
 236                 drm_mtrr_del(dev_priv->fb_mtrr,
 237                              pci_resource_start(dev->pdev, 1),
 238                              pci_resource_len(dev->pdev, 1), DRM_MTRR_WC);
 239                 dev_priv->fb_mtrr = -1;
 240         }
 241 }
 242
 243 void
 244 nouveau_mem_gart_fini(struct drm_device *dev)
 245 {
 246         nouveau_sgdma_takedown(dev);
 247
 248         if (drm_core_has_AGP(dev) && dev->agp) {
 249                 struct drm_agp_mem *entry, *tempe;
 250
 251                 /* Remove AGP resources, but leave dev->agp
 252                    intact until drv_cleanup is called. */
 253                 list_for_each_entry_safe(entry, tempe, &dev->agp->memory, head) {
 254                         if (entry->bound)
 255                                 drm_unbind_agp(entry->memory);
 256                         drm_free_agp(entry->memory, entry->pages);
 257                         kfree(entry);
 258                 }
 259                 INIT_LIST_HEAD(&dev->agp->memory);
 260
 261                 if (dev->agp->acquired)
 262                         drm_agp_release(dev);
 263
 264                 dev->agp->acquired = 0;
 265                 dev->agp->enabled = 0;
 266         }
 267 }
 268
 269 static uint32_t
 270 nouveau_mem_detect_nv04(struct drm_device *dev)
 271 {
 272         uint32_t boot0 = nv_rd32(dev, NV04_PFB_BOOT_0);
 273
 274         if (boot0 & 0x00000100)
 275                 return (((boot0 >> 12) & 0xf) * 2 + 2) * 1024 * 1024;
 276
 277         switch (boot0 & NV04_PFB_BOOT_0_RAM_AMOUNT) {
 278         case NV04_PFB_BOOT_0_RAM_AMOUNT_32MB:
 279                 return 32 * 1024 * 1024;
 280         case NV04_PFB_BOOT_0_RAM_AMOUNT_16MB:
 281                 return 16 * 1024 * 1024;
 282         case NV04_PFB_BOOT_0_RAM_AMOUNT_8MB:
 283                 return 8 * 1024 * 1024;
 284         case NV04_PFB_BOOT_0_RAM_AMOUNT_4MB:
 285                 return 4 * 1024 * 1024;
 286         }
 287
 288         return 0;
 289 }
 290
 291 static uint32_t
 292 nouveau_mem_detect_nforce(struct drm_device *dev)
 293 {
 294         struct drm_nouveau_private *dev_priv = dev->dev_private;
 295         struct pci_dev *bridge;
 296         uint32_t mem;
 297
 298         bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1));
 299         if (!bridge) {
 300                 NV_ERROR(dev, "no bridge device\n");
 301                 return 0;
 302         }
 303
 304         if (dev_priv->flags & NV_NFORCE) {
 305                 pci_read_config_dword(bridge, 0x7C, &mem);
 306                 return (uint64_t)(((mem >> 6) & 31) + 1)*1024*1024;
 307         } else
 308         if (dev_priv->flags & NV_NFORCE2) {
 309                 pci_read_config_dword(bridge, 0x84, &mem);
 310                 return (uint64_t)(((mem >> 4) & 127) + 1)*1024*1024;
 311         }
 312
 313         NV_ERROR(dev, "impossible!\n");
 314         return 0;
 315 }
 316
 317 static void
 318 nv50_vram_preinit(struct drm_device *dev)
 319 {
 320         struct drm_nouveau_private *dev_priv = dev->dev_private;
 321         int i, parts, colbits, rowbitsa, rowbitsb, banks;
 322         u64 rowsize, predicted;
 323         u32 r0, r4, rt, ru;
 324
 325         r0 = nv_rd32(dev, 0x100200);
 326         r4 = nv_rd32(dev, 0x100204);
 327         rt = nv_rd32(dev, 0x100250);
 328         ru = nv_rd32(dev, 0x001540);
 329         NV_DEBUG(dev, "memcfg 0x%08x 0x%08x 0x%08x 0x%08x\n", r0, r4, rt, ru);
 330
 331         for (i = 0, parts = 0; i < 8; i++) {
 332                 if (ru & (0x00010000 << i))
 333                         parts++;
 334         }
 335
 336         colbits  =  (r4 & 0x0000f000) >> 12;
 337         rowbitsa = ((r4 & 0x000f0000) >> 16) + 8;
 338         rowbitsb = ((r4 & 0x00f00000) >> 20) + 8;
 339         banks    = ((r4 & 0x01000000) ? 8 : 4);
 340
 341         rowsize = parts * banks * (1 << colbits) * 8;
 342         predicted = rowsize << rowbitsa;
 343         if (r0 & 0x00000004)
 344                 predicted += rowsize << rowbitsb;
 345
 346         if (predicted != dev_priv->vram_size) {
 347                 NV_WARN(dev, "memory controller reports %dMiB VRAM\n",
 348                         (u32)(dev_priv->vram_size >> 20));
 349                 NV_WARN(dev, "we calculated %dMiB VRAM\n",
 350                         (u32)(predicted >> 20));
 351         }
 352
 353         dev_priv->vram_rblock_size = rowsize >> 12;
 354         if (rt & 1)
 355                 dev_priv->vram_rblock_size *= 3;
 356
 357         NV_DEBUG(dev, "rblock %lld bytes\n",
 358                  (u64)dev_priv->vram_rblock_size << 12);
 359 }
 360
 361 static void
 362 nvaa_vram_preinit(struct drm_device *dev)
 363 {
 364         struct drm_nouveau_private *dev_priv = dev->dev_private;
 365
 366         /* To our knowledge, there's no large scale reordering of pages
 367          * that occurs on IGP chipsets.
 368          */
 369         dev_priv->vram_rblock_size = 1;
 370 }
 371
 372 static int
 373 nouveau_mem_detect(struct drm_device *dev)
 374 {
 375         struct drm_nouveau_private *dev_priv = dev->dev_private;
 376
 377         if (dev_priv->card_type == NV_04) {
 378                 dev_priv->vram_size = nouveau_mem_detect_nv04(dev);
 379         } else
 380         if (dev_priv->flags & (NV_NFORCE | NV_NFORCE2)) {
 381                 dev_priv->vram_size = nouveau_mem_detect_nforce(dev);
 382         } else
 383         if (dev_priv->card_type < NV_50) {
 384                 dev_priv->vram_size  = nv_rd32(dev, NV04_PFB_FIFO_DATA);
 385                 dev_priv->vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
 386         } else
 387         if (dev_priv->card_type < NV_C0) {
 388                 dev_priv->vram_size = nv_rd32(dev, NV04_PFB_FIFO_DATA);
 389                 dev_priv->vram_size |= (dev_priv->vram_size & 0xff) << 32;
 390                 dev_priv->vram_size &= 0xffffffff00ll;
 391
 392                 switch (dev_priv->chipset) {
 393                 case 0xaa:
 394                 case 0xac:
 395                 case 0xaf:
 396                         dev_priv->vram_sys_base = nv_rd32(dev, 0x100e10);
 397                         dev_priv->vram_sys_base <<= 12;
 398                         nvaa_vram_preinit(dev);
 399                         break;
 400                 default:
 401                         nv50_vram_preinit(dev);
 402                         break;
 403                 }
 404         } else {
 405                 dev_priv->vram_size  = nv_rd32(dev, 0x10f20c) << 20;
 406                 dev_priv->vram_size *= nv_rd32(dev, 0x121c74);
 407         }
 408
 409         NV_INFO(dev, "Detected %dMiB VRAM\n", (int)(dev_priv->vram_size >> 20));
 410         if (dev_priv->vram_sys_base) {
 411                 NV_INFO(dev, "Stolen system memory at: 0x%010llx\n",
 412                         dev_priv->vram_sys_base);
 413         }
 414
 415         if (dev_priv->vram_size)
 416                 return 0;
 417         return -ENOMEM;
 418 }
 419
 420 #if __OS_HAS_AGP
 421 static unsigned long
 422 get_agp_mode(struct drm_device *dev, unsigned long mode)
 423 {
 424         struct drm_nouveau_private *dev_priv = dev->dev_private;
 425
 426         /*
 427          * FW seems to be broken on nv18, it makes the card lock up
 428          * randomly.
 429          */
 430         if (dev_priv->chipset == 0x18)
 431                 mode &= ~PCI_AGP_COMMAND_FW;
 432
 433         /*
 434          * AGP mode set in the command line.
 435          */
 436         if (nouveau_agpmode > 0) {
 437                 bool agpv3 = mode & 0x8;
 438                 int rate = agpv3 ? nouveau_agpmode / 4 : nouveau_agpmode;
 439
 440                 mode = (mode & ~0x7) | (rate & 0x7);
 441         }
 442
 443         return mode;
 444 }
 445 #endif
 446
 447 int
 448 nouveau_mem_reset_agp(struct drm_device *dev)
 449 {
 450 #if __OS_HAS_AGP
 451         uint32_t saved_pci_nv_1, pmc_enable;
 452         int ret;
 453
 454         /* First of all, disable fast writes, otherwise if it's
 455          * already enabled in the AGP bridge and we disable the card's
 456          * AGP controller we might be locking ourselves out of it. */
 457         if ((nv_rd32(dev, NV04_PBUS_PCI_NV_19) |
 458              dev->agp->mode) & PCI_AGP_COMMAND_FW) {
 459                 struct drm_agp_info info;
 460                 struct drm_agp_mode mode;
 461
 462                 ret = drm_agp_info(dev, &info);
 463                 if (ret)
 464                         return ret;
 465
 466                 mode.mode = get_agp_mode(dev, info.mode) & ~PCI_AGP_COMMAND_FW;
 467                 ret = drm_agp_enable(dev, mode);
 468                 if (ret)
 469                         return ret;
 470         }
 471
 472         saved_pci_nv_1 = nv_rd32(dev, NV04_PBUS_PCI_NV_1);
 473
 474         /* clear busmaster bit */
 475         nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1 & ~0x4);
 476         /* disable AGP */
 477         nv_wr32(dev, NV04_PBUS_PCI_NV_19, 0);
 478
 479         /* power cycle pgraph, if enabled */
 480         pmc_enable = nv_rd32(dev, NV03_PMC_ENABLE);
 481         if (pmc_enable & NV_PMC_ENABLE_PGRAPH) {
 482                 nv_wr32(dev, NV03_PMC_ENABLE,
 483                                 pmc_enable & ~NV_PMC_ENABLE_PGRAPH);
 484                 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
 485                                 NV_PMC_ENABLE_PGRAPH);
 486         }
 487
 488         /* and restore (gives effect of resetting AGP) */
 489         nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1);
 490 #endif
 491
 492         return 0;
 493 }
 494
 495 int
 496 nouveau_mem_init_agp(struct drm_device *dev)
 497 {
 498 #if __OS_HAS_AGP
 499         struct drm_nouveau_private *dev_priv = dev->dev_private;
 500         struct drm_agp_info info;
 501         struct drm_agp_mode mode;
 502         int ret;
 503
 504         if (!dev->agp->acquired) {
 505                 ret = drm_agp_acquire(dev);
 506                 if (ret) {
 507                         NV_ERROR(dev, "Unable to acquire AGP: %d\n", ret);
 508                         return ret;
 509                 }
 510         }
 511
 512         nouveau_mem_reset_agp(dev);
 513
 514         ret = drm_agp_info(dev, &info);
 515         if (ret) {
 516                 NV_ERROR(dev, "Unable to get AGP info: %d\n", ret);
 517                 return ret;
 518         }
 519
 520         /* see agp.h for the AGPSTAT_* modes available */
 521         mode.mode = get_agp_mode(dev, info.mode);
 522         ret = drm_agp_enable(dev, mode);
 523         if (ret) {
 524                 NV_ERROR(dev, "Unable to enable AGP: %d\n", ret);
 525                 return ret;
 526         }
 527
 528         dev_priv->gart_info.type        = NOUVEAU_GART_AGP;
 529         dev_priv->gart_info.aper_base   = info.aperture_base;
 530         dev_priv->gart_info.aper_size   = info.aperture_size;
 531 #endif
 532         return 0;
 533 }
 534
 535 int
 536 nouveau_mem_vram_init(struct drm_device *dev)
 537 {
 538         struct drm_nouveau_private *dev_priv = dev->dev_private;
 539         struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
 540         int ret, dma_bits;
 541
 542         if (dev_priv->card_type >= NV_50 &&
 543             pci_dma_supported(dev->pdev, DMA_BIT_MASK(40)))
 544                 dma_bits = 40;
 545         else
 546                 dma_bits = 32;
 547
 548         ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits));
 549         if (ret)
 550                 return ret;
 551
 552         ret = nouveau_mem_detect(dev);
 553         if (ret)
 554                 return ret;
 555
 556         dev_priv->fb_phys = pci_resource_start(dev->pdev, 1);
 557
 558         ret = nouveau_ttm_global_init(dev_priv);
 559         if (ret)
 560                 return ret;
 561
 562         ret = ttm_bo_device_init(&dev_priv->ttm.bdev,
 563                                  dev_priv->ttm.bo_global_ref.ref.object,
 564                                  &nouveau_bo_driver, DRM_FILE_PAGE_OFFSET,
 565                                  dma_bits <= 32 ? true : false);
 566         if (ret) {
 567                 NV_ERROR(dev, "Error initialising bo driver: %d\n", ret);
 568                 return ret;
 569         }
 570
 571         spin_lock_init(&dev_priv->tile.lock);
 572
 573         dev_priv->fb_available_size = dev_priv->vram_size;
 574         dev_priv->fb_mappable_pages = dev_priv->fb_available_size;
 575         if (dev_priv->fb_mappable_pages > pci_resource_len(dev->pdev, 1))
 576                 dev_priv->fb_mappable_pages =
 577                         pci_resource_len(dev->pdev, 1);
 578         dev_priv->fb_mappable_pages >>= PAGE_SHIFT;
 579
 580         /* reserve space at end of VRAM for PRAMIN */
 581         if (dev_priv->chipset == 0x40 || dev_priv->chipset == 0x47 ||
 582             dev_priv->chipset == 0x49 || dev_priv->chipset == 0x4b)
 583                 dev_priv->ramin_rsvd_vram = (2 * 1024 * 1024);
 584         else
 585         if (dev_priv->card_type >= NV_40)
 586                 dev_priv->ramin_rsvd_vram = (1 * 1024 * 1024);
 587         else
 588                 dev_priv->ramin_rsvd_vram = (512 * 1024);
 589
 590         dev_priv->fb_available_size -= dev_priv->ramin_rsvd_vram;
 591         dev_priv->fb_aper_free = dev_priv->fb_available_size;
 592
 593         /* mappable vram */
 594         ret = ttm_bo_init_mm(bdev, TTM_PL_VRAM,
 595                              dev_priv->fb_available_size >> PAGE_SHIFT);
 596         if (ret) {
 597                 NV_ERROR(dev, "Failed VRAM mm init: %d\n", ret);
 598                 return ret;
 599         }
 600
 601         ret = nouveau_bo_new(dev, NULL, 256*1024, 0, TTM_PL_FLAG_VRAM,
 602                              0, 0, true, true, &dev_priv->vga_ram);
 603         if (ret == 0)
 604                 ret = nouveau_bo_pin(dev_priv->vga_ram, TTM_PL_FLAG_VRAM);
 605         if (ret) {
 606                 NV_WARN(dev, "failed to reserve VGA memory\n");
 607                 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
 608         }
 609
 610         dev_priv->fb_mtrr = drm_mtrr_add(pci_resource_start(dev->pdev, 1),
 611                                          pci_resource_len(dev->pdev, 1),
 612                                          DRM_MTRR_WC);
 613         return 0;
 614 }
 615
 616 int
 617 nouveau_mem_gart_init(struct drm_device *dev)
 618 {
 619         struct drm_nouveau_private *dev_priv = dev->dev_private;
 620         struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
 621         int ret;
 622
 623         dev_priv->gart_info.type = NOUVEAU_GART_NONE;
 624
 625 #if !defined(__powerpc__) && !defined(__ia64__)
 626         if (drm_device_is_agp(dev) && dev->agp && nouveau_agpmode) {
 627                 ret = nouveau_mem_init_agp(dev);
 628                 if (ret)
 629                         NV_ERROR(dev, "Error initialising AGP: %d\n", ret);
 630         }
 631 #endif
 632
 633         if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) {
 634                 ret = nouveau_sgdma_init(dev);
 635                 if (ret) {
 636                         NV_ERROR(dev, "Error initialising PCI(E): %d\n", ret);
 637                         return ret;
 638                 }
 639         }
 640
 641         NV_INFO(dev, "%d MiB GART (aperture)\n",
 642                 (int)(dev_priv->gart_info.aper_size >> 20));
 643         dev_priv->gart_info.aper_free = dev_priv->gart_info.aper_size;
 644
 645         ret = ttm_bo_init_mm(bdev, TTM_PL_TT,
 646                              dev_priv->gart_info.aper_size >> PAGE_SHIFT);
 647         if (ret) {
 648                 NV_ERROR(dev, "Failed TT mm init: %d\n", ret);
 649                 return ret;
 650         }
 651
 652         return 0;
 653 }
 654