drivers/gpu/drm/nouveau/nouveau_chan.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <nvif/os.h>
  26 #include <nvif/class.h>
  27 #include <nvif/ioctl.h>
  28
  29 /*XXX*/
  30 #include <core/client.h>
  31
  32 #include "nouveau_drm.h"
  33 #include "nouveau_dma.h"
  34 #include "nouveau_bo.h"
  35 #include "nouveau_chan.h"
  36 #include "nouveau_fence.h"
  37 #include "nouveau_abi16.h"
  38
  39 MODULE_PARM_DESC(vram_pushbuf, "Create DMA push buffers in VRAM");
  40 int nouveau_vram_pushbuf;
  41 module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);
  42
  43 int
  44 nouveau_channel_idle(struct nouveau_channel *chan)
  45 {
  46         struct nouveau_cli *cli = (void *)chan->user.client;
  47         struct nouveau_fence *fence = NULL;
  48         int ret;
  49
  50         ret = nouveau_fence_new(chan, false, &fence);
  51         if (!ret) {
  52                 ret = nouveau_fence_wait(fence, false, false);
  53                 nouveau_fence_unref(&fence);
  54         }
  55
  56         if (ret)
  57                 NV_PRINTK(err, cli, "failed to idle channel 0x%08x [%s]\n",
  58                           chan->user.handle, nvxx_client(&cli->base)->name);
  59         return ret;
  60 }
  61
  62 void
  63 nouveau_channel_del(struct nouveau_channel **pchan)
  64 {
  65         struct nouveau_channel *chan = *pchan;
  66         if (chan) {
  67                 if (chan->fence) {
  68                         nouveau_channel_idle(chan);
  69                         nouveau_fence(chan->drm)->context_del(chan);
  70                 }
  71                 nvif_object_fini(&chan->nvsw);
  72                 nvif_object_fini(&chan->gart);
  73                 nvif_object_fini(&chan->vram);
  74                 nvif_object_fini(&chan->user);
  75                 nvif_object_fini(&chan->push.ctxdma);
  76                 nouveau_bo_vma_del(chan->push.buffer, &chan->push.vma);
  77                 nouveau_bo_unmap(chan->push.buffer);
  78                 if (chan->push.buffer && chan->push.buffer->pin_refcnt)
  79                         nouveau_bo_unpin(chan->push.buffer);
  80                 nouveau_bo_ref(NULL, &chan->push.buffer);
  81                 kfree(chan);
  82         }
  83         *pchan = NULL;
  84 }
  85
  86 static int
  87 nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device,
  88                      u32 handle, u32 size, struct nouveau_channel **pchan)
  89 {
  90         struct nouveau_cli *cli = (void *)device->object.client;
  91         struct nvkm_mmu *mmu = nvxx_mmu(device);
  92         struct nv_dma_v0 args = {};
  93         struct nouveau_channel *chan;
  94         u32 target;
  95         int ret;
  96
  97         chan = *pchan = kzalloc(sizeof(*chan), GFP_KERNEL);
  98         if (!chan)
  99                 return -ENOMEM;
 100
 101         chan->device = device;
 102         chan->drm = drm;
 103
 104         /* allocate memory for dma push buffer */
 105         target = TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED;
 106         if (nouveau_vram_pushbuf)
 107                 target = TTM_PL_FLAG_VRAM;
 108
 109         ret = nouveau_bo_new(drm->dev, size, 0, target, 0, 0, NULL, NULL,
 110                             &chan->push.buffer);
 111         if (ret == 0) {
 112                 ret = nouveau_bo_pin(chan->push.buffer, target, false);
 113                 if (ret == 0)
 114                         ret = nouveau_bo_map(chan->push.buffer);
 115         }
 116
 117         if (ret) {
 118                 nouveau_channel_del(pchan);
 119                 return ret;
 120         }
 121
 122         /* create dma object covering the *entire* memory space that the
 123          * pushbuf lives in, this is because the GEM code requires that
 124          * we be able to call out to other (indirect) push buffers
 125          */
 126         chan->push.vma.offset = chan->push.buffer->bo.offset;
 127
 128         if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
 129                 ret = nouveau_bo_vma_add(chan->push.buffer, cli->vm,
 130                                         &chan->push.vma);
 131                 if (ret) {
 132                         nouveau_channel_del(pchan);
 133                         return ret;
 134                 }
 135
 136                 args.target = NV_DMA_V0_TARGET_VM;
 137                 args.access = NV_DMA_V0_ACCESS_VM;
 138                 args.start = 0;
 139                 args.limit = cli->vm->mmu->limit - 1;
 140         } else
 141         if (chan->push.buffer->bo.mem.mem_type == TTM_PL_VRAM) {
 142                 if (device->info.family == NV_DEVICE_INFO_V0_TNT) {
 143                         /* nv04 vram pushbuf hack, retarget to its location in
 144                          * the framebuffer bar rather than direct vram access..
 145                          * nfi why this exists, it came from the -nv ddx.
 146                          */
 147                         args.target = NV_DMA_V0_TARGET_PCI;
 148                         args.access = NV_DMA_V0_ACCESS_RDWR;
 149                         args.start = nv_device_resource_start(nvxx_device(device), 1);
 150                         args.limit = args.start + device->info.ram_user - 1;
 151                 } else {
 152                         args.target = NV_DMA_V0_TARGET_VRAM;
 153                         args.access = NV_DMA_V0_ACCESS_RDWR;
 154                         args.start = 0;
 155                         args.limit = device->info.ram_user - 1;
 156                 }
 157         } else {
 158                 if (chan->drm->agp.stat == ENABLED) {
 159                         args.target = NV_DMA_V0_TARGET_AGP;
 160                         args.access = NV_DMA_V0_ACCESS_RDWR;
 161                         args.start = chan->drm->agp.base;
 162                         args.limit = chan->drm->agp.base +
 163                                      chan->drm->agp.size - 1;
 164                 } else {
 165                         args.target = NV_DMA_V0_TARGET_VM;
 166                         args.access = NV_DMA_V0_ACCESS_RDWR;
 167                         args.start = 0;
 168                         args.limit = mmu->limit - 1;
 169                 }
 170         }
 171
 172         ret = nvif_object_init(&device->object, NVDRM_PUSH |
 173                                (handle & 0xffff), NV_DMA_FROM_MEMORY,
 174                                &args, sizeof(args), &chan->push.ctxdma);
 175         if (ret) {
 176                 nouveau_channel_del(pchan);
 177                 return ret;
 178         }
 179
 180         return 0;
 181 }
 182
 183 static int
 184 nouveau_channel_ind(struct nouveau_drm *drm, struct nvif_device *device,
 185                     u32 handle, u32 engine, struct nouveau_channel **pchan)
 186 {
 187         static const u16 oclasses[] = { MAXWELL_CHANNEL_GPFIFO_A,
 188                                         KEPLER_CHANNEL_GPFIFO_A,
 189                                         FERMI_CHANNEL_GPFIFO,
 190                                         G82_CHANNEL_GPFIFO,
 191                                         NV50_CHANNEL_GPFIFO,
 192                                         0 };
 193         const u16 *oclass = oclasses;
 194         union {
 195                 struct nv50_channel_gpfifo_v0 nv50;
 196                 struct kepler_channel_gpfifo_a_v0 kepler;
 197         } args;
 198         struct nouveau_channel *chan;
 199         u32 size;
 200         int ret;
 201
 202         /* allocate dma push buffer */
 203         ret = nouveau_channel_prep(drm, device, handle, 0x12000, &chan);
 204         *pchan = chan;
 205         if (ret)
 206                 return ret;
 207
 208         /* create channel object */
 209         do {
 210                 if (oclass[0] >= KEPLER_CHANNEL_GPFIFO_A) {
 211                         args.kepler.version = 0;
 212                         args.kepler.engine  = engine;
 213                         args.kepler.pushbuf = nvif_handle(&chan->push.ctxdma);
 214                         args.kepler.ilength = 0x02000;
 215                         args.kepler.ioffset = 0x10000 + chan->push.vma.offset;
 216                         size = sizeof(args.kepler);
 217                 } else {
 218                         args.nv50.version = 0;
 219                         args.nv50.pushbuf = nvif_handle(&chan->push.ctxdma);
 220                         args.nv50.ilength = 0x02000;
 221                         args.nv50.ioffset = 0x10000 + chan->push.vma.offset;
 222                         size = sizeof(args.nv50);
 223                 }
 224
 225                 ret = nvif_object_init(&device->object, handle, *oclass++,
 226                                        &args, size, &chan->user);
 227                 if (ret == 0) {
 228                         if (chan->user.oclass >= KEPLER_CHANNEL_GPFIFO_A)
 229                                 chan->chid = args.kepler.chid;
 230                         else
 231                                 chan->chid = args.nv50.chid;
 232                         return ret;
 233                 }
 234         } while (*oclass);
 235
 236         nouveau_channel_del(pchan);
 237         return ret;
 238 }
 239
 240 static int
 241 nouveau_channel_dma(struct nouveau_drm *drm, struct nvif_device *device,
 242                     u32 handle, struct nouveau_channel **pchan)
 243 {
 244         static const u16 oclasses[] = { NV40_CHANNEL_DMA,
 245                                         NV17_CHANNEL_DMA,
 246                                         NV10_CHANNEL_DMA,
 247                                         NV03_CHANNEL_DMA,
 248                                         0 };
 249         const u16 *oclass = oclasses;
 250         struct nv03_channel_dma_v0 args;
 251         struct nouveau_channel *chan;
 252         int ret;
 253
 254         /* allocate dma push buffer */
 255         ret = nouveau_channel_prep(drm, device, handle, 0x10000, &chan);
 256         *pchan = chan;
 257         if (ret)
 258                 return ret;
 259
 260         /* create channel object */
 261         args.version = 0;
 262         args.pushbuf = nvif_handle(&chan->push.ctxdma);
 263         args.offset = chan->push.vma.offset;
 264
 265         do {
 266                 ret = nvif_object_init(&device->object, handle, *oclass++,
 267                                        &args, sizeof(args), &chan->user);
 268                 if (ret == 0) {
 269                         chan->chid = args.chid;
 270                         return ret;
 271                 }
 272         } while (ret && *oclass);
 273
 274         nouveau_channel_del(pchan);
 275         return ret;
 276 }
 277
 278 static int
 279 nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
 280 {
 281         struct nvif_device *device = chan->device;
 282         struct nouveau_cli *cli = (void *)chan->user.client;
 283         struct nvkm_mmu *mmu = nvxx_mmu(device);
 284         struct nvkm_sw_chan *swch;
 285         struct nv_dma_v0 args = {};
 286         int ret, i;
 287
 288         nvif_object_map(&chan->user);
 289
 290         /* allocate dma objects to cover all allowed vram, and gart */
 291         if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
 292                 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
 293                         args.target = NV_DMA_V0_TARGET_VM;
 294                         args.access = NV_DMA_V0_ACCESS_VM;
 295                         args.start = 0;
 296                         args.limit = cli->vm->mmu->limit - 1;
 297                 } else {
 298                         args.target = NV_DMA_V0_TARGET_VRAM;
 299                         args.access = NV_DMA_V0_ACCESS_RDWR;
 300                         args.start = 0;
 301                         args.limit = device->info.ram_user - 1;
 302                 }
 303
 304                 ret = nvif_object_init(&chan->user, vram, NV_DMA_IN_MEMORY,
 305                                        &args, sizeof(args), &chan->vram);
 306                 if (ret)
 307                         return ret;
 308
 309                 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
 310                         args.target = NV_DMA_V0_TARGET_VM;
 311                         args.access = NV_DMA_V0_ACCESS_VM;
 312                         args.start = 0;
 313                         args.limit = cli->vm->mmu->limit - 1;
 314                 } else
 315                 if (chan->drm->agp.stat == ENABLED) {
 316                         args.target = NV_DMA_V0_TARGET_AGP;
 317                         args.access = NV_DMA_V0_ACCESS_RDWR;
 318                         args.start = chan->drm->agp.base;
 319                         args.limit = chan->drm->agp.base +
 320                                      chan->drm->agp.size - 1;
 321                 } else {
 322                         args.target = NV_DMA_V0_TARGET_VM;
 323                         args.access = NV_DMA_V0_ACCESS_RDWR;
 324                         args.start = 0;
 325                         args.limit = mmu->limit - 1;
 326                 }
 327
 328                 ret = nvif_object_init(&chan->user, gart, NV_DMA_IN_MEMORY,
 329                                        &args, sizeof(args), &chan->gart);
 330                 if (ret)
 331                         return ret;
 332         }
 333
 334         /* initialise dma tracking parameters */
 335         switch (chan->user.oclass & 0x00ff) {
 336         case 0x006b:
 337         case 0x006e:
 338                 chan->user_put = 0x40;
 339                 chan->user_get = 0x44;
 340                 chan->dma.max = (0x10000 / 4) - 2;
 341                 break;
 342         default:
 343                 chan->user_put = 0x40;
 344                 chan->user_get = 0x44;
 345                 chan->user_get_hi = 0x60;
 346                 chan->dma.ib_base =  0x10000 / 4;
 347                 chan->dma.ib_max  = (0x02000 / 8) - 1;
 348                 chan->dma.ib_put  = 0;
 349                 chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put;
 350                 chan->dma.max = chan->dma.ib_base;
 351                 break;
 352         }
 353
 354         chan->dma.put = 0;
 355         chan->dma.cur = chan->dma.put;
 356         chan->dma.free = chan->dma.max - chan->dma.cur;
 357
 358         ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS);
 359         if (ret)
 360                 return ret;
 361
 362         for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
 363                 OUT_RING(chan, 0x00000000);
 364
 365         /* allocate software object class (used for fences on <= nv05) */
 366         if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) {
 367                 ret = nvif_object_init(&chan->user, 0x006e,
 368                                        NVIF_IOCTL_NEW_V0_SW_NV04,
 369                                        NULL, 0, &chan->nvsw);
 370                 if (ret)
 371                         return ret;
 372
 373                 swch = (void *)nvxx_object(&chan->nvsw)->parent;
 374                 swch->flip = nouveau_flip_complete;
 375                 swch->flip_data = chan;
 376
 377                 ret = RING_SPACE(chan, 2);
 378                 if (ret)
 379                         return ret;
 380
 381                 BEGIN_NV04(chan, NvSubSw, 0x0000, 1);
 382                 OUT_RING  (chan, chan->nvsw.handle);
 383                 FIRE_RING (chan);
 384         }
 385
 386         /* initialise synchronisation */
 387         return nouveau_fence(chan->drm)->context_new(chan);
 388 }
 389
 390 int
 391 nouveau_channel_new(struct nouveau_drm *drm, struct nvif_device *device,
 392                     u32 handle, u32 arg0, u32 arg1,
 393                     struct nouveau_channel **pchan)
 394 {
 395         struct nouveau_cli *cli = (void *)device->object.client;
 396         bool super;
 397         int ret;
 398
 399         /* hack until fencenv50 is fixed, and agp access relaxed */
 400         super = cli->base.super;
 401         cli->base.super = true;
 402
 403         ret = nouveau_channel_ind(drm, device, handle, arg0, pchan);
 404         if (ret) {
 405                 NV_PRINTK(dbg, cli, "ib channel create, %d\n", ret);
 406                 ret = nouveau_channel_dma(drm, device, handle, pchan);
 407                 if (ret) {
 408                         NV_PRINTK(dbg, cli, "dma channel create, %d\n", ret);
 409                         goto done;
 410                 }
 411         }
 412
 413         ret = nouveau_channel_init(*pchan, arg0, arg1);
 414         if (ret) {
 415                 NV_PRINTK(err, cli, "channel failed to initialise, %d\n", ret);
 416                 nouveau_channel_del(pchan);
 417         }
 418
 419 done:
 420         cli->base.super = super;
 421         return ret;
 422 }