2 * Copyright 2007 Dave Airlied
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
32 #include "nouveau_drm.h"
33 #include "nouveau_drv.h"
34 #include "nouveau_dma.h"
36 #include <linux/log2.h>
37 #include <linux/slab.h>
40 nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
42 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
43 struct drm_device *dev = dev_priv->dev;
44 struct nouveau_bo *nvbo = nouveau_bo(bo);
46 if (unlikely(nvbo->gem))
47 DRM_ERROR("bo %p still attached to GEM object\n", bo);
50 nv10_mem_expire_tiling(dev, nvbo->tile, NULL);
56 nouveau_bo_fixup_align(struct drm_device *dev,
57 uint32_t tile_mode, uint32_t tile_flags,
58 int *align, int *size)
60 struct drm_nouveau_private *dev_priv = dev->dev_private;
63 * Some of the tile_flags have a periodic structure of N*4096 bytes,
64 * align to to that as well as the page size. Align the size to the
65 * appropriate boundaries. This does imply that sizes are rounded up
66 * 3-7 pages, so be aware of this and do not waste memory by allocating
69 if (dev_priv->card_type == NV_50) {
70 uint32_t block_size = dev_priv->vram_size >> 15;
78 if (is_power_of_2(block_size)) {
79 for (i = 1; i < 10; i++) {
80 *align = 12 * i * block_size;
81 if (!(*align % 65536))
85 for (i = 1; i < 10; i++) {
86 *align = 8 * i * block_size;
87 if (!(*align % 65536))
91 *size = roundup(*size, *align);
99 if (dev_priv->chipset >= 0x40) {
101 *size = roundup(*size, 64 * tile_mode);
103 } else if (dev_priv->chipset >= 0x30) {
105 *size = roundup(*size, 64 * tile_mode);
107 } else if (dev_priv->chipset >= 0x20) {
109 *size = roundup(*size, 64 * tile_mode);
111 } else if (dev_priv->chipset >= 0x10) {
113 *size = roundup(*size, 32 * tile_mode);
118 /* ALIGN works only on powers of two. */
119 *size = roundup(*size, PAGE_SIZE);
121 if (dev_priv->card_type == NV_50) {
122 *size = roundup(*size, 65536);
123 *align = max(65536, *align);
128 nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan,
129 int size, int align, uint32_t flags, uint32_t tile_mode,
130 uint32_t tile_flags, bool no_vm, bool mappable,
131 struct nouveau_bo **pnvbo)
133 struct drm_nouveau_private *dev_priv = dev->dev_private;
134 struct nouveau_bo *nvbo;
137 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
140 INIT_LIST_HEAD(&nvbo->head);
141 INIT_LIST_HEAD(&nvbo->entry);
142 nvbo->mappable = mappable;
144 nvbo->tile_mode = tile_mode;
145 nvbo->tile_flags = tile_flags;
146 nvbo->bo.bdev = &dev_priv->ttm.bdev;
148 nouveau_bo_fixup_align(dev, tile_mode, nouveau_bo_tile_layout(nvbo),
150 align >>= PAGE_SHIFT;
152 nouveau_bo_placement_set(nvbo, flags, 0);
154 nvbo->channel = chan;
155 ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size,
156 ttm_bo_type_device, &nvbo->placement, align, 0,
157 false, NULL, size, nouveau_bo_del_ttm);
159 /* ttm will call nouveau_bo_del_ttm if it fails.. */
162 nvbo->channel = NULL;
169 set_placement_list(uint32_t *pl, unsigned *n, uint32_t type, uint32_t flags)
173 if (type & TTM_PL_FLAG_VRAM)
174 pl[(*n)++] = TTM_PL_FLAG_VRAM | flags;
175 if (type & TTM_PL_FLAG_TT)
176 pl[(*n)++] = TTM_PL_FLAG_TT | flags;
177 if (type & TTM_PL_FLAG_SYSTEM)
178 pl[(*n)++] = TTM_PL_FLAG_SYSTEM | flags;
182 set_placement_range(struct nouveau_bo *nvbo, uint32_t type)
184 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
186 if (dev_priv->card_type == NV_10 &&
187 nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM)) {
189 * Make sure that the color and depth buffers are handled
190 * by independent memory controller units. Up to a 9x
191 * speed up when alpha-blending and depth-test are enabled
194 int vram_pages = dev_priv->vram_size >> PAGE_SHIFT;
196 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_ZETA) {
197 nvbo->placement.fpfn = vram_pages / 2;
198 nvbo->placement.lpfn = ~0;
200 nvbo->placement.fpfn = 0;
201 nvbo->placement.lpfn = vram_pages / 2;
207 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
209 struct ttm_placement *pl = &nvbo->placement;
210 uint32_t flags = TTM_PL_MASK_CACHING |
211 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
213 pl->placement = nvbo->placements;
214 set_placement_list(nvbo->placements, &pl->num_placement,
217 pl->busy_placement = nvbo->busy_placements;
218 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
221 set_placement_range(nvbo, type);
225 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype)
227 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
228 struct ttm_buffer_object *bo = &nvbo->bo;
231 if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) {
232 NV_ERROR(nouveau_bdev(bo->bdev)->dev,
233 "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo,
234 1 << bo->mem.mem_type, memtype);
238 if (nvbo->pin_refcnt++)
241 ret = ttm_bo_reserve(bo, false, false, false, 0);
245 nouveau_bo_placement_set(nvbo, memtype, 0);
247 ret = ttm_bo_validate(bo, &nvbo->placement, false, false, false);
249 switch (bo->mem.mem_type) {
251 dev_priv->fb_aper_free -= bo->mem.size;
254 dev_priv->gart_info.aper_free -= bo->mem.size;
260 ttm_bo_unreserve(bo);
268 nouveau_bo_unpin(struct nouveau_bo *nvbo)
270 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
271 struct ttm_buffer_object *bo = &nvbo->bo;
274 if (--nvbo->pin_refcnt)
277 ret = ttm_bo_reserve(bo, false, false, false, 0);
281 nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
283 ret = ttm_bo_validate(bo, &nvbo->placement, false, false, false);
285 switch (bo->mem.mem_type) {
287 dev_priv->fb_aper_free += bo->mem.size;
290 dev_priv->gart_info.aper_free += bo->mem.size;
297 ttm_bo_unreserve(bo);
302 nouveau_bo_map(struct nouveau_bo *nvbo)
306 ret = ttm_bo_reserve(&nvbo->bo, false, false, false, 0);
310 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
311 ttm_bo_unreserve(&nvbo->bo);
316 nouveau_bo_unmap(struct nouveau_bo *nvbo)
319 ttm_bo_kunmap(&nvbo->kmap);
323 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index)
326 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
329 return ioread16_native((void __force __iomem *)mem);
335 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
338 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
341 iowrite16_native(val, (void __force __iomem *)mem);
347 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
350 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
353 return ioread32_native((void __force __iomem *)mem);
359 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
362 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
365 iowrite32_native(val, (void __force __iomem *)mem);
370 static struct ttm_backend *
371 nouveau_bo_create_ttm_backend_entry(struct ttm_bo_device *bdev)
373 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
374 struct drm_device *dev = dev_priv->dev;
376 switch (dev_priv->gart_info.type) {
378 case NOUVEAU_GART_AGP:
379 return ttm_agp_backend_init(bdev, dev->agp->bridge);
381 case NOUVEAU_GART_SGDMA:
382 return nouveau_sgdma_init_ttm(dev);
384 NV_ERROR(dev, "Unknown GART type %d\n",
385 dev_priv->gart_info.type);
393 nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
395 /* We'll do this from user space. */
400 nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
401 struct ttm_mem_type_manager *man)
403 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
404 struct drm_device *dev = dev_priv->dev;
408 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
409 man->available_caching = TTM_PL_MASK_CACHING;
410 man->default_caching = TTM_PL_FLAG_CACHED;
413 man->func = &ttm_bo_manager_func;
414 man->flags = TTM_MEMTYPE_FLAG_FIXED |
415 TTM_MEMTYPE_FLAG_MAPPABLE;
416 man->available_caching = TTM_PL_FLAG_UNCACHED |
418 man->default_caching = TTM_PL_FLAG_WC;
419 if (dev_priv->card_type == NV_50)
420 man->gpu_offset = 0x40000000;
425 man->func = &ttm_bo_manager_func;
426 switch (dev_priv->gart_info.type) {
427 case NOUVEAU_GART_AGP:
428 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
429 man->available_caching = TTM_PL_FLAG_UNCACHED;
430 man->default_caching = TTM_PL_FLAG_UNCACHED;
432 case NOUVEAU_GART_SGDMA:
433 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
434 TTM_MEMTYPE_FLAG_CMA;
435 man->available_caching = TTM_PL_MASK_CACHING;
436 man->default_caching = TTM_PL_FLAG_CACHED;
439 NV_ERROR(dev, "Unknown GART type: %d\n",
440 dev_priv->gart_info.type);
443 man->gpu_offset = dev_priv->vm_gart_base;
446 NV_ERROR(dev, "Unsupported memory type %u\n", (unsigned)type);
453 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
455 struct nouveau_bo *nvbo = nouveau_bo(bo);
457 switch (bo->mem.mem_type) {
459 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
463 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
467 *pl = nvbo->placement;
471 /* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
472 * TTM_PL_{VRAM,TT} directly.
476 nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan,
477 struct nouveau_bo *nvbo, bool evict,
478 bool no_wait_reserve, bool no_wait_gpu,
479 struct ttm_mem_reg *new_mem)
481 struct nouveau_fence *fence = NULL;
484 ret = nouveau_fence_new(chan, &fence, true);
489 ret = nouveau_fence_sync(fence, nvbo->channel);
494 ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, NULL, evict,
495 no_wait_reserve, no_wait_gpu, new_mem);
497 nouveau_fence_unref((void *)&fence);
501 static inline uint32_t
502 nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo,
503 struct nouveau_channel *chan, struct ttm_mem_reg *mem)
505 struct nouveau_bo *nvbo = nouveau_bo(bo);
508 if (mem->mem_type == TTM_PL_TT)
513 if (mem->mem_type == TTM_PL_TT)
514 return chan->gart_handle;
515 return chan->vram_handle;
519 nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
520 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
522 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
523 struct nouveau_bo *nvbo = nouveau_bo(bo);
524 u64 length = (new_mem->num_pages << PAGE_SHIFT);
525 u64 src_offset, dst_offset;
528 src_offset = old_mem->start << PAGE_SHIFT;
529 dst_offset = new_mem->start << PAGE_SHIFT;
531 if (old_mem->mem_type == TTM_PL_VRAM)
532 src_offset += dev_priv->vm_vram_base;
534 src_offset += dev_priv->vm_gart_base;
536 if (new_mem->mem_type == TTM_PL_VRAM)
537 dst_offset += dev_priv->vm_vram_base;
539 dst_offset += dev_priv->vm_gart_base;
542 ret = RING_SPACE(chan, 3);
546 BEGIN_RING(chan, NvSubM2MF, 0x0184, 2);
547 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem));
548 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem));
551 u32 amount, stride, height;
553 amount = min(length, (u64)(4 * 1024 * 1024));
555 height = amount / stride;
557 if (new_mem->mem_type == TTM_PL_VRAM &&
558 nouveau_bo_tile_layout(nvbo)) {
559 ret = RING_SPACE(chan, 8);
563 BEGIN_RING(chan, NvSubM2MF, 0x0200, 7);
566 OUT_RING (chan, stride);
567 OUT_RING (chan, height);
572 ret = RING_SPACE(chan, 2);
576 BEGIN_RING(chan, NvSubM2MF, 0x0200, 1);
579 if (old_mem->mem_type == TTM_PL_VRAM &&
580 nouveau_bo_tile_layout(nvbo)) {
581 ret = RING_SPACE(chan, 8);
585 BEGIN_RING(chan, NvSubM2MF, 0x021c, 7);
588 OUT_RING (chan, stride);
589 OUT_RING (chan, height);
594 ret = RING_SPACE(chan, 2);
598 BEGIN_RING(chan, NvSubM2MF, 0x021c, 1);
602 ret = RING_SPACE(chan, 14);
606 BEGIN_RING(chan, NvSubM2MF, 0x0238, 2);
607 OUT_RING (chan, upper_32_bits(src_offset));
608 OUT_RING (chan, upper_32_bits(dst_offset));
609 BEGIN_RING(chan, NvSubM2MF, 0x030c, 8);
610 OUT_RING (chan, lower_32_bits(src_offset));
611 OUT_RING (chan, lower_32_bits(dst_offset));
612 OUT_RING (chan, stride);
613 OUT_RING (chan, stride);
614 OUT_RING (chan, stride);
615 OUT_RING (chan, height);
616 OUT_RING (chan, 0x00000101);
617 OUT_RING (chan, 0x00000000);
618 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
622 src_offset += amount;
623 dst_offset += amount;
630 nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
631 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
633 u32 src_offset = old_mem->start << PAGE_SHIFT;
634 u32 dst_offset = new_mem->start << PAGE_SHIFT;
635 u32 page_count = new_mem->num_pages;
638 ret = RING_SPACE(chan, 3);
642 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
643 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem));
644 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem));
646 page_count = new_mem->num_pages;
648 int line_count = (page_count > 2047) ? 2047 : page_count;
650 ret = RING_SPACE(chan, 11);
654 BEGIN_RING(chan, NvSubM2MF,
655 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
656 OUT_RING (chan, src_offset);
657 OUT_RING (chan, dst_offset);
658 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
659 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
660 OUT_RING (chan, PAGE_SIZE); /* line_length */
661 OUT_RING (chan, line_count);
662 OUT_RING (chan, 0x00000101);
663 OUT_RING (chan, 0x00000000);
664 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
667 page_count -= line_count;
668 src_offset += (PAGE_SIZE * line_count);
669 dst_offset += (PAGE_SIZE * line_count);
676 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
677 bool no_wait_reserve, bool no_wait_gpu,
678 struct ttm_mem_reg *new_mem)
680 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
681 struct nouveau_bo *nvbo = nouveau_bo(bo);
682 struct nouveau_channel *chan;
685 chan = nvbo->channel;
686 if (!chan || nvbo->no_vm)
687 chan = dev_priv->channel;
689 if (dev_priv->card_type < NV_50)
690 ret = nv04_bo_move_m2mf(chan, bo, &bo->mem, new_mem);
692 ret = nv50_bo_move_m2mf(chan, bo, &bo->mem, new_mem);
696 return nouveau_bo_move_accel_cleanup(chan, nvbo, evict, no_wait_reserve, no_wait_gpu, new_mem);
700 nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
701 bool no_wait_reserve, bool no_wait_gpu,
702 struct ttm_mem_reg *new_mem)
704 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
705 struct ttm_placement placement;
706 struct ttm_mem_reg tmp_mem;
709 placement.fpfn = placement.lpfn = 0;
710 placement.num_placement = placement.num_busy_placement = 1;
711 placement.placement = placement.busy_placement = &placement_memtype;
714 tmp_mem.mm_node = NULL;
715 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
719 ret = ttm_tt_bind(bo->ttm, &tmp_mem);
723 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, &tmp_mem);
727 ret = ttm_bo_move_ttm(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
729 ttm_bo_mem_put(bo, &tmp_mem);
734 nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
735 bool no_wait_reserve, bool no_wait_gpu,
736 struct ttm_mem_reg *new_mem)
738 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
739 struct ttm_placement placement;
740 struct ttm_mem_reg tmp_mem;
743 placement.fpfn = placement.lpfn = 0;
744 placement.num_placement = placement.num_busy_placement = 1;
745 placement.placement = placement.busy_placement = &placement_memtype;
748 tmp_mem.mm_node = NULL;
749 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
753 ret = ttm_bo_move_ttm(bo, evict, no_wait_reserve, no_wait_gpu, &tmp_mem);
757 ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
762 ttm_bo_mem_put(bo, &tmp_mem);
767 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
768 struct nouveau_tile_reg **new_tile)
770 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
771 struct drm_device *dev = dev_priv->dev;
772 struct nouveau_bo *nvbo = nouveau_bo(bo);
776 if (nvbo->no_vm || new_mem->mem_type != TTM_PL_VRAM) {
782 offset = new_mem->start << PAGE_SHIFT;
784 if (dev_priv->card_type == NV_50) {
785 ret = nv50_mem_vm_bind_linear(dev,
786 offset + dev_priv->vm_vram_base,
788 nouveau_bo_tile_layout(nvbo),
793 } else if (dev_priv->card_type >= NV_10) {
794 *new_tile = nv10_mem_set_tiling(dev, offset, new_mem->size,
802 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
803 struct nouveau_tile_reg *new_tile,
804 struct nouveau_tile_reg **old_tile)
806 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
807 struct drm_device *dev = dev_priv->dev;
809 if (dev_priv->card_type >= NV_10 &&
810 dev_priv->card_type < NV_50) {
812 nv10_mem_expire_tiling(dev, *old_tile, bo->sync_obj);
814 *old_tile = new_tile;
819 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
820 bool no_wait_reserve, bool no_wait_gpu,
821 struct ttm_mem_reg *new_mem)
823 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
824 struct nouveau_bo *nvbo = nouveau_bo(bo);
825 struct ttm_mem_reg *old_mem = &bo->mem;
826 struct nouveau_tile_reg *new_tile = NULL;
829 ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
834 if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
835 BUG_ON(bo->mem.mm_node != NULL);
837 new_mem->mm_node = NULL;
841 /* Software copy if the card isn't up and running yet. */
842 if (!dev_priv->channel) {
843 ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
847 /* Hardware assisted copy. */
848 if (new_mem->mem_type == TTM_PL_SYSTEM)
849 ret = nouveau_bo_move_flipd(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
850 else if (old_mem->mem_type == TTM_PL_SYSTEM)
851 ret = nouveau_bo_move_flips(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
853 ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
858 /* Fallback to software copy. */
859 ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
863 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
865 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
871 nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
877 nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
879 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
880 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
881 struct drm_device *dev = dev_priv->dev;
883 mem->bus.addr = NULL;
885 mem->bus.size = mem->num_pages << PAGE_SHIFT;
887 mem->bus.is_iomem = false;
888 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
890 switch (mem->mem_type) {
896 if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
897 mem->bus.offset = mem->start << PAGE_SHIFT;
898 mem->bus.base = dev_priv->gart_info.aper_base;
899 mem->bus.is_iomem = true;
904 mem->bus.offset = mem->start << PAGE_SHIFT;
905 mem->bus.base = pci_resource_start(dev->pdev, 1);
906 mem->bus.is_iomem = true;
915 nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
920 nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
922 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
923 struct nouveau_bo *nvbo = nouveau_bo(bo);
925 /* as long as the bo isn't in vram, and isn't tiled, we've got
926 * nothing to do here.
928 if (bo->mem.mem_type != TTM_PL_VRAM) {
929 if (dev_priv->card_type < NV_50 ||
930 !nouveau_bo_tile_layout(nvbo))
934 /* make sure bo is in mappable vram */
935 if (bo->mem.start + bo->mem.num_pages < dev_priv->fb_mappable_pages)
939 nvbo->placement.fpfn = 0;
940 nvbo->placement.lpfn = dev_priv->fb_mappable_pages;
941 nouveau_bo_placement_set(nvbo, TTM_PL_VRAM, 0);
942 return ttm_bo_validate(bo, &nvbo->placement, false, true, false);
945 struct ttm_bo_driver nouveau_bo_driver = {
946 .create_ttm_backend_entry = nouveau_bo_create_ttm_backend_entry,
947 .invalidate_caches = nouveau_bo_invalidate_caches,
948 .init_mem_type = nouveau_bo_init_mem_type,
949 .evict_flags = nouveau_bo_evict_flags,
950 .move = nouveau_bo_move,
951 .verify_access = nouveau_bo_verify_access,
952 .sync_obj_signaled = nouveau_fence_signalled,
953 .sync_obj_wait = nouveau_fence_wait,
954 .sync_obj_flush = nouveau_fence_flush,
955 .sync_obj_unref = nouveau_fence_unref,
956 .sync_obj_ref = nouveau_fence_ref,
957 .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
958 .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
959 .io_mem_free = &nouveau_ttm_io_mem_free,