1 #ifndef __NVBIOS_PLL_H__
2 #define __NVBIOS_PLL_H__
8 uint8_t N1, M1, N2, M2;
10 uint8_t M1, N1, M2, N2;
15 } __attribute__((packed));
22 /* these match types in pll limits table version 0x40,
23 * nvkm uses them on all chipsets internally where a
24 * specific pll needs to be referenced, but the exact
25 * register isn't known.
27 enum nvbios_pll_type {
44 enum nvbios_pll_type type;
53 * for most pre nv50 cards setting a log2P of 7 (the common max_log2p
54 * value) is no different to 6 (at least for vplls) so allowing the MNP
55 * calc to use 7 causes the generated clock to be out by a factor of 2.
56 * however, max_log2p cannot be fixed-up during parsing as the
57 * unmodified max_log2p value is still needed for setting mplls, hence
58 * an additional max_usable_log2p member
74 int nvbios_pll_parse(struct nvkm_bios *, u32 type, struct nvbios_pll *);