2 * Copyright 2014 Red Hat Inc.
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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25 #include <subdev/fb.h>
26 #include <subdev/timer.h>
31 gm107_ltc_cbc_clear(struct nvkm_ltc_priv *priv, u32 start, u32 limit)
33 nv_wr32(priv, 0x17e270, start);
34 nv_wr32(priv, 0x17e274, limit);
35 nv_wr32(priv, 0x17e26c, 0x00000004);
39 gm107_ltc_cbc_wait(struct nvkm_ltc_priv *priv)
42 for (c = 0; c < priv->ltc_nr; c++) {
43 for (s = 0; s < priv->lts_nr; s++)
44 nv_wait(priv, 0x14046c + c * 0x2000 + s * 0x200, ~0, 0);
49 gm107_ltc_zbc_clear_color(struct nvkm_ltc_priv *priv, int i, const u32 color[4])
51 nv_mask(priv, 0x17e338, 0x0000000f, i);
52 nv_wr32(priv, 0x17e33c, color[0]);
53 nv_wr32(priv, 0x17e340, color[1]);
54 nv_wr32(priv, 0x17e344, color[2]);
55 nv_wr32(priv, 0x17e348, color[3]);
59 gm107_ltc_zbc_clear_depth(struct nvkm_ltc_priv *priv, int i, const u32 depth)
61 nv_mask(priv, 0x17e338, 0x0000000f, i);
62 nv_wr32(priv, 0x17e34c, depth);
66 gm107_ltc_lts_isr(struct nvkm_ltc_priv *priv, int ltc, int lts)
68 u32 base = 0x140000 + (ltc * 0x2000) + (lts * 0x400);
69 u32 stat = nv_rd32(priv, base + 0x00c);
72 nv_info(priv, "LTC%d_LTS%d: 0x%08x\n", ltc, lts, stat);
73 nv_wr32(priv, base + 0x00c, stat);
78 gm107_ltc_intr(struct nouveau_subdev *subdev)
80 struct nvkm_ltc_priv *priv = (void *)subdev;
83 mask = nv_rd32(priv, 0x00017c);
85 u32 lts, ltc = __ffs(mask);
86 for (lts = 0; lts < priv->lts_nr; lts++)
87 gm107_ltc_lts_isr(priv, ltc, lts);
91 /* we do something horribly wrong and upset PMFB a lot, so mask off
92 * interrupts from it after the first one until it's fixed
94 nv_mask(priv, 0x000640, 0x02000000, 0x00000000);
98 gm107_ltc_init(struct nouveau_object *object)
100 struct nvkm_ltc_priv *priv = (void *)object;
103 ret = nvkm_ltc_init(priv);
107 nv_wr32(priv, 0x17e27c, priv->ltc_nr);
108 nv_wr32(priv, 0x17e278, priv->tag_base);
113 gm107_ltc_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
114 struct nouveau_oclass *oclass, void *data, u32 size,
115 struct nouveau_object **pobject)
117 struct nouveau_fb *pfb = nouveau_fb(parent);
118 struct nvkm_ltc_priv *priv;
122 ret = nvkm_ltc_create(parent, engine, oclass, &priv);
123 *pobject = nv_object(priv);
127 parts = nv_rd32(priv, 0x022438);
128 mask = nv_rd32(priv, 0x021c14);
129 for (i = 0; i < parts; i++) {
130 if (!(mask & (1 << i)))
133 priv->lts_nr = nv_rd32(priv, 0x17e280) >> 28;
135 ret = gf100_ltc_init_tag_ram(pfb, priv);
142 struct nouveau_oclass *
143 gm107_ltc_oclass = &(struct nvkm_ltc_impl) {
144 .base.handle = NV_SUBDEV(LTC, 0xff),
145 .base.ofuncs = &(struct nouveau_ofuncs) {
146 .ctor = gm107_ltc_ctor,
147 .dtor = gf100_ltc_dtor,
148 .init = gm107_ltc_init,
149 .fini = _nvkm_ltc_fini,
151 .intr = gm107_ltc_intr,
152 .cbc_clear = gm107_ltc_cbc_clear,
153 .cbc_wait = gm107_ltc_cbc_wait,
155 .zbc_clear_color = gm107_ltc_zbc_clear_color,
156 .zbc_clear_depth = gm107_ltc_zbc_clear_depth,