2 * Copyright (C) 2009 Francisco Jerez.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <subdev/gpio.h>
29 struct nv10_gpio_priv {
30 struct nouveau_gpio base;
34 nv10_gpio_sense(struct nouveau_gpio *gpio, int line)
38 line = nv_rd32(gpio, 0x600818) >> line;
39 return !!(line & 0x0100);
42 line = (line - 2) * 4;
43 line = nv_rd32(gpio, 0x60081c) >> line;
44 return !!(line & 0x04);
47 line = (line - 10) * 4;
48 line = nv_rd32(gpio, 0x600850) >> line;
49 return !!(line & 0x04);
56 nv10_gpio_drive(struct nouveau_gpio *gpio, int line, int dir, int out)
64 data = (dir << 4) | out;
67 line = (line - 2) * 4;
70 data = (dir << 1) | out;
73 line = (line - 10) * 4;
76 data = (dir << 1) | out;
81 nv_mask(gpio, reg, mask << line, data << line);
86 nv10_gpio_irq_enable(struct nouveau_gpio *gpio, int line, bool on)
88 u32 mask = 0x00010001 << line;
90 nv_wr32(gpio, 0x001104, mask);
91 nv_mask(gpio, 0x001144, mask, on ? mask : 0);
95 nv10_gpio_intr(struct nouveau_subdev *subdev)
97 struct nv10_gpio_priv *priv = (void *)subdev;
98 u32 intr = nv_rd32(priv, 0x001104);
99 u32 hi = (intr & 0x0000ffff) >> 0;
100 u32 lo = (intr & 0xffff0000) >> 16;
102 priv->base.isr_run(&priv->base, 0, hi | lo);
104 nv_wr32(priv, 0x001104, intr);
108 nv10_gpio_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
109 struct nouveau_oclass *oclass, void *data, u32 size,
110 struct nouveau_object **pobject)
112 struct nv10_gpio_priv *priv;
115 ret = nouveau_gpio_create(parent, engine, oclass, &priv);
116 *pobject = nv_object(priv);
120 priv->base.drive = nv10_gpio_drive;
121 priv->base.sense = nv10_gpio_sense;
122 priv->base.irq_enable = nv10_gpio_irq_enable;
123 nv_subdev(priv)->intr = nv10_gpio_intr;
128 nv10_gpio_dtor(struct nouveau_object *object)
130 struct nv10_gpio_priv *priv = (void *)object;
131 nouveau_gpio_destroy(&priv->base);
135 nv10_gpio_init(struct nouveau_object *object)
137 struct nv10_gpio_priv *priv = (void *)object;
140 ret = nouveau_gpio_init(&priv->base);
144 nv_wr32(priv, 0x001140, 0x00000000);
145 nv_wr32(priv, 0x001100, 0xffffffff);
146 nv_wr32(priv, 0x001144, 0x00000000);
147 nv_wr32(priv, 0x001104, 0xffffffff);
152 nv10_gpio_fini(struct nouveau_object *object, bool suspend)
154 struct nv10_gpio_priv *priv = (void *)object;
155 nv_wr32(priv, 0x001140, 0x00000000);
156 nv_wr32(priv, 0x001144, 0x00000000);
157 return nouveau_gpio_fini(&priv->base, suspend);
160 struct nouveau_oclass
162 .handle = NV_SUBDEV(GPIO, 0x10),
163 .ofuncs = &(struct nouveau_ofuncs) {
164 .ctor = nv10_gpio_ctor,
165 .dtor = nv10_gpio_dtor,
166 .init = nv10_gpio_init,
167 .fini = nv10_gpio_fini,