1 #include <core/engine.h>
2 #include <core/device.h>
4 #include <subdev/bios.h>
5 #include <subdev/bios/bmp.h>
6 #include <subdev/bios/bit.h>
7 #include <subdev/bios/conn.h>
8 #include <subdev/bios/dcb.h>
9 #include <subdev/bios/dp.h>
10 #include <subdev/bios/gpio.h>
11 #include <subdev/bios/init.h>
12 #include <subdev/devinit.h>
13 #include <subdev/clock.h>
14 #include <subdev/i2c.h>
15 #include <subdev/vga.h>
16 #include <subdev/gpio.h>
18 #define bioslog(lvl, fmt, args...) do { \
19 nv_printk(init->bios, lvl, "0x%04x[%c]: "fmt, init->offset, \
20 init_exec(init) ? '0' + (init->nested - 1) : ' ', ##args); \
22 #define cont(fmt, args...) do { \
23 if (nv_subdev(init->bios)->debug >= NV_DBG_TRACE) \
24 printk(fmt, ##args); \
26 #define trace(fmt, args...) bioslog(TRACE, fmt, ##args)
27 #define warn(fmt, args...) bioslog(WARN, fmt, ##args)
28 #define error(fmt, args...) bioslog(ERROR, fmt, ##args)
30 /******************************************************************************
31 * init parser control flow helpers
32 *****************************************************************************/
35 init_exec(struct nvbios_init *init)
37 return (init->execute == 1) || ((init->execute & 5) == 5);
41 init_exec_set(struct nvbios_init *init, bool exec)
43 if (exec) init->execute &= 0xfd;
44 else init->execute |= 0x02;
48 init_exec_inv(struct nvbios_init *init)
50 init->execute ^= 0x02;
54 init_exec_force(struct nvbios_init *init, bool exec)
56 if (exec) init->execute |= 0x04;
57 else init->execute &= 0xfb;
60 /******************************************************************************
61 * init parser wrappers for normal register/i2c/whatever accessors
62 *****************************************************************************/
65 init_or(struct nvbios_init *init)
67 if (init_exec(init)) {
69 return ffs(init->outp->or) - 1;
70 error("script needs OR!!\n");
76 init_link(struct nvbios_init *init)
78 if (init_exec(init)) {
80 return !(init->outp->sorconf.link & 1);
81 error("script needs OR link\n");
87 init_crtc(struct nvbios_init *init)
89 if (init_exec(init)) {
92 error("script needs crtc\n");
98 init_conn(struct nvbios_init *init)
100 struct nouveau_bios *bios = init->bios;
104 if (init_exec(init)) {
106 conn = init->outp->connector;
107 conn = dcb_conn(bios, conn, &ver, &len);
109 return nv_ro08(bios, conn);
112 error("script needs connector type\n");
119 init_nvreg(struct nvbios_init *init, u32 reg)
121 /* C51 (at least) sometimes has the lower bits set which the VBIOS
122 * interprets to mean that access needs to go through certain IO
123 * ports instead. The NVIDIA binary driver has been seen to access
124 * these through the NV register address, so lets assume we can
129 /* GF8+ display scripts need register addresses mangled a bit to
130 * select a specific CRTC/OR
132 if (nv_device(init->bios)->card_type >= NV_50) {
133 if (reg & 0x80000000) {
134 reg += init_crtc(init) * 0x800;
138 if (reg & 0x40000000) {
139 reg += init_or(init) * 0x800;
141 if (reg & 0x20000000) {
142 reg += init_link(init) * 0x80;
148 if (reg & ~0x00fffffc)
149 warn("unknown bits in register 0x%08x\n", reg);
154 init_rd32(struct nvbios_init *init, u32 reg)
156 reg = init_nvreg(init, reg);
158 return nv_rd32(init->subdev, reg);
163 init_wr32(struct nvbios_init *init, u32 reg, u32 val)
165 reg = init_nvreg(init, reg);
167 nv_wr32(init->subdev, reg, val);
171 init_mask(struct nvbios_init *init, u32 reg, u32 mask, u32 val)
173 reg = init_nvreg(init, reg);
174 if (init_exec(init)) {
175 u32 tmp = nv_rd32(init->subdev, reg);
176 nv_wr32(init->subdev, reg, (tmp & ~mask) | val);
183 init_rdport(struct nvbios_init *init, u16 port)
186 return nv_rdport(init->subdev, init->crtc, port);
191 init_wrport(struct nvbios_init *init, u16 port, u8 value)
194 nv_wrport(init->subdev, init->crtc, port, value);
198 init_rdvgai(struct nvbios_init *init, u16 port, u8 index)
200 struct nouveau_subdev *subdev = init->subdev;
201 if (init_exec(init)) {
202 int head = init->crtc < 0 ? 0 : init->crtc;
203 return nv_rdvgai(subdev, head, port, index);
209 init_wrvgai(struct nvbios_init *init, u16 port, u8 index, u8 value)
211 /* force head 0 for updates to cr44, it only exists on first head */
212 if (nv_device(init->subdev)->card_type < NV_50) {
213 if (port == 0x03d4 && index == 0x44)
217 if (init_exec(init)) {
218 int head = init->crtc < 0 ? 0 : init->crtc;
219 nv_wrvgai(init->subdev, head, port, index, value);
222 /* select head 1 if cr44 write selected it */
223 if (nv_device(init->subdev)->card_type < NV_50) {
224 if (port == 0x03d4 && index == 0x44 && value == 3)
229 static struct nouveau_i2c_port *
230 init_i2c(struct nvbios_init *init, int index)
232 struct nouveau_i2c *i2c = nouveau_i2c(init->bios);
235 index = NV_I2C_DEFAULT(0);
236 if (init->outp && init->outp->i2c_upper_default)
237 index = NV_I2C_DEFAULT(1);
242 error("script needs output for i2c\n");
246 if (index == -2 && init->outp->location) {
247 index = NV_I2C_TYPE_EXTAUX(init->outp->extdev);
248 return i2c->find_type(i2c, index);
251 index = init->outp->i2c_index;
254 return i2c->find(i2c, index);
258 init_rdi2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg)
260 struct nouveau_i2c_port *port = init_i2c(init, index);
261 if (port && init_exec(init))
262 return nv_rdi2cr(port, addr, reg);
267 init_wri2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg, u8 val)
269 struct nouveau_i2c_port *port = init_i2c(init, index);
270 if (port && init_exec(init))
271 return nv_wri2cr(port, addr, reg, val);
276 init_rdauxr(struct nvbios_init *init, u32 addr)
278 struct nouveau_i2c_port *port = init_i2c(init, -2);
281 if (port && init_exec(init)) {
282 int ret = nv_rdaux(port, addr, &data, 1);
292 init_wrauxr(struct nvbios_init *init, u32 addr, u8 data)
294 struct nouveau_i2c_port *port = init_i2c(init, -2);
295 if (port && init_exec(init))
296 return nv_wraux(port, addr, &data, 1);
301 init_prog_pll(struct nvbios_init *init, u32 id, u32 freq)
303 struct nouveau_clock *clk = nouveau_clock(init->bios);
304 if (clk && clk->pll_set && init_exec(init)) {
305 int ret = clk->pll_set(clk, id, freq);
307 warn("failed to prog pll 0x%08x to %dkHz\n", id, freq);
311 /******************************************************************************
312 * parsing of bios structures that are required to execute init tables
313 *****************************************************************************/
316 init_table(struct nouveau_bios *bios, u16 *len)
318 struct bit_entry bit_I;
320 if (!bit_entry(bios, 'I', &bit_I)) {
325 if (bmp_version(bios) >= 0x0510) {
327 return bios->bmp_offset + 75;
334 init_table_(struct nvbios_init *init, u16 offset, const char *name)
336 struct nouveau_bios *bios = init->bios;
337 u16 len, data = init_table(bios, &len);
339 if (len >= offset + 2) {
340 data = nv_ro16(bios, data + offset);
344 warn("%s pointer invalid\n", name);
348 warn("init data too short for %s pointer", name);
352 warn("init data not found\n");
356 #define init_script_table(b) init_table_((b), 0x00, "script table")
357 #define init_macro_index_table(b) init_table_((b), 0x02, "macro index table")
358 #define init_macro_table(b) init_table_((b), 0x04, "macro table")
359 #define init_condition_table(b) init_table_((b), 0x06, "condition table")
360 #define init_io_condition_table(b) init_table_((b), 0x08, "io condition table")
361 #define init_io_flag_condition_table(b) init_table_((b), 0x0a, "io flag conditon table")
362 #define init_function_table(b) init_table_((b), 0x0c, "function table")
363 #define init_xlat_table(b) init_table_((b), 0x10, "xlat table");
366 init_script(struct nouveau_bios *bios, int index)
368 struct nvbios_init init = { .bios = bios };
371 if (bmp_version(bios) && bmp_version(bios) < 0x0510) {
375 data = bios->bmp_offset + (bios->version.major < 2 ? 14 : 18);
376 return nv_ro16(bios, data + (index * 2));
379 data = init_script_table(&init);
381 return nv_ro16(bios, data + (index * 2));
387 init_unknown_script(struct nouveau_bios *bios)
389 u16 len, data = init_table(bios, &len);
390 if (data && len >= 16)
391 return nv_ro16(bios, data + 14);
396 init_ram_restrict_table(struct nvbios_init *init)
398 struct nouveau_bios *bios = init->bios;
399 struct bit_entry bit_M;
402 if (!bit_entry(bios, 'M', &bit_M)) {
403 if (bit_M.version == 1 && bit_M.length >= 5)
404 data = nv_ro16(bios, bit_M.offset + 3);
405 if (bit_M.version == 2 && bit_M.length >= 3)
406 data = nv_ro16(bios, bit_M.offset + 1);
410 warn("ram restrict table not found\n");
415 init_ram_restrict_group_count(struct nvbios_init *init)
417 struct nouveau_bios *bios = init->bios;
418 struct bit_entry bit_M;
420 if (!bit_entry(bios, 'M', &bit_M)) {
421 if (bit_M.version == 1 && bit_M.length >= 5)
422 return nv_ro08(bios, bit_M.offset + 2);
423 if (bit_M.version == 2 && bit_M.length >= 3)
424 return nv_ro08(bios, bit_M.offset + 0);
431 init_ram_restrict_strap(struct nvbios_init *init)
433 /* This appears to be the behaviour of the VBIOS parser, and *is*
434 * important to cache the NV_PEXTDEV_BOOT0 on later chipsets to
435 * avoid fucking up the memory controller (somehow) by reading it
436 * on every INIT_RAM_RESTRICT_ZM_GROUP opcode.
438 * Preserving the non-caching behaviour on earlier chipsets just
439 * in case *not* re-reading the strap causes similar breakage.
441 if (!init->ramcfg || init->bios->version.major < 0x70)
442 init->ramcfg = init_rd32(init, 0x101000);
443 return (init->ramcfg & 0x00000003c) >> 2;
447 init_ram_restrict(struct nvbios_init *init)
449 u8 strap = init_ram_restrict_strap(init);
450 u16 table = init_ram_restrict_table(init);
452 return nv_ro08(init->bios, table + strap);
457 init_xlat_(struct nvbios_init *init, u8 index, u8 offset)
459 struct nouveau_bios *bios = init->bios;
460 u16 table = init_xlat_table(init);
462 u16 data = nv_ro16(bios, table + (index * 2));
464 return nv_ro08(bios, data + offset);
465 warn("xlat table pointer %d invalid\n", index);
470 /******************************************************************************
471 * utility functions used by various init opcode handlers
472 *****************************************************************************/
475 init_condition_met(struct nvbios_init *init, u8 cond)
477 struct nouveau_bios *bios = init->bios;
478 u16 table = init_condition_table(init);
480 u32 reg = nv_ro32(bios, table + (cond * 12) + 0);
481 u32 msk = nv_ro32(bios, table + (cond * 12) + 4);
482 u32 val = nv_ro32(bios, table + (cond * 12) + 8);
483 trace("\t[0x%02x] (R[0x%06x] & 0x%08x) == 0x%08x\n",
484 cond, reg, msk, val);
485 return (init_rd32(init, reg) & msk) == val;
491 init_io_condition_met(struct nvbios_init *init, u8 cond)
493 struct nouveau_bios *bios = init->bios;
494 u16 table = init_io_condition_table(init);
496 u16 port = nv_ro16(bios, table + (cond * 5) + 0);
497 u8 index = nv_ro08(bios, table + (cond * 5) + 2);
498 u8 mask = nv_ro08(bios, table + (cond * 5) + 3);
499 u8 value = nv_ro08(bios, table + (cond * 5) + 4);
500 trace("\t[0x%02x] (0x%04x[0x%02x] & 0x%02x) == 0x%02x\n",
501 cond, port, index, mask, value);
502 return (init_rdvgai(init, port, index) & mask) == value;
508 init_io_flag_condition_met(struct nvbios_init *init, u8 cond)
510 struct nouveau_bios *bios = init->bios;
511 u16 table = init_io_flag_condition_table(init);
513 u16 port = nv_ro16(bios, table + (cond * 9) + 0);
514 u8 index = nv_ro08(bios, table + (cond * 9) + 2);
515 u8 mask = nv_ro08(bios, table + (cond * 9) + 3);
516 u8 shift = nv_ro08(bios, table + (cond * 9) + 4);
517 u16 data = nv_ro16(bios, table + (cond * 9) + 5);
518 u8 dmask = nv_ro08(bios, table + (cond * 9) + 7);
519 u8 value = nv_ro08(bios, table + (cond * 9) + 8);
520 u8 ioval = (init_rdvgai(init, port, index) & mask) >> shift;
521 return (nv_ro08(bios, data + ioval) & dmask) == value;
527 init_shift(u32 data, u8 shift)
530 return data >> shift;
531 return data << (0x100 - shift);
535 init_tmds_reg(struct nvbios_init *init, u8 tmds)
537 /* For mlv < 0x80, it is an index into a table of TMDS base addresses.
538 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
539 * CR58 for CR57 = 0 to index a table of offsets to the basic
541 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
542 * CR58 for CR57 = 0 to index a table of offsets to the basic
543 * 0x6808b0 address, and then flip the offset by 8.
546 const int pramdac_offset[13] = {
547 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
548 const u32 pramdac_table[4] = {
549 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
553 u32 dacoffset = pramdac_offset[init->outp->or];
556 return 0x6808b0 + dacoffset;
560 error("tmds opcodes need dcb\n");
562 if (tmds < ARRAY_SIZE(pramdac_table))
563 return pramdac_table[tmds];
565 error("tmds selector 0x%02x unknown\n", tmds);
571 /******************************************************************************
572 * init opcode handlers
573 *****************************************************************************/
576 * init_reserved - stub for various unknown/unused single-byte opcodes
580 init_reserved(struct nvbios_init *init)
582 u8 opcode = nv_ro08(init->bios, init->offset);
594 trace("RESERVED 0x%02x\t", opcode);
595 for (i = 1; i < length; i++)
596 cont(" 0x%02x", nv_ro08(init->bios, init->offset + i));
598 init->offset += length;
602 * INIT_DONE - opcode 0x71
606 init_done(struct nvbios_init *init)
609 init->offset = 0x0000;
613 * INIT_IO_RESTRICT_PROG - opcode 0x32
617 init_io_restrict_prog(struct nvbios_init *init)
619 struct nouveau_bios *bios = init->bios;
620 u16 port = nv_ro16(bios, init->offset + 1);
621 u8 index = nv_ro08(bios, init->offset + 3);
622 u8 mask = nv_ro08(bios, init->offset + 4);
623 u8 shift = nv_ro08(bios, init->offset + 5);
624 u8 count = nv_ro08(bios, init->offset + 6);
625 u32 reg = nv_ro32(bios, init->offset + 7);
628 trace("IO_RESTRICT_PROG\tR[0x%06x] = "
629 "((0x%04x[0x%02x] & 0x%02x) >> %d) [{\n",
630 reg, port, index, mask, shift);
633 conf = (init_rdvgai(init, port, index) & mask) >> shift;
634 for (i = 0; i < count; i++) {
635 u32 data = nv_ro32(bios, init->offset);
638 trace("\t0x%08x *\n", data);
639 init_wr32(init, reg, data);
641 trace("\t0x%08x\n", data);
650 * INIT_REPEAT - opcode 0x33
654 init_repeat(struct nvbios_init *init)
656 struct nouveau_bios *bios = init->bios;
657 u8 count = nv_ro08(bios, init->offset + 1);
658 u16 repeat = init->repeat;
660 trace("REPEAT\t0x%02x\n", count);
663 init->repeat = init->offset;
664 init->repend = init->offset;
666 init->offset = init->repeat;
669 trace("REPEAT\t0x%02x\n", count);
671 init->offset = init->repend;
672 init->repeat = repeat;
676 * INIT_IO_RESTRICT_PLL - opcode 0x34
680 init_io_restrict_pll(struct nvbios_init *init)
682 struct nouveau_bios *bios = init->bios;
683 u16 port = nv_ro16(bios, init->offset + 1);
684 u8 index = nv_ro08(bios, init->offset + 3);
685 u8 mask = nv_ro08(bios, init->offset + 4);
686 u8 shift = nv_ro08(bios, init->offset + 5);
687 s8 iofc = nv_ro08(bios, init->offset + 6);
688 u8 count = nv_ro08(bios, init->offset + 7);
689 u32 reg = nv_ro32(bios, init->offset + 8);
692 trace("IO_RESTRICT_PLL\tR[0x%06x] =PLL= "
693 "((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) IOFCOND 0x%02x [{\n",
694 reg, port, index, mask, shift, iofc);
697 conf = (init_rdvgai(init, port, index) & mask) >> shift;
698 for (i = 0; i < count; i++) {
699 u32 freq = nv_ro16(bios, init->offset) * 10;
702 trace("\t%dkHz *\n", freq);
703 if (iofc > 0 && init_io_flag_condition_met(init, iofc))
705 init_prog_pll(init, reg, freq);
707 trace("\t%dkHz\n", freq);
716 * INIT_END_REPEAT - opcode 0x36
720 init_end_repeat(struct nvbios_init *init)
722 trace("END_REPEAT\n");
726 init->repend = init->offset;
732 * INIT_COPY - opcode 0x37
736 init_copy(struct nvbios_init *init)
738 struct nouveau_bios *bios = init->bios;
739 u32 reg = nv_ro32(bios, init->offset + 1);
740 u8 shift = nv_ro08(bios, init->offset + 5);
741 u8 smask = nv_ro08(bios, init->offset + 6);
742 u16 port = nv_ro16(bios, init->offset + 7);
743 u8 index = nv_ro08(bios, init->offset + 9);
744 u8 mask = nv_ro08(bios, init->offset + 10);
747 trace("COPY\t0x%04x[0x%02x] &= 0x%02x |= "
748 "((R[0x%06x] %s 0x%02x) & 0x%02x)\n",
749 port, index, mask, reg, (shift & 0x80) ? "<<" : ">>",
750 (shift & 0x80) ? (0x100 - shift) : shift, smask);
753 data = init_rdvgai(init, port, index) & mask;
754 data |= init_shift(init_rd32(init, reg), shift) & smask;
755 init_wrvgai(init, port, index, data);
759 * INIT_NOT - opcode 0x38
763 init_not(struct nvbios_init *init)
771 * INIT_IO_FLAG_CONDITION - opcode 0x39
775 init_io_flag_condition(struct nvbios_init *init)
777 struct nouveau_bios *bios = init->bios;
778 u8 cond = nv_ro08(bios, init->offset + 1);
780 trace("IO_FLAG_CONDITION\t0x%02x\n", cond);
783 if (!init_io_flag_condition_met(init, cond))
784 init_exec_set(init, false);
788 * INIT_DP_CONDITION - opcode 0x3a
792 init_dp_condition(struct nvbios_init *init)
794 struct nouveau_bios *bios = init->bios;
795 struct nvbios_dpout info;
796 u8 cond = nv_ro08(bios, init->offset + 1);
797 u8 unkn = nv_ro08(bios, init->offset + 2);
798 u8 ver, hdr, cnt, len;
801 trace("DP_CONDITION\t0x%02x 0x%02x\n", cond, unkn);
806 if (init_conn(init) != DCB_CONNECTOR_eDP)
807 init_exec_set(init, false);
812 (data = nvbios_dpout_match(bios, DCB_OUTPUT_DP,
813 (init->outp->or << 0) |
814 (init->outp->sorconf.link << 6),
815 &ver, &hdr, &cnt, &len, &info)))
817 if (!(info.flags & cond))
818 init_exec_set(init, false);
823 warn("script needs dp output table data\n");
826 if (!(init_rdauxr(init, 0x0d) & 1))
827 init_exec_set(init, false);
830 warn("unknown dp condition 0x%02x\n", cond);
836 * INIT_IO_MASK_OR - opcode 0x3b
840 init_io_mask_or(struct nvbios_init *init)
842 struct nouveau_bios *bios = init->bios;
843 u8 index = nv_ro08(bios, init->offset + 1);
844 u8 or = init_or(init);
847 trace("IO_MASK_OR\t0x03d4[0x%02x] &= ~(1 << 0x%02x)\n", index, or);
850 data = init_rdvgai(init, 0x03d4, index);
851 init_wrvgai(init, 0x03d4, index, data &= ~(1 << or));
855 * INIT_IO_OR - opcode 0x3c
859 init_io_or(struct nvbios_init *init)
861 struct nouveau_bios *bios = init->bios;
862 u8 index = nv_ro08(bios, init->offset + 1);
863 u8 or = init_or(init);
866 trace("IO_OR\t0x03d4[0x%02x] |= (1 << 0x%02x)\n", index, or);
869 data = init_rdvgai(init, 0x03d4, index);
870 init_wrvgai(init, 0x03d4, index, data | (1 << or));
874 * INIT_INDEX_ADDRESS_LATCHED - opcode 0x49
878 init_idx_addr_latched(struct nvbios_init *init)
880 struct nouveau_bios *bios = init->bios;
881 u32 creg = nv_ro32(bios, init->offset + 1);
882 u32 dreg = nv_ro32(bios, init->offset + 5);
883 u32 mask = nv_ro32(bios, init->offset + 9);
884 u32 data = nv_ro32(bios, init->offset + 13);
885 u8 count = nv_ro08(bios, init->offset + 17);
887 trace("INDEX_ADDRESS_LATCHED\t"
888 "R[0x%06x] : R[0x%06x]\n\tCTRL &= 0x%08x |= 0x%08x\n",
889 creg, dreg, mask, data);
893 u8 iaddr = nv_ro08(bios, init->offset + 0);
894 u8 idata = nv_ro08(bios, init->offset + 1);
896 trace("\t[0x%02x] = 0x%02x\n", iaddr, idata);
899 init_wr32(init, dreg, idata);
900 init_mask(init, creg, ~mask, data | iaddr);
905 * INIT_IO_RESTRICT_PLL2 - opcode 0x4a
909 init_io_restrict_pll2(struct nvbios_init *init)
911 struct nouveau_bios *bios = init->bios;
912 u16 port = nv_ro16(bios, init->offset + 1);
913 u8 index = nv_ro08(bios, init->offset + 3);
914 u8 mask = nv_ro08(bios, init->offset + 4);
915 u8 shift = nv_ro08(bios, init->offset + 5);
916 u8 count = nv_ro08(bios, init->offset + 6);
917 u32 reg = nv_ro32(bios, init->offset + 7);
920 trace("IO_RESTRICT_PLL2\t"
921 "R[0x%06x] =PLL= ((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) [{\n",
922 reg, port, index, mask, shift);
925 conf = (init_rdvgai(init, port, index) & mask) >> shift;
926 for (i = 0; i < count; i++) {
927 u32 freq = nv_ro32(bios, init->offset);
929 trace("\t%dkHz *\n", freq);
930 init_prog_pll(init, reg, freq);
932 trace("\t%dkHz\n", freq);
940 * INIT_PLL2 - opcode 0x4b
944 init_pll2(struct nvbios_init *init)
946 struct nouveau_bios *bios = init->bios;
947 u32 reg = nv_ro32(bios, init->offset + 1);
948 u32 freq = nv_ro32(bios, init->offset + 5);
950 trace("PLL2\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
953 init_prog_pll(init, reg, freq);
957 * INIT_I2C_BYTE - opcode 0x4c
961 init_i2c_byte(struct nvbios_init *init)
963 struct nouveau_bios *bios = init->bios;
964 u8 index = nv_ro08(bios, init->offset + 1);
965 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
966 u8 count = nv_ro08(bios, init->offset + 3);
968 trace("I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
972 u8 reg = nv_ro08(bios, init->offset + 0);
973 u8 mask = nv_ro08(bios, init->offset + 1);
974 u8 data = nv_ro08(bios, init->offset + 2);
977 trace("\t[0x%02x] &= 0x%02x |= 0x%02x\n", reg, mask, data);
980 val = init_rdi2cr(init, index, addr, reg);
983 init_wri2cr(init, index, addr, reg, (val & mask) | data);
988 * INIT_ZM_I2C_BYTE - opcode 0x4d
992 init_zm_i2c_byte(struct nvbios_init *init)
994 struct nouveau_bios *bios = init->bios;
995 u8 index = nv_ro08(bios, init->offset + 1);
996 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
997 u8 count = nv_ro08(bios, init->offset + 3);
999 trace("ZM_I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
1003 u8 reg = nv_ro08(bios, init->offset + 0);
1004 u8 data = nv_ro08(bios, init->offset + 1);
1006 trace("\t[0x%02x] = 0x%02x\n", reg, data);
1009 init_wri2cr(init, index, addr, reg, data);
1015 * INIT_ZM_I2C - opcode 0x4e
1019 init_zm_i2c(struct nvbios_init *init)
1021 struct nouveau_bios *bios = init->bios;
1022 u8 index = nv_ro08(bios, init->offset + 1);
1023 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
1024 u8 count = nv_ro08(bios, init->offset + 3);
1027 trace("ZM_I2C\tI2C[0x%02x][0x%02x]\n", index, addr);
1030 for (i = 0; i < count; i++) {
1031 data[i] = nv_ro08(bios, init->offset);
1032 trace("\t0x%02x\n", data[i]);
1036 if (init_exec(init)) {
1037 struct nouveau_i2c_port *port = init_i2c(init, index);
1038 struct i2c_msg msg = {
1039 .addr = addr, .flags = 0, .len = count, .buf = data,
1043 if (port && (ret = i2c_transfer(&port->adapter, &msg, 1)) != 1)
1044 warn("i2c wr failed, %d\n", ret);
1049 * INIT_TMDS - opcode 0x4f
1053 init_tmds(struct nvbios_init *init)
1055 struct nouveau_bios *bios = init->bios;
1056 u8 tmds = nv_ro08(bios, init->offset + 1);
1057 u8 addr = nv_ro08(bios, init->offset + 2);
1058 u8 mask = nv_ro08(bios, init->offset + 3);
1059 u8 data = nv_ro08(bios, init->offset + 4);
1060 u32 reg = init_tmds_reg(init, tmds);
1062 trace("TMDS\tT[0x%02x][0x%02x] &= 0x%02x |= 0x%02x\n",
1063 tmds, addr, mask, data);
1069 init_wr32(init, reg + 0, addr | 0x00010000);
1070 init_wr32(init, reg + 4, data | (init_rd32(init, reg + 4) & mask));
1071 init_wr32(init, reg + 0, addr);
1075 * INIT_ZM_TMDS_GROUP - opcode 0x50
1079 init_zm_tmds_group(struct nvbios_init *init)
1081 struct nouveau_bios *bios = init->bios;
1082 u8 tmds = nv_ro08(bios, init->offset + 1);
1083 u8 count = nv_ro08(bios, init->offset + 2);
1084 u32 reg = init_tmds_reg(init, tmds);
1086 trace("TMDS_ZM_GROUP\tT[0x%02x]\n", tmds);
1090 u8 addr = nv_ro08(bios, init->offset + 0);
1091 u8 data = nv_ro08(bios, init->offset + 1);
1093 trace("\t[0x%02x] = 0x%02x\n", addr, data);
1096 init_wr32(init, reg + 4, data);
1097 init_wr32(init, reg + 0, addr);
1102 * INIT_CR_INDEX_ADDRESS_LATCHED - opcode 0x51
1106 init_cr_idx_adr_latch(struct nvbios_init *init)
1108 struct nouveau_bios *bios = init->bios;
1109 u8 addr0 = nv_ro08(bios, init->offset + 1);
1110 u8 addr1 = nv_ro08(bios, init->offset + 2);
1111 u8 base = nv_ro08(bios, init->offset + 3);
1112 u8 count = nv_ro08(bios, init->offset + 4);
1115 trace("CR_INDEX_ADDR C[%02x] C[%02x]\n", addr0, addr1);
1118 save0 = init_rdvgai(init, 0x03d4, addr0);
1120 u8 data = nv_ro08(bios, init->offset);
1122 trace("\t\t[0x%02x] = 0x%02x\n", base, data);
1125 init_wrvgai(init, 0x03d4, addr0, base++);
1126 init_wrvgai(init, 0x03d4, addr1, data);
1128 init_wrvgai(init, 0x03d4, addr0, save0);
1132 * INIT_CR - opcode 0x52
1136 init_cr(struct nvbios_init *init)
1138 struct nouveau_bios *bios = init->bios;
1139 u8 addr = nv_ro08(bios, init->offset + 1);
1140 u8 mask = nv_ro08(bios, init->offset + 2);
1141 u8 data = nv_ro08(bios, init->offset + 3);
1144 trace("CR\t\tC[0x%02x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
1147 val = init_rdvgai(init, 0x03d4, addr) & mask;
1148 init_wrvgai(init, 0x03d4, addr, val | data);
1152 * INIT_ZM_CR - opcode 0x53
1156 init_zm_cr(struct nvbios_init *init)
1158 struct nouveau_bios *bios = init->bios;
1159 u8 addr = nv_ro08(bios, init->offset + 1);
1160 u8 data = nv_ro08(bios, init->offset + 2);
1162 trace("ZM_CR\tC[0x%02x] = 0x%02x\n", addr, data);
1165 init_wrvgai(init, 0x03d4, addr, data);
1169 * INIT_ZM_CR_GROUP - opcode 0x54
1173 init_zm_cr_group(struct nvbios_init *init)
1175 struct nouveau_bios *bios = init->bios;
1176 u8 count = nv_ro08(bios, init->offset + 1);
1178 trace("ZM_CR_GROUP\n");
1182 u8 addr = nv_ro08(bios, init->offset + 0);
1183 u8 data = nv_ro08(bios, init->offset + 1);
1185 trace("\t\tC[0x%02x] = 0x%02x\n", addr, data);
1188 init_wrvgai(init, 0x03d4, addr, data);
1193 * INIT_CONDITION_TIME - opcode 0x56
1197 init_condition_time(struct nvbios_init *init)
1199 struct nouveau_bios *bios = init->bios;
1200 u8 cond = nv_ro08(bios, init->offset + 1);
1201 u8 retry = nv_ro08(bios, init->offset + 2);
1202 u8 wait = min((u16)retry * 50, 100);
1204 trace("CONDITION_TIME\t0x%02x 0x%02x\n", cond, retry);
1207 if (!init_exec(init))
1211 if (init_condition_met(init, cond))
1216 init_exec_set(init, false);
1220 * INIT_LTIME - opcode 0x57
1224 init_ltime(struct nvbios_init *init)
1226 struct nouveau_bios *bios = init->bios;
1227 u16 msec = nv_ro16(bios, init->offset + 1);
1229 trace("LTIME\t0x%04x\n", msec);
1232 if (init_exec(init))
1237 * INIT_ZM_REG_SEQUENCE - opcode 0x58
1241 init_zm_reg_sequence(struct nvbios_init *init)
1243 struct nouveau_bios *bios = init->bios;
1244 u32 base = nv_ro32(bios, init->offset + 1);
1245 u8 count = nv_ro08(bios, init->offset + 5);
1247 trace("ZM_REG_SEQUENCE\t0x%02x\n", count);
1251 u32 data = nv_ro32(bios, init->offset);
1253 trace("\t\tR[0x%06x] = 0x%08x\n", base, data);
1256 init_wr32(init, base, data);
1262 * INIT_SUB_DIRECT - opcode 0x5b
1266 init_sub_direct(struct nvbios_init *init)
1268 struct nouveau_bios *bios = init->bios;
1269 u16 addr = nv_ro16(bios, init->offset + 1);
1272 trace("SUB_DIRECT\t0x%04x\n", addr);
1274 if (init_exec(init)) {
1275 save = init->offset;
1276 init->offset = addr;
1277 if (nvbios_exec(init)) {
1278 error("error parsing sub-table\n");
1281 init->offset = save;
1288 * INIT_JUMP - opcode 0x5c
1292 init_jump(struct nvbios_init *init)
1294 struct nouveau_bios *bios = init->bios;
1295 u16 offset = nv_ro16(bios, init->offset + 1);
1297 trace("JUMP\t0x%04x\n", offset);
1298 init->offset = offset;
1302 * INIT_I2C_IF - opcode 0x5e
1306 init_i2c_if(struct nvbios_init *init)
1308 struct nouveau_bios *bios = init->bios;
1309 u8 index = nv_ro08(bios, init->offset + 1);
1310 u8 addr = nv_ro08(bios, init->offset + 2);
1311 u8 reg = nv_ro08(bios, init->offset + 3);
1312 u8 mask = nv_ro08(bios, init->offset + 4);
1313 u8 data = nv_ro08(bios, init->offset + 5);
1316 trace("I2C_IF\tI2C[0x%02x][0x%02x][0x%02x] & 0x%02x == 0x%02x\n",
1317 index, addr, reg, mask, data);
1319 init_exec_force(init, true);
1321 value = init_rdi2cr(init, index, addr, reg);
1322 if ((value & mask) != data)
1323 init_exec_set(init, false);
1325 init_exec_force(init, false);
1329 * INIT_COPY_NV_REG - opcode 0x5f
1333 init_copy_nv_reg(struct nvbios_init *init)
1335 struct nouveau_bios *bios = init->bios;
1336 u32 sreg = nv_ro32(bios, init->offset + 1);
1337 u8 shift = nv_ro08(bios, init->offset + 5);
1338 u32 smask = nv_ro32(bios, init->offset + 6);
1339 u32 sxor = nv_ro32(bios, init->offset + 10);
1340 u32 dreg = nv_ro32(bios, init->offset + 14);
1341 u32 dmask = nv_ro32(bios, init->offset + 18);
1344 trace("COPY_NV_REG\tR[0x%06x] &= 0x%08x |= "
1345 "((R[0x%06x] %s 0x%02x) & 0x%08x ^ 0x%08x)\n",
1346 dreg, dmask, sreg, (shift & 0x80) ? "<<" : ">>",
1347 (shift & 0x80) ? (0x100 - shift) : shift, smask, sxor);
1350 data = init_shift(init_rd32(init, sreg), shift);
1351 init_mask(init, dreg, ~dmask, (data & smask) ^ sxor);
1355 * INIT_ZM_INDEX_IO - opcode 0x62
1359 init_zm_index_io(struct nvbios_init *init)
1361 struct nouveau_bios *bios = init->bios;
1362 u16 port = nv_ro16(bios, init->offset + 1);
1363 u8 index = nv_ro08(bios, init->offset + 3);
1364 u8 data = nv_ro08(bios, init->offset + 4);
1366 trace("ZM_INDEX_IO\tI[0x%04x][0x%02x] = 0x%02x\n", port, index, data);
1369 init_wrvgai(init, port, index, data);
1373 * INIT_COMPUTE_MEM - opcode 0x63
1377 init_compute_mem(struct nvbios_init *init)
1379 struct nouveau_devinit *devinit = nouveau_devinit(init->bios);
1381 trace("COMPUTE_MEM\n");
1384 init_exec_force(init, true);
1385 if (init_exec(init) && devinit->meminit)
1386 devinit->meminit(devinit);
1387 init_exec_force(init, false);
1391 * INIT_RESET - opcode 0x65
1395 init_reset(struct nvbios_init *init)
1397 struct nouveau_bios *bios = init->bios;
1398 u32 reg = nv_ro32(bios, init->offset + 1);
1399 u32 data1 = nv_ro32(bios, init->offset + 5);
1400 u32 data2 = nv_ro32(bios, init->offset + 9);
1403 trace("RESET\tR[0x%08x] = 0x%08x, 0x%08x", reg, data1, data2);
1405 init_exec_force(init, true);
1407 savepci19 = init_mask(init, 0x00184c, 0x00000f00, 0x00000000);
1408 init_wr32(init, reg, data1);
1410 init_wr32(init, reg, data2);
1411 init_wr32(init, 0x00184c, savepci19);
1412 init_mask(init, 0x001850, 0x00000001, 0x00000000);
1414 init_exec_force(init, false);
1418 * INIT_CONFIGURE_MEM - opcode 0x66
1422 init_configure_mem_clk(struct nvbios_init *init)
1424 u16 mdata = bmp_mem_init_table(init->bios);
1426 mdata += (init_rdvgai(init, 0x03d4, 0x3c) >> 4) * 66;
1431 init_configure_mem(struct nvbios_init *init)
1433 struct nouveau_bios *bios = init->bios;
1437 trace("CONFIGURE_MEM\n");
1440 if (bios->version.major > 2) {
1444 init_exec_force(init, true);
1446 mdata = init_configure_mem_clk(init);
1447 sdata = bmp_sdr_seq_table(bios);
1448 if (nv_ro08(bios, mdata) & 0x01)
1449 sdata = bmp_ddr_seq_table(bios);
1450 mdata += 6; /* skip to data */
1452 data = init_rdvgai(init, 0x03c4, 0x01);
1453 init_wrvgai(init, 0x03c4, 0x01, data | 0x20);
1455 while ((addr = nv_ro32(bios, sdata)) != 0xffffffff) {
1457 case 0x10021c: /* CKE_NORMAL */
1458 case 0x1002d0: /* CMD_REFRESH */
1459 case 0x1002d4: /* CMD_PRECHARGE */
1463 data = nv_ro32(bios, mdata);
1465 if (data == 0xffffffff)
1470 init_wr32(init, addr, data);
1473 init_exec_force(init, false);
1477 * INIT_CONFIGURE_CLK - opcode 0x67
1481 init_configure_clk(struct nvbios_init *init)
1483 struct nouveau_bios *bios = init->bios;
1486 trace("CONFIGURE_CLK\n");
1489 if (bios->version.major > 2) {
1493 init_exec_force(init, true);
1495 mdata = init_configure_mem_clk(init);
1498 clock = nv_ro16(bios, mdata + 4) * 10;
1499 init_prog_pll(init, 0x680500, clock);
1502 clock = nv_ro16(bios, mdata + 2) * 10;
1503 if (nv_ro08(bios, mdata) & 0x01)
1505 init_prog_pll(init, 0x680504, clock);
1507 init_exec_force(init, false);
1511 * INIT_CONFIGURE_PREINIT - opcode 0x68
1515 init_configure_preinit(struct nvbios_init *init)
1517 struct nouveau_bios *bios = init->bios;
1520 trace("CONFIGURE_PREINIT\n");
1523 if (bios->version.major > 2) {
1527 init_exec_force(init, true);
1529 strap = init_rd32(init, 0x101000);
1530 strap = ((strap << 2) & 0xf0) | ((strap & 0x40) >> 6);
1531 init_wrvgai(init, 0x03d4, 0x3c, strap);
1533 init_exec_force(init, false);
1537 * INIT_IO - opcode 0x69
1541 init_io(struct nvbios_init *init)
1543 struct nouveau_bios *bios = init->bios;
1544 u16 port = nv_ro16(bios, init->offset + 1);
1545 u8 mask = nv_ro16(bios, init->offset + 3);
1546 u8 data = nv_ro16(bios, init->offset + 4);
1549 trace("IO\t\tI[0x%04x] &= 0x%02x |= 0x%02x\n", port, mask, data);
1552 /* ummm.. yes.. should really figure out wtf this is and why it's
1553 * needed some day.. it's almost certainly wrong, but, it also
1554 * somehow makes things work...
1556 if (nv_device(init->bios)->card_type >= NV_50 &&
1557 port == 0x03c3 && data == 0x01) {
1558 init_mask(init, 0x614100, 0xf0800000, 0x00800000);
1559 init_mask(init, 0x00e18c, 0x00020000, 0x00020000);
1560 init_mask(init, 0x614900, 0xf0800000, 0x00800000);
1561 init_mask(init, 0x000200, 0x40000000, 0x00000000);
1563 init_mask(init, 0x00e18c, 0x00020000, 0x00000000);
1564 init_mask(init, 0x000200, 0x40000000, 0x40000000);
1565 init_wr32(init, 0x614100, 0x00800018);
1566 init_wr32(init, 0x614900, 0x00800018);
1568 init_wr32(init, 0x614100, 0x10000018);
1569 init_wr32(init, 0x614900, 0x10000018);
1572 value = init_rdport(init, port) & mask;
1573 init_wrport(init, port, data | value);
1577 * INIT_SUB - opcode 0x6b
1581 init_sub(struct nvbios_init *init)
1583 struct nouveau_bios *bios = init->bios;
1584 u8 index = nv_ro08(bios, init->offset + 1);
1587 trace("SUB\t0x%02x\n", index);
1589 addr = init_script(bios, index);
1590 if (addr && init_exec(init)) {
1591 save = init->offset;
1592 init->offset = addr;
1593 if (nvbios_exec(init)) {
1594 error("error parsing sub-table\n");
1597 init->offset = save;
1604 * INIT_RAM_CONDITION - opcode 0x6d
1608 init_ram_condition(struct nvbios_init *init)
1610 struct nouveau_bios *bios = init->bios;
1611 u8 mask = nv_ro08(bios, init->offset + 1);
1612 u8 value = nv_ro08(bios, init->offset + 2);
1614 trace("RAM_CONDITION\t"
1615 "(R[0x100000] & 0x%02x) == 0x%02x\n", mask, value);
1618 if ((init_rd32(init, 0x100000) & mask) != value)
1619 init_exec_set(init, false);
1623 * INIT_NV_REG - opcode 0x6e
1627 init_nv_reg(struct nvbios_init *init)
1629 struct nouveau_bios *bios = init->bios;
1630 u32 reg = nv_ro32(bios, init->offset + 1);
1631 u32 mask = nv_ro32(bios, init->offset + 5);
1632 u32 data = nv_ro32(bios, init->offset + 9);
1634 trace("NV_REG\tR[0x%06x] &= 0x%08x |= 0x%08x\n", reg, mask, data);
1637 init_mask(init, reg, ~mask, data);
1641 * INIT_MACRO - opcode 0x6f
1645 init_macro(struct nvbios_init *init)
1647 struct nouveau_bios *bios = init->bios;
1648 u8 macro = nv_ro08(bios, init->offset + 1);
1651 trace("MACRO\t0x%02x\n", macro);
1653 table = init_macro_table(init);
1655 u32 addr = nv_ro32(bios, table + (macro * 8) + 0);
1656 u32 data = nv_ro32(bios, table + (macro * 8) + 4);
1657 trace("\t\tR[0x%06x] = 0x%08x\n", addr, data);
1658 init_wr32(init, addr, data);
1665 * INIT_RESUME - opcode 0x72
1669 init_resume(struct nvbios_init *init)
1673 init_exec_set(init, true);
1677 * INIT_TIME - opcode 0x74
1681 init_time(struct nvbios_init *init)
1683 struct nouveau_bios *bios = init->bios;
1684 u16 usec = nv_ro16(bios, init->offset + 1);
1686 trace("TIME\t0x%04x\n", usec);
1689 if (init_exec(init)) {
1693 mdelay((usec + 900) / 1000);
1698 * INIT_CONDITION - opcode 0x75
1702 init_condition(struct nvbios_init *init)
1704 struct nouveau_bios *bios = init->bios;
1705 u8 cond = nv_ro08(bios, init->offset + 1);
1707 trace("CONDITION\t0x%02x\n", cond);
1710 if (!init_condition_met(init, cond))
1711 init_exec_set(init, false);
1715 * INIT_IO_CONDITION - opcode 0x76
1719 init_io_condition(struct nvbios_init *init)
1721 struct nouveau_bios *bios = init->bios;
1722 u8 cond = nv_ro08(bios, init->offset + 1);
1724 trace("IO_CONDITION\t0x%02x\n", cond);
1727 if (!init_io_condition_met(init, cond))
1728 init_exec_set(init, false);
1732 * INIT_INDEX_IO - opcode 0x78
1736 init_index_io(struct nvbios_init *init)
1738 struct nouveau_bios *bios = init->bios;
1739 u16 port = nv_ro16(bios, init->offset + 1);
1740 u8 index = nv_ro16(bios, init->offset + 3);
1741 u8 mask = nv_ro08(bios, init->offset + 4);
1742 u8 data = nv_ro08(bios, init->offset + 5);
1745 trace("INDEX_IO\tI[0x%04x][0x%02x] &= 0x%02x |= 0x%02x\n",
1746 port, index, mask, data);
1749 value = init_rdvgai(init, port, index) & mask;
1750 init_wrvgai(init, port, index, data | value);
1754 * INIT_PLL - opcode 0x79
1758 init_pll(struct nvbios_init *init)
1760 struct nouveau_bios *bios = init->bios;
1761 u32 reg = nv_ro32(bios, init->offset + 1);
1762 u32 freq = nv_ro16(bios, init->offset + 5) * 10;
1764 trace("PLL\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
1767 init_prog_pll(init, reg, freq);
1771 * INIT_ZM_REG - opcode 0x7a
1775 init_zm_reg(struct nvbios_init *init)
1777 struct nouveau_bios *bios = init->bios;
1778 u32 addr = nv_ro32(bios, init->offset + 1);
1779 u32 data = nv_ro32(bios, init->offset + 5);
1781 trace("ZM_REG\tR[0x%06x] = 0x%08x\n", addr, data);
1784 if (addr == 0x000200)
1787 init_wr32(init, addr, data);
1791 * INIT_RAM_RESTRICT_PLL - opcde 0x87
1795 init_ram_restrict_pll(struct nvbios_init *init)
1797 struct nouveau_bios *bios = init->bios;
1798 u8 type = nv_ro08(bios, init->offset + 1);
1799 u8 count = init_ram_restrict_group_count(init);
1800 u8 strap = init_ram_restrict(init);
1803 trace("RAM_RESTRICT_PLL\t0x%02x\n", type);
1806 for (cconf = 0; cconf < count; cconf++) {
1807 u32 freq = nv_ro32(bios, init->offset);
1809 if (cconf == strap) {
1810 trace("%dkHz *\n", freq);
1811 init_prog_pll(init, type, freq);
1813 trace("%dkHz\n", freq);
1821 * INIT_GPIO - opcode 0x8e
1825 init_gpio(struct nvbios_init *init)
1827 struct nouveau_gpio *gpio = nouveau_gpio(init->bios);
1832 if (init_exec(init) && gpio && gpio->reset)
1833 gpio->reset(gpio, DCB_GPIO_UNUSED);
1837 * INIT_RAM_RESTRICT_ZM_GROUP - opcode 0x8f
1841 init_ram_restrict_zm_reg_group(struct nvbios_init *init)
1843 struct nouveau_bios *bios = init->bios;
1844 u32 addr = nv_ro32(bios, init->offset + 1);
1845 u8 incr = nv_ro08(bios, init->offset + 5);
1846 u8 num = nv_ro08(bios, init->offset + 6);
1847 u8 count = init_ram_restrict_group_count(init);
1848 u8 index = init_ram_restrict(init);
1851 trace("RAM_RESTRICT_ZM_REG_GROUP\t"
1852 "R[0x%08x] 0x%02x 0x%02x\n", addr, incr, num);
1855 for (i = 0; i < num; i++) {
1856 trace("\tR[0x%06x] = {\n", addr);
1857 for (j = 0; j < count; j++) {
1858 u32 data = nv_ro32(bios, init->offset);
1861 trace("\t\t0x%08x *\n", data);
1862 init_wr32(init, addr, data);
1864 trace("\t\t0x%08x\n", data);
1875 * INIT_COPY_ZM_REG - opcode 0x90
1879 init_copy_zm_reg(struct nvbios_init *init)
1881 struct nouveau_bios *bios = init->bios;
1882 u32 sreg = nv_ro32(bios, init->offset + 1);
1883 u32 dreg = nv_ro32(bios, init->offset + 5);
1885 trace("COPY_ZM_REG\tR[0x%06x] = R[0x%06x]\n", dreg, sreg);
1888 init_wr32(init, dreg, init_rd32(init, sreg));
1892 * INIT_ZM_REG_GROUP - opcode 0x91
1896 init_zm_reg_group(struct nvbios_init *init)
1898 struct nouveau_bios *bios = init->bios;
1899 u32 addr = nv_ro32(bios, init->offset + 1);
1900 u8 count = nv_ro08(bios, init->offset + 5);
1902 trace("ZM_REG_GROUP\tR[0x%06x] =\n", addr);
1906 u32 data = nv_ro32(bios, init->offset);
1907 trace("\t0x%08x\n", data);
1908 init_wr32(init, addr, data);
1914 * INIT_XLAT - opcode 0x96
1918 init_xlat(struct nvbios_init *init)
1920 struct nouveau_bios *bios = init->bios;
1921 u32 saddr = nv_ro32(bios, init->offset + 1);
1922 u8 sshift = nv_ro08(bios, init->offset + 5);
1923 u8 smask = nv_ro08(bios, init->offset + 6);
1924 u8 index = nv_ro08(bios, init->offset + 7);
1925 u32 daddr = nv_ro32(bios, init->offset + 8);
1926 u32 dmask = nv_ro32(bios, init->offset + 12);
1927 u8 shift = nv_ro08(bios, init->offset + 16);
1930 trace("INIT_XLAT\tR[0x%06x] &= 0x%08x |= "
1931 "(X%02x((R[0x%06x] %s 0x%02x) & 0x%02x) << 0x%02x)\n",
1932 daddr, dmask, index, saddr, (sshift & 0x80) ? "<<" : ">>",
1933 (sshift & 0x80) ? (0x100 - sshift) : sshift, smask, shift);
1936 data = init_shift(init_rd32(init, saddr), sshift) & smask;
1937 data = init_xlat_(init, index, data) << shift;
1938 init_mask(init, daddr, ~dmask, data);
1942 * INIT_ZM_MASK_ADD - opcode 0x97
1946 init_zm_mask_add(struct nvbios_init *init)
1948 struct nouveau_bios *bios = init->bios;
1949 u32 addr = nv_ro32(bios, init->offset + 1);
1950 u32 mask = nv_ro32(bios, init->offset + 5);
1951 u32 add = nv_ro32(bios, init->offset + 9);
1954 trace("ZM_MASK_ADD\tR[0x%06x] &= 0x%08x += 0x%08x\n", addr, mask, add);
1957 data = init_rd32(init, addr);
1958 data = (data & mask) | ((data + add) & ~mask);
1959 init_wr32(init, addr, data);
1963 * INIT_AUXCH - opcode 0x98
1967 init_auxch(struct nvbios_init *init)
1969 struct nouveau_bios *bios = init->bios;
1970 u32 addr = nv_ro32(bios, init->offset + 1);
1971 u8 count = nv_ro08(bios, init->offset + 5);
1973 trace("AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
1977 u8 mask = nv_ro08(bios, init->offset + 0);
1978 u8 data = nv_ro08(bios, init->offset + 1);
1979 trace("\tAUX[0x%08x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
1980 mask = init_rdauxr(init, addr) & mask;
1981 init_wrauxr(init, addr, mask | data);
1987 * INIT_AUXCH - opcode 0x99
1991 init_zm_auxch(struct nvbios_init *init)
1993 struct nouveau_bios *bios = init->bios;
1994 u32 addr = nv_ro32(bios, init->offset + 1);
1995 u8 count = nv_ro08(bios, init->offset + 5);
1997 trace("ZM_AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
2001 u8 data = nv_ro08(bios, init->offset + 0);
2002 trace("\tAUX[0x%08x] = 0x%02x\n", addr, data);
2003 init_wrauxr(init, addr, data);
2009 * INIT_I2C_LONG_IF - opcode 0x9a
2013 init_i2c_long_if(struct nvbios_init *init)
2015 struct nouveau_bios *bios = init->bios;
2016 u8 index = nv_ro08(bios, init->offset + 1);
2017 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
2018 u8 reglo = nv_ro08(bios, init->offset + 3);
2019 u8 reghi = nv_ro08(bios, init->offset + 4);
2020 u8 mask = nv_ro08(bios, init->offset + 5);
2021 u8 data = nv_ro08(bios, init->offset + 6);
2022 struct nouveau_i2c_port *port;
2024 trace("I2C_LONG_IF\t"
2025 "I2C[0x%02x][0x%02x][0x%02x%02x] & 0x%02x == 0x%02x\n",
2026 index, addr, reglo, reghi, mask, data);
2029 port = init_i2c(init, index);
2031 u8 i[2] = { reghi, reglo };
2033 struct i2c_msg msg[] = {
2034 { .addr = addr, .flags = 0, .len = 2, .buf = i },
2035 { .addr = addr, .flags = I2C_M_RD, .len = 1, .buf = o }
2039 ret = i2c_transfer(&port->adapter, msg, 2);
2040 if (ret == 2 && ((o[0] & mask) == data))
2044 init_exec_set(init, false);
2048 * INIT_GPIO_NE - opcode 0xa9
2052 init_gpio_ne(struct nvbios_init *init)
2054 struct nouveau_bios *bios = init->bios;
2055 struct nouveau_gpio *gpio = nouveau_gpio(bios);
2056 struct dcb_gpio_func func;
2057 u8 count = nv_ro08(bios, init->offset + 1);
2058 u8 idx = 0, ver, len;
2064 for (i = init->offset; i < init->offset + count; i++)
2065 cont("0x%02x ", nv_ro08(bios, i));
2068 while ((data = dcb_gpio_parse(bios, 0, idx++, &ver, &len, &func))) {
2069 if (func.func != DCB_GPIO_UNUSED) {
2070 for (i = init->offset; i < init->offset + count; i++) {
2071 if (func.func == nv_ro08(bios, i))
2075 trace("\tFUNC[0x%02x]", func.func);
2076 if (i == (init->offset + count)) {
2078 if (init_exec(init) && gpio && gpio->reset)
2079 gpio->reset(gpio, func.func);
2085 init->offset += count;
2088 static struct nvbios_init_opcode {
2089 void (*exec)(struct nvbios_init *);
2091 [0x32] = { init_io_restrict_prog },
2092 [0x33] = { init_repeat },
2093 [0x34] = { init_io_restrict_pll },
2094 [0x36] = { init_end_repeat },
2095 [0x37] = { init_copy },
2096 [0x38] = { init_not },
2097 [0x39] = { init_io_flag_condition },
2098 [0x3a] = { init_dp_condition },
2099 [0x3b] = { init_io_mask_or },
2100 [0x3c] = { init_io_or },
2101 [0x49] = { init_idx_addr_latched },
2102 [0x4a] = { init_io_restrict_pll2 },
2103 [0x4b] = { init_pll2 },
2104 [0x4c] = { init_i2c_byte },
2105 [0x4d] = { init_zm_i2c_byte },
2106 [0x4e] = { init_zm_i2c },
2107 [0x4f] = { init_tmds },
2108 [0x50] = { init_zm_tmds_group },
2109 [0x51] = { init_cr_idx_adr_latch },
2110 [0x52] = { init_cr },
2111 [0x53] = { init_zm_cr },
2112 [0x54] = { init_zm_cr_group },
2113 [0x56] = { init_condition_time },
2114 [0x57] = { init_ltime },
2115 [0x58] = { init_zm_reg_sequence },
2116 [0x5b] = { init_sub_direct },
2117 [0x5c] = { init_jump },
2118 [0x5e] = { init_i2c_if },
2119 [0x5f] = { init_copy_nv_reg },
2120 [0x62] = { init_zm_index_io },
2121 [0x63] = { init_compute_mem },
2122 [0x65] = { init_reset },
2123 [0x66] = { init_configure_mem },
2124 [0x67] = { init_configure_clk },
2125 [0x68] = { init_configure_preinit },
2126 [0x69] = { init_io },
2127 [0x6b] = { init_sub },
2128 [0x6d] = { init_ram_condition },
2129 [0x6e] = { init_nv_reg },
2130 [0x6f] = { init_macro },
2131 [0x71] = { init_done },
2132 [0x72] = { init_resume },
2133 [0x74] = { init_time },
2134 [0x75] = { init_condition },
2135 [0x76] = { init_io_condition },
2136 [0x78] = { init_index_io },
2137 [0x79] = { init_pll },
2138 [0x7a] = { init_zm_reg },
2139 [0x87] = { init_ram_restrict_pll },
2140 [0x8c] = { init_reserved },
2141 [0x8d] = { init_reserved },
2142 [0x8e] = { init_gpio },
2143 [0x8f] = { init_ram_restrict_zm_reg_group },
2144 [0x90] = { init_copy_zm_reg },
2145 [0x91] = { init_zm_reg_group },
2146 [0x92] = { init_reserved },
2147 [0x96] = { init_xlat },
2148 [0x97] = { init_zm_mask_add },
2149 [0x98] = { init_auxch },
2150 [0x99] = { init_zm_auxch },
2151 [0x9a] = { init_i2c_long_if },
2152 [0xa9] = { init_gpio_ne },
2153 [0xaa] = { init_reserved },
2156 #define init_opcode_nr (sizeof(init_opcode) / sizeof(init_opcode[0]))
2159 nvbios_exec(struct nvbios_init *init)
2162 while (init->offset) {
2163 u8 opcode = nv_ro08(init->bios, init->offset);
2164 if (opcode >= init_opcode_nr || !init_opcode[opcode].exec) {
2165 error("unknown opcode 0x%02x\n", opcode);
2169 init_opcode[opcode].exec(init);
2176 nvbios_init(struct nouveau_subdev *subdev, bool execute)
2178 struct nouveau_bios *bios = nouveau_bios(subdev);
2184 nv_info(bios, "running init tables\n");
2185 while (!ret && (data = (init_script(bios, ++i)))) {
2186 struct nvbios_init init = {
2192 .execute = execute ? 1 : 0,
2195 ret = nvbios_exec(&init);
2198 /* the vbios parser will run this right after the normal init
2199 * tables, whereas the binary driver appears to run it later.
2201 if (!ret && (data = init_unknown_script(bios))) {
2202 struct nvbios_init init = {
2208 .execute = execute ? 1 : 0,
2211 ret = nvbios_exec(&init);