2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <core/class.h>
27 #include <core/handle.h>
28 #include <core/engctx.h>
30 #include <subdev/fb.h>
31 #include <subdev/timer.h>
33 #include <engine/graph.h>
34 #include <engine/fifo.h>
39 struct nv40_graph_priv {
40 struct nouveau_graph base;
44 struct nv40_graph_chan {
45 struct nouveau_graph_chan base;
48 /*******************************************************************************
49 * Graphics object classes
50 ******************************************************************************/
53 nv40_graph_object_ctor(struct nouveau_object *parent,
54 struct nouveau_object *engine,
55 struct nouveau_oclass *oclass, void *data, u32 size,
56 struct nouveau_object **pobject)
58 struct nouveau_gpuobj *obj;
61 ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent,
63 *pobject = nv_object(obj);
67 nv_wo32(obj, 0x00, nv_mclass(obj));
68 nv_wo32(obj, 0x04, 0x00000000);
69 nv_wo32(obj, 0x08, 0x00000000);
71 nv_mo32(obj, 0x08, 0x01000000, 0x01000000);
73 nv_wo32(obj, 0x0c, 0x00000000);
74 nv_wo32(obj, 0x10, 0x00000000);
78 static struct nouveau_ofuncs
80 .ctor = nv40_graph_object_ctor,
81 .dtor = _nouveau_gpuobj_dtor,
82 .init = _nouveau_gpuobj_init,
83 .fini = _nouveau_gpuobj_fini,
84 .rd32 = _nouveau_gpuobj_rd32,
85 .wr32 = _nouveau_gpuobj_wr32,
88 static struct nouveau_oclass
89 nv40_graph_sclass[] = {
90 { 0x0012, &nv40_graph_ofuncs, NULL }, /* beta1 */
91 { 0x0019, &nv40_graph_ofuncs, NULL }, /* clip */
92 { 0x0030, &nv40_graph_ofuncs, NULL }, /* null */
93 { 0x0039, &nv40_graph_ofuncs, NULL }, /* m2mf */
94 { 0x0043, &nv40_graph_ofuncs, NULL }, /* rop */
95 { 0x0044, &nv40_graph_ofuncs, NULL }, /* patt */
96 { 0x004a, &nv40_graph_ofuncs, NULL }, /* gdi */
97 { 0x0062, &nv40_graph_ofuncs, NULL }, /* surf2d */
98 { 0x0072, &nv40_graph_ofuncs, NULL }, /* beta4 */
99 { 0x0089, &nv40_graph_ofuncs, NULL }, /* sifm */
100 { 0x008a, &nv40_graph_ofuncs, NULL }, /* ifc */
101 { 0x009f, &nv40_graph_ofuncs, NULL }, /* imageblit */
102 { 0x3062, &nv40_graph_ofuncs, NULL }, /* surf2d (nv40) */
103 { 0x3089, &nv40_graph_ofuncs, NULL }, /* sifm (nv40) */
104 { 0x309e, &nv40_graph_ofuncs, NULL }, /* swzsurf (nv40) */
105 { 0x4097, &nv40_graph_ofuncs, NULL }, /* curie */
109 static struct nouveau_oclass
110 nv44_graph_sclass[] = {
111 { 0x0012, &nv40_graph_ofuncs, NULL }, /* beta1 */
112 { 0x0019, &nv40_graph_ofuncs, NULL }, /* clip */
113 { 0x0030, &nv40_graph_ofuncs, NULL }, /* null */
114 { 0x0039, &nv40_graph_ofuncs, NULL }, /* m2mf */
115 { 0x0043, &nv40_graph_ofuncs, NULL }, /* rop */
116 { 0x0044, &nv40_graph_ofuncs, NULL }, /* patt */
117 { 0x004a, &nv40_graph_ofuncs, NULL }, /* gdi */
118 { 0x0062, &nv40_graph_ofuncs, NULL }, /* surf2d */
119 { 0x0072, &nv40_graph_ofuncs, NULL }, /* beta4 */
120 { 0x0089, &nv40_graph_ofuncs, NULL }, /* sifm */
121 { 0x008a, &nv40_graph_ofuncs, NULL }, /* ifc */
122 { 0x009f, &nv40_graph_ofuncs, NULL }, /* imageblit */
123 { 0x3062, &nv40_graph_ofuncs, NULL }, /* surf2d (nv40) */
124 { 0x3089, &nv40_graph_ofuncs, NULL }, /* sifm (nv40) */
125 { 0x309e, &nv40_graph_ofuncs, NULL }, /* swzsurf (nv40) */
126 { 0x4497, &nv40_graph_ofuncs, NULL }, /* curie */
130 /*******************************************************************************
132 ******************************************************************************/
135 nv40_graph_context_ctor(struct nouveau_object *parent,
136 struct nouveau_object *engine,
137 struct nouveau_oclass *oclass, void *data, u32 size,
138 struct nouveau_object **pobject)
140 struct nv40_graph_priv *priv = (void *)engine;
141 struct nv40_graph_chan *chan;
144 ret = nouveau_graph_context_create(parent, engine, oclass, NULL,
146 NVOBJ_FLAG_ZERO_ALLOC, &chan);
147 *pobject = nv_object(chan);
151 nv40_grctx_fill(nv_device(priv), nv_gpuobj(chan));
152 nv_wo32(chan, 0x00000, nv_gpuobj(chan)->addr >> 4);
157 nv40_graph_context_fini(struct nouveau_object *object, bool suspend)
159 struct nv40_graph_priv *priv = (void *)object->engine;
160 struct nv40_graph_chan *chan = (void *)object;
161 u32 inst = 0x01000000 | nv_gpuobj(chan)->addr >> 4;
164 nv_mask(priv, 0x400720, 0x00000001, 0x00000000);
166 if (nv_rd32(priv, 0x40032c) == inst) {
168 nv_wr32(priv, 0x400720, 0x00000000);
169 nv_wr32(priv, 0x400784, inst);
170 nv_mask(priv, 0x400310, 0x00000020, 0x00000020);
171 nv_mask(priv, 0x400304, 0x00000001, 0x00000001);
172 if (!nv_wait(priv, 0x400300, 0x00000001, 0x00000000)) {
173 u32 insn = nv_rd32(priv, 0x400308);
174 nv_warn(priv, "ctxprog timeout 0x%08x\n", insn);
179 nv_mask(priv, 0x40032c, 0x01000000, 0x00000000);
182 if (nv_rd32(priv, 0x400330) == inst)
183 nv_mask(priv, 0x400330, 0x01000000, 0x00000000);
185 nv_mask(priv, 0x400720, 0x00000001, 0x00000001);
189 static struct nouveau_oclass
190 nv40_graph_cclass = {
191 .handle = NV_ENGCTX(GR, 0x40),
192 .ofuncs = &(struct nouveau_ofuncs) {
193 .ctor = nv40_graph_context_ctor,
194 .dtor = _nouveau_graph_context_dtor,
195 .init = _nouveau_graph_context_init,
196 .fini = nv40_graph_context_fini,
197 .rd32 = _nouveau_graph_context_rd32,
198 .wr32 = _nouveau_graph_context_wr32,
202 /*******************************************************************************
203 * PGRAPH engine/subdev functions
204 ******************************************************************************/
207 nv40_graph_tile_prog(struct nouveau_engine *engine, int i)
209 struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i];
210 struct nouveau_fifo *pfifo = nouveau_fifo(engine);
211 struct nv40_graph_priv *priv = (void *)engine;
214 pfifo->pause(pfifo, &flags);
215 nv04_graph_idle(priv);
217 switch (nv_device(priv)->chipset) {
219 case 0x41: /* guess */
222 case 0x45: /* guess */
224 nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch);
225 nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit);
226 nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr);
227 nv_wr32(priv, NV40_PGRAPH_TSIZE1(i), tile->pitch);
228 nv_wr32(priv, NV40_PGRAPH_TLIMIT1(i), tile->limit);
229 nv_wr32(priv, NV40_PGRAPH_TILE1(i), tile->addr);
233 nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch);
234 nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit);
235 nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr);
244 nv_wr32(priv, NV47_PGRAPH_TSIZE(i), tile->pitch);
245 nv_wr32(priv, NV47_PGRAPH_TLIMIT(i), tile->limit);
246 nv_wr32(priv, NV47_PGRAPH_TILE(i), tile->addr);
247 nv_wr32(priv, NV40_PGRAPH_TSIZE1(i), tile->pitch);
248 nv_wr32(priv, NV40_PGRAPH_TLIMIT1(i), tile->limit);
249 nv_wr32(priv, NV40_PGRAPH_TILE1(i), tile->addr);
253 pfifo->start(pfifo, &flags);
257 nv40_graph_intr(struct nouveau_subdev *subdev)
259 struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
260 struct nouveau_engine *engine = nv_engine(subdev);
261 struct nouveau_object *engctx;
262 struct nouveau_handle *handle = NULL;
263 struct nv40_graph_priv *priv = (void *)subdev;
264 u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);
265 u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE);
266 u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS);
267 u32 inst = nv_rd32(priv, 0x40032c) & 0x000fffff;
268 u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR);
269 u32 subc = (addr & 0x00070000) >> 16;
270 u32 mthd = (addr & 0x00001ffc);
271 u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA);
272 u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xffff;
276 engctx = nouveau_engctx_get(engine, inst);
277 chid = pfifo->chid(pfifo, engctx);
279 if (stat & NV_PGRAPH_INTR_ERROR) {
280 if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
281 handle = nouveau_handle_get_class(engctx, class);
282 if (handle && !nv_call(handle->object, mthd, data))
283 show &= ~NV_PGRAPH_INTR_ERROR;
284 nouveau_handle_put(handle);
287 if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) {
288 nv_mask(priv, 0x402000, 0, 0);
292 nv_wr32(priv, NV03_PGRAPH_INTR, stat);
293 nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001);
297 nouveau_bitfield_print(nv10_graph_intr_name, show);
299 nouveau_bitfield_print(nv04_graph_nsource, nsource);
301 nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
303 nv_error(priv, "ch %d [0x%08x] subc %d class 0x%04x "
304 "mthd 0x%04x data 0x%08x\n",
305 chid, inst << 4, subc, class, mthd, data);
308 nouveau_engctx_put(engctx);
312 nv40_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
313 struct nouveau_oclass *oclass, void *data, u32 size,
314 struct nouveau_object **pobject)
316 struct nv40_graph_priv *priv;
319 ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
320 *pobject = nv_object(priv);
324 nv_subdev(priv)->unit = 0x00001000;
325 nv_subdev(priv)->intr = nv40_graph_intr;
326 nv_engine(priv)->cclass = &nv40_graph_cclass;
327 if (nv44_graph_class(priv))
328 nv_engine(priv)->sclass = nv44_graph_sclass;
330 nv_engine(priv)->sclass = nv40_graph_sclass;
331 nv_engine(priv)->tile_prog = nv40_graph_tile_prog;
336 nv40_graph_init(struct nouveau_object *object)
338 struct nouveau_engine *engine = nv_engine(object);
339 struct nouveau_fb *pfb = nouveau_fb(object);
340 struct nv40_graph_priv *priv = (void *)engine;
344 ret = nouveau_graph_init(&priv->base);
348 /* generate and upload context program */
349 ret = nv40_grctx_init(nv_device(priv), &priv->size);
353 /* No context present currently */
354 nv_wr32(priv, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
356 nv_wr32(priv, NV03_PGRAPH_INTR , 0xFFFFFFFF);
357 nv_wr32(priv, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);
359 nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
360 nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000);
361 nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x401287c0);
362 nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xe0de8055);
363 nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00008000);
364 nv_wr32(priv, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f);
366 nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
367 nv_wr32(priv, NV10_PGRAPH_STATE , 0xFFFFFFFF);
369 j = nv_rd32(priv, 0x1540) & 0xff;
371 for (i = 0; !(j & 1); j >>= 1, i++)
373 nv_wr32(priv, 0x405000, i);
376 if (nv_device(priv)->chipset == 0x40) {
377 nv_wr32(priv, 0x4009b0, 0x83280fff);
378 nv_wr32(priv, 0x4009b4, 0x000000a0);
380 nv_wr32(priv, 0x400820, 0x83280eff);
381 nv_wr32(priv, 0x400824, 0x000000a0);
384 switch (nv_device(priv)->chipset) {
387 nv_wr32(priv, 0x4009b8, 0x0078e366);
388 nv_wr32(priv, 0x4009bc, 0x0000014c);
391 case 0x42: /* pciid also 0x00Cx */
392 /* case 0x0120: XXX (pciid) */
393 nv_wr32(priv, 0x400828, 0x007596ff);
394 nv_wr32(priv, 0x40082c, 0x00000108);
397 nv_wr32(priv, 0x400828, 0x0072cb77);
398 nv_wr32(priv, 0x40082c, 0x00000108);
403 case 0x4c: /* G7x-based C51 */
405 nv_wr32(priv, 0x400860, 0);
406 nv_wr32(priv, 0x400864, 0);
411 nv_wr32(priv, 0x400828, 0x07830610);
412 nv_wr32(priv, 0x40082c, 0x0000016A);
418 nv_wr32(priv, 0x400b38, 0x2ffff800);
419 nv_wr32(priv, 0x400b3c, 0x00006000);
421 /* Tiling related stuff. */
422 switch (nv_device(priv)->chipset) {
425 nv_wr32(priv, 0x400bc4, 0x1003d888);
426 nv_wr32(priv, 0x400bbc, 0xb7a7b500);
429 nv_wr32(priv, 0x400bc4, 0x0000e024);
430 nv_wr32(priv, 0x400bbc, 0xb7a7b520);
435 nv_wr32(priv, 0x400bc4, 0x1003d888);
436 nv_wr32(priv, 0x400bbc, 0xb7a7b540);
442 /* Turn all the tiling regions off. */
443 for (i = 0; i < pfb->tile.regions; i++)
444 engine->tile_prog(engine, i);
446 /* begin RAM config */
447 vramsz = pci_resource_len(nv_device(priv)->pdev, 0) - 1;
448 switch (nv_device(priv)->chipset) {
450 nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200));
451 nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204));
452 nv_wr32(priv, 0x4069A4, nv_rd32(priv, 0x100200));
453 nv_wr32(priv, 0x4069A8, nv_rd32(priv, 0x100204));
454 nv_wr32(priv, 0x400820, 0);
455 nv_wr32(priv, 0x400824, 0);
456 nv_wr32(priv, 0x400864, vramsz);
457 nv_wr32(priv, 0x400868, vramsz);
460 switch (nv_device(priv)->chipset) {
468 nv_wr32(priv, 0x4009F0, nv_rd32(priv, 0x100200));
469 nv_wr32(priv, 0x4009F4, nv_rd32(priv, 0x100204));
472 nv_wr32(priv, 0x400DF0, nv_rd32(priv, 0x100200));
473 nv_wr32(priv, 0x400DF4, nv_rd32(priv, 0x100204));
476 nv_wr32(priv, 0x4069F0, nv_rd32(priv, 0x100200));
477 nv_wr32(priv, 0x4069F4, nv_rd32(priv, 0x100204));
478 nv_wr32(priv, 0x400840, 0);
479 nv_wr32(priv, 0x400844, 0);
480 nv_wr32(priv, 0x4008A0, vramsz);
481 nv_wr32(priv, 0x4008A4, vramsz);
488 struct nouveau_oclass
489 nv40_graph_oclass = {
490 .handle = NV_ENGINE(GR, 0x40),
491 .ofuncs = &(struct nouveau_ofuncs) {
492 .ctor = nv40_graph_ctor,
493 .dtor = _nouveau_graph_dtor,
494 .init = nv40_graph_init,
495 .fini = _nouveau_graph_fini,