drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <core/gpuobj.h>
  26 #include <core/class.h>
  27
  28 #include <subdev/fb.h>
  29 #include <engine/dmaobj.h>
  30
  31 struct nv50_dmaeng_priv {
  32         struct nouveau_dmaeng base;
  33 };
  34
  35 static int
  36 nv50_dmaobj_bind(struct nouveau_dmaeng *dmaeng,
  37                  struct nouveau_object *parent,
  38                  struct nouveau_dmaobj *dmaobj,
  39                  struct nouveau_gpuobj **pgpuobj)
  40 {
  41         u32 flags0 = nv_mclass(dmaobj);
  42         u32 flags5 = 0x00000000;
  43         int ret;
  44
  45         if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
  46                 switch (nv_mclass(parent->parent)) {
  47                 case NV50_CHANNEL_DMA_CLASS:
  48                 case NV84_CHANNEL_DMA_CLASS:
  49                 case NV50_CHANNEL_IND_CLASS:
  50                 case NV84_CHANNEL_IND_CLASS:
  51                 case NV50_DISP_MAST_CLASS:
  52                 case NV84_DISP_MAST_CLASS:
  53                 case NV94_DISP_MAST_CLASS:
  54                 case NVA0_DISP_MAST_CLASS:
  55                 case NVA3_DISP_MAST_CLASS:
  56                 case NV50_DISP_SYNC_CLASS:
  57                 case NV84_DISP_SYNC_CLASS:
  58                 case NV94_DISP_SYNC_CLASS:
  59                 case NVA0_DISP_SYNC_CLASS:
  60                 case NVA3_DISP_SYNC_CLASS:
  61                 case NV50_DISP_OVLY_CLASS:
  62                 case NV84_DISP_OVLY_CLASS:
  63                 case NV94_DISP_OVLY_CLASS:
  64                 case NVA0_DISP_OVLY_CLASS:
  65                 case NVA3_DISP_OVLY_CLASS:
  66                         break;
  67                 default:
  68                         return -EINVAL;
  69                 }
  70         }
  71
  72         if (!(dmaobj->conf0 & NV50_DMA_CONF0_ENABLE)) {
  73                 if (dmaobj->target == NV_MEM_TARGET_VM) {
  74                         dmaobj->conf0  = NV50_DMA_CONF0_PRIV_VM;
  75                         dmaobj->conf0 |= NV50_DMA_CONF0_PART_VM;
  76                         dmaobj->conf0 |= NV50_DMA_CONF0_COMP_VM;
  77                         dmaobj->conf0 |= NV50_DMA_CONF0_TYPE_VM;
  78                 } else {
  79                         dmaobj->conf0  = NV50_DMA_CONF0_PRIV_US;
  80                         dmaobj->conf0 |= NV50_DMA_CONF0_PART_256;
  81                         dmaobj->conf0 |= NV50_DMA_CONF0_COMP_NONE;
  82                         dmaobj->conf0 |= NV50_DMA_CONF0_TYPE_LINEAR;
  83                 }
  84         }
  85
  86         flags0 |= (dmaobj->conf0 & NV50_DMA_CONF0_COMP) << 22;
  87         flags0 |= (dmaobj->conf0 & NV50_DMA_CONF0_TYPE) << 22;
  88         flags0 |= (dmaobj->conf0 & NV50_DMA_CONF0_PRIV);
  89         flags5 |= (dmaobj->conf0 & NV50_DMA_CONF0_PART);
  90
  91         switch (dmaobj->target) {
  92         case NV_MEM_TARGET_VM:
  93                 flags0 |= 0x00000000;
  94                 break;
  95         case NV_MEM_TARGET_VRAM:
  96                 flags0 |= 0x00010000;
  97                 break;
  98         case NV_MEM_TARGET_PCI:
  99                 flags0 |= 0x00020000;
 100                 break;
 101         case NV_MEM_TARGET_PCI_NOSNOOP:
 102                 flags0 |= 0x00030000;
 103                 break;
 104         default:
 105                 return -EINVAL;
 106         }
 107
 108         switch (dmaobj->access) {
 109         case NV_MEM_ACCESS_VM:
 110                 break;
 111         case NV_MEM_ACCESS_RO:
 112                 flags0 |= 0x00040000;
 113                 break;
 114         case NV_MEM_ACCESS_WO:
 115         case NV_MEM_ACCESS_RW:
 116                 flags0 |= 0x00080000;
 117                 break;
 118         }
 119
 120         ret = nouveau_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj);
 121         if (ret == 0) {
 122                 nv_wo32(*pgpuobj, 0x00, flags0);
 123                 nv_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->limit));
 124                 nv_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->start));
 125                 nv_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->limit) << 24 |
 126                                         upper_32_bits(dmaobj->start));
 127                 nv_wo32(*pgpuobj, 0x10, 0x00000000);
 128                 nv_wo32(*pgpuobj, 0x14, flags5);
 129         }
 130
 131         return ret;
 132 }
 133
 134 static int
 135 nv50_dmaeng_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 136                  struct nouveau_oclass *oclass, void *data, u32 size,
 137                  struct nouveau_object **pobject)
 138 {
 139         struct nv50_dmaeng_priv *priv;
 140         int ret;
 141
 142         ret = nouveau_dmaeng_create(parent, engine, oclass, &priv);
 143         *pobject = nv_object(priv);
 144         if (ret)
 145                 return ret;
 146
 147         nv_engine(priv)->sclass = nouveau_dmaobj_sclass;
 148         priv->base.bind = nv50_dmaobj_bind;
 149         return 0;
 150 }
 151
 152 struct nouveau_oclass
 153 nv50_dmaeng_oclass = {
 154         .handle = NV_ENGINE(DMAOBJ, 0x50),
 155         .ofuncs = &(struct nouveau_ofuncs) {
 156                 .ctor = nv50_dmaeng_ctor,
 157                 .dtor = _nouveau_dmaeng_dtor,
 158                 .init = _nouveau_dmaeng_init,
 159                 .fini = _nouveau_dmaeng_fini,
 160         },
 161 };