2 * Copyright 2012 Red Hat Inc.
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26 #include <core/class.h>
31 nv84_hdmi_ctrl(struct nv50_disp_priv *priv, int head, int or, u32 data)
33 const u32 hoff = (head * 0x800);
35 if (!(data & NV84_DISP_SOR_HDMI_PWR_STATE_ON)) {
36 nv_mask(priv, 0x6165a4 + hoff, 0x40000000, 0x00000000);
37 nv_mask(priv, 0x616520 + hoff, 0x00000001, 0x00000000);
38 nv_mask(priv, 0x616500 + hoff, 0x00000001, 0x00000000);
43 nv_mask(priv, 0x616520 + hoff, 0x00000001, 0x00000000);
44 nv_wr32(priv, 0x616528 + hoff, 0x000d0282);
45 nv_wr32(priv, 0x61652c + hoff, 0x0000006f);
46 nv_wr32(priv, 0x616530 + hoff, 0x00000000);
47 nv_wr32(priv, 0x616534 + hoff, 0x00000000);
48 nv_wr32(priv, 0x616538 + hoff, 0x00000000);
49 nv_mask(priv, 0x616520 + hoff, 0x00000001, 0x00000001);
52 nv_mask(priv, 0x616500 + hoff, 0x00000001, 0x00000000);
53 nv_wr32(priv, 0x616508 + hoff, 0x000a0184);
54 nv_wr32(priv, 0x61650c + hoff, 0x00000071);
55 nv_wr32(priv, 0x616510 + hoff, 0x00000000);
56 nv_mask(priv, 0x616500 + hoff, 0x00000001, 0x00000001);
58 nv_mask(priv, 0x6165d0 + hoff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */
59 nv_mask(priv, 0x616568 + hoff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */
60 nv_mask(priv, 0x616578 + hoff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */
63 nv_mask(priv, 0x61733c, 0x00100000, 0x00100000); /* RESETF */
64 nv_mask(priv, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */
65 nv_mask(priv, 0x61733c, 0x00100000, 0x00000000); /* !RESETF */
68 nv_mask(priv, 0x6165a4 + hoff, 0x5f1f007f, data | 0x1f000000 /* ??? */);