drivers/gpu/drm/imx/imx-hdmi.c

   1 /*
   2  * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * SH-Mobile High-Definition Multimedia Interface (HDMI) driver
  10  * for SLISHDMI13T and SLIPHDMIT IP cores
  11  *
  12  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
  13  */
  14
  15 #include <linux/component.h>
  16 #include <linux/irq.h>
  17 #include <linux/delay.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/hdmi.h>
  21 #include <linux/regmap.h>
  22 #include <linux/mfd/syscon.h>
  23 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  24 #include <linux/of_device.h>
  25
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <drm/drm_edid.h>
  29 #include <drm/drm_encoder_slave.h>
  30 #include <video/imx-ipu-v3.h>
  31
  32 #include "imx-hdmi.h"
  33 #include "imx-drm.h"
  34
  35 #define HDMI_EDID_LEN           512
  36
  37 #define RGB                     0
  38 #define YCBCR444                1
  39 #define YCBCR422_16BITS         2
  40 #define YCBCR422_8BITS          3
  41 #define XVYCC444                4
  42
  43 enum hdmi_datamap {
  44         RGB444_8B = 0x01,
  45         RGB444_10B = 0x03,
  46         RGB444_12B = 0x05,
  47         RGB444_16B = 0x07,
  48         YCbCr444_8B = 0x09,
  49         YCbCr444_10B = 0x0B,
  50         YCbCr444_12B = 0x0D,
  51         YCbCr444_16B = 0x0F,
  52         YCbCr422_8B = 0x16,
  53         YCbCr422_10B = 0x14,
  54         YCbCr422_12B = 0x12,
  55 };
  56
  57 enum imx_hdmi_devtype {
  58         IMX6Q_HDMI,
  59         IMX6DL_HDMI,
  60 };
  61
  62 static const u16 csc_coeff_default[3][4] = {
  63         { 0x2000, 0x0000, 0x0000, 0x0000 },
  64         { 0x0000, 0x2000, 0x0000, 0x0000 },
  65         { 0x0000, 0x0000, 0x2000, 0x0000 }
  66 };
  67
  68 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
  69         { 0x2000, 0x6926, 0x74fd, 0x010e },
  70         { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
  71         { 0x2000, 0x0000, 0x38b4, 0x7e3b }
  72 };
  73
  74 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
  75         { 0x2000, 0x7106, 0x7a02, 0x00a7 },
  76         { 0x2000, 0x3264, 0x0000, 0x7e6d },
  77         { 0x2000, 0x0000, 0x3b61, 0x7e25 }
  78 };
  79
  80 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
  81         { 0x2591, 0x1322, 0x074b, 0x0000 },
  82         { 0x6535, 0x2000, 0x7acc, 0x0200 },
  83         { 0x6acd, 0x7534, 0x2000, 0x0200 }
  84 };
  85
  86 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
  87         { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
  88         { 0x62f0, 0x2000, 0x7d11, 0x0200 },
  89         { 0x6756, 0x78ab, 0x2000, 0x0200 }
  90 };
  91
  92 struct hdmi_vmode {
  93         bool mdvi;
  94         bool mhsyncpolarity;
  95         bool mvsyncpolarity;
  96         bool minterlaced;
  97         bool mdataenablepolarity;
  98
  99         unsigned int mpixelclock;
 100         unsigned int mpixelrepetitioninput;
 101         unsigned int mpixelrepetitionoutput;
 102 };
 103
 104 struct hdmi_data_info {
 105         unsigned int enc_in_format;
 106         unsigned int enc_out_format;
 107         unsigned int enc_color_depth;
 108         unsigned int colorimetry;
 109         unsigned int pix_repet_factor;
 110         unsigned int hdcp_enable;
 111         struct hdmi_vmode video_mode;
 112 };
 113
 114 struct imx_hdmi {
 115         struct drm_connector connector;
 116         struct drm_encoder encoder;
 117
 118         enum imx_hdmi_devtype dev_type;
 119         struct device *dev;
 120         struct clk *isfr_clk;
 121         struct clk *iahb_clk;
 122
 123         struct hdmi_data_info hdmi_data;
 124         int vic;
 125
 126         u8 edid[HDMI_EDID_LEN];
 127         bool cable_plugin;
 128
 129         bool phy_enabled;
 130         struct drm_display_mode previous_mode;
 131
 132         struct regmap *regmap;
 133         struct i2c_adapter *ddc;
 134         void __iomem *regs;
 135
 136         unsigned int sample_rate;
 137         int ratio;
 138 };
 139
 140 static void imx_hdmi_set_ipu_di_mux(struct imx_hdmi *hdmi, int ipu_di)
 141 {
 142         regmap_update_bits(hdmi->regmap, IOMUXC_GPR3,
 143                            IMX6Q_GPR3_HDMI_MUX_CTL_MASK,
 144                            ipu_di << IMX6Q_GPR3_HDMI_MUX_CTL_SHIFT);
 145 }
 146
 147 static inline void hdmi_writeb(struct imx_hdmi *hdmi, u8 val, int offset)
 148 {
 149         writeb(val, hdmi->regs + offset);
 150 }
 151
 152 static inline u8 hdmi_readb(struct imx_hdmi *hdmi, int offset)
 153 {
 154         return readb(hdmi->regs + offset);
 155 }
 156
 157 static void hdmi_modb(struct imx_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
 158 {
 159         u8 val = hdmi_readb(hdmi, reg) & ~mask;
 160
 161         val |= data & mask;
 162         hdmi_writeb(hdmi, val, reg);
 163 }
 164
 165 static void hdmi_mask_writeb(struct imx_hdmi *hdmi, u8 data, unsigned int reg,
 166                              u8 shift, u8 mask)
 167 {
 168         hdmi_modb(hdmi, data << shift, mask, reg);
 169 }
 170
 171 static void hdmi_set_clock_regenerator_n(struct imx_hdmi *hdmi,
 172                                          unsigned int value)
 173 {
 174         hdmi_writeb(hdmi, value & 0xff, HDMI_AUD_N1);
 175         hdmi_writeb(hdmi, (value >> 8) & 0xff, HDMI_AUD_N2);
 176         hdmi_writeb(hdmi, (value >> 16) & 0x0f, HDMI_AUD_N3);
 177
 178         /* nshift factor = 0 */
 179         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
 180 }
 181
 182 static void hdmi_regenerate_cts(struct imx_hdmi *hdmi, unsigned int cts)
 183 {
 184         /* Must be set/cleared first */
 185         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 186
 187         hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
 188         hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
 189         hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
 190                     HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 191 }
 192
 193 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk,
 194                                    unsigned int ratio)
 195 {
 196         unsigned int n = (128 * freq) / 1000;
 197
 198         switch (freq) {
 199         case 32000:
 200                 if (pixel_clk == 25170000)
 201                         n = (ratio == 150) ? 9152 : 4576;
 202                 else if (pixel_clk == 27020000)
 203                         n = (ratio == 150) ? 8192 : 4096;
 204                 else if (pixel_clk == 74170000 || pixel_clk == 148350000)
 205                         n = 11648;
 206                 else
 207                         n = 4096;
 208                 break;
 209
 210         case 44100:
 211                 if (pixel_clk == 25170000)
 212                         n = 7007;
 213                 else if (pixel_clk == 74170000)
 214                         n = 17836;
 215                 else if (pixel_clk == 148350000)
 216                         n = (ratio == 150) ? 17836 : 8918;
 217                 else
 218                         n = 6272;
 219                 break;
 220
 221         case 48000:
 222                 if (pixel_clk == 25170000)
 223                         n = (ratio == 150) ? 9152 : 6864;
 224                 else if (pixel_clk == 27020000)
 225                         n = (ratio == 150) ? 8192 : 6144;
 226                 else if (pixel_clk == 74170000)
 227                         n = 11648;
 228                 else if (pixel_clk == 148350000)
 229                         n = (ratio == 150) ? 11648 : 5824;
 230                 else
 231                         n = 6144;
 232                 break;
 233
 234         case 88200:
 235                 n = hdmi_compute_n(44100, pixel_clk, ratio) * 2;
 236                 break;
 237
 238         case 96000:
 239                 n = hdmi_compute_n(48000, pixel_clk, ratio) * 2;
 240                 break;
 241
 242         case 176400:
 243                 n = hdmi_compute_n(44100, pixel_clk, ratio) * 4;
 244                 break;
 245
 246         case 192000:
 247                 n = hdmi_compute_n(48000, pixel_clk, ratio) * 4;
 248                 break;
 249
 250         default:
 251                 break;
 252         }
 253
 254         return n;
 255 }
 256
 257 static unsigned int hdmi_compute_cts(unsigned int freq, unsigned long pixel_clk,
 258                                      unsigned int ratio)
 259 {
 260         unsigned int cts = 0;
 261
 262         pr_debug("%s: freq: %d pixel_clk: %ld ratio: %d\n", __func__, freq,
 263                  pixel_clk, ratio);
 264
 265         switch (freq) {
 266         case 32000:
 267                 if (pixel_clk == 297000000) {
 268                         cts = 222750;
 269                         break;
 270                 }
 271         case 48000:
 272         case 96000:
 273         case 192000:
 274                 switch (pixel_clk) {
 275                 case 25200000:
 276                 case 27000000:
 277                 case 54000000:
 278                 case 74250000:
 279                 case 148500000:
 280                         cts = pixel_clk / 1000;
 281                         break;
 282                 case 297000000:
 283                         cts = 247500;
 284                         break;
 285                 /*
 286                  * All other TMDS clocks are not supported by
 287                  * DWC_hdmi_tx. The TMDS clocks divided or
 288                  * multiplied by 1,001 coefficients are not
 289                  * supported.
 290                  */
 291                 default:
 292                         break;
 293                 }
 294                 break;
 295         case 44100:
 296         case 88200:
 297         case 176400:
 298                 switch (pixel_clk) {
 299                 case 25200000:
 300                         cts = 28000;
 301                         break;
 302                 case 27000000:
 303                         cts = 30000;
 304                         break;
 305                 case 54000000:
 306                         cts = 60000;
 307                         break;
 308                 case 74250000:
 309                         cts = 82500;
 310                         break;
 311                 case 148500000:
 312                         cts = 165000;
 313                         break;
 314                 case 297000000:
 315                         cts = 247500;
 316                         break;
 317                 default:
 318                         break;
 319                 }
 320                 break;
 321         default:
 322                 break;
 323         }
 324         if (ratio == 100)
 325                 return cts;
 326         return (cts * ratio) / 100;
 327 }
 328
 329 static void hdmi_set_clk_regenerator(struct imx_hdmi *hdmi,
 330                                      unsigned long pixel_clk)
 331 {
 332         unsigned int clk_n, clk_cts;
 333
 334         clk_n = hdmi_compute_n(hdmi->sample_rate, pixel_clk,
 335                                hdmi->ratio);
 336         clk_cts = hdmi_compute_cts(hdmi->sample_rate, pixel_clk,
 337                                    hdmi->ratio);
 338
 339         if (!clk_cts) {
 340                 dev_dbg(hdmi->dev, "%s: pixel clock not supported: %lu\n",
 341                         __func__, pixel_clk);
 342                 return;
 343         }
 344
 345         dev_dbg(hdmi->dev, "%s: samplerate=%d  ratio=%d  pixelclk=%lu  N=%d cts=%d\n",
 346                 __func__, hdmi->sample_rate, hdmi->ratio,
 347                 pixel_clk, clk_n, clk_cts);
 348
 349         hdmi_set_clock_regenerator_n(hdmi, clk_n);
 350         hdmi_regenerate_cts(hdmi, clk_cts);
 351 }
 352
 353 static void hdmi_init_clk_regenerator(struct imx_hdmi *hdmi)
 354 {
 355         hdmi_set_clk_regenerator(hdmi, 74250000);
 356 }
 357
 358 static void hdmi_clk_regenerator_update_pixel_clock(struct imx_hdmi *hdmi)
 359 {
 360         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock);
 361 }
 362
 363 /*
 364  * this submodule is responsible for the video data synchronization.
 365  * for example, for RGB 4:4:4 input, the data map is defined as
 366  *                      pin{47~40} <==> R[7:0]
 367  *                      pin{31~24} <==> G[7:0]
 368  *                      pin{15~8}  <==> B[7:0]
 369  */
 370 static void hdmi_video_sample(struct imx_hdmi *hdmi)
 371 {
 372         int color_format = 0;
 373         u8 val;
 374
 375         if (hdmi->hdmi_data.enc_in_format == RGB) {
 376                 if (hdmi->hdmi_data.enc_color_depth == 8)
 377                         color_format = 0x01;
 378                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 379                         color_format = 0x03;
 380                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 381                         color_format = 0x05;
 382                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 383                         color_format = 0x07;
 384                 else
 385                         return;
 386         } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
 387                 if (hdmi->hdmi_data.enc_color_depth == 8)
 388                         color_format = 0x09;
 389                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 390                         color_format = 0x0B;
 391                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 392                         color_format = 0x0D;
 393                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 394                         color_format = 0x0F;
 395                 else
 396                         return;
 397         } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
 398                 if (hdmi->hdmi_data.enc_color_depth == 8)
 399                         color_format = 0x16;
 400                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 401                         color_format = 0x14;
 402                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 403                         color_format = 0x12;
 404                 else
 405                         return;
 406         }
 407
 408         val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
 409                 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
 410                 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
 411         hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
 412
 413         /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
 414         val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
 415                 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
 416                 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
 417         hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
 418         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
 419         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
 420         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
 421         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
 422         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
 423         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
 424 }
 425
 426 static int is_color_space_conversion(struct imx_hdmi *hdmi)
 427 {
 428         return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format;
 429 }
 430
 431 static int is_color_space_decimation(struct imx_hdmi *hdmi)
 432 {
 433         if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS)
 434                 return 0;
 435         if (hdmi->hdmi_data.enc_in_format == RGB ||
 436             hdmi->hdmi_data.enc_in_format == YCBCR444)
 437                 return 1;
 438         return 0;
 439 }
 440
 441 static int is_color_space_interpolation(struct imx_hdmi *hdmi)
 442 {
 443         if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS)
 444                 return 0;
 445         if (hdmi->hdmi_data.enc_out_format == RGB ||
 446             hdmi->hdmi_data.enc_out_format == YCBCR444)
 447                 return 1;
 448         return 0;
 449 }
 450
 451 static void imx_hdmi_update_csc_coeffs(struct imx_hdmi *hdmi)
 452 {
 453         const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
 454         unsigned i;
 455         u32 csc_scale = 1;
 456
 457         if (is_color_space_conversion(hdmi)) {
 458                 if (hdmi->hdmi_data.enc_out_format == RGB) {
 459                         if (hdmi->hdmi_data.colorimetry ==
 460                                         HDMI_COLORIMETRY_ITU_601)
 461                                 csc_coeff = &csc_coeff_rgb_out_eitu601;
 462                         else
 463                                 csc_coeff = &csc_coeff_rgb_out_eitu709;
 464                 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
 465                         if (hdmi->hdmi_data.colorimetry ==
 466                                         HDMI_COLORIMETRY_ITU_601)
 467                                 csc_coeff = &csc_coeff_rgb_in_eitu601;
 468                         else
 469                                 csc_coeff = &csc_coeff_rgb_in_eitu709;
 470                         csc_scale = 0;
 471                 }
 472         }
 473
 474         /* The CSC registers are sequential, alternating MSB then LSB */
 475         for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
 476                 u16 coeff_a = (*csc_coeff)[0][i];
 477                 u16 coeff_b = (*csc_coeff)[1][i];
 478                 u16 coeff_c = (*csc_coeff)[2][i];
 479
 480                 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
 481                 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
 482                 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
 483                 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
 484                 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
 485                 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
 486         }
 487
 488         hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
 489                   HDMI_CSC_SCALE);
 490 }
 491
 492 static void hdmi_video_csc(struct imx_hdmi *hdmi)
 493 {
 494         int color_depth = 0;
 495         int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
 496         int decimation = 0;
 497
 498         /* YCC422 interpolation to 444 mode */
 499         if (is_color_space_interpolation(hdmi))
 500                 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
 501         else if (is_color_space_decimation(hdmi))
 502                 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
 503
 504         if (hdmi->hdmi_data.enc_color_depth == 8)
 505                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
 506         else if (hdmi->hdmi_data.enc_color_depth == 10)
 507                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
 508         else if (hdmi->hdmi_data.enc_color_depth == 12)
 509                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
 510         else if (hdmi->hdmi_data.enc_color_depth == 16)
 511                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
 512         else
 513                 return;
 514
 515         /* Configure the CSC registers */
 516         hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
 517         hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
 518                   HDMI_CSC_SCALE);
 519
 520         imx_hdmi_update_csc_coeffs(hdmi);
 521 }
 522
 523 /*
 524  * HDMI video packetizer is used to packetize the data.
 525  * for example, if input is YCC422 mode or repeater is used,
 526  * data should be repacked this module can be bypassed.
 527  */
 528 static void hdmi_video_packetize(struct imx_hdmi *hdmi)
 529 {
 530         unsigned int color_depth = 0;
 531         unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
 532         unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
 533         struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
 534         u8 val, vp_conf;
 535
 536         if (hdmi_data->enc_out_format == RGB ||
 537             hdmi_data->enc_out_format == YCBCR444) {
 538                 if (!hdmi_data->enc_color_depth) {
 539                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 540                 } else if (hdmi_data->enc_color_depth == 8) {
 541                         color_depth = 4;
 542                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 543                 } else if (hdmi_data->enc_color_depth == 10) {
 544                         color_depth = 5;
 545                 } else if (hdmi_data->enc_color_depth == 12) {
 546                         color_depth = 6;
 547                 } else if (hdmi_data->enc_color_depth == 16) {
 548                         color_depth = 7;
 549                 } else {
 550                         return;
 551                 }
 552         } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
 553                 if (!hdmi_data->enc_color_depth ||
 554                     hdmi_data->enc_color_depth == 8)
 555                         remap_size = HDMI_VP_REMAP_YCC422_16bit;
 556                 else if (hdmi_data->enc_color_depth == 10)
 557                         remap_size = HDMI_VP_REMAP_YCC422_20bit;
 558                 else if (hdmi_data->enc_color_depth == 12)
 559                         remap_size = HDMI_VP_REMAP_YCC422_24bit;
 560                 else
 561                         return;
 562                 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
 563         } else {
 564                 return;
 565         }
 566
 567         /* set the packetizer registers */
 568         val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
 569                 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
 570                 ((hdmi_data->pix_repet_factor <<
 571                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
 572                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
 573         hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
 574
 575         hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
 576                   HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
 577
 578         /* Data from pixel repeater block */
 579         if (hdmi_data->pix_repet_factor > 1) {
 580                 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
 581                           HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
 582         } else { /* data from packetizer block */
 583                 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
 584                           HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
 585         }
 586
 587         hdmi_modb(hdmi, vp_conf,
 588                   HDMI_VP_CONF_PR_EN_MASK |
 589                   HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
 590
 591         hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
 592                   HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
 593
 594         hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
 595
 596         if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
 597                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 598                           HDMI_VP_CONF_PP_EN_ENABLE |
 599                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 600         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
 601                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 602                           HDMI_VP_CONF_PP_EN_DISABLE |
 603                           HDMI_VP_CONF_YCC422_EN_ENABLE;
 604         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
 605                 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
 606                           HDMI_VP_CONF_PP_EN_DISABLE |
 607                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 608         } else {
 609                 return;
 610         }
 611
 612         hdmi_modb(hdmi, vp_conf,
 613                   HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
 614                   HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
 615
 616         hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
 617                         HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
 618                   HDMI_VP_STUFF_PP_STUFFING_MASK |
 619                   HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
 620
 621         hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
 622                   HDMI_VP_CONF);
 623 }
 624
 625 static inline void hdmi_phy_test_clear(struct imx_hdmi *hdmi,
 626                                        unsigned char bit)
 627 {
 628         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
 629                   HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
 630 }
 631
 632 static inline void hdmi_phy_test_enable(struct imx_hdmi *hdmi,
 633                                         unsigned char bit)
 634 {
 635         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
 636                   HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
 637 }
 638
 639 static inline void hdmi_phy_test_clock(struct imx_hdmi *hdmi,
 640                                        unsigned char bit)
 641 {
 642         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
 643                   HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
 644 }
 645
 646 static inline void hdmi_phy_test_din(struct imx_hdmi *hdmi,
 647                                      unsigned char bit)
 648 {
 649         hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
 650 }
 651
 652 static inline void hdmi_phy_test_dout(struct imx_hdmi *hdmi,
 653                                       unsigned char bit)
 654 {
 655         hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
 656 }
 657
 658 static bool hdmi_phy_wait_i2c_done(struct imx_hdmi *hdmi, int msec)
 659 {
 660         while ((hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
 661                 if (msec-- == 0)
 662                         return false;
 663                 udelay(1000);
 664         }
 665         return true;
 666 }
 667
 668 static void __hdmi_phy_i2c_write(struct imx_hdmi *hdmi, unsigned short data,
 669                                  unsigned char addr)
 670 {
 671         hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
 672         hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
 673         hdmi_writeb(hdmi, (unsigned char)(data >> 8),
 674                     HDMI_PHY_I2CM_DATAO_1_ADDR);
 675         hdmi_writeb(hdmi, (unsigned char)(data >> 0),
 676                     HDMI_PHY_I2CM_DATAO_0_ADDR);
 677         hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
 678                     HDMI_PHY_I2CM_OPERATION_ADDR);
 679         hdmi_phy_wait_i2c_done(hdmi, 1000);
 680 }
 681
 682 static int hdmi_phy_i2c_write(struct imx_hdmi *hdmi, unsigned short data,
 683                               unsigned char addr)
 684 {
 685         __hdmi_phy_i2c_write(hdmi, data, addr);
 686         return 0;
 687 }
 688
 689 static void imx_hdmi_phy_enable_power(struct imx_hdmi *hdmi, u8 enable)
 690 {
 691         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 692                          HDMI_PHY_CONF0_PDZ_OFFSET,
 693                          HDMI_PHY_CONF0_PDZ_MASK);
 694 }
 695
 696 static void imx_hdmi_phy_enable_tmds(struct imx_hdmi *hdmi, u8 enable)
 697 {
 698         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 699                          HDMI_PHY_CONF0_ENTMDS_OFFSET,
 700                          HDMI_PHY_CONF0_ENTMDS_MASK);
 701 }
 702
 703 static void imx_hdmi_phy_gen2_pddq(struct imx_hdmi *hdmi, u8 enable)
 704 {
 705         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 706                          HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
 707                          HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
 708 }
 709
 710 static void imx_hdmi_phy_gen2_txpwron(struct imx_hdmi *hdmi, u8 enable)
 711 {
 712         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 713                          HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
 714                          HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
 715 }
 716
 717 static void imx_hdmi_phy_sel_data_en_pol(struct imx_hdmi *hdmi, u8 enable)
 718 {
 719         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 720                          HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
 721                          HDMI_PHY_CONF0_SELDATAENPOL_MASK);
 722 }
 723
 724 static void imx_hdmi_phy_sel_interface_control(struct imx_hdmi *hdmi, u8 enable)
 725 {
 726         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 727                          HDMI_PHY_CONF0_SELDIPIF_OFFSET,
 728                          HDMI_PHY_CONF0_SELDIPIF_MASK);
 729 }
 730
 731 enum {
 732         RES_8,
 733         RES_10,
 734         RES_12,
 735         RES_MAX,
 736 };
 737
 738 struct mpll_config {
 739         unsigned long mpixelclock;
 740         struct {
 741                 u16 cpce;
 742                 u16 gmp;
 743         } res[RES_MAX];
 744 };
 745
 746 static const struct mpll_config mpll_config[] = {
 747         {
 748                 45250000, {
 749                         { 0x01e0, 0x0000 },
 750                         { 0x21e1, 0x0000 },
 751                         { 0x41e2, 0x0000 }
 752                 },
 753         }, {
 754                 92500000, {
 755                         { 0x0140, 0x0005 },
 756                         { 0x2141, 0x0005 },
 757                         { 0x4142, 0x0005 },
 758                 },
 759         }, {
 760                 148500000, {
 761                         { 0x00a0, 0x000a },
 762                         { 0x20a1, 0x000a },
 763                         { 0x40a2, 0x000a },
 764                 },
 765         }, {
 766                 ~0UL, {
 767                         { 0x00a0, 0x000a },
 768                         { 0x2001, 0x000f },
 769                         { 0x4002, 0x000f },
 770                 },
 771         }
 772 };
 773
 774 struct curr_ctrl {
 775         unsigned long mpixelclock;
 776         u16 curr[RES_MAX];
 777 };
 778
 779 static const struct curr_ctrl curr_ctrl[] = {
 780         /*      pixelclk     bpp8    bpp10   bpp12 */
 781         {
 782                  54000000, { 0x091c, 0x091c, 0x06dc },
 783         }, {
 784                  58400000, { 0x091c, 0x06dc, 0x06dc },
 785         }, {
 786                  72000000, { 0x06dc, 0x06dc, 0x091c },
 787         }, {
 788                  74250000, { 0x06dc, 0x0b5c, 0x091c },
 789         }, {
 790                 118800000, { 0x091c, 0x091c, 0x06dc },
 791         }, {
 792                 216000000, { 0x06dc, 0x0b5c, 0x091c },
 793         }
 794 };
 795
 796 static int hdmi_phy_configure(struct imx_hdmi *hdmi, unsigned char prep,
 797                               unsigned char res, int cscon)
 798 {
 799         unsigned res_idx, i;
 800         u8 val, msec;
 801
 802         if (prep)
 803                 return -EINVAL;
 804
 805         switch (res) {
 806         case 0: /* color resolution 0 is 8 bit colour depth */
 807         case 8:
 808                 res_idx = RES_8;
 809                 break;
 810         case 10:
 811                 res_idx = RES_10;
 812                 break;
 813         case 12:
 814                 res_idx = RES_12;
 815                 break;
 816         default:
 817                 return -EINVAL;
 818         }
 819
 820         /* Enable csc path */
 821         if (cscon)
 822                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
 823         else
 824                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
 825
 826         hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
 827
 828         /* gen2 tx power off */
 829         imx_hdmi_phy_gen2_txpwron(hdmi, 0);
 830
 831         /* gen2 pddq */
 832         imx_hdmi_phy_gen2_pddq(hdmi, 1);
 833
 834         /* PHY reset */
 835         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
 836         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
 837
 838         hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
 839
 840         hdmi_phy_test_clear(hdmi, 1);
 841         hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
 842                     HDMI_PHY_I2CM_SLAVE_ADDR);
 843         hdmi_phy_test_clear(hdmi, 0);
 844
 845         /* PLL/MPLL Cfg - always match on final entry */
 846         for (i = 0; i < ARRAY_SIZE(mpll_config) - 1; i++)
 847                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
 848                     mpll_config[i].mpixelclock)
 849                         break;
 850
 851         hdmi_phy_i2c_write(hdmi, mpll_config[i].res[res_idx].cpce, 0x06);
 852         hdmi_phy_i2c_write(hdmi, mpll_config[i].res[res_idx].gmp, 0x15);
 853
 854         for (i = 0; i < ARRAY_SIZE(curr_ctrl); i++)
 855                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
 856                     curr_ctrl[i].mpixelclock)
 857                         break;
 858
 859         if (i >= ARRAY_SIZE(curr_ctrl)) {
 860                 dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n",
 861                         hdmi->hdmi_data.video_mode.mpixelclock);
 862                 return -EINVAL;
 863         }
 864
 865         /* CURRCTRL */
 866         hdmi_phy_i2c_write(hdmi, curr_ctrl[i].curr[res_idx], 0x10);
 867
 868         hdmi_phy_i2c_write(hdmi, 0x0000, 0x13);  /* PLLPHBYCTRL */
 869         hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
 870         /* RESISTANCE TERM 133Ohm Cfg */
 871         hdmi_phy_i2c_write(hdmi, 0x0005, 0x19);  /* TXTERM */
 872         /* PREEMP Cgf 0.00 */
 873         hdmi_phy_i2c_write(hdmi, 0x800d, 0x09);  /* CKSYMTXCTRL */
 874         /* TX/CK LVL 10 */
 875         hdmi_phy_i2c_write(hdmi, 0x01ad, 0x0E);  /* VLEVCTRL */
 876         /* REMOVE CLK TERM */
 877         hdmi_phy_i2c_write(hdmi, 0x8000, 0x05);  /* CKCALCTRL */
 878
 879         imx_hdmi_phy_enable_power(hdmi, 1);
 880
 881         /* toggle TMDS enable */
 882         imx_hdmi_phy_enable_tmds(hdmi, 0);
 883         imx_hdmi_phy_enable_tmds(hdmi, 1);
 884
 885         /* gen2 tx power on */
 886         imx_hdmi_phy_gen2_txpwron(hdmi, 1);
 887         imx_hdmi_phy_gen2_pddq(hdmi, 0);
 888
 889         /*Wait for PHY PLL lock */
 890         msec = 5;
 891         do {
 892                 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
 893                 if (!val)
 894                         break;
 895
 896                 if (msec == 0) {
 897                         dev_err(hdmi->dev, "PHY PLL not locked\n");
 898                         return -ETIMEDOUT;
 899                 }
 900
 901                 udelay(1000);
 902                 msec--;
 903         } while (1);
 904
 905         return 0;
 906 }
 907
 908 static int imx_hdmi_phy_init(struct imx_hdmi *hdmi)
 909 {
 910         int i, ret;
 911         bool cscon = false;
 912
 913         /*check csc whether needed activated in HDMI mode */
 914         cscon = (is_color_space_conversion(hdmi) &&
 915                         !hdmi->hdmi_data.video_mode.mdvi);
 916
 917         /* HDMI Phy spec says to do the phy initialization sequence twice */
 918         for (i = 0; i < 2; i++) {
 919                 imx_hdmi_phy_sel_data_en_pol(hdmi, 1);
 920                 imx_hdmi_phy_sel_interface_control(hdmi, 0);
 921                 imx_hdmi_phy_enable_tmds(hdmi, 0);
 922                 imx_hdmi_phy_enable_power(hdmi, 0);
 923
 924                 /* Enable CSC */
 925                 ret = hdmi_phy_configure(hdmi, 0, 8, cscon);
 926                 if (ret)
 927                         return ret;
 928         }
 929
 930         hdmi->phy_enabled = true;
 931         return 0;
 932 }
 933
 934 static void hdmi_tx_hdcp_config(struct imx_hdmi *hdmi)
 935 {
 936         u8 de;
 937
 938         if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
 939                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
 940         else
 941                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
 942
 943         /* disable rx detect */
 944         hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
 945                   HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
 946
 947         hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
 948
 949         hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
 950                   HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
 951 }
 952
 953 static void hdmi_config_AVI(struct imx_hdmi *hdmi)
 954 {
 955         u8 val, pix_fmt, under_scan;
 956         u8 act_ratio, coded_ratio, colorimetry, ext_colorimetry;
 957         bool aspect_16_9;
 958
 959         aspect_16_9 = false; /* FIXME */
 960
 961         /* AVI Data Byte 1 */
 962         if (hdmi->hdmi_data.enc_out_format == YCBCR444)
 963                 pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_YCBCR444;
 964         else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
 965                 pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_YCBCR422;
 966         else
 967                 pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_RGB;
 968
 969                 under_scan =  HDMI_FC_AVICONF0_SCAN_INFO_NODATA;
 970
 971         /*
 972          * Active format identification data is present in the AVI InfoFrame.
 973          * Under scan info, no bar data
 974          */
 975         val = pix_fmt | under_scan |
 976                 HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT |
 977                 HDMI_FC_AVICONF0_BAR_DATA_NO_DATA;
 978
 979         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
 980
 981         /* AVI Data Byte 2 -Set the Aspect Ratio */
 982         if (aspect_16_9) {
 983                 act_ratio = HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9;
 984                 coded_ratio = HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9;
 985         } else {
 986                 act_ratio = HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3;
 987                 coded_ratio = HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3;
 988         }
 989
 990         /* Set up colorimetry */
 991         if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
 992                 colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO;
 993                 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
 994                         ext_colorimetry =
 995                                 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
 996                 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
 997                         ext_colorimetry =
 998                                 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709;
 999         } else if (hdmi->hdmi_data.enc_out_format != RGB) {
1000                 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
1001                         colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_SMPTE;
1002                 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
1003                         colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_ITUR;
1004                 ext_colorimetry = HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
1005         } else { /* Carries no data */
1006                 colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA;
1007                 ext_colorimetry = HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
1008         }
1009
1010         val = colorimetry | coded_ratio | act_ratio;
1011         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1012
1013         /* AVI Data Byte 3 */
1014         val = HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA | ext_colorimetry |
1015                 HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT |
1016                 HDMI_FC_AVICONF2_SCALING_NONE;
1017         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1018
1019         /* AVI Data Byte 4 */
1020         hdmi_writeb(hdmi, hdmi->vic, HDMI_FC_AVIVID);
1021
1022         /* AVI Data Byte 5- set up input and output pixel repetition */
1023         val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1024                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1025                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1026                 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1027                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1028                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1029         hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1030
1031         /* IT Content and quantization range = don't care */
1032         val = HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS |
1033                 HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED;
1034         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1035
1036         /* AVI Data Bytes 6-13 */
1037         hdmi_writeb(hdmi, 0, HDMI_FC_AVIETB0);
1038         hdmi_writeb(hdmi, 0, HDMI_FC_AVIETB1);
1039         hdmi_writeb(hdmi, 0, HDMI_FC_AVISBB0);
1040         hdmi_writeb(hdmi, 0, HDMI_FC_AVISBB1);
1041         hdmi_writeb(hdmi, 0, HDMI_FC_AVIELB0);
1042         hdmi_writeb(hdmi, 0, HDMI_FC_AVIELB1);
1043         hdmi_writeb(hdmi, 0, HDMI_FC_AVISRB0);
1044         hdmi_writeb(hdmi, 0, HDMI_FC_AVISRB1);
1045 }
1046
1047 static void hdmi_av_composer(struct imx_hdmi *hdmi,
1048                              const struct drm_display_mode *mode)
1049 {
1050         u8 inv_val;
1051         struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1052         int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1053
1054         vmode->mhsyncpolarity = !!(mode->flags & DRM_MODE_FLAG_PHSYNC);
1055         vmode->mvsyncpolarity = !!(mode->flags & DRM_MODE_FLAG_PVSYNC);
1056         vmode->minterlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1057         vmode->mpixelclock = mode->clock * 1000;
1058
1059         dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1060
1061         /* Set up HDMI_FC_INVIDCONF */
1062         inv_val = (hdmi->hdmi_data.hdcp_enable ?
1063                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1064                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1065
1066         inv_val |= (vmode->mvsyncpolarity ?
1067                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1068                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW);
1069
1070         inv_val |= (vmode->mhsyncpolarity ?
1071                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1072                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW);
1073
1074         inv_val |= (vmode->mdataenablepolarity ?
1075                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1076                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1077
1078         if (hdmi->vic == 39)
1079                 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1080         else
1081                 inv_val |= (vmode->minterlaced ?
1082                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1083                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW);
1084
1085         inv_val |= (vmode->minterlaced ?
1086                 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1087                 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE);
1088
1089         inv_val |= (vmode->mdvi ?
1090                 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE :
1091                 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE);
1092
1093         hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1094
1095         /* Set up horizontal active pixel width */
1096         hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
1097         hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
1098
1099         /* Set up vertical active lines */
1100         hdmi_writeb(hdmi, mode->vdisplay >> 8, HDMI_FC_INVACTV1);
1101         hdmi_writeb(hdmi, mode->vdisplay, HDMI_FC_INVACTV0);
1102
1103         /* Set up horizontal blanking pixel region width */
1104         hblank = mode->htotal - mode->hdisplay;
1105         hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1106         hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1107
1108         /* Set up vertical blanking pixel region width */
1109         vblank = mode->vtotal - mode->vdisplay;
1110         hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1111
1112         /* Set up HSYNC active edge delay width (in pixel clks) */
1113         h_de_hs = mode->hsync_start - mode->hdisplay;
1114         hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1115         hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1116
1117         /* Set up VSYNC active edge delay (in lines) */
1118         v_de_vs = mode->vsync_start - mode->vdisplay;
1119         hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1120
1121         /* Set up HSYNC active pulse width (in pixel clks) */
1122         hsync_len = mode->hsync_end - mode->hsync_start;
1123         hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1124         hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1125
1126         /* Set up VSYNC active edge delay (in lines) */
1127         vsync_len = mode->vsync_end - mode->vsync_start;
1128         hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1129 }
1130
1131 static void imx_hdmi_phy_disable(struct imx_hdmi *hdmi)
1132 {
1133         if (!hdmi->phy_enabled)
1134                 return;
1135
1136         imx_hdmi_phy_enable_tmds(hdmi, 0);
1137         imx_hdmi_phy_enable_power(hdmi, 0);
1138
1139         hdmi->phy_enabled = false;
1140 }
1141
1142 /* HDMI Initialization Step B.4 */
1143 static void imx_hdmi_enable_video_path(struct imx_hdmi *hdmi)
1144 {
1145         u8 clkdis;
1146
1147         /* control period minimum duration */
1148         hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1149         hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1150         hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1151
1152         /* Set to fill TMDS data channels */
1153         hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1154         hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1155         hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1156
1157         /* Enable pixel clock and tmds data path */
1158         clkdis = 0x7F;
1159         clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1160         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1161
1162         clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1163         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1164
1165         /* Enable csc path */
1166         if (is_color_space_conversion(hdmi)) {
1167                 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1168                 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1169         }
1170 }
1171
1172 static void hdmi_enable_audio_clk(struct imx_hdmi *hdmi)
1173 {
1174         hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
1175 }
1176
1177 /* Workaround to clear the overflow condition */
1178 static void imx_hdmi_clear_overflow(struct imx_hdmi *hdmi)
1179 {
1180         int count;
1181         u8 val;
1182
1183         /* TMDS software reset */
1184         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1185
1186         val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1187         if (hdmi->dev_type == IMX6DL_HDMI) {
1188                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1189                 return;
1190         }
1191
1192         for (count = 0; count < 4; count++)
1193                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1194 }
1195
1196 static void hdmi_enable_overflow_interrupts(struct imx_hdmi *hdmi)
1197 {
1198         hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1199         hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1200 }
1201
1202 static void hdmi_disable_overflow_interrupts(struct imx_hdmi *hdmi)
1203 {
1204         hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1205                     HDMI_IH_MUTE_FC_STAT2);
1206 }
1207
1208 static int imx_hdmi_setup(struct imx_hdmi *hdmi, struct drm_display_mode *mode)
1209 {
1210         int ret;
1211
1212         hdmi_disable_overflow_interrupts(hdmi);
1213
1214         hdmi->vic = drm_match_cea_mode(mode);
1215
1216         if (!hdmi->vic) {
1217                 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1218                 hdmi->hdmi_data.video_mode.mdvi = true;
1219         } else {
1220                 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1221                 hdmi->hdmi_data.video_mode.mdvi = false;
1222         }
1223
1224         if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1225             (hdmi->vic == 21) || (hdmi->vic == 22) ||
1226             (hdmi->vic == 2) || (hdmi->vic == 3) ||
1227             (hdmi->vic == 17) || (hdmi->vic == 18))
1228                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
1229         else
1230                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
1231
1232         if ((hdmi->vic == 10) || (hdmi->vic == 11) ||
1233             (hdmi->vic == 12) || (hdmi->vic == 13) ||
1234             (hdmi->vic == 14) || (hdmi->vic == 15) ||
1235             (hdmi->vic == 25) || (hdmi->vic == 26) ||
1236             (hdmi->vic == 27) || (hdmi->vic == 28) ||
1237             (hdmi->vic == 29) || (hdmi->vic == 30) ||
1238             (hdmi->vic == 35) || (hdmi->vic == 36) ||
1239             (hdmi->vic == 37) || (hdmi->vic == 38))
1240                 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1;
1241         else
1242                 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1243
1244         hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1245
1246         /* TODO: Get input format from IPU (via FB driver interface) */
1247         hdmi->hdmi_data.enc_in_format = RGB;
1248
1249         hdmi->hdmi_data.enc_out_format = RGB;
1250
1251         hdmi->hdmi_data.enc_color_depth = 8;
1252         hdmi->hdmi_data.pix_repet_factor = 0;
1253         hdmi->hdmi_data.hdcp_enable = 0;
1254         hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1255
1256         /* HDMI Initialization Step B.1 */
1257         hdmi_av_composer(hdmi, mode);
1258
1259         /* HDMI Initializateion Step B.2 */
1260         ret = imx_hdmi_phy_init(hdmi);
1261         if (ret)
1262                 return ret;
1263
1264         /* HDMI Initialization Step B.3 */
1265         imx_hdmi_enable_video_path(hdmi);
1266
1267         /* not for DVI mode */
1268         if (hdmi->hdmi_data.video_mode.mdvi) {
1269                 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1270         } else {
1271                 dev_dbg(hdmi->dev, "%s CEA mode\n", __func__);
1272
1273                 /* HDMI Initialization Step E - Configure audio */
1274                 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1275                 hdmi_enable_audio_clk(hdmi);
1276
1277                 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1278                 hdmi_config_AVI(hdmi);
1279         }
1280
1281         hdmi_video_packetize(hdmi);
1282         hdmi_video_csc(hdmi);
1283         hdmi_video_sample(hdmi);
1284         hdmi_tx_hdcp_config(hdmi);
1285
1286         imx_hdmi_clear_overflow(hdmi);
1287         if (hdmi->cable_plugin && !hdmi->hdmi_data.video_mode.mdvi)
1288                 hdmi_enable_overflow_interrupts(hdmi);
1289
1290         return 0;
1291 }
1292
1293 /* Wait until we are registered to enable interrupts */
1294 static int imx_hdmi_fb_registered(struct imx_hdmi *hdmi)
1295 {
1296         hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
1297                     HDMI_PHY_I2CM_INT_ADDR);
1298
1299         hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
1300                     HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
1301                     HDMI_PHY_I2CM_CTLINT_ADDR);
1302
1303         /* enable cable hot plug irq */
1304         hdmi_writeb(hdmi, (u8)~HDMI_PHY_HPD, HDMI_PHY_MASK0);
1305
1306         /* Clear Hotplug interrupts */
1307         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
1308
1309         return 0;
1310 }
1311
1312 static void initialize_hdmi_ih_mutes(struct imx_hdmi *hdmi)
1313 {
1314         u8 ih_mute;
1315
1316         /*
1317          * Boot up defaults are:
1318          * HDMI_IH_MUTE   = 0x03 (disabled)
1319          * HDMI_IH_MUTE_* = 0x00 (enabled)
1320          *
1321          * Disable top level interrupt bits in HDMI block
1322          */
1323         ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1324                   HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1325                   HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1326
1327         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1328
1329         /* by default mask all interrupts */
1330         hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1331         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1332         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1333         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1334         hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1335         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1336         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1337         hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1338         hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1339         hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1340         hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1341         hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1342         hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1343         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1344         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1345
1346         /* Disable interrupts in the IH_MUTE_* registers */
1347         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1348         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1349         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1350         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1351         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1352         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1353         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1354         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1355         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1356         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1357
1358         /* Enable top level interrupt bits in HDMI block */
1359         ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1360                     HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1361         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1362 }
1363
1364 static void imx_hdmi_poweron(struct imx_hdmi *hdmi)
1365 {
1366         imx_hdmi_setup(hdmi, &hdmi->previous_mode);
1367 }
1368
1369 static void imx_hdmi_poweroff(struct imx_hdmi *hdmi)
1370 {
1371         imx_hdmi_phy_disable(hdmi);
1372 }
1373
1374 static enum drm_connector_status imx_hdmi_connector_detect(struct drm_connector
1375                                                         *connector, bool force)
1376 {
1377         struct imx_hdmi *hdmi = container_of(connector, struct imx_hdmi,
1378                                              connector);
1379
1380         return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1381                 connector_status_connected : connector_status_disconnected;
1382 }
1383
1384 static int imx_hdmi_connector_get_modes(struct drm_connector *connector)
1385 {
1386         struct imx_hdmi *hdmi = container_of(connector, struct imx_hdmi,
1387                                              connector);
1388         struct edid *edid;
1389         int ret;
1390
1391         if (!hdmi->ddc)
1392                 return 0;
1393
1394         edid = drm_get_edid(connector, hdmi->ddc);
1395         if (edid) {
1396                 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1397                         edid->width_cm, edid->height_cm);
1398
1399                 drm_mode_connector_update_edid_property(connector, edid);
1400                 ret = drm_add_edid_modes(connector, edid);
1401                 kfree(edid);
1402         } else {
1403                 dev_dbg(hdmi->dev, "failed to get edid\n");
1404         }
1405
1406         return 0;
1407 }
1408
1409 static struct drm_encoder *imx_hdmi_connector_best_encoder(struct drm_connector
1410                                                            *connector)
1411 {
1412         struct imx_hdmi *hdmi = container_of(connector, struct imx_hdmi,
1413                                              connector);
1414
1415         return &hdmi->encoder;
1416 }
1417
1418 static void imx_hdmi_encoder_mode_set(struct drm_encoder *encoder,
1419                         struct drm_display_mode *mode,
1420                         struct drm_display_mode *adjusted_mode)
1421 {
1422         struct imx_hdmi *hdmi = container_of(encoder, struct imx_hdmi, encoder);
1423
1424         imx_hdmi_setup(hdmi, mode);
1425
1426         /* Store the display mode for plugin/DKMS poweron events */
1427         memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1428 }
1429
1430 static bool imx_hdmi_encoder_mode_fixup(struct drm_encoder *encoder,
1431                         const struct drm_display_mode *mode,
1432                         struct drm_display_mode *adjusted_mode)
1433 {
1434         return true;
1435 }
1436
1437 static void imx_hdmi_encoder_disable(struct drm_encoder *encoder)
1438 {
1439 }
1440
1441 static void imx_hdmi_encoder_dpms(struct drm_encoder *encoder, int mode)
1442 {
1443         struct imx_hdmi *hdmi = container_of(encoder, struct imx_hdmi, encoder);
1444
1445         if (mode)
1446                 imx_hdmi_poweroff(hdmi);
1447         else
1448                 imx_hdmi_poweron(hdmi);
1449 }
1450
1451 static void imx_hdmi_encoder_prepare(struct drm_encoder *encoder)
1452 {
1453         struct imx_hdmi *hdmi = container_of(encoder, struct imx_hdmi, encoder);
1454
1455         imx_hdmi_poweroff(hdmi);
1456         imx_drm_panel_format(encoder, V4L2_PIX_FMT_RGB24);
1457 }
1458
1459 static void imx_hdmi_encoder_commit(struct drm_encoder *encoder)
1460 {
1461         struct imx_hdmi *hdmi = container_of(encoder, struct imx_hdmi, encoder);
1462         int mux = imx_drm_encoder_get_mux_id(hdmi->dev->of_node, encoder);
1463
1464         imx_hdmi_set_ipu_di_mux(hdmi, mux);
1465
1466         imx_hdmi_poweron(hdmi);
1467 }
1468
1469 static struct drm_encoder_funcs imx_hdmi_encoder_funcs = {
1470         .destroy = imx_drm_encoder_destroy,
1471 };
1472
1473 static struct drm_encoder_helper_funcs imx_hdmi_encoder_helper_funcs = {
1474         .dpms = imx_hdmi_encoder_dpms,
1475         .prepare = imx_hdmi_encoder_prepare,
1476         .commit = imx_hdmi_encoder_commit,
1477         .mode_set = imx_hdmi_encoder_mode_set,
1478         .mode_fixup = imx_hdmi_encoder_mode_fixup,
1479         .disable = imx_hdmi_encoder_disable,
1480 };
1481
1482 static struct drm_connector_funcs imx_hdmi_connector_funcs = {
1483         .dpms = drm_helper_connector_dpms,
1484         .fill_modes = drm_helper_probe_single_connector_modes,
1485         .detect = imx_hdmi_connector_detect,
1486         .destroy = imx_drm_connector_destroy,
1487 };
1488
1489 static struct drm_connector_helper_funcs imx_hdmi_connector_helper_funcs = {
1490         .get_modes = imx_hdmi_connector_get_modes,
1491         .best_encoder = imx_hdmi_connector_best_encoder,
1492 };
1493
1494 static irqreturn_t imx_hdmi_hardirq(int irq, void *dev_id)
1495 {
1496         struct imx_hdmi *hdmi = dev_id;
1497         u8 intr_stat;
1498
1499         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1500         if (intr_stat)
1501                 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1502
1503         return intr_stat ? IRQ_WAKE_THREAD : IRQ_NONE;
1504 }
1505
1506 static irqreturn_t imx_hdmi_irq(int irq, void *dev_id)
1507 {
1508         struct imx_hdmi *hdmi = dev_id;
1509         u8 intr_stat;
1510         u8 phy_int_pol;
1511
1512         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1513
1514         phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
1515
1516         if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
1517                 if (phy_int_pol & HDMI_PHY_HPD) {
1518                         dev_dbg(hdmi->dev, "EVENT=plugin\n");
1519
1520                         hdmi_modb(hdmi, 0, HDMI_PHY_HPD, HDMI_PHY_POL0);
1521
1522                         imx_hdmi_poweron(hdmi);
1523                 } else {
1524                         dev_dbg(hdmi->dev, "EVENT=plugout\n");
1525
1526                         hdmi_modb(hdmi, HDMI_PHY_HPD, HDMI_PHY_HPD,
1527                                   HDMI_PHY_POL0);
1528
1529                         imx_hdmi_poweroff(hdmi);
1530                 }
1531                 drm_helper_hpd_irq_event(hdmi->connector.dev);
1532         }
1533
1534         hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
1535         hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
1536
1537         return IRQ_HANDLED;
1538 }
1539
1540 static int imx_hdmi_register(struct drm_device *drm, struct imx_hdmi *hdmi)
1541 {
1542         int ret;
1543
1544         ret = imx_drm_encoder_parse_of(drm, &hdmi->encoder,
1545                                        hdmi->dev->of_node);
1546         if (ret)
1547                 return ret;
1548
1549         hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
1550
1551         drm_encoder_helper_add(&hdmi->encoder, &imx_hdmi_encoder_helper_funcs);
1552         drm_encoder_init(drm, &hdmi->encoder, &imx_hdmi_encoder_funcs,
1553                          DRM_MODE_ENCODER_TMDS);
1554
1555         drm_connector_helper_add(&hdmi->connector,
1556                                  &imx_hdmi_connector_helper_funcs);
1557         drm_connector_init(drm, &hdmi->connector, &imx_hdmi_connector_funcs,
1558                            DRM_MODE_CONNECTOR_HDMIA);
1559
1560         hdmi->connector.encoder = &hdmi->encoder;
1561
1562         drm_mode_connector_attach_encoder(&hdmi->connector, &hdmi->encoder);
1563
1564         return 0;
1565 }
1566
1567 static struct platform_device_id imx_hdmi_devtype[] = {
1568         {
1569                 .name = "imx6q-hdmi",
1570                 .driver_data = IMX6Q_HDMI,
1571         }, {
1572                 .name = "imx6dl-hdmi",
1573                 .driver_data = IMX6DL_HDMI,
1574         }, { /* sentinel */ }
1575 };
1576 MODULE_DEVICE_TABLE(platform, imx_hdmi_devtype);
1577
1578 static const struct of_device_id imx_hdmi_dt_ids[] = {
1579 { .compatible = "fsl,imx6q-hdmi", .data = &imx_hdmi_devtype[IMX6Q_HDMI], },
1580 { .compatible = "fsl,imx6dl-hdmi", .data = &imx_hdmi_devtype[IMX6DL_HDMI], },
1581 { /* sentinel */ }
1582 };
1583 MODULE_DEVICE_TABLE(of, imx_hdmi_dt_ids);
1584
1585 static int imx_hdmi_bind(struct device *dev, struct device *master, void *data)
1586 {
1587         struct platform_device *pdev = to_platform_device(dev);
1588         const struct of_device_id *of_id =
1589                                 of_match_device(imx_hdmi_dt_ids, dev);
1590         struct drm_device *drm = data;
1591         struct device_node *np = dev->of_node;
1592         struct device_node *ddc_node;
1593         struct imx_hdmi *hdmi;
1594         struct resource *iores;
1595         int ret, irq;
1596
1597         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1598         if (!hdmi)
1599                 return -ENOMEM;
1600
1601         hdmi->dev = dev;
1602         hdmi->sample_rate = 48000;
1603         hdmi->ratio = 100;
1604
1605         if (of_id) {
1606                 const struct platform_device_id *device_id = of_id->data;
1607
1608                 hdmi->dev_type = device_id->driver_data;
1609         }
1610
1611         ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
1612         if (ddc_node) {
1613                 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
1614                 if (!hdmi->ddc)
1615                         dev_dbg(hdmi->dev, "failed to read ddc node\n");
1616
1617                 of_node_put(ddc_node);
1618         } else {
1619                 dev_dbg(hdmi->dev, "no ddc property found\n");
1620         }
1621
1622         irq = platform_get_irq(pdev, 0);
1623         if (irq < 0)
1624                 return irq;
1625
1626         ret = devm_request_threaded_irq(dev, irq, imx_hdmi_hardirq,
1627                                         imx_hdmi_irq, IRQF_SHARED,
1628                                         dev_name(dev), hdmi);
1629         if (ret)
1630                 return ret;
1631
1632         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1633         hdmi->regs = devm_ioremap_resource(dev, iores);
1634         if (IS_ERR(hdmi->regs))
1635                 return PTR_ERR(hdmi->regs);
1636
1637         hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
1638         if (IS_ERR(hdmi->regmap))
1639                 return PTR_ERR(hdmi->regmap);
1640
1641         hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
1642         if (IS_ERR(hdmi->isfr_clk)) {
1643                 ret = PTR_ERR(hdmi->isfr_clk);
1644                 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
1645                 return ret;
1646         }
1647
1648         ret = clk_prepare_enable(hdmi->isfr_clk);
1649         if (ret) {
1650                 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
1651                 return ret;
1652         }
1653
1654         hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
1655         if (IS_ERR(hdmi->iahb_clk)) {
1656                 ret = PTR_ERR(hdmi->iahb_clk);
1657                 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
1658                 goto err_isfr;
1659         }
1660
1661         ret = clk_prepare_enable(hdmi->iahb_clk);
1662         if (ret) {
1663                 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
1664                 goto err_isfr;
1665         }
1666
1667         /* Product and revision IDs */
1668         dev_info(dev,
1669                  "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
1670                  hdmi_readb(hdmi, HDMI_DESIGN_ID),
1671                  hdmi_readb(hdmi, HDMI_REVISION_ID),
1672                  hdmi_readb(hdmi, HDMI_PRODUCT_ID0),
1673                  hdmi_readb(hdmi, HDMI_PRODUCT_ID1));
1674
1675         initialize_hdmi_ih_mutes(hdmi);
1676
1677         /*
1678          * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
1679          * N and cts values before enabling phy
1680          */
1681         hdmi_init_clk_regenerator(hdmi);
1682
1683         /*
1684          * Configure registers related to HDMI interrupt
1685          * generation before registering IRQ.
1686          */
1687         hdmi_writeb(hdmi, HDMI_PHY_HPD, HDMI_PHY_POL0);
1688
1689         /* Clear Hotplug interrupts */
1690         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
1691
1692         ret = imx_hdmi_fb_registered(hdmi);
1693         if (ret)
1694                 goto err_iahb;
1695
1696         ret = imx_hdmi_register(drm, hdmi);
1697         if (ret)
1698                 goto err_iahb;
1699
1700         /* Unmute interrupts */
1701         hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
1702
1703         dev_set_drvdata(dev, hdmi);
1704
1705         return 0;
1706
1707 err_iahb:
1708         clk_disable_unprepare(hdmi->iahb_clk);
1709 err_isfr:
1710         clk_disable_unprepare(hdmi->isfr_clk);
1711
1712         return ret;
1713 }
1714
1715 static void imx_hdmi_unbind(struct device *dev, struct device *master,
1716         void *data)
1717 {
1718         struct imx_hdmi *hdmi = dev_get_drvdata(dev);
1719
1720         /* Disable all interrupts */
1721         hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1722
1723         hdmi->connector.funcs->destroy(&hdmi->connector);
1724         hdmi->encoder.funcs->destroy(&hdmi->encoder);
1725
1726         clk_disable_unprepare(hdmi->iahb_clk);
1727         clk_disable_unprepare(hdmi->isfr_clk);
1728         i2c_put_adapter(hdmi->ddc);
1729 }
1730
1731 static const struct component_ops hdmi_ops = {
1732         .bind   = imx_hdmi_bind,
1733         .unbind = imx_hdmi_unbind,
1734 };
1735
1736 static int imx_hdmi_platform_probe(struct platform_device *pdev)
1737 {
1738         return component_add(&pdev->dev, &hdmi_ops);
1739 }
1740
1741 static int imx_hdmi_platform_remove(struct platform_device *pdev)
1742 {
1743         component_del(&pdev->dev, &hdmi_ops);
1744         return 0;
1745 }
1746
1747 static struct platform_driver imx_hdmi_driver = {
1748         .probe  = imx_hdmi_platform_probe,
1749         .remove = imx_hdmi_platform_remove,
1750         .driver = {
1751                 .name = "imx-hdmi",
1752                 .of_match_table = imx_hdmi_dt_ids,
1753         },
1754 };
1755
1756 module_platform_driver(imx_hdmi_driver);
1757
1758 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1759 MODULE_DESCRIPTION("i.MX6 HDMI transmitter driver");
1760 MODULE_LICENSE("GPL");
1761 MODULE_ALIAS("platform:imx-hdmi");