drivers/gpu/drm/i915/intel_runtime_pm.c

   1 /*
   2  * Copyright © 2012-2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *    Daniel Vetter <daniel.vetter@ffwll.ch>
  26  *
  27  */
  28
  29 #include <linux/pm_runtime.h>
  30 #include <linux/vgaarb.h>
  31
  32 #include "i915_drv.h"
  33 #include "intel_drv.h"
  34
  35 /**
  36  * DOC: runtime pm
  37  *
  38  * The i915 driver supports dynamic enabling and disabling of entire hardware
  39  * blocks at runtime. This is especially important on the display side where
  40  * software is supposed to control many power gates manually on recent hardware,
  41  * since on the GT side a lot of the power management is done by the hardware.
  42  * But even there some manual control at the device level is required.
  43  *
  44  * Since i915 supports a diverse set of platforms with a unified codebase and
  45  * hardware engineers just love to shuffle functionality around between power
  46  * domains there's a sizeable amount of indirection required. This file provides
  47  * generic functions to the driver for grabbing and releasing references for
  48  * abstract power domains. It then maps those to the actual power wells
  49  * present for a given platform.
  50  */
  51
  52 #define GEN9_ENABLE_DC5(dev) 0
  53 #define SKL_ENABLE_DC6(dev) IS_SKYLAKE(dev)
  54
  55 #define for_each_power_well(i, power_well, domain_mask, power_domains)  \
  56         for (i = 0;                                                     \
  57              i < (power_domains)->power_well_count &&                   \
  58                  ((power_well) = &(power_domains)->power_wells[i]);     \
  59              i++)                                                       \
  60                 if ((power_well)->domains & (domain_mask))
  61
  62 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
  63         for (i = (power_domains)->power_well_count - 1;                  \
  64              i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
  65              i--)                                                        \
  66                 if ((power_well)->domains & (domain_mask))
  67
  68 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
  69                                     int power_well_id);
  70
  71 static void intel_power_well_enable(struct drm_i915_private *dev_priv,
  72                                     struct i915_power_well *power_well)
  73 {
  74         DRM_DEBUG_KMS("enabling %s\n", power_well->name);
  75         power_well->ops->enable(dev_priv, power_well);
  76         power_well->hw_enabled = true;
  77 }
  78
  79 static void intel_power_well_disable(struct drm_i915_private *dev_priv,
  80                                      struct i915_power_well *power_well)
  81 {
  82         DRM_DEBUG_KMS("disabling %s\n", power_well->name);
  83         power_well->hw_enabled = false;
  84         power_well->ops->disable(dev_priv, power_well);
  85 }
  86
  87 /*
  88  * We should only use the power well if we explicitly asked the hardware to
  89  * enable it, so check if it's enabled and also check if we've requested it to
  90  * be enabled.
  91  */
  92 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
  93                                    struct i915_power_well *power_well)
  94 {
  95         return I915_READ(HSW_PWR_WELL_DRIVER) ==
  96                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
  97 }
  98
  99 /**
 100  * __intel_display_power_is_enabled - unlocked check for a power domain
 101  * @dev_priv: i915 device instance
 102  * @domain: power domain to check
 103  *
 104  * This is the unlocked version of intel_display_power_is_enabled() and should
 105  * only be used from error capture and recovery code where deadlocks are
 106  * possible.
 107  *
 108  * Returns:
 109  * True when the power domain is enabled, false otherwise.
 110  */
 111 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 112                                       enum intel_display_power_domain domain)
 113 {
 114         struct i915_power_domains *power_domains;
 115         struct i915_power_well *power_well;
 116         bool is_enabled;
 117         int i;
 118
 119         if (dev_priv->pm.suspended)
 120                 return false;
 121
 122         power_domains = &dev_priv->power_domains;
 123
 124         is_enabled = true;
 125
 126         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
 127                 if (power_well->always_on)
 128                         continue;
 129
 130                 if (!power_well->hw_enabled) {
 131                         is_enabled = false;
 132                         break;
 133                 }
 134         }
 135
 136         return is_enabled;
 137 }
 138
 139 /**
 140  * intel_display_power_is_enabled - check for a power domain
 141  * @dev_priv: i915 device instance
 142  * @domain: power domain to check
 143  *
 144  * This function can be used to check the hw power domain state. It is mostly
 145  * used in hardware state readout functions. Everywhere else code should rely
 146  * upon explicit power domain reference counting to ensure that the hardware
 147  * block is powered up before accessing it.
 148  *
 149  * Callers must hold the relevant modesetting locks to ensure that concurrent
 150  * threads can't disable the power well while the caller tries to read a few
 151  * registers.
 152  *
 153  * Returns:
 154  * True when the power domain is enabled, false otherwise.
 155  */
 156 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 157                                     enum intel_display_power_domain domain)
 158 {
 159         struct i915_power_domains *power_domains;
 160         bool ret;
 161
 162         power_domains = &dev_priv->power_domains;
 163
 164         mutex_lock(&power_domains->lock);
 165         ret = __intel_display_power_is_enabled(dev_priv, domain);
 166         mutex_unlock(&power_domains->lock);
 167
 168         return ret;
 169 }
 170
 171 /**
 172  * intel_display_set_init_power - set the initial power domain state
 173  * @dev_priv: i915 device instance
 174  * @enable: whether to enable or disable the initial power domain state
 175  *
 176  * For simplicity our driver load/unload and system suspend/resume code assumes
 177  * that all power domains are always enabled. This functions controls the state
 178  * of this little hack. While the initial power domain state is enabled runtime
 179  * pm is effectively disabled.
 180  */
 181 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
 182                                   bool enable)
 183 {
 184         if (dev_priv->power_domains.init_power_on == enable)
 185                 return;
 186
 187         if (enable)
 188                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 189         else
 190                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 191
 192         dev_priv->power_domains.init_power_on = enable;
 193 }
 194
 195 /*
 196  * Starting with Haswell, we have a "Power Down Well" that can be turned off
 197  * when not needed anymore. We have 4 registers that can request the power well
 198  * to be enabled, and it will only be disabled if none of the registers is
 199  * requesting it to be enabled.
 200  */
 201 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
 202 {
 203         struct drm_device *dev = dev_priv->dev;
 204
 205         /*
 206          * After we re-enable the power well, if we touch VGA register 0x3d5
 207          * we'll get unclaimed register interrupts. This stops after we write
 208          * anything to the VGA MSR register. The vgacon module uses this
 209          * register all the time, so if we unbind our driver and, as a
 210          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 211          * console_unlock(). So make here we touch the VGA MSR register, making
 212          * sure vgacon can keep working normally without triggering interrupts
 213          * and error messages.
 214          */
 215         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 216         outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 217         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 218
 219         if (IS_BROADWELL(dev))
 220                 gen8_irq_power_well_post_enable(dev_priv,
 221                                                 1 << PIPE_C | 1 << PIPE_B);
 222 }
 223
 224 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
 225                                        struct i915_power_well *power_well)
 226 {
 227         struct drm_device *dev = dev_priv->dev;
 228
 229         /*
 230          * After we re-enable the power well, if we touch VGA register 0x3d5
 231          * we'll get unclaimed register interrupts. This stops after we write
 232          * anything to the VGA MSR register. The vgacon module uses this
 233          * register all the time, so if we unbind our driver and, as a
 234          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 235          * console_unlock(). So make here we touch the VGA MSR register, making
 236          * sure vgacon can keep working normally without triggering interrupts
 237          * and error messages.
 238          */
 239         if (power_well->data == SKL_DISP_PW_2) {
 240                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 241                 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 242                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 243
 244                 gen8_irq_power_well_post_enable(dev_priv,
 245                                                 1 << PIPE_C | 1 << PIPE_B);
 246         }
 247
 248         if (power_well->data == SKL_DISP_PW_1) {
 249                 intel_prepare_ddi(dev);
 250                 gen8_irq_power_well_post_enable(dev_priv, 1 << PIPE_A);
 251         }
 252 }
 253
 254 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
 255                                struct i915_power_well *power_well, bool enable)
 256 {
 257         bool is_enabled, enable_requested;
 258         uint32_t tmp;
 259
 260         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 261         is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
 262         enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
 263
 264         if (enable) {
 265                 if (!enable_requested)
 266                         I915_WRITE(HSW_PWR_WELL_DRIVER,
 267                                    HSW_PWR_WELL_ENABLE_REQUEST);
 268
 269                 if (!is_enabled) {
 270                         DRM_DEBUG_KMS("Enabling power well\n");
 271                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
 272                                       HSW_PWR_WELL_STATE_ENABLED), 20))
 273                                 DRM_ERROR("Timeout enabling power well\n");
 274                         hsw_power_well_post_enable(dev_priv);
 275                 }
 276
 277         } else {
 278                 if (enable_requested) {
 279                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
 280                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 281                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
 282                 }
 283         }
 284 }
 285
 286 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 287         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 288         BIT(POWER_DOMAIN_PIPE_B) |                      \
 289         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 290         BIT(POWER_DOMAIN_PIPE_C) |                      \
 291         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 292         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 293         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 294         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |          \
 295         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |          \
 296         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |          \
 297         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |          \
 298         BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |          \
 299         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |          \
 300         BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) |          \
 301         BIT(POWER_DOMAIN_AUX_B) |                       \
 302         BIT(POWER_DOMAIN_AUX_C) |                       \
 303         BIT(POWER_DOMAIN_AUX_D) |                       \
 304         BIT(POWER_DOMAIN_AUDIO) |                       \
 305         BIT(POWER_DOMAIN_VGA) |                         \
 306         BIT(POWER_DOMAIN_INIT))
 307 #define SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS (         \
 308         SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 309         BIT(POWER_DOMAIN_PLLS) |                        \
 310         BIT(POWER_DOMAIN_PIPE_A) |                      \
 311         BIT(POWER_DOMAIN_TRANSCODER_EDP) |              \
 312         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |         \
 313         BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |          \
 314         BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |          \
 315         BIT(POWER_DOMAIN_AUX_A) |                       \
 316         BIT(POWER_DOMAIN_INIT))
 317 #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS (             \
 318         BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |          \
 319         BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |          \
 320         BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) |          \
 321         BIT(POWER_DOMAIN_INIT))
 322 #define SKL_DISPLAY_DDI_B_POWER_DOMAINS (               \
 323         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |          \
 324         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |          \
 325         BIT(POWER_DOMAIN_INIT))
 326 #define SKL_DISPLAY_DDI_C_POWER_DOMAINS (               \
 327         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |          \
 328         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |          \
 329         BIT(POWER_DOMAIN_INIT))
 330 #define SKL_DISPLAY_DDI_D_POWER_DOMAINS (               \
 331         BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |          \
 332         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |          \
 333         BIT(POWER_DOMAIN_INIT))
 334 #define SKL_DISPLAY_MISC_IO_POWER_DOMAINS (             \
 335         SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS |         \
 336         BIT(POWER_DOMAIN_PLLS) |                        \
 337         BIT(POWER_DOMAIN_INIT))
 338 #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS (           \
 339         (POWER_DOMAIN_MASK & ~(SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS |  \
 340         SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 341         SKL_DISPLAY_DDI_A_E_POWER_DOMAINS |             \
 342         SKL_DISPLAY_DDI_B_POWER_DOMAINS |               \
 343         SKL_DISPLAY_DDI_C_POWER_DOMAINS |               \
 344         SKL_DISPLAY_DDI_D_POWER_DOMAINS |               \
 345         SKL_DISPLAY_MISC_IO_POWER_DOMAINS)) |           \
 346         BIT(POWER_DOMAIN_INIT))
 347
 348 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 349         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 350         BIT(POWER_DOMAIN_PIPE_B) |                      \
 351         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 352         BIT(POWER_DOMAIN_PIPE_C) |                      \
 353         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 354         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 355         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 356         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |          \
 357         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |          \
 358         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |          \
 359         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |          \
 360         BIT(POWER_DOMAIN_AUX_B) |                       \
 361         BIT(POWER_DOMAIN_AUX_C) |                       \
 362         BIT(POWER_DOMAIN_AUDIO) |                       \
 363         BIT(POWER_DOMAIN_VGA) |                         \
 364         BIT(POWER_DOMAIN_INIT))
 365 #define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS (         \
 366         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 367         BIT(POWER_DOMAIN_PIPE_A) |                      \
 368         BIT(POWER_DOMAIN_TRANSCODER_EDP) |              \
 369         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |         \
 370         BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |          \
 371         BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |          \
 372         BIT(POWER_DOMAIN_AUX_A) |                       \
 373         BIT(POWER_DOMAIN_PLLS) |                        \
 374         BIT(POWER_DOMAIN_INIT))
 375 #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS (           \
 376         (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS |  \
 377         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) |       \
 378         BIT(POWER_DOMAIN_INIT))
 379
 380 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
 381 {
 382         struct drm_device *dev = dev_priv->dev;
 383
 384         WARN(!IS_BROXTON(dev), "Platform doesn't support DC9.\n");
 385         WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
 386                 "DC9 already programmed to be enabled.\n");
 387         WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 388                 "DC5 still not disabled to enable DC9.\n");
 389         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");
 390         WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
 391
 392          /*
 393           * TODO: check for the following to verify the conditions to enter DC9
 394           * state are satisfied:
 395           * 1] Check relevant display engine registers to verify if mode set
 396           * disable sequence was followed.
 397           * 2] Check if display uninitialize sequence is initialized.
 398           */
 399 }
 400
 401 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
 402 {
 403         WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
 404         WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
 405                 "DC9 already programmed to be disabled.\n");
 406         WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 407                 "DC5 still not disabled.\n");
 408
 409          /*
 410           * TODO: check for the following to verify DC9 state was indeed
 411           * entered before programming to disable it:
 412           * 1] Check relevant display engine registers to verify if mode
 413           *  set disable sequence was followed.
 414           * 2] Check if display uninitialize sequence is initialized.
 415           */
 416 }
 417
 418 void bxt_enable_dc9(struct drm_i915_private *dev_priv)
 419 {
 420         uint32_t val;
 421
 422         assert_can_enable_dc9(dev_priv);
 423
 424         DRM_DEBUG_KMS("Enabling DC9\n");
 425
 426         val = I915_READ(DC_STATE_EN);
 427         val |= DC_STATE_EN_DC9;
 428         I915_WRITE(DC_STATE_EN, val);
 429         POSTING_READ(DC_STATE_EN);
 430 }
 431
 432 void bxt_disable_dc9(struct drm_i915_private *dev_priv)
 433 {
 434         uint32_t val;
 435
 436         assert_can_disable_dc9(dev_priv);
 437
 438         DRM_DEBUG_KMS("Disabling DC9\n");
 439
 440         val = I915_READ(DC_STATE_EN);
 441         val &= ~DC_STATE_EN_DC9;
 442         I915_WRITE(DC_STATE_EN, val);
 443         POSTING_READ(DC_STATE_EN);
 444 }
 445
 446 static void gen9_set_dc_state_debugmask_memory_up(
 447                         struct drm_i915_private *dev_priv)
 448 {
 449         uint32_t val;
 450
 451         /* The below bit doesn't need to be cleared ever afterwards */
 452         val = I915_READ(DC_STATE_DEBUG);
 453         if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) {
 454                 val |= DC_STATE_DEBUG_MASK_MEMORY_UP;
 455                 I915_WRITE(DC_STATE_DEBUG, val);
 456                 POSTING_READ(DC_STATE_DEBUG);
 457         }
 458 }
 459
 460 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
 461 {
 462         struct drm_device *dev = dev_priv->dev;
 463         bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
 464                                         SKL_DISP_PW_2);
 465
 466         WARN_ONCE(!IS_SKYLAKE(dev), "Platform doesn't support DC5.\n");
 467         WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
 468         WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
 469
 470         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
 471                   "DC5 already programmed to be enabled.\n");
 472         WARN_ONCE(dev_priv->pm.suspended,
 473                   "DC5 cannot be enabled, if platform is runtime-suspended.\n");
 474
 475         assert_csr_loaded(dev_priv);
 476 }
 477
 478 static void assert_can_disable_dc5(struct drm_i915_private *dev_priv)
 479 {
 480         bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
 481                                         SKL_DISP_PW_2);
 482         /*
 483          * During initialization, the firmware may not be loaded yet.
 484          * We still want to make sure that the DC enabling flag is cleared.
 485          */
 486         if (dev_priv->power_domains.initializing)
 487                 return;
 488
 489         WARN_ONCE(!pg2_enabled, "PG2 not enabled to disable DC5.\n");
 490         WARN_ONCE(dev_priv->pm.suspended,
 491                 "Disabling of DC5 while platform is runtime-suspended should never happen.\n");
 492 }
 493
 494 static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
 495 {
 496         uint32_t val;
 497
 498         assert_can_enable_dc5(dev_priv);
 499
 500         DRM_DEBUG_KMS("Enabling DC5\n");
 501
 502         gen9_set_dc_state_debugmask_memory_up(dev_priv);
 503
 504         val = I915_READ(DC_STATE_EN);
 505         val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK;
 506         val |= DC_STATE_EN_UPTO_DC5;
 507         I915_WRITE(DC_STATE_EN, val);
 508         POSTING_READ(DC_STATE_EN);
 509 }
 510
 511 static void gen9_disable_dc5(struct drm_i915_private *dev_priv)
 512 {
 513         uint32_t val;
 514
 515         assert_can_disable_dc5(dev_priv);
 516
 517         DRM_DEBUG_KMS("Disabling DC5\n");
 518
 519         val = I915_READ(DC_STATE_EN);
 520         val &= ~DC_STATE_EN_UPTO_DC5;
 521         I915_WRITE(DC_STATE_EN, val);
 522         POSTING_READ(DC_STATE_EN);
 523 }
 524
 525 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
 526 {
 527         struct drm_device *dev = dev_priv->dev;
 528
 529         WARN_ONCE(!IS_SKYLAKE(dev), "Platform doesn't support DC6.\n");
 530         WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
 531         WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
 532                   "Backlight is not disabled.\n");
 533         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
 534                   "DC6 already programmed to be enabled.\n");
 535
 536         assert_csr_loaded(dev_priv);
 537 }
 538
 539 static void assert_can_disable_dc6(struct drm_i915_private *dev_priv)
 540 {
 541         /*
 542          * During initialization, the firmware may not be loaded yet.
 543          * We still want to make sure that the DC enabling flag is cleared.
 544          */
 545         if (dev_priv->power_domains.initializing)
 546                 return;
 547
 548         assert_csr_loaded(dev_priv);
 549         WARN_ONCE(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
 550                   "DC6 already programmed to be disabled.\n");
 551 }
 552
 553 static void skl_enable_dc6(struct drm_i915_private *dev_priv)
 554 {
 555         uint32_t val;
 556
 557         assert_can_enable_dc6(dev_priv);
 558
 559         DRM_DEBUG_KMS("Enabling DC6\n");
 560
 561         gen9_set_dc_state_debugmask_memory_up(dev_priv);
 562
 563         val = I915_READ(DC_STATE_EN);
 564         val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK;
 565         val |= DC_STATE_EN_UPTO_DC6;
 566         I915_WRITE(DC_STATE_EN, val);
 567         POSTING_READ(DC_STATE_EN);
 568 }
 569
 570 static void skl_disable_dc6(struct drm_i915_private *dev_priv)
 571 {
 572         uint32_t val;
 573
 574         assert_can_disable_dc6(dev_priv);
 575
 576         DRM_DEBUG_KMS("Disabling DC6\n");
 577
 578         val = I915_READ(DC_STATE_EN);
 579         val &= ~DC_STATE_EN_UPTO_DC6;
 580         I915_WRITE(DC_STATE_EN, val);
 581         POSTING_READ(DC_STATE_EN);
 582 }
 583
 584 static void skl_set_power_well(struct drm_i915_private *dev_priv,
 585                         struct i915_power_well *power_well, bool enable)
 586 {
 587         struct drm_device *dev = dev_priv->dev;
 588         uint32_t tmp, fuse_status;
 589         uint32_t req_mask, state_mask;
 590         bool is_enabled, enable_requested, check_fuse_status = false;
 591
 592         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 593         fuse_status = I915_READ(SKL_FUSE_STATUS);
 594
 595         switch (power_well->data) {
 596         case SKL_DISP_PW_1:
 597                 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 598                         SKL_FUSE_PG0_DIST_STATUS), 1)) {
 599                         DRM_ERROR("PG0 not enabled\n");
 600                         return;
 601                 }
 602                 break;
 603         case SKL_DISP_PW_2:
 604                 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
 605                         DRM_ERROR("PG1 in disabled state\n");
 606                         return;
 607                 }
 608                 break;
 609         case SKL_DISP_PW_DDI_A_E:
 610         case SKL_DISP_PW_DDI_B:
 611         case SKL_DISP_PW_DDI_C:
 612         case SKL_DISP_PW_DDI_D:
 613         case SKL_DISP_PW_MISC_IO:
 614                 break;
 615         default:
 616                 WARN(1, "Unknown power well %lu\n", power_well->data);
 617                 return;
 618         }
 619
 620         req_mask = SKL_POWER_WELL_REQ(power_well->data);
 621         enable_requested = tmp & req_mask;
 622         state_mask = SKL_POWER_WELL_STATE(power_well->data);
 623         is_enabled = tmp & state_mask;
 624
 625         if (enable) {
 626                 if (!enable_requested) {
 627                         WARN((tmp & state_mask) &&
 628                                 !I915_READ(HSW_PWR_WELL_BIOS),
 629                                 "Invalid for power well status to be enabled, unless done by the BIOS, \
 630                                 when request is to disable!\n");
 631                         if ((GEN9_ENABLE_DC5(dev) || SKL_ENABLE_DC6(dev)) &&
 632                                 power_well->data == SKL_DISP_PW_2) {
 633                                 if (SKL_ENABLE_DC6(dev)) {
 634                                         skl_disable_dc6(dev_priv);
 635                                         /*
 636                                          * DDI buffer programming unnecessary during driver-load/resume
 637                                          * as it's already done during modeset initialization then.
 638                                          * It's also invalid here as encoder list is still uninitialized.
 639                                          */
 640                                         if (!dev_priv->power_domains.initializing)
 641                                                 intel_prepare_ddi(dev);
 642                                 } else {
 643                                         gen9_disable_dc5(dev_priv);
 644                                 }
 645                         }
 646                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
 647                 }
 648
 649                 if (!is_enabled) {
 650                         DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
 651                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
 652                                 state_mask), 1))
 653                                 DRM_ERROR("%s enable timeout\n",
 654                                         power_well->name);
 655                         check_fuse_status = true;
 656                 }
 657         } else {
 658                 if (enable_requested) {
 659                         if (IS_SKYLAKE(dev) &&
 660                                 (power_well->data == SKL_DISP_PW_1) &&
 661                                 (intel_csr_load_status_get(dev_priv) == FW_LOADED))
 662                                 DRM_DEBUG_KMS("Not Disabling PW1, dmc will handle\n");
 663                         else {
 664                                 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
 665                                 POSTING_READ(HSW_PWR_WELL_DRIVER);
 666                                 DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
 667                         }
 668
 669                         if ((GEN9_ENABLE_DC5(dev) || SKL_ENABLE_DC6(dev)) &&
 670                                 power_well->data == SKL_DISP_PW_2) {
 671                                 enum csr_state state;
 672                                 /* TODO: wait for a completion event or
 673                                  * similar here instead of busy
 674                                  * waiting using wait_for function.
 675                                  */
 676                                 wait_for((state = intel_csr_load_status_get(dev_priv)) !=
 677                                                 FW_UNINITIALIZED, 1000);
 678                                 if (state != FW_LOADED)
 679                                         DRM_DEBUG("CSR firmware not ready (%d)\n",
 680                                                         state);
 681                                 else
 682                                         if (SKL_ENABLE_DC6(dev))
 683                                                 skl_enable_dc6(dev_priv);
 684                                         else
 685                                                 gen9_enable_dc5(dev_priv);
 686                         }
 687                 }
 688         }
 689
 690         if (check_fuse_status) {
 691                 if (power_well->data == SKL_DISP_PW_1) {
 692                         if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 693                                 SKL_FUSE_PG1_DIST_STATUS), 1))
 694                                 DRM_ERROR("PG1 distributing status timeout\n");
 695                 } else if (power_well->data == SKL_DISP_PW_2) {
 696                         if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 697                                 SKL_FUSE_PG2_DIST_STATUS), 1))
 698                                 DRM_ERROR("PG2 distributing status timeout\n");
 699                 }
 700         }
 701
 702         if (enable && !is_enabled)
 703                 skl_power_well_post_enable(dev_priv, power_well);
 704 }
 705
 706 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
 707                                    struct i915_power_well *power_well)
 708 {
 709         hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
 710
 711         /*
 712          * We're taking over the BIOS, so clear any requests made by it since
 713          * the driver is in charge now.
 714          */
 715         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
 716                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 717 }
 718
 719 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
 720                                   struct i915_power_well *power_well)
 721 {
 722         hsw_set_power_well(dev_priv, power_well, true);
 723 }
 724
 725 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
 726                                    struct i915_power_well *power_well)
 727 {
 728         hsw_set_power_well(dev_priv, power_well, false);
 729 }
 730
 731 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
 732                                         struct i915_power_well *power_well)
 733 {
 734         uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) |
 735                 SKL_POWER_WELL_STATE(power_well->data);
 736
 737         return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
 738 }
 739
 740 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
 741                                 struct i915_power_well *power_well)
 742 {
 743         skl_set_power_well(dev_priv, power_well, power_well->count > 0);
 744
 745         /* Clear any request made by BIOS as driver is taking over */
 746         I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 747 }
 748
 749 static void skl_power_well_enable(struct drm_i915_private *dev_priv,
 750                                 struct i915_power_well *power_well)
 751 {
 752         skl_set_power_well(dev_priv, power_well, true);
 753 }
 754
 755 static void skl_power_well_disable(struct drm_i915_private *dev_priv,
 756                                 struct i915_power_well *power_well)
 757 {
 758         skl_set_power_well(dev_priv, power_well, false);
 759 }
 760
 761 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
 762                                            struct i915_power_well *power_well)
 763 {
 764 }
 765
 766 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
 767                                              struct i915_power_well *power_well)
 768 {
 769         return true;
 770 }
 771
 772 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
 773                                struct i915_power_well *power_well, bool enable)
 774 {
 775         enum punit_power_well power_well_id = power_well->data;
 776         u32 mask;
 777         u32 state;
 778         u32 ctrl;
 779
 780         mask = PUNIT_PWRGT_MASK(power_well_id);
 781         state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
 782                          PUNIT_PWRGT_PWR_GATE(power_well_id);
 783
 784         mutex_lock(&dev_priv->rps.hw_lock);
 785
 786 #define COND \
 787         ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
 788
 789         if (COND)
 790                 goto out;
 791
 792         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
 793         ctrl &= ~mask;
 794         ctrl |= state;
 795         vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
 796
 797         if (wait_for(COND, 100))
 798                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
 799                           state,
 800                           vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
 801
 802 #undef COND
 803
 804 out:
 805         mutex_unlock(&dev_priv->rps.hw_lock);
 806 }
 807
 808 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
 809                                    struct i915_power_well *power_well)
 810 {
 811         vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
 812 }
 813
 814 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
 815                                   struct i915_power_well *power_well)
 816 {
 817         vlv_set_power_well(dev_priv, power_well, true);
 818 }
 819
 820 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
 821                                    struct i915_power_well *power_well)
 822 {
 823         vlv_set_power_well(dev_priv, power_well, false);
 824 }
 825
 826 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
 827                                    struct i915_power_well *power_well)
 828 {
 829         int power_well_id = power_well->data;
 830         bool enabled = false;
 831         u32 mask;
 832         u32 state;
 833         u32 ctrl;
 834
 835         mask = PUNIT_PWRGT_MASK(power_well_id);
 836         ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
 837
 838         mutex_lock(&dev_priv->rps.hw_lock);
 839
 840         state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
 841         /*
 842          * We only ever set the power-on and power-gate states, anything
 843          * else is unexpected.
 844          */
 845         WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
 846                 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
 847         if (state == ctrl)
 848                 enabled = true;
 849
 850         /*
 851          * A transient state at this point would mean some unexpected party
 852          * is poking at the power controls too.
 853          */
 854         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
 855         WARN_ON(ctrl != state);
 856
 857         mutex_unlock(&dev_priv->rps.hw_lock);
 858
 859         return enabled;
 860 }
 861
 862 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
 863 {
 864         enum pipe pipe;
 865
 866         /*
 867          * Enable the CRI clock source so we can get at the
 868          * display and the reference clock for VGA
 869          * hotplug / manual detection. Supposedly DSI also
 870          * needs the ref clock up and running.
 871          *
 872          * CHV DPLL B/C have some issues if VGA mode is enabled.
 873          */
 874         for_each_pipe(dev_priv->dev, pipe) {
 875                 u32 val = I915_READ(DPLL(pipe));
 876
 877                 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
 878                 if (pipe != PIPE_A)
 879                         val |= DPLL_INTEGRATED_CRI_CLK_VLV;
 880
 881                 I915_WRITE(DPLL(pipe), val);
 882         }
 883
 884         spin_lock_irq(&dev_priv->irq_lock);
 885         valleyview_enable_display_irqs(dev_priv);
 886         spin_unlock_irq(&dev_priv->irq_lock);
 887
 888         /*
 889          * During driver initialization/resume we can avoid restoring the
 890          * part of the HW/SW state that will be inited anyway explicitly.
 891          */
 892         if (dev_priv->power_domains.initializing)
 893                 return;
 894
 895         intel_hpd_init(dev_priv);
 896
 897         i915_redisable_vga_power_on(dev_priv->dev);
 898 }
 899
 900 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
 901 {
 902         spin_lock_irq(&dev_priv->irq_lock);
 903         valleyview_disable_display_irqs(dev_priv);
 904         spin_unlock_irq(&dev_priv->irq_lock);
 905
 906         vlv_power_sequencer_reset(dev_priv);
 907 }
 908
 909 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
 910                                           struct i915_power_well *power_well)
 911 {
 912         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
 913
 914         vlv_set_power_well(dev_priv, power_well, true);
 915
 916         vlv_display_power_well_init(dev_priv);
 917 }
 918
 919 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
 920                                            struct i915_power_well *power_well)
 921 {
 922         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
 923
 924         vlv_display_power_well_deinit(dev_priv);
 925
 926         vlv_set_power_well(dev_priv, power_well, false);
 927 }
 928
 929 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
 930                                            struct i915_power_well *power_well)
 931 {
 932         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
 933
 934         /* since ref/cri clock was enabled */
 935         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
 936
 937         vlv_set_power_well(dev_priv, power_well, true);
 938
 939         /*
 940          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
 941          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
 942          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
 943          *   b. The other bits such as sfr settings / modesel may all
 944          *      be set to 0.
 945          *
 946          * This should only be done on init and resume from S3 with
 947          * both PLLs disabled, or we risk losing DPIO and PLL
 948          * synchronization.
 949          */
 950         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
 951 }
 952
 953 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
 954                                             struct i915_power_well *power_well)
 955 {
 956         enum pipe pipe;
 957
 958         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
 959
 960         for_each_pipe(dev_priv, pipe)
 961                 assert_pll_disabled(dev_priv, pipe);
 962
 963         /* Assert common reset */
 964         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
 965
 966         vlv_set_power_well(dev_priv, power_well, false);
 967 }
 968
 969 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
 970
 971 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
 972                                                  int power_well_id)
 973 {
 974         struct i915_power_domains *power_domains = &dev_priv->power_domains;
 975         struct i915_power_well *power_well;
 976         int i;
 977
 978         for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
 979                 if (power_well->data == power_well_id)
 980                         return power_well;
 981         }
 982
 983         return NULL;
 984 }
 985
 986 #define BITS_SET(val, bits) (((val) & (bits)) == (bits))
 987
 988 static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
 989 {
 990         struct i915_power_well *cmn_bc =
 991                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
 992         struct i915_power_well *cmn_d =
 993                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
 994         u32 phy_control = dev_priv->chv_phy_control;
 995         u32 phy_status = 0;
 996         u32 phy_status_mask = 0xffffffff;
 997         u32 tmp;
 998
 999         /*
1000          * The BIOS can leave the PHY is some weird state
1001          * where it doesn't fully power down some parts.
1002          * Disable the asserts until the PHY has been fully
1003          * reset (ie. the power well has been disabled at
1004          * least once).
1005          */
1006         if (!dev_priv->chv_phy_assert[DPIO_PHY0])
1007                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
1008                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
1009                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
1010                                      PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) |
1011                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
1012                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
1013
1014         if (!dev_priv->chv_phy_assert[DPIO_PHY1])
1015                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
1016                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
1017                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
1018
1019         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
1020                 phy_status |= PHY_POWERGOOD(DPIO_PHY0);
1021
1022                 /* this assumes override is only used to enable lanes */
1023                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0)
1024                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0);
1025
1026                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)
1027                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);
1028
1029                 /* CL1 is on whenever anything is on in either channel */
1030                 if (BITS_SET(phy_control,
1031                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) |
1032                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))
1033                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0);
1034
1035                 /*
1036                  * The DPLLB check accounts for the pipe B + port A usage
1037                  * with CL2 powered up but all the lanes in the second channel
1038                  * powered down.
1039                  */
1040                 if (BITS_SET(phy_control,
1041                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
1042                     (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1043                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
1044
1045                 if (BITS_SET(phy_control,
1046                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)))
1047                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0);
1048                 if (BITS_SET(phy_control,
1049                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)))
1050                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1);
1051
1052                 if (BITS_SET(phy_control,
1053                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))
1054                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);
1055                 if (BITS_SET(phy_control,
1056                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))
1057                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
1058         }
1059
1060         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
1061                 phy_status |= PHY_POWERGOOD(DPIO_PHY1);
1062
1063                 /* this assumes override is only used to enable lanes */
1064                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)
1065                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);
1066
1067                 if (BITS_SET(phy_control,
1068                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))
1069                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);
1070
1071                 if (BITS_SET(phy_control,
1072                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))
1073                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);
1074                 if (BITS_SET(phy_control,
1075                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))
1076                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);
1077         }
1078
1079         phy_status &= phy_status_mask;
1080
1081         /*
1082          * The PHY may be busy with some initial calibration and whatnot,
1083          * so the power state can take a while to actually change.
1084          */
1085         if (wait_for((tmp = I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask) == phy_status, 10))
1086                 WARN(phy_status != tmp,
1087                      "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1088                      tmp, phy_status, dev_priv->chv_phy_control);
1089 }
1090
1091 #undef BITS_SET
1092
1093 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1094                                            struct i915_power_well *power_well)
1095 {
1096         enum dpio_phy phy;
1097         enum pipe pipe;
1098         uint32_t tmp;
1099
1100         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1101                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1102
1103         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1104                 pipe = PIPE_A;
1105                 phy = DPIO_PHY0;
1106         } else {
1107                 pipe = PIPE_C;
1108                 phy = DPIO_PHY1;
1109         }
1110
1111         /* since ref/cri clock was enabled */
1112         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1113         vlv_set_power_well(dev_priv, power_well, true);
1114
1115         /* Poll for phypwrgood signal */
1116         if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
1117                 DRM_ERROR("Display PHY %d is not power up\n", phy);
1118
1119         mutex_lock(&dev_priv->sb_lock);
1120
1121         /* Enable dynamic power down */
1122         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
1123         tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
1124                 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
1125         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
1126
1127         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1128                 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
1129                 tmp |= DPIO_DYNPWRDOWNEN_CH1;
1130                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
1131         } else {
1132                 /*
1133                  * Force the non-existing CL2 off. BXT does this
1134                  * too, so maybe it saves some power even though
1135                  * CL2 doesn't exist?
1136                  */
1137                 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1138                 tmp |= DPIO_CL2_LDOFUSE_PWRENB;
1139                 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
1140         }
1141
1142         mutex_unlock(&dev_priv->sb_lock);
1143
1144         dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
1145         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1146
1147         DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1148                       phy, dev_priv->chv_phy_control);
1149
1150         assert_chv_phy_status(dev_priv);
1151 }
1152
1153 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1154                                             struct i915_power_well *power_well)
1155 {
1156         enum dpio_phy phy;
1157
1158         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1159                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1160
1161         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1162                 phy = DPIO_PHY0;
1163                 assert_pll_disabled(dev_priv, PIPE_A);
1164                 assert_pll_disabled(dev_priv, PIPE_B);
1165         } else {
1166                 phy = DPIO_PHY1;
1167                 assert_pll_disabled(dev_priv, PIPE_C);
1168         }
1169
1170         dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1171         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1172
1173         vlv_set_power_well(dev_priv, power_well, false);
1174
1175         DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1176                       phy, dev_priv->chv_phy_control);
1177
1178         /* PHY is fully reset now, so we can enable the PHY state asserts */
1179         dev_priv->chv_phy_assert[phy] = true;
1180
1181         assert_chv_phy_status(dev_priv);
1182 }
1183
1184 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1185                                      enum dpio_channel ch, bool override, unsigned int mask)
1186 {
1187         enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
1188         u32 reg, val, expected, actual;
1189
1190         /*
1191          * The BIOS can leave the PHY is some weird state
1192          * where it doesn't fully power down some parts.
1193          * Disable the asserts until the PHY has been fully
1194          * reset (ie. the power well has been disabled at
1195          * least once).
1196          */
1197         if (!dev_priv->chv_phy_assert[phy])
1198                 return;
1199
1200         if (ch == DPIO_CH0)
1201                 reg = _CHV_CMN_DW0_CH0;
1202         else
1203                 reg = _CHV_CMN_DW6_CH1;
1204
1205         mutex_lock(&dev_priv->sb_lock);
1206         val = vlv_dpio_read(dev_priv, pipe, reg);
1207         mutex_unlock(&dev_priv->sb_lock);
1208
1209         /*
1210          * This assumes !override is only used when the port is disabled.
1211          * All lanes should power down even without the override when
1212          * the port is disabled.
1213          */
1214         if (!override || mask == 0xf) {
1215                 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1216                 /*
1217                  * If CH1 common lane is not active anymore
1218                  * (eg. for pipe B DPLL) the entire channel will
1219                  * shut down, which causes the common lane registers
1220                  * to read as 0. That means we can't actually check
1221                  * the lane power down status bits, but as the entire
1222                  * register reads as 0 it's a good indication that the
1223                  * channel is indeed entirely powered down.
1224                  */
1225                 if (ch == DPIO_CH1 && val == 0)
1226                         expected = 0;
1227         } else if (mask != 0x0) {
1228                 expected = DPIO_ANYDL_POWERDOWN;
1229         } else {
1230                 expected = 0;
1231         }
1232
1233         if (ch == DPIO_CH0)
1234                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
1235         else
1236                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
1237         actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1238
1239         WARN(actual != expected,
1240              "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
1241              !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN),
1242              !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN),
1243              reg, val);
1244 }
1245
1246 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1247                           enum dpio_channel ch, bool override)
1248 {
1249         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1250         bool was_override;
1251
1252         mutex_lock(&power_domains->lock);
1253
1254         was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1255
1256         if (override == was_override)
1257                 goto out;
1258
1259         if (override)
1260                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1261         else
1262                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1263
1264         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1265
1266         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1267                       phy, ch, dev_priv->chv_phy_control);
1268
1269         assert_chv_phy_status(dev_priv);
1270
1271 out:
1272         mutex_unlock(&power_domains->lock);
1273
1274         return was_override;
1275 }
1276
1277 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1278                              bool override, unsigned int mask)
1279 {
1280         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1281         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1282         enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base));
1283         enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1284
1285         mutex_lock(&power_domains->lock);
1286
1287         dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
1288         dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
1289
1290         if (override)
1291                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1292         else
1293                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1294
1295         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1296
1297         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1298                       phy, ch, mask, dev_priv->chv_phy_control);
1299
1300         assert_chv_phy_status(dev_priv);
1301
1302         assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
1303
1304         mutex_unlock(&power_domains->lock);
1305 }
1306
1307 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
1308                                         struct i915_power_well *power_well)
1309 {
1310         enum pipe pipe = power_well->data;
1311         bool enabled;
1312         u32 state, ctrl;
1313
1314         mutex_lock(&dev_priv->rps.hw_lock);
1315
1316         state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
1317         /*
1318          * We only ever set the power-on and power-gate states, anything
1319          * else is unexpected.
1320          */
1321         WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
1322         enabled = state == DP_SSS_PWR_ON(pipe);
1323
1324         /*
1325          * A transient state at this point would mean some unexpected party
1326          * is poking at the power controls too.
1327          */
1328         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
1329         WARN_ON(ctrl << 16 != state);
1330
1331         mutex_unlock(&dev_priv->rps.hw_lock);
1332
1333         return enabled;
1334 }
1335
1336 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
1337                                     struct i915_power_well *power_well,
1338                                     bool enable)
1339 {
1340         enum pipe pipe = power_well->data;
1341         u32 state;
1342         u32 ctrl;
1343
1344         state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
1345
1346         mutex_lock(&dev_priv->rps.hw_lock);
1347
1348 #define COND \
1349         ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
1350
1351         if (COND)
1352                 goto out;
1353
1354         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
1355         ctrl &= ~DP_SSC_MASK(pipe);
1356         ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
1357         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
1358
1359         if (wait_for(COND, 100))
1360                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
1361                           state,
1362                           vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
1363
1364 #undef COND
1365
1366 out:
1367         mutex_unlock(&dev_priv->rps.hw_lock);
1368 }
1369
1370 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
1371                                         struct i915_power_well *power_well)
1372 {
1373         WARN_ON_ONCE(power_well->data != PIPE_A);
1374
1375         chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
1376 }
1377
1378 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
1379                                        struct i915_power_well *power_well)
1380 {
1381         WARN_ON_ONCE(power_well->data != PIPE_A);
1382
1383         chv_set_pipe_power_well(dev_priv, power_well, true);
1384
1385         vlv_display_power_well_init(dev_priv);
1386 }
1387
1388 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
1389                                         struct i915_power_well *power_well)
1390 {
1391         WARN_ON_ONCE(power_well->data != PIPE_A);
1392
1393         vlv_display_power_well_deinit(dev_priv);
1394
1395         chv_set_pipe_power_well(dev_priv, power_well, false);
1396 }
1397
1398 /**
1399  * intel_display_power_get - grab a power domain reference
1400  * @dev_priv: i915 device instance
1401  * @domain: power domain to reference
1402  *
1403  * This function grabs a power domain reference for @domain and ensures that the
1404  * power domain and all its parents are powered up. Therefore users should only
1405  * grab a reference to the innermost power domain they need.
1406  *
1407  * Any power domain reference obtained by this function must have a symmetric
1408  * call to intel_display_power_put() to release the reference again.
1409  */
1410 void intel_display_power_get(struct drm_i915_private *dev_priv,
1411                              enum intel_display_power_domain domain)
1412 {
1413         struct i915_power_domains *power_domains;
1414         struct i915_power_well *power_well;
1415         int i;
1416
1417         intel_runtime_pm_get(dev_priv);
1418
1419         power_domains = &dev_priv->power_domains;
1420
1421         mutex_lock(&power_domains->lock);
1422
1423         for_each_power_well(i, power_well, BIT(domain), power_domains) {
1424                 if (!power_well->count++)
1425                         intel_power_well_enable(dev_priv, power_well);
1426         }
1427
1428         power_domains->domain_use_count[domain]++;
1429
1430         mutex_unlock(&power_domains->lock);
1431 }
1432
1433 /**
1434  * intel_display_power_put - release a power domain reference
1435  * @dev_priv: i915 device instance
1436  * @domain: power domain to reference
1437  *
1438  * This function drops the power domain reference obtained by
1439  * intel_display_power_get() and might power down the corresponding hardware
1440  * block right away if this is the last reference.
1441  */
1442 void intel_display_power_put(struct drm_i915_private *dev_priv,
1443                              enum intel_display_power_domain domain)
1444 {
1445         struct i915_power_domains *power_domains;
1446         struct i915_power_well *power_well;
1447         int i;
1448
1449         power_domains = &dev_priv->power_domains;
1450
1451         mutex_lock(&power_domains->lock);
1452
1453         WARN_ON(!power_domains->domain_use_count[domain]);
1454         power_domains->domain_use_count[domain]--;
1455
1456         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
1457                 WARN_ON(!power_well->count);
1458
1459                 if (!--power_well->count && i915.disable_power_well)
1460                         intel_power_well_disable(dev_priv, power_well);
1461         }
1462
1463         mutex_unlock(&power_domains->lock);
1464
1465         intel_runtime_pm_put(dev_priv);
1466 }
1467
1468 #define HSW_ALWAYS_ON_POWER_DOMAINS (                   \
1469         BIT(POWER_DOMAIN_PIPE_A) |                      \
1470         BIT(POWER_DOMAIN_TRANSCODER_EDP) |              \
1471         BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |          \
1472         BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |          \
1473         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |          \
1474         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |          \
1475         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |          \
1476         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |          \
1477         BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |          \
1478         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |          \
1479         BIT(POWER_DOMAIN_PORT_CRT) |                    \
1480         BIT(POWER_DOMAIN_PLLS) |                        \
1481         BIT(POWER_DOMAIN_AUX_A) |                       \
1482         BIT(POWER_DOMAIN_AUX_B) |                       \
1483         BIT(POWER_DOMAIN_AUX_C) |                       \
1484         BIT(POWER_DOMAIN_AUX_D) |                       \
1485         BIT(POWER_DOMAIN_INIT))
1486 #define HSW_DISPLAY_POWER_DOMAINS (                             \
1487         (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) |    \
1488         BIT(POWER_DOMAIN_INIT))
1489
1490 #define BDW_ALWAYS_ON_POWER_DOMAINS (                   \
1491         HSW_ALWAYS_ON_POWER_DOMAINS |                   \
1492         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
1493 #define BDW_DISPLAY_POWER_DOMAINS (                             \
1494         (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) |    \
1495         BIT(POWER_DOMAIN_INIT))
1496
1497 #define VLV_ALWAYS_ON_POWER_DOMAINS     BIT(POWER_DOMAIN_INIT)
1498 #define VLV_DISPLAY_POWER_DOMAINS       POWER_DOMAIN_MASK
1499
1500 #define VLV_DPIO_CMN_BC_POWER_DOMAINS (         \
1501         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |  \
1502         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
1503         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |  \
1504         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
1505         BIT(POWER_DOMAIN_PORT_CRT) |            \
1506         BIT(POWER_DOMAIN_AUX_B) |               \
1507         BIT(POWER_DOMAIN_AUX_C) |               \
1508         BIT(POWER_DOMAIN_INIT))
1509
1510 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS (  \
1511         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |  \
1512         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
1513         BIT(POWER_DOMAIN_AUX_B) |               \
1514         BIT(POWER_DOMAIN_INIT))
1515
1516 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS (  \
1517         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
1518         BIT(POWER_DOMAIN_AUX_B) |               \
1519         BIT(POWER_DOMAIN_INIT))
1520
1521 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS (  \
1522         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |  \
1523         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
1524         BIT(POWER_DOMAIN_AUX_C) |               \
1525         BIT(POWER_DOMAIN_INIT))
1526
1527 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS (  \
1528         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
1529         BIT(POWER_DOMAIN_AUX_C) |               \
1530         BIT(POWER_DOMAIN_INIT))
1531
1532 #define CHV_DPIO_CMN_BC_POWER_DOMAINS (         \
1533         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |  \
1534         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
1535         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |  \
1536         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
1537         BIT(POWER_DOMAIN_AUX_B) |               \
1538         BIT(POWER_DOMAIN_AUX_C) |               \
1539         BIT(POWER_DOMAIN_INIT))
1540
1541 #define CHV_DPIO_CMN_D_POWER_DOMAINS (          \
1542         BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |  \
1543         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |  \
1544         BIT(POWER_DOMAIN_AUX_D) |               \
1545         BIT(POWER_DOMAIN_INIT))
1546
1547 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
1548         .sync_hw = i9xx_always_on_power_well_noop,
1549         .enable = i9xx_always_on_power_well_noop,
1550         .disable = i9xx_always_on_power_well_noop,
1551         .is_enabled = i9xx_always_on_power_well_enabled,
1552 };
1553
1554 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
1555         .sync_hw = chv_pipe_power_well_sync_hw,
1556         .enable = chv_pipe_power_well_enable,
1557         .disable = chv_pipe_power_well_disable,
1558         .is_enabled = chv_pipe_power_well_enabled,
1559 };
1560
1561 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
1562         .sync_hw = vlv_power_well_sync_hw,
1563         .enable = chv_dpio_cmn_power_well_enable,
1564         .disable = chv_dpio_cmn_power_well_disable,
1565         .is_enabled = vlv_power_well_enabled,
1566 };
1567
1568 static struct i915_power_well i9xx_always_on_power_well[] = {
1569         {
1570                 .name = "always-on",
1571                 .always_on = 1,
1572                 .domains = POWER_DOMAIN_MASK,
1573                 .ops = &i9xx_always_on_power_well_ops,
1574         },
1575 };
1576
1577 static const struct i915_power_well_ops hsw_power_well_ops = {
1578         .sync_hw = hsw_power_well_sync_hw,
1579         .enable = hsw_power_well_enable,
1580         .disable = hsw_power_well_disable,
1581         .is_enabled = hsw_power_well_enabled,
1582 };
1583
1584 static const struct i915_power_well_ops skl_power_well_ops = {
1585         .sync_hw = skl_power_well_sync_hw,
1586         .enable = skl_power_well_enable,
1587         .disable = skl_power_well_disable,
1588         .is_enabled = skl_power_well_enabled,
1589 };
1590
1591 static struct i915_power_well hsw_power_wells[] = {
1592         {
1593                 .name = "always-on",
1594                 .always_on = 1,
1595                 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
1596                 .ops = &i9xx_always_on_power_well_ops,
1597         },
1598         {
1599                 .name = "display",
1600                 .domains = HSW_DISPLAY_POWER_DOMAINS,
1601                 .ops = &hsw_power_well_ops,
1602         },
1603 };
1604
1605 static struct i915_power_well bdw_power_wells[] = {
1606         {
1607                 .name = "always-on",
1608                 .always_on = 1,
1609                 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
1610                 .ops = &i9xx_always_on_power_well_ops,
1611         },
1612         {
1613                 .name = "display",
1614                 .domains = BDW_DISPLAY_POWER_DOMAINS,
1615                 .ops = &hsw_power_well_ops,
1616         },
1617 };
1618
1619 static const struct i915_power_well_ops vlv_display_power_well_ops = {
1620         .sync_hw = vlv_power_well_sync_hw,
1621         .enable = vlv_display_power_well_enable,
1622         .disable = vlv_display_power_well_disable,
1623         .is_enabled = vlv_power_well_enabled,
1624 };
1625
1626 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
1627         .sync_hw = vlv_power_well_sync_hw,
1628         .enable = vlv_dpio_cmn_power_well_enable,
1629         .disable = vlv_dpio_cmn_power_well_disable,
1630         .is_enabled = vlv_power_well_enabled,
1631 };
1632
1633 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
1634         .sync_hw = vlv_power_well_sync_hw,
1635         .enable = vlv_power_well_enable,
1636         .disable = vlv_power_well_disable,
1637         .is_enabled = vlv_power_well_enabled,
1638 };
1639
1640 static struct i915_power_well vlv_power_wells[] = {
1641         {
1642                 .name = "always-on",
1643                 .always_on = 1,
1644                 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1645                 .ops = &i9xx_always_on_power_well_ops,
1646         },
1647         {
1648                 .name = "display",
1649                 .domains = VLV_DISPLAY_POWER_DOMAINS,
1650                 .data = PUNIT_POWER_WELL_DISP2D,
1651                 .ops = &vlv_display_power_well_ops,
1652         },
1653         {
1654                 .name = "dpio-tx-b-01",
1655                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1656                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1657                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1658                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1659                 .ops = &vlv_dpio_power_well_ops,
1660                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
1661         },
1662         {
1663                 .name = "dpio-tx-b-23",
1664                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1665                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1666                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1667                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1668                 .ops = &vlv_dpio_power_well_ops,
1669                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
1670         },
1671         {
1672                 .name = "dpio-tx-c-01",
1673                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1674                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1675                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1676                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1677                 .ops = &vlv_dpio_power_well_ops,
1678                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
1679         },
1680         {
1681                 .name = "dpio-tx-c-23",
1682                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1683                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1684                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1685                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1686                 .ops = &vlv_dpio_power_well_ops,
1687                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
1688         },
1689         {
1690                 .name = "dpio-common",
1691                 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
1692                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1693                 .ops = &vlv_dpio_cmn_power_well_ops,
1694         },
1695 };
1696
1697 static struct i915_power_well chv_power_wells[] = {
1698         {
1699                 .name = "always-on",
1700                 .always_on = 1,
1701                 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1702                 .ops = &i9xx_always_on_power_well_ops,
1703         },
1704         {
1705                 .name = "display",
1706                 /*
1707                  * Pipe A power well is the new disp2d well. Pipe B and C
1708                  * power wells don't actually exist. Pipe A power well is
1709                  * required for any pipe to work.
1710                  */
1711                 .domains = VLV_DISPLAY_POWER_DOMAINS,
1712                 .data = PIPE_A,
1713                 .ops = &chv_pipe_power_well_ops,
1714         },
1715         {
1716                 .name = "dpio-common-bc",
1717                 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
1718                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1719                 .ops = &chv_dpio_cmn_power_well_ops,
1720         },
1721         {
1722                 .name = "dpio-common-d",
1723                 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
1724                 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
1725                 .ops = &chv_dpio_cmn_power_well_ops,
1726         },
1727 };
1728
1729 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
1730                                     int power_well_id)
1731 {
1732         struct i915_power_well *power_well;
1733         bool ret;
1734
1735         power_well = lookup_power_well(dev_priv, power_well_id);
1736         ret = power_well->ops->is_enabled(dev_priv, power_well);
1737
1738         return ret;
1739 }
1740
1741 static struct i915_power_well skl_power_wells[] = {
1742         {
1743                 .name = "always-on",
1744                 .always_on = 1,
1745                 .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1746                 .ops = &i9xx_always_on_power_well_ops,
1747         },
1748         {
1749                 .name = "power well 1",
1750                 .domains = SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS,
1751                 .ops = &skl_power_well_ops,
1752                 .data = SKL_DISP_PW_1,
1753         },
1754         {
1755                 .name = "MISC IO power well",
1756                 .domains = SKL_DISPLAY_MISC_IO_POWER_DOMAINS,
1757                 .ops = &skl_power_well_ops,
1758                 .data = SKL_DISP_PW_MISC_IO,
1759         },
1760         {
1761                 .name = "power well 2",
1762                 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1763                 .ops = &skl_power_well_ops,
1764                 .data = SKL_DISP_PW_2,
1765         },
1766         {
1767                 .name = "DDI A/E power well",
1768                 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
1769                 .ops = &skl_power_well_ops,
1770                 .data = SKL_DISP_PW_DDI_A_E,
1771         },
1772         {
1773                 .name = "DDI B power well",
1774                 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS,
1775                 .ops = &skl_power_well_ops,
1776                 .data = SKL_DISP_PW_DDI_B,
1777         },
1778         {
1779                 .name = "DDI C power well",
1780                 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS,
1781                 .ops = &skl_power_well_ops,
1782                 .data = SKL_DISP_PW_DDI_C,
1783         },
1784         {
1785                 .name = "DDI D power well",
1786                 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS,
1787                 .ops = &skl_power_well_ops,
1788                 .data = SKL_DISP_PW_DDI_D,
1789         },
1790 };
1791
1792 static struct i915_power_well bxt_power_wells[] = {
1793         {
1794                 .name = "always-on",
1795                 .always_on = 1,
1796                 .domains = BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1797                 .ops = &i9xx_always_on_power_well_ops,
1798         },
1799         {
1800                 .name = "power well 1",
1801                 .domains = BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS,
1802                 .ops = &skl_power_well_ops,
1803                 .data = SKL_DISP_PW_1,
1804         },
1805         {
1806                 .name = "power well 2",
1807                 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1808                 .ops = &skl_power_well_ops,
1809                 .data = SKL_DISP_PW_2,
1810         }
1811 };
1812
1813 #define set_power_wells(power_domains, __power_wells) ({                \
1814         (power_domains)->power_wells = (__power_wells);                 \
1815         (power_domains)->power_well_count = ARRAY_SIZE(__power_wells);  \
1816 })
1817
1818 /**
1819  * intel_power_domains_init - initializes the power domain structures
1820  * @dev_priv: i915 device instance
1821  *
1822  * Initializes the power domain structures for @dev_priv depending upon the
1823  * supported platform.
1824  */
1825 int intel_power_domains_init(struct drm_i915_private *dev_priv)
1826 {
1827         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1828
1829         mutex_init(&power_domains->lock);
1830
1831         /*
1832          * The enabling order will be from lower to higher indexed wells,
1833          * the disabling order is reversed.
1834          */
1835         if (IS_HASWELL(dev_priv->dev)) {
1836                 set_power_wells(power_domains, hsw_power_wells);
1837         } else if (IS_BROADWELL(dev_priv->dev)) {
1838                 set_power_wells(power_domains, bdw_power_wells);
1839         } else if (IS_SKYLAKE(dev_priv->dev)) {
1840                 set_power_wells(power_domains, skl_power_wells);
1841         } else if (IS_BROXTON(dev_priv->dev)) {
1842                 set_power_wells(power_domains, bxt_power_wells);
1843         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1844                 set_power_wells(power_domains, chv_power_wells);
1845         } else if (IS_VALLEYVIEW(dev_priv->dev)) {
1846                 set_power_wells(power_domains, vlv_power_wells);
1847         } else {
1848                 set_power_wells(power_domains, i9xx_always_on_power_well);
1849         }
1850
1851         return 0;
1852 }
1853
1854 static void intel_runtime_pm_disable(struct drm_i915_private *dev_priv)
1855 {
1856         struct drm_device *dev = dev_priv->dev;
1857         struct device *device = &dev->pdev->dev;
1858
1859         if (!HAS_RUNTIME_PM(dev))
1860                 return;
1861
1862         if (!intel_enable_rc6(dev))
1863                 return;
1864
1865         /* Make sure we're not suspended first. */
1866         pm_runtime_get_sync(device);
1867 }
1868
1869 /**
1870  * intel_power_domains_fini - finalizes the power domain structures
1871  * @dev_priv: i915 device instance
1872  *
1873  * Finalizes the power domain structures for @dev_priv depending upon the
1874  * supported platform. This function also disables runtime pm and ensures that
1875  * the device stays powered up so that the driver can be reloaded.
1876  */
1877 void intel_power_domains_fini(struct drm_i915_private *dev_priv)
1878 {
1879         intel_runtime_pm_disable(dev_priv);
1880
1881         /* The i915.ko module is still not prepared to be loaded when
1882          * the power well is not enabled, so just enable it in case
1883          * we're going to unload/reload. */
1884         intel_display_set_init_power(dev_priv, true);
1885 }
1886
1887 static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
1888 {
1889         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1890         struct i915_power_well *power_well;
1891         int i;
1892
1893         mutex_lock(&power_domains->lock);
1894         for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
1895                 power_well->ops->sync_hw(dev_priv, power_well);
1896                 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
1897                                                                      power_well);
1898         }
1899         mutex_unlock(&power_domains->lock);
1900 }
1901
1902 static void chv_phy_control_init(struct drm_i915_private *dev_priv)
1903 {
1904         struct i915_power_well *cmn_bc =
1905                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1906         struct i915_power_well *cmn_d =
1907                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
1908
1909         /*
1910          * DISPLAY_PHY_CONTROL can get corrupted if read. As a
1911          * workaround never ever read DISPLAY_PHY_CONTROL, and
1912          * instead maintain a shadow copy ourselves. Use the actual
1913          * power well state and lane status to reconstruct the
1914          * expected initial value.
1915          */
1916         dev_priv->chv_phy_control =
1917                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
1918                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
1919                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
1920                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) |
1921                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0);
1922
1923         /*
1924          * If all lanes are disabled we leave the override disabled
1925          * with all power down bits cleared to match the state we
1926          * would use after disabling the port. Otherwise enable the
1927          * override and set the lane powerdown bits accding to the
1928          * current lane status.
1929          */
1930         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
1931                 uint32_t status = I915_READ(DPLL(PIPE_A));
1932                 unsigned int mask;
1933
1934                 mask = status & DPLL_PORTB_READY_MASK;
1935                 if (mask == 0xf)
1936                         mask = 0x0;
1937                 else
1938                         dev_priv->chv_phy_control |=
1939                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
1940
1941                 dev_priv->chv_phy_control |=
1942                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
1943
1944                 mask = (status & DPLL_PORTC_READY_MASK) >> 4;
1945                 if (mask == 0xf)
1946                         mask = 0x0;
1947                 else
1948                         dev_priv->chv_phy_control |=
1949                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
1950
1951                 dev_priv->chv_phy_control |=
1952                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
1953
1954                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
1955
1956                 dev_priv->chv_phy_assert[DPIO_PHY0] = false;
1957         } else {
1958                 dev_priv->chv_phy_assert[DPIO_PHY0] = true;
1959         }
1960
1961         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
1962                 uint32_t status = I915_READ(DPIO_PHY_STATUS);
1963                 unsigned int mask;
1964
1965                 mask = status & DPLL_PORTD_READY_MASK;
1966
1967                 if (mask == 0xf)
1968                         mask = 0x0;
1969                 else
1970                         dev_priv->chv_phy_control |=
1971                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
1972
1973                 dev_priv->chv_phy_control |=
1974                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
1975
1976                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
1977
1978                 dev_priv->chv_phy_assert[DPIO_PHY1] = false;
1979         } else {
1980                 dev_priv->chv_phy_assert[DPIO_PHY1] = true;
1981         }
1982
1983         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1984
1985         DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n",
1986                       dev_priv->chv_phy_control);
1987 }
1988
1989 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
1990 {
1991         struct i915_power_well *cmn =
1992                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1993         struct i915_power_well *disp2d =
1994                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
1995
1996         /* If the display might be already active skip this */
1997         if (cmn->ops->is_enabled(dev_priv, cmn) &&
1998             disp2d->ops->is_enabled(dev_priv, disp2d) &&
1999             I915_READ(DPIO_CTL) & DPIO_CMNRST)
2000                 return;
2001
2002         DRM_DEBUG_KMS("toggling display PHY side reset\n");
2003
2004         /* cmnlane needs DPLL registers */
2005         disp2d->ops->enable(dev_priv, disp2d);
2006
2007         /*
2008          * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
2009          * Need to assert and de-assert PHY SB reset by gating the
2010          * common lane power, then un-gating it.
2011          * Simply ungating isn't enough to reset the PHY enough to get
2012          * ports and lanes running.
2013          */
2014         cmn->ops->disable(dev_priv, cmn);
2015 }
2016
2017 /**
2018  * intel_power_domains_init_hw - initialize hardware power domain state
2019  * @dev_priv: i915 device instance
2020  *
2021  * This function initializes the hardware power domain state and enables all
2022  * power domains using intel_display_set_init_power().
2023  */
2024 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
2025 {
2026         struct drm_device *dev = dev_priv->dev;
2027         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2028
2029         power_domains->initializing = true;
2030
2031         if (IS_CHERRYVIEW(dev)) {
2032                 mutex_lock(&power_domains->lock);
2033                 chv_phy_control_init(dev_priv);
2034                 mutex_unlock(&power_domains->lock);
2035         } else if (IS_VALLEYVIEW(dev)) {
2036                 mutex_lock(&power_domains->lock);
2037                 vlv_cmnlane_wa(dev_priv);
2038                 mutex_unlock(&power_domains->lock);
2039         }
2040
2041         /* For now, we need the power well to be always enabled. */
2042         intel_display_set_init_power(dev_priv, true);
2043         intel_power_domains_resume(dev_priv);
2044         power_domains->initializing = false;
2045 }
2046
2047 /**
2048  * intel_aux_display_runtime_get - grab an auxiliary power domain reference
2049  * @dev_priv: i915 device instance
2050  *
2051  * This function grabs a power domain reference for the auxiliary power domain
2052  * (for access to the GMBUS and DP AUX blocks) and ensures that it and all its
2053  * parents are powered up. Therefore users should only grab a reference to the
2054  * innermost power domain they need.
2055  *
2056  * Any power domain reference obtained by this function must have a symmetric
2057  * call to intel_aux_display_runtime_put() to release the reference again.
2058  */
2059 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
2060 {
2061         intel_runtime_pm_get(dev_priv);
2062 }
2063
2064 /**
2065  * intel_aux_display_runtime_put - release an auxiliary power domain reference
2066  * @dev_priv: i915 device instance
2067  *
2068  * This function drops the auxiliary power domain reference obtained by
2069  * intel_aux_display_runtime_get() and might power down the corresponding
2070  * hardware block right away if this is the last reference.
2071  */
2072 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
2073 {
2074         intel_runtime_pm_put(dev_priv);
2075 }
2076
2077 /**
2078  * intel_runtime_pm_get - grab a runtime pm reference
2079  * @dev_priv: i915 device instance
2080  *
2081  * This function grabs a device-level runtime pm reference (mostly used for GEM
2082  * code to ensure the GTT or GT is on) and ensures that it is powered up.
2083  *
2084  * Any runtime pm reference obtained by this function must have a symmetric
2085  * call to intel_runtime_pm_put() to release the reference again.
2086  */
2087 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
2088 {
2089         struct drm_device *dev = dev_priv->dev;
2090         struct device *device = &dev->pdev->dev;
2091
2092         if (!HAS_RUNTIME_PM(dev))
2093                 return;
2094
2095         pm_runtime_get_sync(device);
2096         WARN(dev_priv->pm.suspended, "Device still suspended.\n");
2097 }
2098
2099 /**
2100  * intel_runtime_pm_get_noresume - grab a runtime pm reference
2101  * @dev_priv: i915 device instance
2102  *
2103  * This function grabs a device-level runtime pm reference (mostly used for GEM
2104  * code to ensure the GTT or GT is on).
2105  *
2106  * It will _not_ power up the device but instead only check that it's powered
2107  * on.  Therefore it is only valid to call this functions from contexts where
2108  * the device is known to be powered up and where trying to power it up would
2109  * result in hilarity and deadlocks. That pretty much means only the system
2110  * suspend/resume code where this is used to grab runtime pm references for
2111  * delayed setup down in work items.
2112  *
2113  * Any runtime pm reference obtained by this function must have a symmetric
2114  * call to intel_runtime_pm_put() to release the reference again.
2115  */
2116 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
2117 {
2118         struct drm_device *dev = dev_priv->dev;
2119         struct device *device = &dev->pdev->dev;
2120
2121         if (!HAS_RUNTIME_PM(dev))
2122                 return;
2123
2124         WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
2125         pm_runtime_get_noresume(device);
2126 }
2127
2128 /**
2129  * intel_runtime_pm_put - release a runtime pm reference
2130  * @dev_priv: i915 device instance
2131  *
2132  * This function drops the device-level runtime pm reference obtained by
2133  * intel_runtime_pm_get() and might power down the corresponding
2134  * hardware block right away if this is the last reference.
2135  */
2136 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
2137 {
2138         struct drm_device *dev = dev_priv->dev;
2139         struct device *device = &dev->pdev->dev;
2140
2141         if (!HAS_RUNTIME_PM(dev))
2142                 return;
2143
2144         pm_runtime_mark_last_busy(device);
2145         pm_runtime_put_autosuspend(device);
2146 }
2147
2148 /**
2149  * intel_runtime_pm_enable - enable runtime pm
2150  * @dev_priv: i915 device instance
2151  *
2152  * This function enables runtime pm at the end of the driver load sequence.
2153  *
2154  * Note that this function does currently not enable runtime pm for the
2155  * subordinate display power domains. That is only done on the first modeset
2156  * using intel_display_set_init_power().
2157  */
2158 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
2159 {
2160         struct drm_device *dev = dev_priv->dev;
2161         struct device *device = &dev->pdev->dev;
2162
2163         if (!HAS_RUNTIME_PM(dev))
2164                 return;
2165
2166         /*
2167          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
2168          * requirement.
2169          */
2170         if (!intel_enable_rc6(dev)) {
2171                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
2172                 return;
2173         }
2174
2175         pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
2176         pm_runtime_mark_last_busy(device);
2177         pm_runtime_use_autosuspend(device);
2178
2179         pm_runtime_put_autosuspend(device);
2180 }
2181