1 #ifndef _INTEL_RINGBUFFER_H_
2 #define _INTEL_RINGBUFFER_H_
5 * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
6 * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
7 * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
9 * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
10 * cacheline, the Head Pointer must not be greater than the Tail
13 #define I915_RING_FREE_SPACE 64
15 struct intel_hw_status_page {
17 unsigned int gfx_addr;
18 struct drm_i915_gem_object *obj;
21 #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
22 #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
24 #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
25 #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
27 #define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base))
28 #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
30 #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
31 #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
33 #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
34 #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
36 enum intel_ring_hangcheck_action {
44 #define HANGCHECK_SCORE_RING_HUNG 31
46 struct intel_ring_hangcheck {
51 enum intel_ring_hangcheck_action action;
54 struct intel_ring_buffer {
62 #define I915_NUM_RINGS 4
64 void __iomem *virtual_start;
65 struct drm_device *dev;
66 struct drm_i915_gem_object *obj;
73 struct intel_hw_status_page status_page;
75 /** We track the position of the requests in the ring buffer, and
76 * when each is retired we increment last_retired_head as the GPU
77 * must have finished processing the request and so we know we
78 * can advance the ringbuffer up to that position.
80 * last_retired_head is set to -1 after the value is consumed so
81 * we can detect new retirements.
83 u32 last_retired_head;
85 unsigned irq_refcount; /* protected by dev_priv->irq_lock */
86 u32 irq_enable_mask; /* bitmask to enable ring interrupt */
88 u32 sync_seqno[I915_NUM_RINGS-1];
89 bool __must_check (*irq_get)(struct intel_ring_buffer *ring);
90 void (*irq_put)(struct intel_ring_buffer *ring);
92 int (*init)(struct intel_ring_buffer *ring);
94 void (*write_tail)(struct intel_ring_buffer *ring,
96 int __must_check (*flush)(struct intel_ring_buffer *ring,
97 u32 invalidate_domains,
99 int (*add_request)(struct intel_ring_buffer *ring);
100 /* Some chipsets are not quite as coherent as advertised and need
101 * an expensive kick to force a true read of the up-to-date seqno.
102 * However, the up-to-date seqno is not always required and the last
103 * seen value is good enough. Note that the seqno will always be
104 * monotonic, even if not coherent.
106 u32 (*get_seqno)(struct intel_ring_buffer *ring,
107 bool lazy_coherency);
108 void (*set_seqno)(struct intel_ring_buffer *ring,
110 int (*dispatch_execbuffer)(struct intel_ring_buffer *ring,
111 u32 offset, u32 length,
113 #define I915_DISPATCH_SECURE 0x1
114 #define I915_DISPATCH_PINNED 0x2
115 void (*cleanup)(struct intel_ring_buffer *ring);
116 int (*sync_to)(struct intel_ring_buffer *ring,
117 struct intel_ring_buffer *to,
120 /* our mbox written by others */
121 u32 semaphore_register[I915_NUM_RINGS];
122 /* mboxes this ring signals to */
123 u32 signal_mbox[I915_NUM_RINGS];
126 * List of objects currently involved in rendering from the
129 * Includes buffers having the contents of their GPU caches
130 * flushed, not necessarily primitives. last_rendering_seqno
131 * represents when the rendering involved will be completed.
133 * A reference is held on the buffer while on this list.
135 struct list_head active_list;
138 * List of breadcrumbs associated with GPU requests currently
141 struct list_head request_list;
144 * Do we have some not yet emitted requests outstanding?
146 struct drm_i915_gem_request *preallocated_lazy_request;
147 u32 outstanding_lazy_seqno;
148 bool gpu_caches_dirty;
151 wait_queue_head_t irq_queue;
154 * Do an explicit TLB flush before MI_SET_CONTEXT
156 bool itlb_before_ctx_switch;
157 struct i915_hw_context *default_context;
158 struct i915_hw_context *last_context;
160 struct intel_ring_hangcheck hangcheck;
163 struct drm_i915_gem_object *obj;
165 volatile u32 *cpu_page;
169 * Tables of commands the command parser needs to know about
172 const struct drm_i915_cmd_table *cmd_tables;
176 * Table of registers allowed in commands that read/write registers.
178 const u32 *reg_table;
182 * Table of registers allowed in commands that read/write registers, but
183 * only from the DRM master.
185 const u32 *master_reg_table;
186 int master_reg_count;
189 * Returns the bitmask for the length field of the specified command.
190 * Return 0 for an unrecognized/invalid command.
192 * If the command parser finds an entry for a command in the ring's
193 * cmd_tables, it gets the command's length based on the table entry.
194 * If not, it calls this function to determine the per-ring length field
195 * encoding for the command (i.e. certain opcode ranges use certain bits
196 * to encode the command length in the header).
198 u32 (*get_cmd_length_mask)(u32 cmd_header);
202 intel_ring_initialized(struct intel_ring_buffer *ring)
204 return ring->obj != NULL;
207 static inline unsigned
208 intel_ring_flag(struct intel_ring_buffer *ring)
210 return 1 << ring->id;
214 intel_ring_sync_index(struct intel_ring_buffer *ring,
215 struct intel_ring_buffer *other)
220 * cs -> 0 = vcs, 1 = bcs
221 * vcs -> 0 = bcs, 1 = cs,
222 * bcs -> 0 = cs, 1 = vcs.
225 idx = (other - ring) - 1;
227 idx += I915_NUM_RINGS;
233 intel_read_status_page(struct intel_ring_buffer *ring,
236 /* Ensure that the compiler doesn't optimize away the load. */
238 return ring->status_page.page_addr[reg];
242 intel_write_status_page(struct intel_ring_buffer *ring,
245 ring->status_page.page_addr[reg] = value;
249 * Reads a dword out of the status page, which is written to from the command
250 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
253 * The following dwords have a reserved meaning:
254 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
255 * 0x04: ring 0 head pointer
256 * 0x05: ring 1 head pointer (915-class)
257 * 0x06: ring 2 head pointer (915-class)
258 * 0x10-0x1b: Context status DWords (GM45)
259 * 0x1f: Last written status offset. (GM45)
261 * The area from dword 0x20 to 0x3ff is available for driver usage.
263 #define I915_GEM_HWS_INDEX 0x20
264 #define I915_GEM_HWS_SCRATCH_INDEX 0x30
265 #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
267 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
269 int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n);
270 static inline void intel_ring_emit(struct intel_ring_buffer *ring,
273 iowrite32(data, ring->virtual_start + ring->tail);
276 static inline void intel_ring_advance(struct intel_ring_buffer *ring)
278 ring->tail &= ring->size - 1;
280 void __intel_ring_advance(struct intel_ring_buffer *ring);
282 int __must_check intel_ring_idle(struct intel_ring_buffer *ring);
283 void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno);
284 int intel_ring_flush_all_caches(struct intel_ring_buffer *ring);
285 int intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring);
287 int intel_init_render_ring_buffer(struct drm_device *dev);
288 int intel_init_bsd_ring_buffer(struct drm_device *dev);
289 int intel_init_blt_ring_buffer(struct drm_device *dev);
290 int intel_init_vebox_ring_buffer(struct drm_device *dev);
292 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring);
293 void intel_ring_setup_status_page(struct intel_ring_buffer *ring);
295 static inline u32 intel_ring_get_tail(struct intel_ring_buffer *ring)
300 static inline u32 intel_ring_get_seqno(struct intel_ring_buffer *ring)
302 BUG_ON(ring->outstanding_lazy_seqno == 0);
303 return ring->outstanding_lazy_seqno;
306 static inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno)
308 if (ring->trace_irq_seqno == 0 && ring->irq_get(ring))
309 ring->trace_irq_seqno = seqno;
313 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size);
315 #endif /* _INTEL_RINGBUFFER_H_ */