2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
37 intel_ring_initialized(struct intel_engine_cs *ring)
39 struct drm_device *dev = ring->dev;
44 if (i915.enable_execlists) {
45 struct intel_context *dctx = ring->default_context;
46 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
50 return ring->buffer && ring->buffer->obj;
53 int __intel_ring_space(int head, int tail, int size)
55 int space = head - tail;
58 return space - I915_RING_FREE_SPACE;
61 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
63 if (ringbuf->last_retired_head != -1) {
64 ringbuf->head = ringbuf->last_retired_head;
65 ringbuf->last_retired_head = -1;
68 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
69 ringbuf->tail, ringbuf->size);
72 int intel_ring_space(struct intel_ringbuffer *ringbuf)
74 intel_ring_update_space(ringbuf);
75 return ringbuf->space;
78 bool intel_ring_stopped(struct intel_engine_cs *ring)
80 struct drm_i915_private *dev_priv = ring->dev->dev_private;
81 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
84 static void __intel_ring_advance(struct intel_engine_cs *ring)
86 struct intel_ringbuffer *ringbuf = ring->buffer;
87 ringbuf->tail &= ringbuf->size - 1;
88 if (intel_ring_stopped(ring))
90 ring->write_tail(ring, ringbuf->tail);
94 gen2_render_ring_flush(struct drm_i915_gem_request *req,
95 u32 invalidate_domains,
98 struct intel_engine_cs *ring = req->ring;
103 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
104 cmd |= MI_NO_WRITE_FLUSH;
106 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
107 cmd |= MI_READ_FLUSH;
109 ret = intel_ring_begin(req, 2);
113 intel_ring_emit(ring, cmd);
114 intel_ring_emit(ring, MI_NOOP);
115 intel_ring_advance(ring);
121 gen4_render_ring_flush(struct drm_i915_gem_request *req,
122 u32 invalidate_domains,
125 struct intel_engine_cs *ring = req->ring;
126 struct drm_device *dev = ring->dev;
133 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
134 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
135 * also flushed at 2d versus 3d pipeline switches.
139 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
140 * MI_READ_FLUSH is set, and is always flushed on 965.
142 * I915_GEM_DOMAIN_COMMAND may not exist?
144 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
145 * invalidated when MI_EXE_FLUSH is set.
147 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
148 * invalidated with every MI_FLUSH.
152 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
153 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
154 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
155 * are flushed at any MI_FLUSH.
158 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
159 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
160 cmd &= ~MI_NO_WRITE_FLUSH;
161 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
164 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
165 (IS_G4X(dev) || IS_GEN5(dev)))
166 cmd |= MI_INVALIDATE_ISP;
168 ret = intel_ring_begin(req, 2);
172 intel_ring_emit(ring, cmd);
173 intel_ring_emit(ring, MI_NOOP);
174 intel_ring_advance(ring);
180 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
181 * implementing two workarounds on gen6. From section 1.4.7.1
182 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
184 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
185 * produced by non-pipelined state commands), software needs to first
186 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
189 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
190 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
192 * And the workaround for these two requires this workaround first:
194 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
195 * BEFORE the pipe-control with a post-sync op and no write-cache
198 * And this last workaround is tricky because of the requirements on
199 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
202 * "1 of the following must also be set:
203 * - Render Target Cache Flush Enable ([12] of DW1)
204 * - Depth Cache Flush Enable ([0] of DW1)
205 * - Stall at Pixel Scoreboard ([1] of DW1)
206 * - Depth Stall ([13] of DW1)
207 * - Post-Sync Operation ([13] of DW1)
208 * - Notify Enable ([8] of DW1)"
210 * The cache flushes require the workaround flush that triggered this
211 * one, so we can't use it. Depth stall would trigger the same.
212 * Post-sync nonzero is what triggered this second workaround, so we
213 * can't use that one either. Notify enable is IRQs, which aren't
214 * really our business. That leaves only stall at scoreboard.
217 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
219 struct intel_engine_cs *ring = req->ring;
220 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
223 ret = intel_ring_begin(req, 6);
227 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
228 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
229 PIPE_CONTROL_STALL_AT_SCOREBOARD);
230 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
231 intel_ring_emit(ring, 0); /* low dword */
232 intel_ring_emit(ring, 0); /* high dword */
233 intel_ring_emit(ring, MI_NOOP);
234 intel_ring_advance(ring);
236 ret = intel_ring_begin(req, 6);
240 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
241 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
242 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
243 intel_ring_emit(ring, 0);
244 intel_ring_emit(ring, 0);
245 intel_ring_emit(ring, MI_NOOP);
246 intel_ring_advance(ring);
252 gen6_render_ring_flush(struct drm_i915_gem_request *req,
253 u32 invalidate_domains, u32 flush_domains)
255 struct intel_engine_cs *ring = req->ring;
257 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
260 /* Force SNB workarounds for PIPE_CONTROL flushes */
261 ret = intel_emit_post_sync_nonzero_flush(req);
265 /* Just flush everything. Experiments have shown that reducing the
266 * number of bits based on the write domains has little performance
270 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
271 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
273 * Ensure that any following seqno writes only happen
274 * when the render cache is indeed flushed.
276 flags |= PIPE_CONTROL_CS_STALL;
278 if (invalidate_domains) {
279 flags |= PIPE_CONTROL_TLB_INVALIDATE;
280 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
281 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
282 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
283 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
284 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
286 * TLB invalidate requires a post-sync write.
288 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
291 ret = intel_ring_begin(req, 4);
295 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
296 intel_ring_emit(ring, flags);
297 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
298 intel_ring_emit(ring, 0);
299 intel_ring_advance(ring);
305 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
307 struct intel_engine_cs *ring = req->ring;
310 ret = intel_ring_begin(req, 4);
314 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
315 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
316 PIPE_CONTROL_STALL_AT_SCOREBOARD);
317 intel_ring_emit(ring, 0);
318 intel_ring_emit(ring, 0);
319 intel_ring_advance(ring);
325 gen7_render_ring_flush(struct drm_i915_gem_request *req,
326 u32 invalidate_domains, u32 flush_domains)
328 struct intel_engine_cs *ring = req->ring;
330 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
334 * Ensure that any following seqno writes only happen when the render
335 * cache is indeed flushed.
337 * Workaround: 4th PIPE_CONTROL command (except the ones with only
338 * read-cache invalidate bits set) must have the CS_STALL bit set. We
339 * don't try to be clever and just set it unconditionally.
341 flags |= PIPE_CONTROL_CS_STALL;
343 /* Just flush everything. Experiments have shown that reducing the
344 * number of bits based on the write domains has little performance
348 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
349 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
350 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
351 flags |= PIPE_CONTROL_FLUSH_ENABLE;
353 if (invalidate_domains) {
354 flags |= PIPE_CONTROL_TLB_INVALIDATE;
355 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
356 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
357 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
358 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
359 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
360 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
362 * TLB invalidate requires a post-sync write.
364 flags |= PIPE_CONTROL_QW_WRITE;
365 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
367 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
369 /* Workaround: we must issue a pipe_control with CS-stall bit
370 * set before a pipe_control command that has the state cache
371 * invalidate bit set. */
372 gen7_render_ring_cs_stall_wa(req);
375 ret = intel_ring_begin(req, 4);
379 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
380 intel_ring_emit(ring, flags);
381 intel_ring_emit(ring, scratch_addr);
382 intel_ring_emit(ring, 0);
383 intel_ring_advance(ring);
389 gen8_emit_pipe_control(struct drm_i915_gem_request *req,
390 u32 flags, u32 scratch_addr)
392 struct intel_engine_cs *ring = req->ring;
395 ret = intel_ring_begin(req, 6);
399 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
400 intel_ring_emit(ring, flags);
401 intel_ring_emit(ring, scratch_addr);
402 intel_ring_emit(ring, 0);
403 intel_ring_emit(ring, 0);
404 intel_ring_emit(ring, 0);
405 intel_ring_advance(ring);
411 gen8_render_ring_flush(struct drm_i915_gem_request *req,
412 u32 invalidate_domains, u32 flush_domains)
415 u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
418 flags |= PIPE_CONTROL_CS_STALL;
421 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
422 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
423 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
424 flags |= PIPE_CONTROL_FLUSH_ENABLE;
426 if (invalidate_domains) {
427 flags |= PIPE_CONTROL_TLB_INVALIDATE;
428 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
429 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
430 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
431 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
432 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
433 flags |= PIPE_CONTROL_QW_WRITE;
434 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
436 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
437 ret = gen8_emit_pipe_control(req,
438 PIPE_CONTROL_CS_STALL |
439 PIPE_CONTROL_STALL_AT_SCOREBOARD,
445 return gen8_emit_pipe_control(req, flags, scratch_addr);
448 static void ring_write_tail(struct intel_engine_cs *ring,
451 struct drm_i915_private *dev_priv = ring->dev->dev_private;
452 I915_WRITE_TAIL(ring, value);
455 u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
457 struct drm_i915_private *dev_priv = ring->dev->dev_private;
460 if (INTEL_INFO(ring->dev)->gen >= 8)
461 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
462 RING_ACTHD_UDW(ring->mmio_base));
463 else if (INTEL_INFO(ring->dev)->gen >= 4)
464 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
466 acthd = I915_READ(ACTHD);
471 static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
473 struct drm_i915_private *dev_priv = ring->dev->dev_private;
476 addr = dev_priv->status_page_dmah->busaddr;
477 if (INTEL_INFO(ring->dev)->gen >= 4)
478 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
479 I915_WRITE(HWS_PGA, addr);
482 static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
484 struct drm_device *dev = ring->dev;
485 struct drm_i915_private *dev_priv = ring->dev->dev_private;
488 /* The ring status page addresses are no longer next to the rest of
489 * the ring registers as of gen7.
494 mmio = RENDER_HWS_PGA_GEN7;
497 mmio = BLT_HWS_PGA_GEN7;
500 * VCS2 actually doesn't exist on Gen7. Only shut up
501 * gcc switch check warning
505 mmio = BSD_HWS_PGA_GEN7;
508 mmio = VEBOX_HWS_PGA_GEN7;
511 } else if (IS_GEN6(ring->dev)) {
512 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
514 /* XXX: gen8 returns to sanity */
515 mmio = RING_HWS_PGA(ring->mmio_base);
518 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
522 * Flush the TLB for this page
524 * FIXME: These two bits have disappeared on gen8, so a question
525 * arises: do we still need this and if so how should we go about
526 * invalidating the TLB?
528 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
529 u32 reg = RING_INSTPM(ring->mmio_base);
531 /* ring should be idle before issuing a sync flush*/
532 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
535 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
537 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
539 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
544 static bool stop_ring(struct intel_engine_cs *ring)
546 struct drm_i915_private *dev_priv = to_i915(ring->dev);
548 if (!IS_GEN2(ring->dev)) {
549 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
550 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
551 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
552 /* Sometimes we observe that the idle flag is not
553 * set even though the ring is empty. So double
554 * check before giving up.
556 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
561 I915_WRITE_CTL(ring, 0);
562 I915_WRITE_HEAD(ring, 0);
563 ring->write_tail(ring, 0);
565 if (!IS_GEN2(ring->dev)) {
566 (void)I915_READ_CTL(ring);
567 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
570 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
573 static int init_ring_common(struct intel_engine_cs *ring)
575 struct drm_device *dev = ring->dev;
576 struct drm_i915_private *dev_priv = dev->dev_private;
577 struct intel_ringbuffer *ringbuf = ring->buffer;
578 struct drm_i915_gem_object *obj = ringbuf->obj;
581 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
583 if (!stop_ring(ring)) {
584 /* G45 ring initialization often fails to reset head to zero */
585 DRM_DEBUG_KMS("%s head not reset to zero "
586 "ctl %08x head %08x tail %08x start %08x\n",
589 I915_READ_HEAD(ring),
590 I915_READ_TAIL(ring),
591 I915_READ_START(ring));
593 if (!stop_ring(ring)) {
594 DRM_ERROR("failed to set %s head to zero "
595 "ctl %08x head %08x tail %08x start %08x\n",
598 I915_READ_HEAD(ring),
599 I915_READ_TAIL(ring),
600 I915_READ_START(ring));
606 if (I915_NEED_GFX_HWS(dev))
607 intel_ring_setup_status_page(ring);
609 ring_setup_phys_status_page(ring);
611 /* Enforce ordering by reading HEAD register back */
612 I915_READ_HEAD(ring);
614 /* Initialize the ring. This must happen _after_ we've cleared the ring
615 * registers with the above sequence (the readback of the HEAD registers
616 * also enforces ordering), otherwise the hw might lose the new ring
617 * register values. */
618 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
620 /* WaClearRingBufHeadRegAtInit:ctg,elk */
621 if (I915_READ_HEAD(ring))
622 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
623 ring->name, I915_READ_HEAD(ring));
624 I915_WRITE_HEAD(ring, 0);
625 (void)I915_READ_HEAD(ring);
628 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
631 /* If the head is still not zero, the ring is dead */
632 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
633 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
634 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
635 DRM_ERROR("%s initialization failed "
636 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
638 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
639 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
640 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
645 ringbuf->last_retired_head = -1;
646 ringbuf->head = I915_READ_HEAD(ring);
647 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
648 intel_ring_update_space(ringbuf);
650 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
653 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
659 intel_fini_pipe_control(struct intel_engine_cs *ring)
661 struct drm_device *dev = ring->dev;
663 if (ring->scratch.obj == NULL)
666 if (INTEL_INFO(dev)->gen >= 5) {
667 kunmap(sg_page(ring->scratch.obj->pages->sgl));
668 i915_gem_object_ggtt_unpin(ring->scratch.obj);
671 drm_gem_object_unreference(&ring->scratch.obj->base);
672 ring->scratch.obj = NULL;
676 intel_init_pipe_control(struct intel_engine_cs *ring)
680 WARN_ON(ring->scratch.obj);
682 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
683 if (ring->scratch.obj == NULL) {
684 DRM_ERROR("Failed to allocate seqno page\n");
689 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
693 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
697 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
698 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
699 if (ring->scratch.cpu_page == NULL) {
704 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
705 ring->name, ring->scratch.gtt_offset);
709 i915_gem_object_ggtt_unpin(ring->scratch.obj);
711 drm_gem_object_unreference(&ring->scratch.obj->base);
716 static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
719 struct intel_engine_cs *ring = req->ring;
720 struct drm_device *dev = ring->dev;
721 struct drm_i915_private *dev_priv = dev->dev_private;
722 struct i915_workarounds *w = &dev_priv->workarounds;
727 ring->gpu_caches_dirty = true;
728 ret = intel_ring_flush_all_caches(req);
732 ret = intel_ring_begin(req, (w->count * 2 + 2));
736 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
737 for (i = 0; i < w->count; i++) {
738 intel_ring_emit(ring, w->reg[i].addr);
739 intel_ring_emit(ring, w->reg[i].value);
741 intel_ring_emit(ring, MI_NOOP);
743 intel_ring_advance(ring);
745 ring->gpu_caches_dirty = true;
746 ret = intel_ring_flush_all_caches(req);
750 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
755 static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
759 ret = intel_ring_workarounds_emit(req);
763 ret = i915_gem_render_state_init(req);
765 DRM_ERROR("init render state: %d\n", ret);
770 static int wa_add(struct drm_i915_private *dev_priv,
771 const u32 addr, const u32 mask, const u32 val)
773 const u32 idx = dev_priv->workarounds.count;
775 if (WARN_ON(idx >= I915_MAX_WA_REGS))
778 dev_priv->workarounds.reg[idx].addr = addr;
779 dev_priv->workarounds.reg[idx].value = val;
780 dev_priv->workarounds.reg[idx].mask = mask;
782 dev_priv->workarounds.count++;
787 #define WA_REG(addr, mask, val) do { \
788 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
793 #define WA_SET_BIT_MASKED(addr, mask) \
794 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
796 #define WA_CLR_BIT_MASKED(addr, mask) \
797 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
799 #define WA_SET_FIELD_MASKED(addr, mask, value) \
800 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
802 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
803 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
805 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
807 static int gen8_init_workarounds(struct intel_engine_cs *ring)
809 struct drm_device *dev = ring->dev;
810 struct drm_i915_private *dev_priv = dev->dev_private;
812 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
814 /* WaDisableAsyncFlipPerfMode:bdw,chv */
815 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
817 /* WaDisablePartialInstShootdown:bdw,chv */
818 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
819 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
821 /* Use Force Non-Coherent whenever executing a 3D context. This is a
822 * workaround for for a possible hang in the unlikely event a TLB
823 * invalidation occurs during a PSD flush.
825 /* WaForceEnableNonCoherent:bdw,chv */
826 /* WaHdcDisableFetchWhenMasked:bdw,chv */
827 WA_SET_BIT_MASKED(HDC_CHICKEN0,
828 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
829 HDC_FORCE_NON_COHERENT);
831 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
832 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
833 * polygons in the same 8x4 pixel/sample area to be processed without
834 * stalling waiting for the earlier ones to write to Hierarchical Z
837 * This optimization is off by default for BDW and CHV; turn it on.
839 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
841 /* Wa4x4STCOptimizationDisable:bdw,chv */
842 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
845 * BSpec recommends 8x4 when MSAA is used,
846 * however in practice 16x4 seems fastest.
848 * Note that PS/WM thread counts depend on the WIZ hashing
849 * disable bit, which we don't touch here, but it's good
850 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
852 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
853 GEN6_WIZ_HASHING_MASK,
854 GEN6_WIZ_HASHING_16x4);
859 static int bdw_init_workarounds(struct intel_engine_cs *ring)
862 struct drm_device *dev = ring->dev;
863 struct drm_i915_private *dev_priv = dev->dev_private;
865 ret = gen8_init_workarounds(ring);
869 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
870 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
872 /* WaDisableDopClockGating:bdw */
873 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
874 DOP_CLOCK_GATING_DISABLE);
876 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
877 GEN8_SAMPLER_POWER_BYPASS_DIS);
879 WA_SET_BIT_MASKED(HDC_CHICKEN0,
880 /* WaForceContextSaveRestoreNonCoherent:bdw */
881 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
882 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
883 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
888 static int chv_init_workarounds(struct intel_engine_cs *ring)
891 struct drm_device *dev = ring->dev;
892 struct drm_i915_private *dev_priv = dev->dev_private;
894 ret = gen8_init_workarounds(ring);
898 /* WaDisableThreadStallDopClockGating:chv */
899 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
901 /* Improve HiZ throughput on CHV. */
902 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
907 static int gen9_init_workarounds(struct intel_engine_cs *ring)
909 struct drm_device *dev = ring->dev;
910 struct drm_i915_private *dev_priv = dev->dev_private;
913 /* WaEnableLbsSlaRetryTimerDecrement:skl */
914 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
915 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
917 /* WaDisableKillLogic:bxt,skl */
918 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
921 /* WaDisablePartialInstShootdown:skl,bxt */
922 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
923 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
925 /* Syncing dependencies between camera and graphics:skl,bxt */
926 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
927 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
929 if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 ||
930 INTEL_REVID(dev) == SKL_REVID_B0)) ||
931 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
932 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
933 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
934 GEN9_DG_MIRROR_FIX_ENABLE);
937 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
938 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
939 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
940 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
941 GEN9_RHWO_OPTIMIZATION_DISABLE);
943 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
944 * but we do that in per ctx batchbuffer as there is an issue
945 * with this register not getting restored on ctx restore
949 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) ||
951 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
952 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
953 GEN9_ENABLE_YV12_BUGFIX);
956 /* Wa4x4STCOptimizationDisable:skl,bxt */
957 /* WaDisablePartialResolveInVc:skl,bxt */
958 WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
959 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
961 /* WaCcsTlbPrefetchDisable:skl,bxt */
962 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
963 GEN9_CCS_TLB_PREFETCH_ENABLE);
965 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
966 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) ||
967 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0))
968 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
969 PIXEL_MASK_CAMMING_DISABLE);
971 /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
972 tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
973 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_F0) ||
974 (IS_BROXTON(dev) && INTEL_REVID(dev) >= BXT_REVID_B0))
975 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
976 WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
978 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
979 if (IS_SKYLAKE(dev) ||
980 (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_B0)) {
981 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
982 GEN8_SAMPLER_POWER_BYPASS_DIS);
985 /* WaDisableSTUnitPowerOptimization:skl,bxt */
986 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
991 static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
993 struct drm_device *dev = ring->dev;
994 struct drm_i915_private *dev_priv = dev->dev_private;
995 u8 vals[3] = { 0, 0, 0 };
998 for (i = 0; i < 3; i++) {
1002 * Only consider slices where one, and only one, subslice has 7
1005 if (hweight8(dev_priv->info.subslice_7eu[i]) != 1)
1009 * subslice_7eu[i] != 0 (because of the check above) and
1010 * ss_max == 4 (maximum number of subslices possible per slice)
1014 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1018 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1021 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1022 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1023 GEN9_IZ_HASHING_MASK(2) |
1024 GEN9_IZ_HASHING_MASK(1) |
1025 GEN9_IZ_HASHING_MASK(0),
1026 GEN9_IZ_HASHING(2, vals[2]) |
1027 GEN9_IZ_HASHING(1, vals[1]) |
1028 GEN9_IZ_HASHING(0, vals[0]));
1033 static int skl_init_workarounds(struct intel_engine_cs *ring)
1036 struct drm_device *dev = ring->dev;
1037 struct drm_i915_private *dev_priv = dev->dev_private;
1039 ret = gen9_init_workarounds(ring);
1043 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
1044 /* WaDisableHDCInvalidation:skl */
1045 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
1046 BDW_DISABLE_HDC_INVALIDATION);
1048 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1049 I915_WRITE(FF_SLICE_CS_CHICKEN2,
1050 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
1053 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1054 * involving this register should also be added to WA batch as required.
1056 if (INTEL_REVID(dev) <= SKL_REVID_E0)
1057 /* WaDisableLSQCROPERFforOCL:skl */
1058 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1059 GEN8_LQSC_RO_PERF_DIS);
1061 /* WaEnableGapsTsvCreditFix:skl */
1062 if (IS_SKYLAKE(dev) && (INTEL_REVID(dev) >= SKL_REVID_C0)) {
1063 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1064 GEN9_GAPS_TSV_CREDIT_DISABLE));
1067 /* WaDisablePowerCompilerClockGating:skl */
1068 if (INTEL_REVID(dev) == SKL_REVID_B0)
1069 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1070 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1072 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
1074 *Use Force Non-Coherent whenever executing a 3D context. This
1075 * is a workaround for a possible hang in the unlikely event
1076 * a TLB invalidation occurs during a PSD flush.
1078 /* WaForceEnableNonCoherent:skl */
1079 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1080 HDC_FORCE_NON_COHERENT);
1083 if (INTEL_REVID(dev) == SKL_REVID_C0 ||
1084 INTEL_REVID(dev) == SKL_REVID_D0)
1085 /* WaBarrierPerformanceFixDisable:skl */
1086 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1087 HDC_FENCE_DEST_SLM_DISABLE |
1088 HDC_BARRIER_PERFORMANCE_DISABLE);
1090 /* WaDisableSbeCacheDispatchPortSharing:skl */
1091 if (INTEL_REVID(dev) <= SKL_REVID_F0) {
1093 GEN7_HALF_SLICE_CHICKEN1,
1094 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1097 return skl_tune_iz_hashing(ring);
1100 static int bxt_init_workarounds(struct intel_engine_cs *ring)
1103 struct drm_device *dev = ring->dev;
1104 struct drm_i915_private *dev_priv = dev->dev_private;
1106 ret = gen9_init_workarounds(ring);
1110 /* WaStoreMultiplePTEenable:bxt */
1111 /* This is a requirement according to Hardware specification */
1112 if (INTEL_REVID(dev) == BXT_REVID_A0)
1113 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
1115 /* WaSetClckGatingDisableMedia:bxt */
1116 if (INTEL_REVID(dev) == BXT_REVID_A0) {
1117 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
1118 ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
1121 /* WaDisableThreadStallDopClockGating:bxt */
1122 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1123 STALL_DOP_GATING_DISABLE);
1125 /* WaDisableSbeCacheDispatchPortSharing:bxt */
1126 if (INTEL_REVID(dev) <= BXT_REVID_B0) {
1128 GEN7_HALF_SLICE_CHICKEN1,
1129 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1135 int init_workarounds_ring(struct intel_engine_cs *ring)
1137 struct drm_device *dev = ring->dev;
1138 struct drm_i915_private *dev_priv = dev->dev_private;
1140 WARN_ON(ring->id != RCS);
1142 dev_priv->workarounds.count = 0;
1144 if (IS_BROADWELL(dev))
1145 return bdw_init_workarounds(ring);
1147 if (IS_CHERRYVIEW(dev))
1148 return chv_init_workarounds(ring);
1150 if (IS_SKYLAKE(dev))
1151 return skl_init_workarounds(ring);
1153 if (IS_BROXTON(dev))
1154 return bxt_init_workarounds(ring);
1159 static int init_render_ring(struct intel_engine_cs *ring)
1161 struct drm_device *dev = ring->dev;
1162 struct drm_i915_private *dev_priv = dev->dev_private;
1163 int ret = init_ring_common(ring);
1167 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1168 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
1169 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1171 /* We need to disable the AsyncFlip performance optimisations in order
1172 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1173 * programmed to '1' on all products.
1175 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1177 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1178 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1180 /* Required for the hardware to program scanline values for waiting */
1181 /* WaEnableFlushTlbInvalidationMode:snb */
1182 if (INTEL_INFO(dev)->gen == 6)
1183 I915_WRITE(GFX_MODE,
1184 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1186 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1188 I915_WRITE(GFX_MODE_GEN7,
1189 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1190 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1193 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1194 * "If this bit is set, STCunit will have LRA as replacement
1195 * policy. [...] This bit must be reset. LRA replacement
1196 * policy is not supported."
1198 I915_WRITE(CACHE_MODE_0,
1199 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1202 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1203 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1205 if (HAS_L3_DPF(dev))
1206 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1208 return init_workarounds_ring(ring);
1211 static void render_ring_cleanup(struct intel_engine_cs *ring)
1213 struct drm_device *dev = ring->dev;
1214 struct drm_i915_private *dev_priv = dev->dev_private;
1216 if (dev_priv->semaphore_obj) {
1217 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1218 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1219 dev_priv->semaphore_obj = NULL;
1222 intel_fini_pipe_control(ring);
1225 static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
1226 unsigned int num_dwords)
1228 #define MBOX_UPDATE_DWORDS 8
1229 struct intel_engine_cs *signaller = signaller_req->ring;
1230 struct drm_device *dev = signaller->dev;
1231 struct drm_i915_private *dev_priv = dev->dev_private;
1232 struct intel_engine_cs *waiter;
1233 int i, ret, num_rings;
1235 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1236 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1237 #undef MBOX_UPDATE_DWORDS
1239 ret = intel_ring_begin(signaller_req, num_dwords);
1243 for_each_ring(waiter, dev_priv, i) {
1245 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1246 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1249 seqno = i915_gem_request_get_seqno(signaller_req);
1250 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1251 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1252 PIPE_CONTROL_QW_WRITE |
1253 PIPE_CONTROL_FLUSH_ENABLE);
1254 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1255 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1256 intel_ring_emit(signaller, seqno);
1257 intel_ring_emit(signaller, 0);
1258 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1259 MI_SEMAPHORE_TARGET(waiter->id));
1260 intel_ring_emit(signaller, 0);
1266 static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
1267 unsigned int num_dwords)
1269 #define MBOX_UPDATE_DWORDS 6
1270 struct intel_engine_cs *signaller = signaller_req->ring;
1271 struct drm_device *dev = signaller->dev;
1272 struct drm_i915_private *dev_priv = dev->dev_private;
1273 struct intel_engine_cs *waiter;
1274 int i, ret, num_rings;
1276 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1277 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1278 #undef MBOX_UPDATE_DWORDS
1280 ret = intel_ring_begin(signaller_req, num_dwords);
1284 for_each_ring(waiter, dev_priv, i) {
1286 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1287 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1290 seqno = i915_gem_request_get_seqno(signaller_req);
1291 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1292 MI_FLUSH_DW_OP_STOREDW);
1293 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1294 MI_FLUSH_DW_USE_GTT);
1295 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1296 intel_ring_emit(signaller, seqno);
1297 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1298 MI_SEMAPHORE_TARGET(waiter->id));
1299 intel_ring_emit(signaller, 0);
1305 static int gen6_signal(struct drm_i915_gem_request *signaller_req,
1306 unsigned int num_dwords)
1308 struct intel_engine_cs *signaller = signaller_req->ring;
1309 struct drm_device *dev = signaller->dev;
1310 struct drm_i915_private *dev_priv = dev->dev_private;
1311 struct intel_engine_cs *useless;
1312 int i, ret, num_rings;
1314 #define MBOX_UPDATE_DWORDS 3
1315 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1316 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1317 #undef MBOX_UPDATE_DWORDS
1319 ret = intel_ring_begin(signaller_req, num_dwords);
1323 for_each_ring(useless, dev_priv, i) {
1324 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1325 if (mbox_reg != GEN6_NOSYNC) {
1326 u32 seqno = i915_gem_request_get_seqno(signaller_req);
1327 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1328 intel_ring_emit(signaller, mbox_reg);
1329 intel_ring_emit(signaller, seqno);
1333 /* If num_dwords was rounded, make sure the tail pointer is correct */
1334 if (num_rings % 2 == 0)
1335 intel_ring_emit(signaller, MI_NOOP);
1341 * gen6_add_request - Update the semaphore mailbox registers
1343 * @request - request to write to the ring
1345 * Update the mailbox registers in the *other* rings with the current seqno.
1346 * This acts like a signal in the canonical semaphore.
1349 gen6_add_request(struct drm_i915_gem_request *req)
1351 struct intel_engine_cs *ring = req->ring;
1354 if (ring->semaphore.signal)
1355 ret = ring->semaphore.signal(req, 4);
1357 ret = intel_ring_begin(req, 4);
1362 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1363 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1364 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1365 intel_ring_emit(ring, MI_USER_INTERRUPT);
1366 __intel_ring_advance(ring);
1371 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1374 struct drm_i915_private *dev_priv = dev->dev_private;
1375 return dev_priv->last_seqno < seqno;
1379 * intel_ring_sync - sync the waiter to the signaller on seqno
1381 * @waiter - ring that is waiting
1382 * @signaller - ring which has, or will signal
1383 * @seqno - seqno which the waiter will block on
1387 gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
1388 struct intel_engine_cs *signaller,
1391 struct intel_engine_cs *waiter = waiter_req->ring;
1392 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1395 ret = intel_ring_begin(waiter_req, 4);
1399 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1400 MI_SEMAPHORE_GLOBAL_GTT |
1402 MI_SEMAPHORE_SAD_GTE_SDD);
1403 intel_ring_emit(waiter, seqno);
1404 intel_ring_emit(waiter,
1405 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1406 intel_ring_emit(waiter,
1407 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1408 intel_ring_advance(waiter);
1413 gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
1414 struct intel_engine_cs *signaller,
1417 struct intel_engine_cs *waiter = waiter_req->ring;
1418 u32 dw1 = MI_SEMAPHORE_MBOX |
1419 MI_SEMAPHORE_COMPARE |
1420 MI_SEMAPHORE_REGISTER;
1421 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1424 /* Throughout all of the GEM code, seqno passed implies our current
1425 * seqno is >= the last seqno executed. However for hardware the
1426 * comparison is strictly greater than.
1430 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1432 ret = intel_ring_begin(waiter_req, 4);
1436 /* If seqno wrap happened, omit the wait with no-ops */
1437 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1438 intel_ring_emit(waiter, dw1 | wait_mbox);
1439 intel_ring_emit(waiter, seqno);
1440 intel_ring_emit(waiter, 0);
1441 intel_ring_emit(waiter, MI_NOOP);
1443 intel_ring_emit(waiter, MI_NOOP);
1444 intel_ring_emit(waiter, MI_NOOP);
1445 intel_ring_emit(waiter, MI_NOOP);
1446 intel_ring_emit(waiter, MI_NOOP);
1448 intel_ring_advance(waiter);
1453 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
1455 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1456 PIPE_CONTROL_DEPTH_STALL); \
1457 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1458 intel_ring_emit(ring__, 0); \
1459 intel_ring_emit(ring__, 0); \
1463 pc_render_add_request(struct drm_i915_gem_request *req)
1465 struct intel_engine_cs *ring = req->ring;
1466 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1469 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1470 * incoherent with writes to memory, i.e. completely fubar,
1471 * so we need to use PIPE_NOTIFY instead.
1473 * However, we also need to workaround the qword write
1474 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1475 * memory before requesting an interrupt.
1477 ret = intel_ring_begin(req, 32);
1481 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1482 PIPE_CONTROL_WRITE_FLUSH |
1483 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1484 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1485 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1486 intel_ring_emit(ring, 0);
1487 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1488 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1489 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1490 scratch_addr += 2 * CACHELINE_BYTES;
1491 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1492 scratch_addr += 2 * CACHELINE_BYTES;
1493 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1494 scratch_addr += 2 * CACHELINE_BYTES;
1495 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1496 scratch_addr += 2 * CACHELINE_BYTES;
1497 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1499 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1500 PIPE_CONTROL_WRITE_FLUSH |
1501 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1502 PIPE_CONTROL_NOTIFY);
1503 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1504 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1505 intel_ring_emit(ring, 0);
1506 __intel_ring_advance(ring);
1512 gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1514 /* Workaround to force correct ordering between irq and seqno writes on
1515 * ivb (and maybe also on snb) by reading from a CS register (like
1516 * ACTHD) before reading the status page. */
1517 if (!lazy_coherency) {
1518 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1519 POSTING_READ(RING_ACTHD(ring->mmio_base));
1522 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1526 ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1528 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1532 ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1534 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1538 pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1540 return ring->scratch.cpu_page[0];
1544 pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1546 ring->scratch.cpu_page[0] = seqno;
1550 gen5_ring_get_irq(struct intel_engine_cs *ring)
1552 struct drm_device *dev = ring->dev;
1553 struct drm_i915_private *dev_priv = dev->dev_private;
1554 unsigned long flags;
1556 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1559 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1560 if (ring->irq_refcount++ == 0)
1561 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1562 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1568 gen5_ring_put_irq(struct intel_engine_cs *ring)
1570 struct drm_device *dev = ring->dev;
1571 struct drm_i915_private *dev_priv = dev->dev_private;
1572 unsigned long flags;
1574 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1575 if (--ring->irq_refcount == 0)
1576 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1577 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1581 i9xx_ring_get_irq(struct intel_engine_cs *ring)
1583 struct drm_device *dev = ring->dev;
1584 struct drm_i915_private *dev_priv = dev->dev_private;
1585 unsigned long flags;
1587 if (!intel_irqs_enabled(dev_priv))
1590 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1591 if (ring->irq_refcount++ == 0) {
1592 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1593 I915_WRITE(IMR, dev_priv->irq_mask);
1596 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1602 i9xx_ring_put_irq(struct intel_engine_cs *ring)
1604 struct drm_device *dev = ring->dev;
1605 struct drm_i915_private *dev_priv = dev->dev_private;
1606 unsigned long flags;
1608 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1609 if (--ring->irq_refcount == 0) {
1610 dev_priv->irq_mask |= ring->irq_enable_mask;
1611 I915_WRITE(IMR, dev_priv->irq_mask);
1614 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1618 i8xx_ring_get_irq(struct intel_engine_cs *ring)
1620 struct drm_device *dev = ring->dev;
1621 struct drm_i915_private *dev_priv = dev->dev_private;
1622 unsigned long flags;
1624 if (!intel_irqs_enabled(dev_priv))
1627 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1628 if (ring->irq_refcount++ == 0) {
1629 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1630 I915_WRITE16(IMR, dev_priv->irq_mask);
1631 POSTING_READ16(IMR);
1633 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1639 i8xx_ring_put_irq(struct intel_engine_cs *ring)
1641 struct drm_device *dev = ring->dev;
1642 struct drm_i915_private *dev_priv = dev->dev_private;
1643 unsigned long flags;
1645 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1646 if (--ring->irq_refcount == 0) {
1647 dev_priv->irq_mask |= ring->irq_enable_mask;
1648 I915_WRITE16(IMR, dev_priv->irq_mask);
1649 POSTING_READ16(IMR);
1651 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1655 bsd_ring_flush(struct drm_i915_gem_request *req,
1656 u32 invalidate_domains,
1659 struct intel_engine_cs *ring = req->ring;
1662 ret = intel_ring_begin(req, 2);
1666 intel_ring_emit(ring, MI_FLUSH);
1667 intel_ring_emit(ring, MI_NOOP);
1668 intel_ring_advance(ring);
1673 i9xx_add_request(struct drm_i915_gem_request *req)
1675 struct intel_engine_cs *ring = req->ring;
1678 ret = intel_ring_begin(req, 4);
1682 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1683 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1684 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1685 intel_ring_emit(ring, MI_USER_INTERRUPT);
1686 __intel_ring_advance(ring);
1692 gen6_ring_get_irq(struct intel_engine_cs *ring)
1694 struct drm_device *dev = ring->dev;
1695 struct drm_i915_private *dev_priv = dev->dev_private;
1696 unsigned long flags;
1698 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1701 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1702 if (ring->irq_refcount++ == 0) {
1703 if (HAS_L3_DPF(dev) && ring->id == RCS)
1704 I915_WRITE_IMR(ring,
1705 ~(ring->irq_enable_mask |
1706 GT_PARITY_ERROR(dev)));
1708 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1709 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1711 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1717 gen6_ring_put_irq(struct intel_engine_cs *ring)
1719 struct drm_device *dev = ring->dev;
1720 struct drm_i915_private *dev_priv = dev->dev_private;
1721 unsigned long flags;
1723 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1724 if (--ring->irq_refcount == 0) {
1725 if (HAS_L3_DPF(dev) && ring->id == RCS)
1726 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1728 I915_WRITE_IMR(ring, ~0);
1729 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1731 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1735 hsw_vebox_get_irq(struct intel_engine_cs *ring)
1737 struct drm_device *dev = ring->dev;
1738 struct drm_i915_private *dev_priv = dev->dev_private;
1739 unsigned long flags;
1741 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1744 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1745 if (ring->irq_refcount++ == 0) {
1746 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1747 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1749 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1755 hsw_vebox_put_irq(struct intel_engine_cs *ring)
1757 struct drm_device *dev = ring->dev;
1758 struct drm_i915_private *dev_priv = dev->dev_private;
1759 unsigned long flags;
1761 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1762 if (--ring->irq_refcount == 0) {
1763 I915_WRITE_IMR(ring, ~0);
1764 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1766 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1770 gen8_ring_get_irq(struct intel_engine_cs *ring)
1772 struct drm_device *dev = ring->dev;
1773 struct drm_i915_private *dev_priv = dev->dev_private;
1774 unsigned long flags;
1776 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1779 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1780 if (ring->irq_refcount++ == 0) {
1781 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1782 I915_WRITE_IMR(ring,
1783 ~(ring->irq_enable_mask |
1784 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1786 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1788 POSTING_READ(RING_IMR(ring->mmio_base));
1790 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1796 gen8_ring_put_irq(struct intel_engine_cs *ring)
1798 struct drm_device *dev = ring->dev;
1799 struct drm_i915_private *dev_priv = dev->dev_private;
1800 unsigned long flags;
1802 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1803 if (--ring->irq_refcount == 0) {
1804 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1805 I915_WRITE_IMR(ring,
1806 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1808 I915_WRITE_IMR(ring, ~0);
1810 POSTING_READ(RING_IMR(ring->mmio_base));
1812 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1816 i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
1817 u64 offset, u32 length,
1818 unsigned dispatch_flags)
1820 struct intel_engine_cs *ring = req->ring;
1823 ret = intel_ring_begin(req, 2);
1827 intel_ring_emit(ring,
1828 MI_BATCH_BUFFER_START |
1830 (dispatch_flags & I915_DISPATCH_SECURE ?
1831 0 : MI_BATCH_NON_SECURE_I965));
1832 intel_ring_emit(ring, offset);
1833 intel_ring_advance(ring);
1838 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1839 #define I830_BATCH_LIMIT (256*1024)
1840 #define I830_TLB_ENTRIES (2)
1841 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1843 i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
1844 u64 offset, u32 len,
1845 unsigned dispatch_flags)
1847 struct intel_engine_cs *ring = req->ring;
1848 u32 cs_offset = ring->scratch.gtt_offset;
1851 ret = intel_ring_begin(req, 6);
1855 /* Evict the invalid PTE TLBs */
1856 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1857 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1858 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1859 intel_ring_emit(ring, cs_offset);
1860 intel_ring_emit(ring, 0xdeadbeef);
1861 intel_ring_emit(ring, MI_NOOP);
1862 intel_ring_advance(ring);
1864 if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1865 if (len > I830_BATCH_LIMIT)
1868 ret = intel_ring_begin(req, 6 + 2);
1872 /* Blit the batch (which has now all relocs applied) to the
1873 * stable batch scratch bo area (so that the CS never
1874 * stumbles over its tlb invalidation bug) ...
1876 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1877 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1878 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1879 intel_ring_emit(ring, cs_offset);
1880 intel_ring_emit(ring, 4096);
1881 intel_ring_emit(ring, offset);
1883 intel_ring_emit(ring, MI_FLUSH);
1884 intel_ring_emit(ring, MI_NOOP);
1885 intel_ring_advance(ring);
1887 /* ... and execute it. */
1891 ret = intel_ring_begin(req, 4);
1895 intel_ring_emit(ring, MI_BATCH_BUFFER);
1896 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1897 0 : MI_BATCH_NON_SECURE));
1898 intel_ring_emit(ring, offset + len - 8);
1899 intel_ring_emit(ring, MI_NOOP);
1900 intel_ring_advance(ring);
1906 i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
1907 u64 offset, u32 len,
1908 unsigned dispatch_flags)
1910 struct intel_engine_cs *ring = req->ring;
1913 ret = intel_ring_begin(req, 2);
1917 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1918 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1919 0 : MI_BATCH_NON_SECURE));
1920 intel_ring_advance(ring);
1925 static void cleanup_status_page(struct intel_engine_cs *ring)
1927 struct drm_i915_gem_object *obj;
1929 obj = ring->status_page.obj;
1933 kunmap(sg_page(obj->pages->sgl));
1934 i915_gem_object_ggtt_unpin(obj);
1935 drm_gem_object_unreference(&obj->base);
1936 ring->status_page.obj = NULL;
1939 static int init_status_page(struct intel_engine_cs *ring)
1941 struct drm_i915_gem_object *obj;
1943 if ((obj = ring->status_page.obj) == NULL) {
1947 obj = i915_gem_alloc_object(ring->dev, 4096);
1949 DRM_ERROR("Failed to allocate status page\n");
1953 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1958 if (!HAS_LLC(ring->dev))
1959 /* On g33, we cannot place HWS above 256MiB, so
1960 * restrict its pinning to the low mappable arena.
1961 * Though this restriction is not documented for
1962 * gen4, gen5, or byt, they also behave similarly
1963 * and hang if the HWS is placed at the top of the
1964 * GTT. To generalise, it appears that all !llc
1965 * platforms have issues with us placing the HWS
1966 * above the mappable region (even though we never
1969 flags |= PIN_MAPPABLE;
1970 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
1973 drm_gem_object_unreference(&obj->base);
1977 ring->status_page.obj = obj;
1980 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1981 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1982 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1984 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1985 ring->name, ring->status_page.gfx_addr);
1990 static int init_phys_status_page(struct intel_engine_cs *ring)
1992 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1994 if (!dev_priv->status_page_dmah) {
1995 dev_priv->status_page_dmah =
1996 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1997 if (!dev_priv->status_page_dmah)
2001 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
2002 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
2007 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2009 iounmap(ringbuf->virtual_start);
2010 ringbuf->virtual_start = NULL;
2011 i915_gem_object_ggtt_unpin(ringbuf->obj);
2014 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
2015 struct intel_ringbuffer *ringbuf)
2017 struct drm_i915_private *dev_priv = to_i915(dev);
2018 struct drm_i915_gem_object *obj = ringbuf->obj;
2021 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
2025 ret = i915_gem_object_set_to_gtt_domain(obj, true);
2027 i915_gem_object_ggtt_unpin(obj);
2031 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
2032 i915_gem_obj_ggtt_offset(obj), ringbuf->size);
2033 if (ringbuf->virtual_start == NULL) {
2034 i915_gem_object_ggtt_unpin(obj);
2041 static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2043 drm_gem_object_unreference(&ringbuf->obj->base);
2044 ringbuf->obj = NULL;
2047 static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
2048 struct intel_ringbuffer *ringbuf)
2050 struct drm_i915_gem_object *obj;
2054 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
2056 obj = i915_gem_alloc_object(dev, ringbuf->size);
2060 /* mark ring buffers as read-only from GPU side by default */
2068 struct intel_ringbuffer *
2069 intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
2071 struct intel_ringbuffer *ring;
2074 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
2076 return ERR_PTR(-ENOMEM);
2078 ring->ring = engine;
2081 /* Workaround an erratum on the i830 which causes a hang if
2082 * the TAIL pointer points to within the last 2 cachelines
2085 ring->effective_size = size;
2086 if (IS_I830(engine->dev) || IS_845G(engine->dev))
2087 ring->effective_size -= 2 * CACHELINE_BYTES;
2089 ring->last_retired_head = -1;
2090 intel_ring_update_space(ring);
2092 ret = intel_alloc_ringbuffer_obj(engine->dev, ring);
2094 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
2097 return ERR_PTR(ret);
2104 intel_ringbuffer_free(struct intel_ringbuffer *ring)
2106 intel_destroy_ringbuffer_obj(ring);
2110 static int intel_init_ring_buffer(struct drm_device *dev,
2111 struct intel_engine_cs *ring)
2113 struct intel_ringbuffer *ringbuf;
2116 WARN_ON(ring->buffer);
2119 INIT_LIST_HEAD(&ring->active_list);
2120 INIT_LIST_HEAD(&ring->request_list);
2121 INIT_LIST_HEAD(&ring->execlist_queue);
2122 i915_gem_batch_pool_init(dev, &ring->batch_pool);
2123 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
2125 init_waitqueue_head(&ring->irq_queue);
2127 ringbuf = intel_engine_create_ringbuffer(ring, 32 * PAGE_SIZE);
2128 if (IS_ERR(ringbuf))
2129 return PTR_ERR(ringbuf);
2130 ring->buffer = ringbuf;
2132 if (I915_NEED_GFX_HWS(dev)) {
2133 ret = init_status_page(ring);
2137 BUG_ON(ring->id != RCS);
2138 ret = init_phys_status_page(ring);
2143 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2145 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2147 intel_destroy_ringbuffer_obj(ringbuf);
2151 ret = i915_cmd_parser_init_ring(ring);
2158 intel_ringbuffer_free(ringbuf);
2159 ring->buffer = NULL;
2163 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
2165 struct drm_i915_private *dev_priv;
2167 if (!intel_ring_initialized(ring))
2170 dev_priv = to_i915(ring->dev);
2172 intel_stop_ring_buffer(ring);
2173 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
2175 intel_unpin_ringbuffer_obj(ring->buffer);
2176 intel_ringbuffer_free(ring->buffer);
2177 ring->buffer = NULL;
2180 ring->cleanup(ring);
2182 cleanup_status_page(ring);
2184 i915_cmd_parser_fini_ring(ring);
2185 i915_gem_batch_pool_fini(&ring->batch_pool);
2188 static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
2190 struct intel_ringbuffer *ringbuf = ring->buffer;
2191 struct drm_i915_gem_request *request;
2195 if (intel_ring_space(ringbuf) >= n)
2198 /* The whole point of reserving space is to not wait! */
2199 WARN_ON(ringbuf->reserved_in_use);
2201 list_for_each_entry(request, &ring->request_list, list) {
2202 space = __intel_ring_space(request->postfix, ringbuf->tail,
2208 if (WARN_ON(&request->list == &ring->request_list))
2211 ret = i915_wait_request(request);
2215 ringbuf->space = space;
2219 static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)
2221 uint32_t __iomem *virt;
2222 int rem = ringbuf->size - ringbuf->tail;
2224 virt = ringbuf->virtual_start + ringbuf->tail;
2227 iowrite32(MI_NOOP, virt++);
2230 intel_ring_update_space(ringbuf);
2233 int intel_ring_idle(struct intel_engine_cs *ring)
2235 struct drm_i915_gem_request *req;
2237 /* Wait upon the last request to be completed */
2238 if (list_empty(&ring->request_list))
2241 req = list_entry(ring->request_list.prev,
2242 struct drm_i915_gem_request,
2245 /* Make sure we do not trigger any retires */
2246 return __i915_wait_request(req,
2247 atomic_read(&to_i915(ring->dev)->gpu_error.reset_counter),
2248 to_i915(ring->dev)->mm.interruptible,
2252 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
2254 request->ringbuf = request->ring->buffer;
2258 int intel_ring_reserve_space(struct drm_i915_gem_request *request)
2261 * The first call merely notes the reserve request and is common for
2262 * all back ends. The subsequent localised _begin() call actually
2263 * ensures that the reservation is available. Without the begin, if
2264 * the request creator immediately submitted the request without
2265 * adding any commands to it then there might not actually be
2266 * sufficient room for the submission commands.
2268 intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
2270 return intel_ring_begin(request, 0);
2273 void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size)
2275 WARN_ON(ringbuf->reserved_size);
2276 WARN_ON(ringbuf->reserved_in_use);
2278 ringbuf->reserved_size = size;
2281 void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf)
2283 WARN_ON(ringbuf->reserved_in_use);
2285 ringbuf->reserved_size = 0;
2286 ringbuf->reserved_in_use = false;
2289 void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf)
2291 WARN_ON(ringbuf->reserved_in_use);
2293 ringbuf->reserved_in_use = true;
2294 ringbuf->reserved_tail = ringbuf->tail;
2297 void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
2299 WARN_ON(!ringbuf->reserved_in_use);
2300 if (ringbuf->tail > ringbuf->reserved_tail) {
2301 WARN(ringbuf->tail > ringbuf->reserved_tail + ringbuf->reserved_size,
2302 "request reserved size too small: %d vs %d!\n",
2303 ringbuf->tail - ringbuf->reserved_tail, ringbuf->reserved_size);
2306 * The ring was wrapped while the reserved space was in use.
2307 * That means that some unknown amount of the ring tail was
2308 * no-op filled and skipped. Thus simply adding the ring size
2309 * to the tail and doing the above space check will not work.
2310 * Rather than attempt to track how much tail was skipped,
2311 * it is much simpler to say that also skipping the sanity
2312 * check every once in a while is not a big issue.
2316 ringbuf->reserved_size = 0;
2317 ringbuf->reserved_in_use = false;
2320 static int __intel_ring_prepare(struct intel_engine_cs *ring, int bytes)
2322 struct intel_ringbuffer *ringbuf = ring->buffer;
2323 int remain_usable = ringbuf->effective_size - ringbuf->tail;
2324 int remain_actual = ringbuf->size - ringbuf->tail;
2325 int ret, total_bytes, wait_bytes = 0;
2326 bool need_wrap = false;
2328 if (ringbuf->reserved_in_use)
2329 total_bytes = bytes;
2331 total_bytes = bytes + ringbuf->reserved_size;
2333 if (unlikely(bytes > remain_usable)) {
2335 * Not enough space for the basic request. So need to flush
2336 * out the remainder and then wait for base + reserved.
2338 wait_bytes = remain_actual + total_bytes;
2341 if (unlikely(total_bytes > remain_usable)) {
2343 * The base request will fit but the reserved space
2344 * falls off the end. So only need to to wait for the
2345 * reserved size after flushing out the remainder.
2347 wait_bytes = remain_actual + ringbuf->reserved_size;
2349 } else if (total_bytes > ringbuf->space) {
2350 /* No wrapping required, just waiting. */
2351 wait_bytes = total_bytes;
2356 ret = ring_wait_for_space(ring, wait_bytes);
2361 __wrap_ring_buffer(ringbuf);
2367 int intel_ring_begin(struct drm_i915_gem_request *req,
2370 struct intel_engine_cs *ring;
2371 struct drm_i915_private *dev_priv;
2374 WARN_ON(req == NULL);
2376 dev_priv = ring->dev->dev_private;
2378 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2379 dev_priv->mm.interruptible);
2383 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2387 ring->buffer->space -= num_dwords * sizeof(uint32_t);
2391 /* Align the ring tail to a cacheline boundary */
2392 int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
2394 struct intel_engine_cs *ring = req->ring;
2395 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2398 if (num_dwords == 0)
2401 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2402 ret = intel_ring_begin(req, num_dwords);
2406 while (num_dwords--)
2407 intel_ring_emit(ring, MI_NOOP);
2409 intel_ring_advance(ring);
2414 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
2416 struct drm_device *dev = ring->dev;
2417 struct drm_i915_private *dev_priv = dev->dev_private;
2419 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
2420 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2421 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
2423 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
2426 ring->set_seqno(ring, seqno);
2427 ring->hangcheck.seqno = seqno;
2430 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
2433 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2435 /* Every tail move must follow the sequence below */
2437 /* Disable notification that the ring is IDLE. The GT
2438 * will then assume that it is busy and bring it out of rc6.
2440 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2441 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2443 /* Clear the context id. Here be magic! */
2444 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2446 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2447 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2448 GEN6_BSD_SLEEP_INDICATOR) == 0,
2450 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2452 /* Now that the ring is fully powered up, update the tail */
2453 I915_WRITE_TAIL(ring, value);
2454 POSTING_READ(RING_TAIL(ring->mmio_base));
2456 /* Let the ring send IDLE messages to the GT again,
2457 * and so let it sleep to conserve power when idle.
2459 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2460 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2463 static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
2464 u32 invalidate, u32 flush)
2466 struct intel_engine_cs *ring = req->ring;
2470 ret = intel_ring_begin(req, 4);
2475 if (INTEL_INFO(ring->dev)->gen >= 8)
2478 /* We always require a command barrier so that subsequent
2479 * commands, such as breadcrumb interrupts, are strictly ordered
2480 * wrt the contents of the write cache being flushed to memory
2481 * (and thus being coherent from the CPU).
2483 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2486 * Bspec vol 1c.5 - video engine command streamer:
2487 * "If ENABLED, all TLBs will be invalidated once the flush
2488 * operation is complete. This bit is only valid when the
2489 * Post-Sync Operation field is a value of 1h or 3h."
2491 if (invalidate & I915_GEM_GPU_DOMAINS)
2492 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2494 intel_ring_emit(ring, cmd);
2495 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2496 if (INTEL_INFO(ring->dev)->gen >= 8) {
2497 intel_ring_emit(ring, 0); /* upper addr */
2498 intel_ring_emit(ring, 0); /* value */
2500 intel_ring_emit(ring, 0);
2501 intel_ring_emit(ring, MI_NOOP);
2503 intel_ring_advance(ring);
2508 gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2509 u64 offset, u32 len,
2510 unsigned dispatch_flags)
2512 struct intel_engine_cs *ring = req->ring;
2513 bool ppgtt = USES_PPGTT(ring->dev) &&
2514 !(dispatch_flags & I915_DISPATCH_SECURE);
2517 ret = intel_ring_begin(req, 4);
2521 /* FIXME(BDW): Address space and security selectors. */
2522 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
2523 (dispatch_flags & I915_DISPATCH_RS ?
2524 MI_BATCH_RESOURCE_STREAMER : 0));
2525 intel_ring_emit(ring, lower_32_bits(offset));
2526 intel_ring_emit(ring, upper_32_bits(offset));
2527 intel_ring_emit(ring, MI_NOOP);
2528 intel_ring_advance(ring);
2534 hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2535 u64 offset, u32 len,
2536 unsigned dispatch_flags)
2538 struct intel_engine_cs *ring = req->ring;
2541 ret = intel_ring_begin(req, 2);
2545 intel_ring_emit(ring,
2546 MI_BATCH_BUFFER_START |
2547 (dispatch_flags & I915_DISPATCH_SECURE ?
2548 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2549 (dispatch_flags & I915_DISPATCH_RS ?
2550 MI_BATCH_RESOURCE_STREAMER : 0));
2551 /* bit0-7 is the length on GEN6+ */
2552 intel_ring_emit(ring, offset);
2553 intel_ring_advance(ring);
2559 gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2560 u64 offset, u32 len,
2561 unsigned dispatch_flags)
2563 struct intel_engine_cs *ring = req->ring;
2566 ret = intel_ring_begin(req, 2);
2570 intel_ring_emit(ring,
2571 MI_BATCH_BUFFER_START |
2572 (dispatch_flags & I915_DISPATCH_SECURE ?
2573 0 : MI_BATCH_NON_SECURE_I965));
2574 /* bit0-7 is the length on GEN6+ */
2575 intel_ring_emit(ring, offset);
2576 intel_ring_advance(ring);
2581 /* Blitter support (SandyBridge+) */
2583 static int gen6_ring_flush(struct drm_i915_gem_request *req,
2584 u32 invalidate, u32 flush)
2586 struct intel_engine_cs *ring = req->ring;
2587 struct drm_device *dev = ring->dev;
2591 ret = intel_ring_begin(req, 4);
2596 if (INTEL_INFO(dev)->gen >= 8)
2599 /* We always require a command barrier so that subsequent
2600 * commands, such as breadcrumb interrupts, are strictly ordered
2601 * wrt the contents of the write cache being flushed to memory
2602 * (and thus being coherent from the CPU).
2604 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2607 * Bspec vol 1c.3 - blitter engine command streamer:
2608 * "If ENABLED, all TLBs will be invalidated once the flush
2609 * operation is complete. This bit is only valid when the
2610 * Post-Sync Operation field is a value of 1h or 3h."
2612 if (invalidate & I915_GEM_DOMAIN_RENDER)
2613 cmd |= MI_INVALIDATE_TLB;
2614 intel_ring_emit(ring, cmd);
2615 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2616 if (INTEL_INFO(dev)->gen >= 8) {
2617 intel_ring_emit(ring, 0); /* upper addr */
2618 intel_ring_emit(ring, 0); /* value */
2620 intel_ring_emit(ring, 0);
2621 intel_ring_emit(ring, MI_NOOP);
2623 intel_ring_advance(ring);
2628 int intel_init_render_ring_buffer(struct drm_device *dev)
2630 struct drm_i915_private *dev_priv = dev->dev_private;
2631 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2632 struct drm_i915_gem_object *obj;
2635 ring->name = "render ring";
2637 ring->mmio_base = RENDER_RING_BASE;
2639 if (INTEL_INFO(dev)->gen >= 8) {
2640 if (i915_semaphore_is_enabled(dev)) {
2641 obj = i915_gem_alloc_object(dev, 4096);
2643 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2644 i915.semaphores = 0;
2646 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2647 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2649 drm_gem_object_unreference(&obj->base);
2650 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2651 i915.semaphores = 0;
2653 dev_priv->semaphore_obj = obj;
2657 ring->init_context = intel_rcs_ctx_init;
2658 ring->add_request = gen6_add_request;
2659 ring->flush = gen8_render_ring_flush;
2660 ring->irq_get = gen8_ring_get_irq;
2661 ring->irq_put = gen8_ring_put_irq;
2662 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2663 ring->get_seqno = gen6_ring_get_seqno;
2664 ring->set_seqno = ring_set_seqno;
2665 if (i915_semaphore_is_enabled(dev)) {
2666 WARN_ON(!dev_priv->semaphore_obj);
2667 ring->semaphore.sync_to = gen8_ring_sync;
2668 ring->semaphore.signal = gen8_rcs_signal;
2669 GEN8_RING_SEMAPHORE_INIT;
2671 } else if (INTEL_INFO(dev)->gen >= 6) {
2672 ring->init_context = intel_rcs_ctx_init;
2673 ring->add_request = gen6_add_request;
2674 ring->flush = gen7_render_ring_flush;
2675 if (INTEL_INFO(dev)->gen == 6)
2676 ring->flush = gen6_render_ring_flush;
2677 ring->irq_get = gen6_ring_get_irq;
2678 ring->irq_put = gen6_ring_put_irq;
2679 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2680 ring->get_seqno = gen6_ring_get_seqno;
2681 ring->set_seqno = ring_set_seqno;
2682 if (i915_semaphore_is_enabled(dev)) {
2683 ring->semaphore.sync_to = gen6_ring_sync;
2684 ring->semaphore.signal = gen6_signal;
2686 * The current semaphore is only applied on pre-gen8
2687 * platform. And there is no VCS2 ring on the pre-gen8
2688 * platform. So the semaphore between RCS and VCS2 is
2689 * initialized as INVALID. Gen8 will initialize the
2690 * sema between VCS2 and RCS later.
2692 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2693 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2694 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2695 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2696 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2697 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2698 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2699 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2700 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2701 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2703 } else if (IS_GEN5(dev)) {
2704 ring->add_request = pc_render_add_request;
2705 ring->flush = gen4_render_ring_flush;
2706 ring->get_seqno = pc_render_get_seqno;
2707 ring->set_seqno = pc_render_set_seqno;
2708 ring->irq_get = gen5_ring_get_irq;
2709 ring->irq_put = gen5_ring_put_irq;
2710 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2711 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2713 ring->add_request = i9xx_add_request;
2714 if (INTEL_INFO(dev)->gen < 4)
2715 ring->flush = gen2_render_ring_flush;
2717 ring->flush = gen4_render_ring_flush;
2718 ring->get_seqno = ring_get_seqno;
2719 ring->set_seqno = ring_set_seqno;
2721 ring->irq_get = i8xx_ring_get_irq;
2722 ring->irq_put = i8xx_ring_put_irq;
2724 ring->irq_get = i9xx_ring_get_irq;
2725 ring->irq_put = i9xx_ring_put_irq;
2727 ring->irq_enable_mask = I915_USER_INTERRUPT;
2729 ring->write_tail = ring_write_tail;
2731 if (IS_HASWELL(dev))
2732 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2733 else if (IS_GEN8(dev))
2734 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2735 else if (INTEL_INFO(dev)->gen >= 6)
2736 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2737 else if (INTEL_INFO(dev)->gen >= 4)
2738 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2739 else if (IS_I830(dev) || IS_845G(dev))
2740 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2742 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2743 ring->init_hw = init_render_ring;
2744 ring->cleanup = render_ring_cleanup;
2746 /* Workaround batchbuffer to combat CS tlb bug. */
2747 if (HAS_BROKEN_CS_TLB(dev)) {
2748 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2750 DRM_ERROR("Failed to allocate batch bo\n");
2754 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2756 drm_gem_object_unreference(&obj->base);
2757 DRM_ERROR("Failed to ping batch bo\n");
2761 ring->scratch.obj = obj;
2762 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2765 ret = intel_init_ring_buffer(dev, ring);
2769 if (INTEL_INFO(dev)->gen >= 5) {
2770 ret = intel_init_pipe_control(ring);
2778 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2780 struct drm_i915_private *dev_priv = dev->dev_private;
2781 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2783 ring->name = "bsd ring";
2786 ring->write_tail = ring_write_tail;
2787 if (INTEL_INFO(dev)->gen >= 6) {
2788 ring->mmio_base = GEN6_BSD_RING_BASE;
2789 /* gen6 bsd needs a special wa for tail updates */
2791 ring->write_tail = gen6_bsd_ring_write_tail;
2792 ring->flush = gen6_bsd_ring_flush;
2793 ring->add_request = gen6_add_request;
2794 ring->get_seqno = gen6_ring_get_seqno;
2795 ring->set_seqno = ring_set_seqno;
2796 if (INTEL_INFO(dev)->gen >= 8) {
2797 ring->irq_enable_mask =
2798 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2799 ring->irq_get = gen8_ring_get_irq;
2800 ring->irq_put = gen8_ring_put_irq;
2801 ring->dispatch_execbuffer =
2802 gen8_ring_dispatch_execbuffer;
2803 if (i915_semaphore_is_enabled(dev)) {
2804 ring->semaphore.sync_to = gen8_ring_sync;
2805 ring->semaphore.signal = gen8_xcs_signal;
2806 GEN8_RING_SEMAPHORE_INIT;
2809 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2810 ring->irq_get = gen6_ring_get_irq;
2811 ring->irq_put = gen6_ring_put_irq;
2812 ring->dispatch_execbuffer =
2813 gen6_ring_dispatch_execbuffer;
2814 if (i915_semaphore_is_enabled(dev)) {
2815 ring->semaphore.sync_to = gen6_ring_sync;
2816 ring->semaphore.signal = gen6_signal;
2817 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2818 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2819 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2820 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2821 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2822 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2823 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2824 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2825 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2826 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2830 ring->mmio_base = BSD_RING_BASE;
2831 ring->flush = bsd_ring_flush;
2832 ring->add_request = i9xx_add_request;
2833 ring->get_seqno = ring_get_seqno;
2834 ring->set_seqno = ring_set_seqno;
2836 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2837 ring->irq_get = gen5_ring_get_irq;
2838 ring->irq_put = gen5_ring_put_irq;
2840 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2841 ring->irq_get = i9xx_ring_get_irq;
2842 ring->irq_put = i9xx_ring_put_irq;
2844 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2846 ring->init_hw = init_ring_common;
2848 return intel_init_ring_buffer(dev, ring);
2852 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2854 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2856 struct drm_i915_private *dev_priv = dev->dev_private;
2857 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2859 ring->name = "bsd2 ring";
2862 ring->write_tail = ring_write_tail;
2863 ring->mmio_base = GEN8_BSD2_RING_BASE;
2864 ring->flush = gen6_bsd_ring_flush;
2865 ring->add_request = gen6_add_request;
2866 ring->get_seqno = gen6_ring_get_seqno;
2867 ring->set_seqno = ring_set_seqno;
2868 ring->irq_enable_mask =
2869 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2870 ring->irq_get = gen8_ring_get_irq;
2871 ring->irq_put = gen8_ring_put_irq;
2872 ring->dispatch_execbuffer =
2873 gen8_ring_dispatch_execbuffer;
2874 if (i915_semaphore_is_enabled(dev)) {
2875 ring->semaphore.sync_to = gen8_ring_sync;
2876 ring->semaphore.signal = gen8_xcs_signal;
2877 GEN8_RING_SEMAPHORE_INIT;
2879 ring->init_hw = init_ring_common;
2881 return intel_init_ring_buffer(dev, ring);
2884 int intel_init_blt_ring_buffer(struct drm_device *dev)
2886 struct drm_i915_private *dev_priv = dev->dev_private;
2887 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2889 ring->name = "blitter ring";
2892 ring->mmio_base = BLT_RING_BASE;
2893 ring->write_tail = ring_write_tail;
2894 ring->flush = gen6_ring_flush;
2895 ring->add_request = gen6_add_request;
2896 ring->get_seqno = gen6_ring_get_seqno;
2897 ring->set_seqno = ring_set_seqno;
2898 if (INTEL_INFO(dev)->gen >= 8) {
2899 ring->irq_enable_mask =
2900 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2901 ring->irq_get = gen8_ring_get_irq;
2902 ring->irq_put = gen8_ring_put_irq;
2903 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2904 if (i915_semaphore_is_enabled(dev)) {
2905 ring->semaphore.sync_to = gen8_ring_sync;
2906 ring->semaphore.signal = gen8_xcs_signal;
2907 GEN8_RING_SEMAPHORE_INIT;
2910 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2911 ring->irq_get = gen6_ring_get_irq;
2912 ring->irq_put = gen6_ring_put_irq;
2913 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2914 if (i915_semaphore_is_enabled(dev)) {
2915 ring->semaphore.signal = gen6_signal;
2916 ring->semaphore.sync_to = gen6_ring_sync;
2918 * The current semaphore is only applied on pre-gen8
2919 * platform. And there is no VCS2 ring on the pre-gen8
2920 * platform. So the semaphore between BCS and VCS2 is
2921 * initialized as INVALID. Gen8 will initialize the
2922 * sema between BCS and VCS2 later.
2924 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2925 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2926 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2927 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2928 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2929 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2930 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2931 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2932 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2933 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2936 ring->init_hw = init_ring_common;
2938 return intel_init_ring_buffer(dev, ring);
2941 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2943 struct drm_i915_private *dev_priv = dev->dev_private;
2944 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2946 ring->name = "video enhancement ring";
2949 ring->mmio_base = VEBOX_RING_BASE;
2950 ring->write_tail = ring_write_tail;
2951 ring->flush = gen6_ring_flush;
2952 ring->add_request = gen6_add_request;
2953 ring->get_seqno = gen6_ring_get_seqno;
2954 ring->set_seqno = ring_set_seqno;
2956 if (INTEL_INFO(dev)->gen >= 8) {
2957 ring->irq_enable_mask =
2958 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2959 ring->irq_get = gen8_ring_get_irq;
2960 ring->irq_put = gen8_ring_put_irq;
2961 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2962 if (i915_semaphore_is_enabled(dev)) {
2963 ring->semaphore.sync_to = gen8_ring_sync;
2964 ring->semaphore.signal = gen8_xcs_signal;
2965 GEN8_RING_SEMAPHORE_INIT;
2968 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2969 ring->irq_get = hsw_vebox_get_irq;
2970 ring->irq_put = hsw_vebox_put_irq;
2971 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2972 if (i915_semaphore_is_enabled(dev)) {
2973 ring->semaphore.sync_to = gen6_ring_sync;
2974 ring->semaphore.signal = gen6_signal;
2975 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2976 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2977 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2978 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2979 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2980 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2981 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2982 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2983 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2984 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2987 ring->init_hw = init_ring_common;
2989 return intel_init_ring_buffer(dev, ring);
2993 intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
2995 struct intel_engine_cs *ring = req->ring;
2998 if (!ring->gpu_caches_dirty)
3001 ret = ring->flush(req, 0, I915_GEM_GPU_DOMAINS);
3005 trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
3007 ring->gpu_caches_dirty = false;
3012 intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
3014 struct intel_engine_cs *ring = req->ring;
3015 uint32_t flush_domains;
3019 if (ring->gpu_caches_dirty)
3020 flush_domains = I915_GEM_GPU_DOMAINS;
3022 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3026 trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3028 ring->gpu_caches_dirty = false;
3033 intel_stop_ring_buffer(struct intel_engine_cs *ring)
3037 if (!intel_ring_initialized(ring))
3040 ret = intel_ring_idle(ring);
3041 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
3042 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",