2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
34 #include "i915_trace.h"
35 #include "intel_drv.h"
38 * 965+ support PIPE_CONTROL commands, which provide finer grained control
39 * over cache flushing.
42 struct drm_i915_gem_object *obj;
43 volatile u32 *cpu_page;
47 static inline int ring_space(struct intel_ring_buffer *ring)
49 int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
56 render_ring_flush(struct intel_ring_buffer *ring,
57 u32 invalidate_domains,
60 struct drm_device *dev = ring->dev;
67 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
68 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
69 * also flushed at 2d versus 3d pipeline switches.
73 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
74 * MI_READ_FLUSH is set, and is always flushed on 965.
76 * I915_GEM_DOMAIN_COMMAND may not exist?
78 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
79 * invalidated when MI_EXE_FLUSH is set.
81 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
82 * invalidated with every MI_FLUSH.
86 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
87 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
88 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
89 * are flushed at any MI_FLUSH.
92 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
93 if ((invalidate_domains|flush_domains) &
94 I915_GEM_DOMAIN_RENDER)
95 cmd &= ~MI_NO_WRITE_FLUSH;
96 if (INTEL_INFO(dev)->gen < 4) {
98 * On the 965, the sampler cache always gets flushed
99 * and this bit is reserved.
101 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
102 cmd |= MI_READ_FLUSH;
104 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
107 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
108 (IS_G4X(dev) || IS_GEN5(dev)))
109 cmd |= MI_INVALIDATE_ISP;
111 ret = intel_ring_begin(ring, 2);
115 intel_ring_emit(ring, cmd);
116 intel_ring_emit(ring, MI_NOOP);
117 intel_ring_advance(ring);
123 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
124 * implementing two workarounds on gen6. From section 1.4.7.1
125 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
127 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
128 * produced by non-pipelined state commands), software needs to first
129 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
132 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
133 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
135 * And the workaround for these two requires this workaround first:
137 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
138 * BEFORE the pipe-control with a post-sync op and no write-cache
141 * And this last workaround is tricky because of the requirements on
142 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
145 * "1 of the following must also be set:
146 * - Render Target Cache Flush Enable ([12] of DW1)
147 * - Depth Cache Flush Enable ([0] of DW1)
148 * - Stall at Pixel Scoreboard ([1] of DW1)
149 * - Depth Stall ([13] of DW1)
150 * - Post-Sync Operation ([13] of DW1)
151 * - Notify Enable ([8] of DW1)"
153 * The cache flushes require the workaround flush that triggered this
154 * one, so we can't use it. Depth stall would trigger the same.
155 * Post-sync nonzero is what triggered this second workaround, so we
156 * can't use that one either. Notify enable is IRQs, which aren't
157 * really our business. That leaves only stall at scoreboard.
160 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
162 struct pipe_control *pc = ring->private;
163 u32 scratch_addr = pc->gtt_offset + 128;
167 ret = intel_ring_begin(ring, 6);
171 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
172 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
173 PIPE_CONTROL_STALL_AT_SCOREBOARD);
174 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
175 intel_ring_emit(ring, 0); /* low dword */
176 intel_ring_emit(ring, 0); /* high dword */
177 intel_ring_emit(ring, MI_NOOP);
178 intel_ring_advance(ring);
180 ret = intel_ring_begin(ring, 6);
184 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
185 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
186 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
187 intel_ring_emit(ring, 0);
188 intel_ring_emit(ring, 0);
189 intel_ring_emit(ring, MI_NOOP);
190 intel_ring_advance(ring);
196 gen6_render_ring_flush(struct intel_ring_buffer *ring,
197 u32 invalidate_domains, u32 flush_domains)
200 struct pipe_control *pc = ring->private;
201 u32 scratch_addr = pc->gtt_offset + 128;
204 /* Force SNB workarounds for PIPE_CONTROL flushes */
205 intel_emit_post_sync_nonzero_flush(ring);
207 /* Just flush everything. Experiments have shown that reducing the
208 * number of bits based on the write domains has little performance
211 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
212 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
213 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
214 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
215 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
216 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
217 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
219 ret = intel_ring_begin(ring, 6);
223 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
224 intel_ring_emit(ring, flags);
225 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
226 intel_ring_emit(ring, 0); /* lower dword */
227 intel_ring_emit(ring, 0); /* uppwer dword */
228 intel_ring_emit(ring, MI_NOOP);
229 intel_ring_advance(ring);
234 static void ring_write_tail(struct intel_ring_buffer *ring,
237 drm_i915_private_t *dev_priv = ring->dev->dev_private;
238 I915_WRITE_TAIL(ring, value);
241 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
243 drm_i915_private_t *dev_priv = ring->dev->dev_private;
244 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
245 RING_ACTHD(ring->mmio_base) : ACTHD;
247 return I915_READ(acthd_reg);
250 static int init_ring_common(struct intel_ring_buffer *ring)
252 drm_i915_private_t *dev_priv = ring->dev->dev_private;
253 struct drm_i915_gem_object *obj = ring->obj;
256 /* Stop the ring if it's running. */
257 I915_WRITE_CTL(ring, 0);
258 I915_WRITE_HEAD(ring, 0);
259 ring->write_tail(ring, 0);
261 /* Initialize the ring. */
262 I915_WRITE_START(ring, obj->gtt_offset);
263 head = I915_READ_HEAD(ring) & HEAD_ADDR;
265 /* G45 ring initialization fails to reset head to zero */
267 DRM_DEBUG_KMS("%s head not reset to zero "
268 "ctl %08x head %08x tail %08x start %08x\n",
271 I915_READ_HEAD(ring),
272 I915_READ_TAIL(ring),
273 I915_READ_START(ring));
275 I915_WRITE_HEAD(ring, 0);
277 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
278 DRM_ERROR("failed to set %s head to zero "
279 "ctl %08x head %08x tail %08x start %08x\n",
282 I915_READ_HEAD(ring),
283 I915_READ_TAIL(ring),
284 I915_READ_START(ring));
289 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
292 /* If the head is still not zero, the ring is dead */
293 if ((I915_READ_CTL(ring) & RING_VALID) == 0 ||
294 I915_READ_START(ring) != obj->gtt_offset ||
295 (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) {
296 DRM_ERROR("%s initialization failed "
297 "ctl %08x head %08x tail %08x start %08x\n",
300 I915_READ_HEAD(ring),
301 I915_READ_TAIL(ring),
302 I915_READ_START(ring));
306 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
307 i915_kernel_lost_context(ring->dev);
309 ring->head = I915_READ_HEAD(ring);
310 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
311 ring->space = ring_space(ring);
318 init_pipe_control(struct intel_ring_buffer *ring)
320 struct pipe_control *pc;
321 struct drm_i915_gem_object *obj;
327 pc = kmalloc(sizeof(*pc), GFP_KERNEL);
331 obj = i915_gem_alloc_object(ring->dev, 4096);
333 DRM_ERROR("Failed to allocate seqno page\n");
338 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
340 ret = i915_gem_object_pin(obj, 4096, true);
344 pc->gtt_offset = obj->gtt_offset;
345 pc->cpu_page = kmap(obj->pages[0]);
346 if (pc->cpu_page == NULL)
354 i915_gem_object_unpin(obj);
356 drm_gem_object_unreference(&obj->base);
363 cleanup_pipe_control(struct intel_ring_buffer *ring)
365 struct pipe_control *pc = ring->private;
366 struct drm_i915_gem_object *obj;
372 kunmap(obj->pages[0]);
373 i915_gem_object_unpin(obj);
374 drm_gem_object_unreference(&obj->base);
377 ring->private = NULL;
380 static int init_render_ring(struct intel_ring_buffer *ring)
382 struct drm_device *dev = ring->dev;
383 struct drm_i915_private *dev_priv = dev->dev_private;
384 int ret = init_ring_common(ring);
386 if (INTEL_INFO(dev)->gen > 3) {
387 int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
388 I915_WRITE(MI_MODE, mode);
390 I915_WRITE(GFX_MODE_GEN7,
391 GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
392 GFX_MODE_ENABLE(GFX_REPLAY_MODE));
395 if (INTEL_INFO(dev)->gen >= 5) {
396 ret = init_pipe_control(ring);
401 if (INTEL_INFO(dev)->gen >= 6) {
403 INSTPM_FORCE_ORDERING << 16 | INSTPM_FORCE_ORDERING);
405 /* From the Sandybridge PRM, volume 1 part 3, page 24:
406 * "If this bit is set, STCunit will have LRA as replacement
407 * policy. [...] This bit must be reset. LRA replacement
408 * policy is not supported."
410 I915_WRITE(CACHE_MODE_0,
411 CM0_STC_EVICT_DISABLE_LRA_SNB << CM0_MASK_SHIFT);
417 static void render_ring_cleanup(struct intel_ring_buffer *ring)
422 cleanup_pipe_control(ring);
426 update_mboxes(struct intel_ring_buffer *ring,
430 intel_ring_emit(ring, MI_SEMAPHORE_MBOX |
431 MI_SEMAPHORE_GLOBAL_GTT |
432 MI_SEMAPHORE_REGISTER |
433 MI_SEMAPHORE_UPDATE);
434 intel_ring_emit(ring, seqno);
435 intel_ring_emit(ring, mmio_offset);
439 * gen6_add_request - Update the semaphore mailbox registers
441 * @ring - ring that is adding a request
442 * @seqno - return seqno stuck into the ring
444 * Update the mailbox registers in the *other* rings with the current seqno.
445 * This acts like a signal in the canonical semaphore.
448 gen6_add_request(struct intel_ring_buffer *ring,
455 ret = intel_ring_begin(ring, 10);
459 mbox1_reg = ring->signal_mbox[0];
460 mbox2_reg = ring->signal_mbox[1];
462 *seqno = i915_gem_next_request_seqno(ring);
464 update_mboxes(ring, *seqno, mbox1_reg);
465 update_mboxes(ring, *seqno, mbox2_reg);
466 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
467 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
468 intel_ring_emit(ring, *seqno);
469 intel_ring_emit(ring, MI_USER_INTERRUPT);
470 intel_ring_advance(ring);
476 * intel_ring_sync - sync the waiter to the signaller on seqno
478 * @waiter - ring that is waiting
479 * @signaller - ring which has, or will signal
480 * @seqno - seqno which the waiter will block on
483 intel_ring_sync(struct intel_ring_buffer *waiter,
484 struct intel_ring_buffer *signaller,
489 u32 dw1 = MI_SEMAPHORE_MBOX |
490 MI_SEMAPHORE_COMPARE |
491 MI_SEMAPHORE_REGISTER;
493 ret = intel_ring_begin(waiter, 4);
497 intel_ring_emit(waiter, dw1 | signaller->semaphore_register[ring]);
498 intel_ring_emit(waiter, seqno);
499 intel_ring_emit(waiter, 0);
500 intel_ring_emit(waiter, MI_NOOP);
501 intel_ring_advance(waiter);
506 /* VCS->RCS (RVSYNC) or BCS->RCS (RBSYNC) */
508 render_ring_sync_to(struct intel_ring_buffer *waiter,
509 struct intel_ring_buffer *signaller,
512 WARN_ON(signaller->semaphore_register[RCS] == MI_SEMAPHORE_SYNC_INVALID);
513 return intel_ring_sync(waiter,
519 /* RCS->VCS (VRSYNC) or BCS->VCS (VBSYNC) */
521 gen6_bsd_ring_sync_to(struct intel_ring_buffer *waiter,
522 struct intel_ring_buffer *signaller,
525 WARN_ON(signaller->semaphore_register[VCS] == MI_SEMAPHORE_SYNC_INVALID);
526 return intel_ring_sync(waiter,
532 /* RCS->BCS (BRSYNC) or VCS->BCS (BVSYNC) */
534 gen6_blt_ring_sync_to(struct intel_ring_buffer *waiter,
535 struct intel_ring_buffer *signaller,
538 WARN_ON(signaller->semaphore_register[BCS] == MI_SEMAPHORE_SYNC_INVALID);
539 return intel_ring_sync(waiter,
547 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
549 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
550 PIPE_CONTROL_DEPTH_STALL); \
551 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
552 intel_ring_emit(ring__, 0); \
553 intel_ring_emit(ring__, 0); \
557 pc_render_add_request(struct intel_ring_buffer *ring,
560 u32 seqno = i915_gem_next_request_seqno(ring);
561 struct pipe_control *pc = ring->private;
562 u32 scratch_addr = pc->gtt_offset + 128;
565 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
566 * incoherent with writes to memory, i.e. completely fubar,
567 * so we need to use PIPE_NOTIFY instead.
569 * However, we also need to workaround the qword write
570 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
571 * memory before requesting an interrupt.
573 ret = intel_ring_begin(ring, 32);
577 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
578 PIPE_CONTROL_WRITE_FLUSH |
579 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
580 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
581 intel_ring_emit(ring, seqno);
582 intel_ring_emit(ring, 0);
583 PIPE_CONTROL_FLUSH(ring, scratch_addr);
584 scratch_addr += 128; /* write to separate cachelines */
585 PIPE_CONTROL_FLUSH(ring, scratch_addr);
587 PIPE_CONTROL_FLUSH(ring, scratch_addr);
589 PIPE_CONTROL_FLUSH(ring, scratch_addr);
591 PIPE_CONTROL_FLUSH(ring, scratch_addr);
593 PIPE_CONTROL_FLUSH(ring, scratch_addr);
595 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
596 PIPE_CONTROL_WRITE_FLUSH |
597 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
598 PIPE_CONTROL_NOTIFY);
599 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
600 intel_ring_emit(ring, seqno);
601 intel_ring_emit(ring, 0);
602 intel_ring_advance(ring);
609 render_ring_add_request(struct intel_ring_buffer *ring,
612 u32 seqno = i915_gem_next_request_seqno(ring);
615 ret = intel_ring_begin(ring, 4);
619 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
620 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
621 intel_ring_emit(ring, seqno);
622 intel_ring_emit(ring, MI_USER_INTERRUPT);
623 intel_ring_advance(ring);
630 gen6_ring_get_seqno(struct intel_ring_buffer *ring)
632 struct drm_device *dev = ring->dev;
634 /* Workaround to force correct ordering between irq and seqno writes on
635 * ivb (and maybe also on snb) by reading from a CS register (like
636 * ACTHD) before reading the status page. */
637 if (IS_GEN6(dev) || IS_GEN7(dev))
638 intel_ring_get_active_head(ring);
639 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
643 ring_get_seqno(struct intel_ring_buffer *ring)
645 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
649 pc_render_get_seqno(struct intel_ring_buffer *ring)
651 struct pipe_control *pc = ring->private;
652 return pc->cpu_page[0];
656 ironlake_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
658 dev_priv->gt_irq_mask &= ~mask;
659 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
664 ironlake_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
666 dev_priv->gt_irq_mask |= mask;
667 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
672 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
674 dev_priv->irq_mask &= ~mask;
675 I915_WRITE(IMR, dev_priv->irq_mask);
680 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
682 dev_priv->irq_mask |= mask;
683 I915_WRITE(IMR, dev_priv->irq_mask);
688 render_ring_get_irq(struct intel_ring_buffer *ring)
690 struct drm_device *dev = ring->dev;
691 drm_i915_private_t *dev_priv = dev->dev_private;
693 if (!dev->irq_enabled)
696 spin_lock(&ring->irq_lock);
697 if (ring->irq_refcount++ == 0) {
698 if (HAS_PCH_SPLIT(dev))
699 ironlake_enable_irq(dev_priv,
700 GT_PIPE_NOTIFY | GT_USER_INTERRUPT);
702 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
704 spin_unlock(&ring->irq_lock);
710 render_ring_put_irq(struct intel_ring_buffer *ring)
712 struct drm_device *dev = ring->dev;
713 drm_i915_private_t *dev_priv = dev->dev_private;
715 spin_lock(&ring->irq_lock);
716 if (--ring->irq_refcount == 0) {
717 if (HAS_PCH_SPLIT(dev))
718 ironlake_disable_irq(dev_priv,
722 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
724 spin_unlock(&ring->irq_lock);
727 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
729 struct drm_device *dev = ring->dev;
730 drm_i915_private_t *dev_priv = ring->dev->dev_private;
733 /* The ring status page addresses are no longer next to the rest of
734 * the ring registers as of gen7.
739 mmio = RENDER_HWS_PGA_GEN7;
742 mmio = BLT_HWS_PGA_GEN7;
745 mmio = BSD_HWS_PGA_GEN7;
748 } else if (IS_GEN6(ring->dev)) {
749 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
751 mmio = RING_HWS_PGA(ring->mmio_base);
754 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
759 bsd_ring_flush(struct intel_ring_buffer *ring,
760 u32 invalidate_domains,
765 ret = intel_ring_begin(ring, 2);
769 intel_ring_emit(ring, MI_FLUSH);
770 intel_ring_emit(ring, MI_NOOP);
771 intel_ring_advance(ring);
776 ring_add_request(struct intel_ring_buffer *ring,
782 ret = intel_ring_begin(ring, 4);
786 seqno = i915_gem_next_request_seqno(ring);
788 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
789 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
790 intel_ring_emit(ring, seqno);
791 intel_ring_emit(ring, MI_USER_INTERRUPT);
792 intel_ring_advance(ring);
799 gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
801 struct drm_device *dev = ring->dev;
802 drm_i915_private_t *dev_priv = dev->dev_private;
804 if (!dev->irq_enabled)
807 /* It looks like we need to prevent the gt from suspending while waiting
808 * for an notifiy irq, otherwise irqs seem to get lost on at least the
809 * blt/bsd rings on ivb. */
810 gen6_gt_force_wake_get(dev_priv);
812 spin_lock(&ring->irq_lock);
813 if (ring->irq_refcount++ == 0) {
814 ring->irq_mask &= ~rflag;
815 I915_WRITE_IMR(ring, ring->irq_mask);
816 ironlake_enable_irq(dev_priv, gflag);
818 spin_unlock(&ring->irq_lock);
824 gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
826 struct drm_device *dev = ring->dev;
827 drm_i915_private_t *dev_priv = dev->dev_private;
829 spin_lock(&ring->irq_lock);
830 if (--ring->irq_refcount == 0) {
831 ring->irq_mask |= rflag;
832 I915_WRITE_IMR(ring, ring->irq_mask);
833 ironlake_disable_irq(dev_priv, gflag);
835 spin_unlock(&ring->irq_lock);
837 gen6_gt_force_wake_put(dev_priv);
841 bsd_ring_get_irq(struct intel_ring_buffer *ring)
843 struct drm_device *dev = ring->dev;
844 drm_i915_private_t *dev_priv = dev->dev_private;
846 if (!dev->irq_enabled)
849 spin_lock(&ring->irq_lock);
850 if (ring->irq_refcount++ == 0) {
852 i915_enable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
854 ironlake_enable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
856 spin_unlock(&ring->irq_lock);
861 bsd_ring_put_irq(struct intel_ring_buffer *ring)
863 struct drm_device *dev = ring->dev;
864 drm_i915_private_t *dev_priv = dev->dev_private;
866 spin_lock(&ring->irq_lock);
867 if (--ring->irq_refcount == 0) {
869 i915_disable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
871 ironlake_disable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
873 spin_unlock(&ring->irq_lock);
877 ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
881 ret = intel_ring_begin(ring, 2);
885 intel_ring_emit(ring,
886 MI_BATCH_BUFFER_START | (2 << 6) |
887 MI_BATCH_NON_SECURE_I965);
888 intel_ring_emit(ring, offset);
889 intel_ring_advance(ring);
895 render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
898 struct drm_device *dev = ring->dev;
901 if (IS_I830(dev) || IS_845G(dev)) {
902 ret = intel_ring_begin(ring, 4);
906 intel_ring_emit(ring, MI_BATCH_BUFFER);
907 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
908 intel_ring_emit(ring, offset + len - 8);
909 intel_ring_emit(ring, 0);
911 ret = intel_ring_begin(ring, 2);
915 if (INTEL_INFO(dev)->gen >= 4) {
916 intel_ring_emit(ring,
917 MI_BATCH_BUFFER_START | (2 << 6) |
918 MI_BATCH_NON_SECURE_I965);
919 intel_ring_emit(ring, offset);
921 intel_ring_emit(ring,
922 MI_BATCH_BUFFER_START | (2 << 6));
923 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
926 intel_ring_advance(ring);
931 static void cleanup_status_page(struct intel_ring_buffer *ring)
933 drm_i915_private_t *dev_priv = ring->dev->dev_private;
934 struct drm_i915_gem_object *obj;
936 obj = ring->status_page.obj;
940 kunmap(obj->pages[0]);
941 i915_gem_object_unpin(obj);
942 drm_gem_object_unreference(&obj->base);
943 ring->status_page.obj = NULL;
945 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
948 static int init_status_page(struct intel_ring_buffer *ring)
950 struct drm_device *dev = ring->dev;
951 drm_i915_private_t *dev_priv = dev->dev_private;
952 struct drm_i915_gem_object *obj;
955 obj = i915_gem_alloc_object(dev, 4096);
957 DRM_ERROR("Failed to allocate status page\n");
962 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
964 ret = i915_gem_object_pin(obj, 4096, true);
969 ring->status_page.gfx_addr = obj->gtt_offset;
970 ring->status_page.page_addr = kmap(obj->pages[0]);
971 if (ring->status_page.page_addr == NULL) {
972 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
975 ring->status_page.obj = obj;
976 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
978 intel_ring_setup_status_page(ring);
979 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
980 ring->name, ring->status_page.gfx_addr);
985 i915_gem_object_unpin(obj);
987 drm_gem_object_unreference(&obj->base);
992 int intel_init_ring_buffer(struct drm_device *dev,
993 struct intel_ring_buffer *ring)
995 struct drm_i915_gem_object *obj;
999 INIT_LIST_HEAD(&ring->active_list);
1000 INIT_LIST_HEAD(&ring->request_list);
1001 INIT_LIST_HEAD(&ring->gpu_write_list);
1003 init_waitqueue_head(&ring->irq_queue);
1004 spin_lock_init(&ring->irq_lock);
1005 ring->irq_mask = ~0;
1007 if (I915_NEED_GFX_HWS(dev)) {
1008 ret = init_status_page(ring);
1013 obj = i915_gem_alloc_object(dev, ring->size);
1015 DRM_ERROR("Failed to allocate ringbuffer\n");
1022 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
1026 ring->map.size = ring->size;
1027 ring->map.offset = dev->agp->base + obj->gtt_offset;
1029 ring->map.flags = 0;
1032 drm_core_ioremap_wc(&ring->map, dev);
1033 if (ring->map.handle == NULL) {
1034 DRM_ERROR("Failed to map ringbuffer.\n");
1039 ring->virtual_start = ring->map.handle;
1040 ret = ring->init(ring);
1044 /* Workaround an erratum on the i830 which causes a hang if
1045 * the TAIL pointer points to within the last 2 cachelines
1048 ring->effective_size = ring->size;
1049 if (IS_I830(ring->dev) || IS_845G(ring->dev))
1050 ring->effective_size -= 128;
1055 drm_core_ioremapfree(&ring->map, dev);
1057 i915_gem_object_unpin(obj);
1059 drm_gem_object_unreference(&obj->base);
1062 cleanup_status_page(ring);
1066 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1068 struct drm_i915_private *dev_priv;
1071 if (ring->obj == NULL)
1074 /* Disable the ring buffer. The ring must be idle at this point */
1075 dev_priv = ring->dev->dev_private;
1076 ret = intel_wait_ring_idle(ring);
1078 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1081 I915_WRITE_CTL(ring, 0);
1083 drm_core_ioremapfree(&ring->map, ring->dev);
1085 i915_gem_object_unpin(ring->obj);
1086 drm_gem_object_unreference(&ring->obj->base);
1090 ring->cleanup(ring);
1092 cleanup_status_page(ring);
1095 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1098 int rem = ring->size - ring->tail;
1100 if (ring->space < rem) {
1101 int ret = intel_wait_ring_buffer(ring, rem);
1106 virt = (unsigned int *)(ring->virtual_start + ring->tail);
1114 ring->space = ring_space(ring);
1119 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1121 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1122 bool was_interruptible;
1125 /* XXX As we have not yet audited all the paths to check that
1126 * they are ready for ERESTARTSYS from intel_ring_begin, do not
1127 * allow us to be interruptible by a signal.
1129 was_interruptible = dev_priv->mm.interruptible;
1130 dev_priv->mm.interruptible = false;
1132 ret = i915_wait_request(ring, seqno, true);
1134 dev_priv->mm.interruptible = was_interruptible;
1139 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1141 struct drm_i915_gem_request *request;
1145 i915_gem_retire_requests_ring(ring);
1147 if (ring->last_retired_head != -1) {
1148 ring->head = ring->last_retired_head;
1149 ring->last_retired_head = -1;
1150 ring->space = ring_space(ring);
1151 if (ring->space >= n)
1155 list_for_each_entry(request, &ring->request_list, list) {
1158 if (request->tail == -1)
1161 space = request->tail - (ring->tail + 8);
1163 space += ring->size;
1165 seqno = request->seqno;
1169 /* Consume this request in case we need more space than
1170 * is available and so need to prevent a race between
1171 * updating last_retired_head and direct reads of
1172 * I915_RING_HEAD. It also provides a nice sanity check.
1180 ret = intel_ring_wait_seqno(ring, seqno);
1184 if (WARN_ON(ring->last_retired_head == -1))
1187 ring->head = ring->last_retired_head;
1188 ring->last_retired_head = -1;
1189 ring->space = ring_space(ring);
1190 if (WARN_ON(ring->space < n))
1196 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
1198 struct drm_device *dev = ring->dev;
1199 struct drm_i915_private *dev_priv = dev->dev_private;
1203 ret = intel_ring_wait_request(ring, n);
1207 trace_i915_ring_wait_begin(ring);
1208 if (drm_core_check_feature(dev, DRIVER_GEM))
1209 /* With GEM the hangcheck timer should kick us out of the loop,
1210 * leaving it early runs the risk of corrupting GEM state (due
1211 * to running on almost untested codepaths). But on resume
1212 * timers don't work yet, so prevent a complete hang in that
1213 * case by choosing an insanely large timeout. */
1214 end = jiffies + 60 * HZ;
1216 end = jiffies + 3 * HZ;
1219 ring->head = I915_READ_HEAD(ring);
1220 ring->space = ring_space(ring);
1221 if (ring->space >= n) {
1222 trace_i915_ring_wait_end(ring);
1226 if (dev->primary->master) {
1227 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1228 if (master_priv->sarea_priv)
1229 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1233 if (atomic_read(&dev_priv->mm.wedged))
1235 } while (!time_after(jiffies, end));
1236 trace_i915_ring_wait_end(ring);
1240 int intel_ring_begin(struct intel_ring_buffer *ring,
1243 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1244 int n = 4*num_dwords;
1247 if (unlikely(atomic_read(&dev_priv->mm.wedged)))
1250 if (unlikely(ring->tail + n > ring->effective_size)) {
1251 ret = intel_wrap_ring_buffer(ring);
1256 if (unlikely(ring->space < n)) {
1257 ret = intel_wait_ring_buffer(ring, n);
1266 void intel_ring_advance(struct intel_ring_buffer *ring)
1268 ring->tail &= ring->size - 1;
1269 ring->write_tail(ring, ring->tail);
1272 static const struct intel_ring_buffer render_ring = {
1273 .name = "render ring",
1275 .mmio_base = RENDER_RING_BASE,
1276 .size = 32 * PAGE_SIZE,
1277 .init = init_render_ring,
1278 .write_tail = ring_write_tail,
1279 .flush = render_ring_flush,
1280 .add_request = render_ring_add_request,
1281 .get_seqno = ring_get_seqno,
1282 .irq_get = render_ring_get_irq,
1283 .irq_put = render_ring_put_irq,
1284 .dispatch_execbuffer = render_ring_dispatch_execbuffer,
1285 .cleanup = render_ring_cleanup,
1286 .sync_to = render_ring_sync_to,
1287 .semaphore_register = {MI_SEMAPHORE_SYNC_INVALID,
1288 MI_SEMAPHORE_SYNC_RV,
1289 MI_SEMAPHORE_SYNC_RB},
1290 .signal_mbox = {GEN6_VRSYNC, GEN6_BRSYNC},
1293 /* ring buffer for bit-stream decoder */
1295 static const struct intel_ring_buffer bsd_ring = {
1298 .mmio_base = BSD_RING_BASE,
1299 .size = 32 * PAGE_SIZE,
1300 .init = init_ring_common,
1301 .write_tail = ring_write_tail,
1302 .flush = bsd_ring_flush,
1303 .add_request = ring_add_request,
1304 .get_seqno = ring_get_seqno,
1305 .irq_get = bsd_ring_get_irq,
1306 .irq_put = bsd_ring_put_irq,
1307 .dispatch_execbuffer = ring_dispatch_execbuffer,
1311 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1314 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1316 /* Every tail move must follow the sequence below */
1317 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1318 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1319 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
1320 I915_WRITE(GEN6_BSD_RNCID, 0x0);
1322 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1323 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
1325 DRM_ERROR("timed out waiting for IDLE Indicator\n");
1327 I915_WRITE_TAIL(ring, value);
1328 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1329 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1330 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
1333 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1334 u32 invalidate, u32 flush)
1339 ret = intel_ring_begin(ring, 4);
1344 if (invalidate & I915_GEM_GPU_DOMAINS)
1345 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1346 intel_ring_emit(ring, cmd);
1347 intel_ring_emit(ring, 0);
1348 intel_ring_emit(ring, 0);
1349 intel_ring_emit(ring, MI_NOOP);
1350 intel_ring_advance(ring);
1355 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1356 u32 offset, u32 len)
1360 ret = intel_ring_begin(ring, 2);
1364 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1365 /* bit0-7 is the length on GEN6+ */
1366 intel_ring_emit(ring, offset);
1367 intel_ring_advance(ring);
1373 gen6_render_ring_get_irq(struct intel_ring_buffer *ring)
1375 return gen6_ring_get_irq(ring,
1377 GEN6_RENDER_USER_INTERRUPT);
1381 gen6_render_ring_put_irq(struct intel_ring_buffer *ring)
1383 return gen6_ring_put_irq(ring,
1385 GEN6_RENDER_USER_INTERRUPT);
1389 gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring)
1391 return gen6_ring_get_irq(ring,
1392 GT_GEN6_BSD_USER_INTERRUPT,
1393 GEN6_BSD_USER_INTERRUPT);
1397 gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring)
1399 return gen6_ring_put_irq(ring,
1400 GT_GEN6_BSD_USER_INTERRUPT,
1401 GEN6_BSD_USER_INTERRUPT);
1404 /* ring buffer for Video Codec for Gen6+ */
1405 static const struct intel_ring_buffer gen6_bsd_ring = {
1406 .name = "gen6 bsd ring",
1408 .mmio_base = GEN6_BSD_RING_BASE,
1409 .size = 32 * PAGE_SIZE,
1410 .init = init_ring_common,
1411 .write_tail = gen6_bsd_ring_write_tail,
1412 .flush = gen6_ring_flush,
1413 .add_request = gen6_add_request,
1414 .get_seqno = gen6_ring_get_seqno,
1415 .irq_get = gen6_bsd_ring_get_irq,
1416 .irq_put = gen6_bsd_ring_put_irq,
1417 .dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
1418 .sync_to = gen6_bsd_ring_sync_to,
1419 .semaphore_register = {MI_SEMAPHORE_SYNC_VR,
1420 MI_SEMAPHORE_SYNC_INVALID,
1421 MI_SEMAPHORE_SYNC_VB},
1422 .signal_mbox = {GEN6_RVSYNC, GEN6_BVSYNC},
1425 /* Blitter support (SandyBridge+) */
1428 blt_ring_get_irq(struct intel_ring_buffer *ring)
1430 return gen6_ring_get_irq(ring,
1431 GT_BLT_USER_INTERRUPT,
1432 GEN6_BLITTER_USER_INTERRUPT);
1436 blt_ring_put_irq(struct intel_ring_buffer *ring)
1438 gen6_ring_put_irq(ring,
1439 GT_BLT_USER_INTERRUPT,
1440 GEN6_BLITTER_USER_INTERRUPT);
1443 static int blt_ring_flush(struct intel_ring_buffer *ring,
1444 u32 invalidate, u32 flush)
1449 ret = intel_ring_begin(ring, 4);
1454 if (invalidate & I915_GEM_DOMAIN_RENDER)
1455 cmd |= MI_INVALIDATE_TLB;
1456 intel_ring_emit(ring, cmd);
1457 intel_ring_emit(ring, 0);
1458 intel_ring_emit(ring, 0);
1459 intel_ring_emit(ring, MI_NOOP);
1460 intel_ring_advance(ring);
1464 static const struct intel_ring_buffer gen6_blt_ring = {
1467 .mmio_base = BLT_RING_BASE,
1468 .size = 32 * PAGE_SIZE,
1469 .init = init_ring_common,
1470 .write_tail = ring_write_tail,
1471 .flush = blt_ring_flush,
1472 .add_request = gen6_add_request,
1473 .get_seqno = gen6_ring_get_seqno,
1474 .irq_get = blt_ring_get_irq,
1475 .irq_put = blt_ring_put_irq,
1476 .dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
1477 .sync_to = gen6_blt_ring_sync_to,
1478 .semaphore_register = {MI_SEMAPHORE_SYNC_BR,
1479 MI_SEMAPHORE_SYNC_BV,
1480 MI_SEMAPHORE_SYNC_INVALID},
1481 .signal_mbox = {GEN6_RBSYNC, GEN6_VBSYNC},
1484 int intel_init_render_ring_buffer(struct drm_device *dev)
1486 drm_i915_private_t *dev_priv = dev->dev_private;
1487 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1489 *ring = render_ring;
1490 if (INTEL_INFO(dev)->gen >= 6) {
1491 ring->add_request = gen6_add_request;
1492 ring->flush = gen6_render_ring_flush;
1493 ring->irq_get = gen6_render_ring_get_irq;
1494 ring->irq_put = gen6_render_ring_put_irq;
1495 ring->get_seqno = gen6_ring_get_seqno;
1496 } else if (IS_GEN5(dev)) {
1497 ring->add_request = pc_render_add_request;
1498 ring->get_seqno = pc_render_get_seqno;
1501 if (!I915_NEED_GFX_HWS(dev)) {
1502 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1503 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1506 return intel_init_ring_buffer(dev, ring);
1509 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1511 drm_i915_private_t *dev_priv = dev->dev_private;
1512 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1514 *ring = render_ring;
1515 if (INTEL_INFO(dev)->gen >= 6) {
1516 ring->add_request = gen6_add_request;
1517 ring->irq_get = gen6_render_ring_get_irq;
1518 ring->irq_put = gen6_render_ring_put_irq;
1519 } else if (IS_GEN5(dev)) {
1520 ring->add_request = pc_render_add_request;
1521 ring->get_seqno = pc_render_get_seqno;
1524 if (!I915_NEED_GFX_HWS(dev))
1525 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1528 INIT_LIST_HEAD(&ring->active_list);
1529 INIT_LIST_HEAD(&ring->request_list);
1530 INIT_LIST_HEAD(&ring->gpu_write_list);
1533 ring->effective_size = ring->size;
1534 if (IS_I830(ring->dev))
1535 ring->effective_size -= 128;
1537 ring->map.offset = start;
1538 ring->map.size = size;
1540 ring->map.flags = 0;
1543 drm_core_ioremap_wc(&ring->map, dev);
1544 if (ring->map.handle == NULL) {
1545 DRM_ERROR("can not ioremap virtual address for"
1550 ring->virtual_start = (void __force __iomem *)ring->map.handle;
1554 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1556 drm_i915_private_t *dev_priv = dev->dev_private;
1557 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1559 if (IS_GEN6(dev) || IS_GEN7(dev))
1560 *ring = gen6_bsd_ring;
1564 return intel_init_ring_buffer(dev, ring);
1567 int intel_init_blt_ring_buffer(struct drm_device *dev)
1569 drm_i915_private_t *dev_priv = dev->dev_private;
1570 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1572 *ring = gen6_blt_ring;
1574 return intel_init_ring_buffer(dev, ring);