drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include "i915_drv.h"
  32 #include <drm/i915_drm.h>
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35
  36 /*
  37  * 965+ support PIPE_CONTROL commands, which provide finer grained control
  38  * over cache flushing.
  39  */
  40 struct pipe_control {
  41         struct drm_i915_gem_object *obj;
  42         volatile u32 *cpu_page;
  43         u32 gtt_offset;
  44 };
  45
  46 static inline int ring_space(struct intel_ring_buffer *ring)
  47 {
  48         int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE);
  49         if (space < 0)
  50                 space += ring->size;
  51         return space;
  52 }
  53
  54 static int
  55 gen2_render_ring_flush(struct intel_ring_buffer *ring,
  56                        u32      invalidate_domains,
  57                        u32      flush_domains)
  58 {
  59         u32 cmd;
  60         int ret;
  61
  62         cmd = MI_FLUSH;
  63         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
  64                 cmd |= MI_NO_WRITE_FLUSH;
  65
  66         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
  67                 cmd |= MI_READ_FLUSH;
  68
  69         ret = intel_ring_begin(ring, 2);
  70         if (ret)
  71                 return ret;
  72
  73         intel_ring_emit(ring, cmd);
  74         intel_ring_emit(ring, MI_NOOP);
  75         intel_ring_advance(ring);
  76
  77         return 0;
  78 }
  79
  80 static int
  81 gen4_render_ring_flush(struct intel_ring_buffer *ring,
  82                        u32      invalidate_domains,
  83                        u32      flush_domains)
  84 {
  85         struct drm_device *dev = ring->dev;
  86         u32 cmd;
  87         int ret;
  88
  89         /*
  90          * read/write caches:
  91          *
  92          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
  93          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
  94          * also flushed at 2d versus 3d pipeline switches.
  95          *
  96          * read-only caches:
  97          *
  98          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
  99          * MI_READ_FLUSH is set, and is always flushed on 965.
 100          *
 101          * I915_GEM_DOMAIN_COMMAND may not exist?
 102          *
 103          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 104          * invalidated when MI_EXE_FLUSH is set.
 105          *
 106          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 107          * invalidated with every MI_FLUSH.
 108          *
 109          * TLBs:
 110          *
 111          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 112          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 113          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 114          * are flushed at any MI_FLUSH.
 115          */
 116
 117         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 118         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 119                 cmd &= ~MI_NO_WRITE_FLUSH;
 120         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 121                 cmd |= MI_EXE_FLUSH;
 122
 123         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 124             (IS_G4X(dev) || IS_GEN5(dev)))
 125                 cmd |= MI_INVALIDATE_ISP;
 126
 127         ret = intel_ring_begin(ring, 2);
 128         if (ret)
 129                 return ret;
 130
 131         intel_ring_emit(ring, cmd);
 132         intel_ring_emit(ring, MI_NOOP);
 133         intel_ring_advance(ring);
 134
 135         return 0;
 136 }
 137
 138 /**
 139  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 140  * implementing two workarounds on gen6.  From section 1.4.7.1
 141  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 142  *
 143  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 144  * produced by non-pipelined state commands), software needs to first
 145  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 146  * 0.
 147  *
 148  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 149  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 150  *
 151  * And the workaround for these two requires this workaround first:
 152  *
 153  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 154  * BEFORE the pipe-control with a post-sync op and no write-cache
 155  * flushes.
 156  *
 157  * And this last workaround is tricky because of the requirements on
 158  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 159  * volume 2 part 1:
 160  *
 161  *     "1 of the following must also be set:
 162  *      - Render Target Cache Flush Enable ([12] of DW1)
 163  *      - Depth Cache Flush Enable ([0] of DW1)
 164  *      - Stall at Pixel Scoreboard ([1] of DW1)
 165  *      - Depth Stall ([13] of DW1)
 166  *      - Post-Sync Operation ([13] of DW1)
 167  *      - Notify Enable ([8] of DW1)"
 168  *
 169  * The cache flushes require the workaround flush that triggered this
 170  * one, so we can't use it.  Depth stall would trigger the same.
 171  * Post-sync nonzero is what triggered this second workaround, so we
 172  * can't use that one either.  Notify enable is IRQs, which aren't
 173  * really our business.  That leaves only stall at scoreboard.
 174  */
 175 static int
 176 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
 177 {
 178         struct pipe_control *pc = ring->private;
 179         u32 scratch_addr = pc->gtt_offset + 128;
 180         int ret;
 181
 182
 183         ret = intel_ring_begin(ring, 6);
 184         if (ret)
 185                 return ret;
 186
 187         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 188         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 189                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 190         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 191         intel_ring_emit(ring, 0); /* low dword */
 192         intel_ring_emit(ring, 0); /* high dword */
 193         intel_ring_emit(ring, MI_NOOP);
 194         intel_ring_advance(ring);
 195
 196         ret = intel_ring_begin(ring, 6);
 197         if (ret)
 198                 return ret;
 199
 200         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 201         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 202         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 203         intel_ring_emit(ring, 0);
 204         intel_ring_emit(ring, 0);
 205         intel_ring_emit(ring, MI_NOOP);
 206         intel_ring_advance(ring);
 207
 208         return 0;
 209 }
 210
 211 static int
 212 gen6_render_ring_flush(struct intel_ring_buffer *ring,
 213                          u32 invalidate_domains, u32 flush_domains)
 214 {
 215         u32 flags = 0;
 216         struct pipe_control *pc = ring->private;
 217         u32 scratch_addr = pc->gtt_offset + 128;
 218         int ret;
 219
 220         /* Force SNB workarounds for PIPE_CONTROL flushes */
 221         ret = intel_emit_post_sync_nonzero_flush(ring);
 222         if (ret)
 223                 return ret;
 224
 225         /* Just flush everything.  Experiments have shown that reducing the
 226          * number of bits based on the write domains has little performance
 227          * impact.
 228          */
 229         if (flush_domains) {
 230                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 231                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 232                 /*
 233                  * Ensure that any following seqno writes only happen
 234                  * when the render cache is indeed flushed.
 235                  */
 236                 flags |= PIPE_CONTROL_CS_STALL;
 237         }
 238         if (invalidate_domains) {
 239                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 240                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 241                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 242                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 243                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 244                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 245                 /*
 246                  * TLB invalidate requires a post-sync write.
 247                  */
 248                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 249         }
 250
 251         ret = intel_ring_begin(ring, 4);
 252         if (ret)
 253                 return ret;
 254
 255         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 256         intel_ring_emit(ring, flags);
 257         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 258         intel_ring_emit(ring, 0);
 259         intel_ring_advance(ring);
 260
 261         return 0;
 262 }
 263
 264 static int
 265 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
 266 {
 267         int ret;
 268
 269         ret = intel_ring_begin(ring, 4);
 270         if (ret)
 271                 return ret;
 272
 273         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 274         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 275                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 276         intel_ring_emit(ring, 0);
 277         intel_ring_emit(ring, 0);
 278         intel_ring_advance(ring);
 279
 280         return 0;
 281 }
 282
 283 static int
 284 gen7_render_ring_flush(struct intel_ring_buffer *ring,
 285                        u32 invalidate_domains, u32 flush_domains)
 286 {
 287         u32 flags = 0;
 288         struct pipe_control *pc = ring->private;
 289         u32 scratch_addr = pc->gtt_offset + 128;
 290         int ret;
 291
 292         /*
 293          * Ensure that any following seqno writes only happen when the render
 294          * cache is indeed flushed.
 295          *
 296          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 297          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 298          * don't try to be clever and just set it unconditionally.
 299          */
 300         flags |= PIPE_CONTROL_CS_STALL;
 301
 302         /* Just flush everything.  Experiments have shown that reducing the
 303          * number of bits based on the write domains has little performance
 304          * impact.
 305          */
 306         if (flush_domains) {
 307                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 308                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 309         }
 310         if (invalidate_domains) {
 311                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 312                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 313                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 314                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 315                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 316                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 317                 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
 318                 /*
 319                  * TLB invalidate requires a post-sync write.
 320                  */
 321                 flags |= PIPE_CONTROL_QW_WRITE;
 322                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 323
 324                 /* Workaround: we must issue a pipe_control with CS-stall bit
 325                  * set before a pipe_control command that has the state cache
 326                  * invalidate bit set. */
 327                 gen7_render_ring_cs_stall_wa(ring);
 328         }
 329
 330         ret = intel_ring_begin(ring, 4);
 331         if (ret)
 332                 return ret;
 333
 334         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 335         intel_ring_emit(ring, flags);
 336         intel_ring_emit(ring, scratch_addr);
 337         intel_ring_emit(ring, 0);
 338         intel_ring_advance(ring);
 339
 340         return 0;
 341 }
 342
 343 static void ring_write_tail(struct intel_ring_buffer *ring,
 344                             u32 value)
 345 {
 346         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 347         I915_WRITE_TAIL(ring, value);
 348 }
 349
 350 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
 351 {
 352         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 353         u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
 354                         RING_ACTHD(ring->mmio_base) : ACTHD;
 355
 356         return I915_READ(acthd_reg);
 357 }
 358
 359 static int init_ring_common(struct intel_ring_buffer *ring)
 360 {
 361         struct drm_device *dev = ring->dev;
 362         drm_i915_private_t *dev_priv = dev->dev_private;
 363         struct drm_i915_gem_object *obj = ring->obj;
 364         int ret = 0;
 365         u32 head;
 366
 367         if (HAS_FORCE_WAKE(dev))
 368                 gen6_gt_force_wake_get(dev_priv);
 369
 370         /* Stop the ring if it's running. */
 371         I915_WRITE_CTL(ring, 0);
 372         I915_WRITE_HEAD(ring, 0);
 373         ring->write_tail(ring, 0);
 374
 375         head = I915_READ_HEAD(ring) & HEAD_ADDR;
 376
 377         /* G45 ring initialization fails to reset head to zero */
 378         if (head != 0) {
 379                 DRM_DEBUG_KMS("%s head not reset to zero "
 380                               "ctl %08x head %08x tail %08x start %08x\n",
 381                               ring->name,
 382                               I915_READ_CTL(ring),
 383                               I915_READ_HEAD(ring),
 384                               I915_READ_TAIL(ring),
 385                               I915_READ_START(ring));
 386
 387                 I915_WRITE_HEAD(ring, 0);
 388
 389                 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
 390                         DRM_ERROR("failed to set %s head to zero "
 391                                   "ctl %08x head %08x tail %08x start %08x\n",
 392                                   ring->name,
 393                                   I915_READ_CTL(ring),
 394                                   I915_READ_HEAD(ring),
 395                                   I915_READ_TAIL(ring),
 396                                   I915_READ_START(ring));
 397                 }
 398         }
 399
 400         /* Enforce ordering by reading HEAD register back */
 401         I915_READ_HEAD(ring);
 402
 403         /* Initialize the ring. This must happen _after_ we've cleared the ring
 404          * registers with the above sequence (the readback of the HEAD registers
 405          * also enforces ordering), otherwise the hw might lose the new ring
 406          * register values. */
 407         I915_WRITE_START(ring, obj->gtt_offset);
 408         I915_WRITE_CTL(ring,
 409                         ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
 410                         | RING_VALID);
 411
 412         /* If the head is still not zero, the ring is dead */
 413         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 414                      I915_READ_START(ring) == obj->gtt_offset &&
 415                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 416                 DRM_ERROR("%s initialization failed "
 417                                 "ctl %08x head %08x tail %08x start %08x\n",
 418                                 ring->name,
 419                                 I915_READ_CTL(ring),
 420                                 I915_READ_HEAD(ring),
 421                                 I915_READ_TAIL(ring),
 422                                 I915_READ_START(ring));
 423                 ret = -EIO;
 424                 goto out;
 425         }
 426
 427         if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
 428                 i915_kernel_lost_context(ring->dev);
 429         else {
 430                 ring->head = I915_READ_HEAD(ring);
 431                 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 432                 ring->space = ring_space(ring);
 433                 ring->last_retired_head = -1;
 434         }
 435
 436 out:
 437         if (HAS_FORCE_WAKE(dev))
 438                 gen6_gt_force_wake_put(dev_priv);
 439
 440         return ret;
 441 }
 442
 443 static int
 444 init_pipe_control(struct intel_ring_buffer *ring)
 445 {
 446         struct pipe_control *pc;
 447         struct drm_i915_gem_object *obj;
 448         int ret;
 449
 450         if (ring->private)
 451                 return 0;
 452
 453         pc = kmalloc(sizeof(*pc), GFP_KERNEL);
 454         if (!pc)
 455                 return -ENOMEM;
 456
 457         obj = i915_gem_alloc_object(ring->dev, 4096);
 458         if (obj == NULL) {
 459                 DRM_ERROR("Failed to allocate seqno page\n");
 460                 ret = -ENOMEM;
 461                 goto err;
 462         }
 463
 464         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
 465
 466         ret = i915_gem_object_pin(obj, 4096, true, false);
 467         if (ret)
 468                 goto err_unref;
 469
 470         pc->gtt_offset = obj->gtt_offset;
 471         pc->cpu_page =  kmap(sg_page(obj->pages->sgl));
 472         if (pc->cpu_page == NULL)
 473                 goto err_unpin;
 474
 475         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 476                          ring->name, pc->gtt_offset);
 477
 478         pc->obj = obj;
 479         ring->private = pc;
 480         return 0;
 481
 482 err_unpin:
 483         i915_gem_object_unpin(obj);
 484 err_unref:
 485         drm_gem_object_unreference(&obj->base);
 486 err:
 487         kfree(pc);
 488         return ret;
 489 }
 490
 491 static void
 492 cleanup_pipe_control(struct intel_ring_buffer *ring)
 493 {
 494         struct pipe_control *pc = ring->private;
 495         struct drm_i915_gem_object *obj;
 496
 497         obj = pc->obj;
 498
 499         kunmap(sg_page(obj->pages->sgl));
 500         i915_gem_object_unpin(obj);
 501         drm_gem_object_unreference(&obj->base);
 502
 503         kfree(pc);
 504 }
 505
 506 static int init_render_ring(struct intel_ring_buffer *ring)
 507 {
 508         struct drm_device *dev = ring->dev;
 509         struct drm_i915_private *dev_priv = dev->dev_private;
 510         int ret = init_ring_common(ring);
 511
 512         if (INTEL_INFO(dev)->gen > 3)
 513                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
 514
 515         /* We need to disable the AsyncFlip performance optimisations in order
 516          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
 517          * programmed to '1' on all products.
 518          */
 519         if (INTEL_INFO(dev)->gen >= 6)
 520                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
 521
 522         /* Required for the hardware to program scanline values for waiting */
 523         if (INTEL_INFO(dev)->gen == 6)
 524                 I915_WRITE(GFX_MODE,
 525                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
 526
 527         if (IS_GEN7(dev))
 528                 I915_WRITE(GFX_MODE_GEN7,
 529                            _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
 530                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
 531
 532         if (INTEL_INFO(dev)->gen >= 5) {
 533                 ret = init_pipe_control(ring);
 534                 if (ret)
 535                         return ret;
 536         }
 537
 538         if (IS_GEN6(dev)) {
 539                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
 540                  * "If this bit is set, STCunit will have LRA as replacement
 541                  *  policy. [...] This bit must be reset.  LRA replacement
 542                  *  policy is not supported."
 543                  */
 544                 I915_WRITE(CACHE_MODE_0,
 545                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
 546
 547                 /* This is not explicitly set for GEN6, so read the register.
 548                  * see intel_ring_mi_set_context() for why we care.
 549                  * TODO: consider explicitly setting the bit for GEN5
 550                  */
 551                 ring->itlb_before_ctx_switch =
 552                         !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
 553         }
 554
 555         if (INTEL_INFO(dev)->gen >= 6)
 556                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 557
 558         if (HAS_L3_GPU_CACHE(dev))
 559                 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
 560
 561         return ret;
 562 }
 563
 564 static void render_ring_cleanup(struct intel_ring_buffer *ring)
 565 {
 566         struct drm_device *dev = ring->dev;
 567
 568         if (!ring->private)
 569                 return;
 570
 571         if (HAS_BROKEN_CS_TLB(dev))
 572                 drm_gem_object_unreference(to_gem_object(ring->private));
 573
 574         if (INTEL_INFO(dev)->gen >= 5)
 575                 cleanup_pipe_control(ring);
 576
 577         ring->private = NULL;
 578 }
 579
 580 static void
 581 update_mboxes(struct intel_ring_buffer *ring,
 582               u32 mmio_offset)
 583 {
 584         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 585         intel_ring_emit(ring, mmio_offset);
 586         intel_ring_emit(ring, ring->outstanding_lazy_request);
 587 }
 588
 589 /**
 590  * gen6_add_request - Update the semaphore mailbox registers
 591  *
 592  * @ring - ring that is adding a request
 593  * @seqno - return seqno stuck into the ring
 594  *
 595  * Update the mailbox registers in the *other* rings with the current seqno.
 596  * This acts like a signal in the canonical semaphore.
 597  */
 598 static int
 599 gen6_add_request(struct intel_ring_buffer *ring)
 600 {
 601         u32 mbox1_reg;
 602         u32 mbox2_reg;
 603         int ret;
 604
 605         ret = intel_ring_begin(ring, 10);
 606         if (ret)
 607                 return ret;
 608
 609         mbox1_reg = ring->signal_mbox[0];
 610         mbox2_reg = ring->signal_mbox[1];
 611
 612         update_mboxes(ring, mbox1_reg);
 613         update_mboxes(ring, mbox2_reg);
 614         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 615         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 616         intel_ring_emit(ring, ring->outstanding_lazy_request);
 617         intel_ring_emit(ring, MI_USER_INTERRUPT);
 618         intel_ring_advance(ring);
 619
 620         return 0;
 621 }
 622
 623 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
 624                                               u32 seqno)
 625 {
 626         struct drm_i915_private *dev_priv = dev->dev_private;
 627         return dev_priv->last_seqno < seqno;
 628 }
 629
 630 /**
 631  * intel_ring_sync - sync the waiter to the signaller on seqno
 632  *
 633  * @waiter - ring that is waiting
 634  * @signaller - ring which has, or will signal
 635  * @seqno - seqno which the waiter will block on
 636  */
 637 static int
 638 gen6_ring_sync(struct intel_ring_buffer *waiter,
 639                struct intel_ring_buffer *signaller,
 640                u32 seqno)
 641 {
 642         int ret;
 643         u32 dw1 = MI_SEMAPHORE_MBOX |
 644                   MI_SEMAPHORE_COMPARE |
 645                   MI_SEMAPHORE_REGISTER;
 646
 647         /* Throughout all of the GEM code, seqno passed implies our current
 648          * seqno is >= the last seqno executed. However for hardware the
 649          * comparison is strictly greater than.
 650          */
 651         seqno -= 1;
 652
 653         WARN_ON(signaller->semaphore_register[waiter->id] ==
 654                 MI_SEMAPHORE_SYNC_INVALID);
 655
 656         ret = intel_ring_begin(waiter, 4);
 657         if (ret)
 658                 return ret;
 659
 660         /* If seqno wrap happened, omit the wait with no-ops */
 661         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
 662                 intel_ring_emit(waiter,
 663                                 dw1 |
 664                                 signaller->semaphore_register[waiter->id]);
 665                 intel_ring_emit(waiter, seqno);
 666                 intel_ring_emit(waiter, 0);
 667                 intel_ring_emit(waiter, MI_NOOP);
 668         } else {
 669                 intel_ring_emit(waiter, MI_NOOP);
 670                 intel_ring_emit(waiter, MI_NOOP);
 671                 intel_ring_emit(waiter, MI_NOOP);
 672                 intel_ring_emit(waiter, MI_NOOP);
 673         }
 674         intel_ring_advance(waiter);
 675
 676         return 0;
 677 }
 678
 679 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
 680 do {                                                                    \
 681         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
 682                  PIPE_CONTROL_DEPTH_STALL);                             \
 683         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
 684         intel_ring_emit(ring__, 0);                                                     \
 685         intel_ring_emit(ring__, 0);                                                     \
 686 } while (0)
 687
 688 static int
 689 pc_render_add_request(struct intel_ring_buffer *ring)
 690 {
 691         struct pipe_control *pc = ring->private;
 692         u32 scratch_addr = pc->gtt_offset + 128;
 693         int ret;
 694
 695         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
 696          * incoherent with writes to memory, i.e. completely fubar,
 697          * so we need to use PIPE_NOTIFY instead.
 698          *
 699          * However, we also need to workaround the qword write
 700          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
 701          * memory before requesting an interrupt.
 702          */
 703         ret = intel_ring_begin(ring, 32);
 704         if (ret)
 705                 return ret;
 706
 707         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 708                         PIPE_CONTROL_WRITE_FLUSH |
 709                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
 710         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 711         intel_ring_emit(ring, ring->outstanding_lazy_request);
 712         intel_ring_emit(ring, 0);
 713         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 714         scratch_addr += 128; /* write to separate cachelines */
 715         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 716         scratch_addr += 128;
 717         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 718         scratch_addr += 128;
 719         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 720         scratch_addr += 128;
 721         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 722         scratch_addr += 128;
 723         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 724
 725         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 726                         PIPE_CONTROL_WRITE_FLUSH |
 727                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
 728                         PIPE_CONTROL_NOTIFY);
 729         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 730         intel_ring_emit(ring, ring->outstanding_lazy_request);
 731         intel_ring_emit(ring, 0);
 732         intel_ring_advance(ring);
 733
 734         return 0;
 735 }
 736
 737 static u32
 738 gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 739 {
 740         /* Workaround to force correct ordering between irq and seqno writes on
 741          * ivb (and maybe also on snb) by reading from a CS register (like
 742          * ACTHD) before reading the status page. */
 743         if (!lazy_coherency)
 744                 intel_ring_get_active_head(ring);
 745         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 746 }
 747
 748 static u32
 749 ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 750 {
 751         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 752 }
 753
 754 static void
 755 ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
 756 {
 757         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
 758 }
 759
 760 static u32
 761 pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 762 {
 763         struct pipe_control *pc = ring->private;
 764         return pc->cpu_page[0];
 765 }
 766
 767 static void
 768 pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
 769 {
 770         struct pipe_control *pc = ring->private;
 771         pc->cpu_page[0] = seqno;
 772 }
 773
 774 static bool
 775 gen5_ring_get_irq(struct intel_ring_buffer *ring)
 776 {
 777         struct drm_device *dev = ring->dev;
 778         drm_i915_private_t *dev_priv = dev->dev_private;
 779         unsigned long flags;
 780
 781         if (!dev->irq_enabled)
 782                 return false;
 783
 784         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 785         if (ring->irq_refcount++ == 0) {
 786                 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
 787                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 788                 POSTING_READ(GTIMR);
 789         }
 790         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 791
 792         return true;
 793 }
 794
 795 static void
 796 gen5_ring_put_irq(struct intel_ring_buffer *ring)
 797 {
 798         struct drm_device *dev = ring->dev;
 799         drm_i915_private_t *dev_priv = dev->dev_private;
 800         unsigned long flags;
 801
 802         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 803         if (--ring->irq_refcount == 0) {
 804                 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
 805                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 806                 POSTING_READ(GTIMR);
 807         }
 808         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 809 }
 810
 811 static bool
 812 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
 813 {
 814         struct drm_device *dev = ring->dev;
 815         drm_i915_private_t *dev_priv = dev->dev_private;
 816         unsigned long flags;
 817
 818         if (!dev->irq_enabled)
 819                 return false;
 820
 821         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 822         if (ring->irq_refcount++ == 0) {
 823                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
 824                 I915_WRITE(IMR, dev_priv->irq_mask);
 825                 POSTING_READ(IMR);
 826         }
 827         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 828
 829         return true;
 830 }
 831
 832 static void
 833 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
 834 {
 835         struct drm_device *dev = ring->dev;
 836         drm_i915_private_t *dev_priv = dev->dev_private;
 837         unsigned long flags;
 838
 839         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 840         if (--ring->irq_refcount == 0) {
 841                 dev_priv->irq_mask |= ring->irq_enable_mask;
 842                 I915_WRITE(IMR, dev_priv->irq_mask);
 843                 POSTING_READ(IMR);
 844         }
 845         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 846 }
 847
 848 static bool
 849 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
 850 {
 851         struct drm_device *dev = ring->dev;
 852         drm_i915_private_t *dev_priv = dev->dev_private;
 853         unsigned long flags;
 854
 855         if (!dev->irq_enabled)
 856                 return false;
 857
 858         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 859         if (ring->irq_refcount++ == 0) {
 860                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
 861                 I915_WRITE16(IMR, dev_priv->irq_mask);
 862                 POSTING_READ16(IMR);
 863         }
 864         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 865
 866         return true;
 867 }
 868
 869 static void
 870 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
 871 {
 872         struct drm_device *dev = ring->dev;
 873         drm_i915_private_t *dev_priv = dev->dev_private;
 874         unsigned long flags;
 875
 876         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 877         if (--ring->irq_refcount == 0) {
 878                 dev_priv->irq_mask |= ring->irq_enable_mask;
 879                 I915_WRITE16(IMR, dev_priv->irq_mask);
 880                 POSTING_READ16(IMR);
 881         }
 882         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 883 }
 884
 885 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
 886 {
 887         struct drm_device *dev = ring->dev;
 888         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 889         u32 mmio = 0;
 890
 891         /* The ring status page addresses are no longer next to the rest of
 892          * the ring registers as of gen7.
 893          */
 894         if (IS_GEN7(dev)) {
 895                 switch (ring->id) {
 896                 case RCS:
 897                         mmio = RENDER_HWS_PGA_GEN7;
 898                         break;
 899                 case BCS:
 900                         mmio = BLT_HWS_PGA_GEN7;
 901                         break;
 902                 case VCS:
 903                         mmio = BSD_HWS_PGA_GEN7;
 904                         break;
 905                 }
 906         } else if (IS_GEN6(ring->dev)) {
 907                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 908         } else {
 909                 mmio = RING_HWS_PGA(ring->mmio_base);
 910         }
 911
 912         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 913         POSTING_READ(mmio);
 914
 915         /* Flush the TLB for this page */
 916         if (INTEL_INFO(dev)->gen >= 6) {
 917                 u32 reg = RING_INSTPM(ring->mmio_base);
 918                 I915_WRITE(reg,
 919                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
 920                                               INSTPM_SYNC_FLUSH));
 921                 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
 922                              1000))
 923                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
 924                                   ring->name);
 925         }
 926 }
 927
 928 static int
 929 bsd_ring_flush(struct intel_ring_buffer *ring,
 930                u32     invalidate_domains,
 931                u32     flush_domains)
 932 {
 933         int ret;
 934
 935         ret = intel_ring_begin(ring, 2);
 936         if (ret)
 937                 return ret;
 938
 939         intel_ring_emit(ring, MI_FLUSH);
 940         intel_ring_emit(ring, MI_NOOP);
 941         intel_ring_advance(ring);
 942         return 0;
 943 }
 944
 945 static int
 946 i9xx_add_request(struct intel_ring_buffer *ring)
 947 {
 948         int ret;
 949
 950         ret = intel_ring_begin(ring, 4);
 951         if (ret)
 952                 return ret;
 953
 954         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 955         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 956         intel_ring_emit(ring, ring->outstanding_lazy_request);
 957         intel_ring_emit(ring, MI_USER_INTERRUPT);
 958         intel_ring_advance(ring);
 959
 960         return 0;
 961 }
 962
 963 static bool
 964 gen6_ring_get_irq(struct intel_ring_buffer *ring)
 965 {
 966         struct drm_device *dev = ring->dev;
 967         drm_i915_private_t *dev_priv = dev->dev_private;
 968         unsigned long flags;
 969
 970         if (!dev->irq_enabled)
 971                return false;
 972
 973         /* It looks like we need to prevent the gt from suspending while waiting
 974          * for an notifiy irq, otherwise irqs seem to get lost on at least the
 975          * blt/bsd rings on ivb. */
 976         gen6_gt_force_wake_get(dev_priv);
 977
 978         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 979         if (ring->irq_refcount++ == 0) {
 980                 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
 981                         I915_WRITE_IMR(ring, ~(ring->irq_enable_mask |
 982                                                 GEN6_RENDER_L3_PARITY_ERROR));
 983                 else
 984                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
 985                 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
 986                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 987                 POSTING_READ(GTIMR);
 988         }
 989         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 990
 991         return true;
 992 }
 993
 994 static void
 995 gen6_ring_put_irq(struct intel_ring_buffer *ring)
 996 {
 997         struct drm_device *dev = ring->dev;
 998         drm_i915_private_t *dev_priv = dev->dev_private;
 999         unsigned long flags;
1000
1001         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1002         if (--ring->irq_refcount == 0) {
1003                 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
1004                         I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
1005                 else
1006                         I915_WRITE_IMR(ring, ~0);
1007                 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
1008                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1009                 POSTING_READ(GTIMR);
1010         }
1011         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1012
1013         gen6_gt_force_wake_put(dev_priv);
1014 }
1015
1016 static int
1017 i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
1018                          u32 offset, u32 length,
1019                          unsigned flags)
1020 {
1021         int ret;
1022
1023         ret = intel_ring_begin(ring, 2);
1024         if (ret)
1025                 return ret;
1026
1027         intel_ring_emit(ring,
1028                         MI_BATCH_BUFFER_START |
1029                         MI_BATCH_GTT |
1030                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1031         intel_ring_emit(ring, offset);
1032         intel_ring_advance(ring);
1033
1034         return 0;
1035 }
1036
1037 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1038 #define I830_BATCH_LIMIT (256*1024)
1039 static int
1040 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
1041                                 u32 offset, u32 len,
1042                                 unsigned flags)
1043 {
1044         int ret;
1045
1046         if (flags & I915_DISPATCH_PINNED) {
1047                 ret = intel_ring_begin(ring, 4);
1048                 if (ret)
1049                         return ret;
1050
1051                 intel_ring_emit(ring, MI_BATCH_BUFFER);
1052                 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1053                 intel_ring_emit(ring, offset + len - 8);
1054                 intel_ring_emit(ring, MI_NOOP);
1055                 intel_ring_advance(ring);
1056         } else {
1057                 struct drm_i915_gem_object *obj = ring->private;
1058                 u32 cs_offset = obj->gtt_offset;
1059
1060                 if (len > I830_BATCH_LIMIT)
1061                         return -ENOSPC;
1062
1063                 ret = intel_ring_begin(ring, 9+3);
1064                 if (ret)
1065                         return ret;
1066                 /* Blit the batch (which has now all relocs applied) to the stable batch
1067                  * scratch bo area (so that the CS never stumbles over its tlb
1068                  * invalidation bug) ... */
1069                 intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD |
1070                                 XY_SRC_COPY_BLT_WRITE_ALPHA |
1071                                 XY_SRC_COPY_BLT_WRITE_RGB);
1072                 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096);
1073                 intel_ring_emit(ring, 0);
1074                 intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024);
1075                 intel_ring_emit(ring, cs_offset);
1076                 intel_ring_emit(ring, 0);
1077                 intel_ring_emit(ring, 4096);
1078                 intel_ring_emit(ring, offset);
1079                 intel_ring_emit(ring, MI_FLUSH);
1080
1081                 /* ... and execute it. */
1082                 intel_ring_emit(ring, MI_BATCH_BUFFER);
1083                 intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1084                 intel_ring_emit(ring, cs_offset + len - 8);
1085                 intel_ring_advance(ring);
1086         }
1087
1088         return 0;
1089 }
1090
1091 static int
1092 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
1093                          u32 offset, u32 len,
1094                          unsigned flags)
1095 {
1096         int ret;
1097
1098         ret = intel_ring_begin(ring, 2);
1099         if (ret)
1100                 return ret;
1101
1102         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1103         intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1104         intel_ring_advance(ring);
1105
1106         return 0;
1107 }
1108
1109 static void cleanup_status_page(struct intel_ring_buffer *ring)
1110 {
1111         struct drm_i915_gem_object *obj;
1112
1113         obj = ring->status_page.obj;
1114         if (obj == NULL)
1115                 return;
1116
1117         kunmap(sg_page(obj->pages->sgl));
1118         i915_gem_object_unpin(obj);
1119         drm_gem_object_unreference(&obj->base);
1120         ring->status_page.obj = NULL;
1121 }
1122
1123 static int init_status_page(struct intel_ring_buffer *ring)
1124 {
1125         struct drm_device *dev = ring->dev;
1126         struct drm_i915_gem_object *obj;
1127         int ret;
1128
1129         obj = i915_gem_alloc_object(dev, 4096);
1130         if (obj == NULL) {
1131                 DRM_ERROR("Failed to allocate status page\n");
1132                 ret = -ENOMEM;
1133                 goto err;
1134         }
1135
1136         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1137
1138         ret = i915_gem_object_pin(obj, 4096, true, false);
1139         if (ret != 0) {
1140                 goto err_unref;
1141         }
1142
1143         ring->status_page.gfx_addr = obj->gtt_offset;
1144         ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1145         if (ring->status_page.page_addr == NULL) {
1146                 ret = -ENOMEM;
1147                 goto err_unpin;
1148         }
1149         ring->status_page.obj = obj;
1150         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1151
1152         intel_ring_setup_status_page(ring);
1153         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1154                         ring->name, ring->status_page.gfx_addr);
1155
1156         return 0;
1157
1158 err_unpin:
1159         i915_gem_object_unpin(obj);
1160 err_unref:
1161         drm_gem_object_unreference(&obj->base);
1162 err:
1163         return ret;
1164 }
1165
1166 static int init_phys_hws_pga(struct intel_ring_buffer *ring)
1167 {
1168         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1169         u32 addr;
1170
1171         if (!dev_priv->status_page_dmah) {
1172                 dev_priv->status_page_dmah =
1173                         drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1174                 if (!dev_priv->status_page_dmah)
1175                         return -ENOMEM;
1176         }
1177
1178         addr = dev_priv->status_page_dmah->busaddr;
1179         if (INTEL_INFO(ring->dev)->gen >= 4)
1180                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
1181         I915_WRITE(HWS_PGA, addr);
1182
1183         ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1184         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1185
1186         return 0;
1187 }
1188
1189 static int intel_init_ring_buffer(struct drm_device *dev,
1190                                   struct intel_ring_buffer *ring)
1191 {
1192         struct drm_i915_gem_object *obj;
1193         struct drm_i915_private *dev_priv = dev->dev_private;
1194         int ret;
1195
1196         ring->dev = dev;
1197         INIT_LIST_HEAD(&ring->active_list);
1198         INIT_LIST_HEAD(&ring->request_list);
1199         ring->size = 32 * PAGE_SIZE;
1200         memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno));
1201
1202         init_waitqueue_head(&ring->irq_queue);
1203
1204         if (I915_NEED_GFX_HWS(dev)) {
1205                 ret = init_status_page(ring);
1206                 if (ret)
1207                         return ret;
1208         } else {
1209                 BUG_ON(ring->id != RCS);
1210                 ret = init_phys_hws_pga(ring);
1211                 if (ret)
1212                         return ret;
1213         }
1214
1215         obj = NULL;
1216         if (!HAS_LLC(dev))
1217                 obj = i915_gem_object_create_stolen(dev, ring->size);
1218         if (obj == NULL)
1219                 obj = i915_gem_alloc_object(dev, ring->size);
1220         if (obj == NULL) {
1221                 DRM_ERROR("Failed to allocate ringbuffer\n");
1222                 ret = -ENOMEM;
1223                 goto err_hws;
1224         }
1225
1226         ring->obj = obj;
1227
1228         ret = i915_gem_object_pin(obj, PAGE_SIZE, true, false);
1229         if (ret)
1230                 goto err_unref;
1231
1232         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1233         if (ret)
1234                 goto err_unpin;
1235
1236         ring->virtual_start =
1237                 ioremap_wc(dev_priv->gtt.mappable_base + obj->gtt_offset,
1238                            ring->size);
1239         if (ring->virtual_start == NULL) {
1240                 DRM_ERROR("Failed to map ringbuffer.\n");
1241                 ret = -EINVAL;
1242                 goto err_unpin;
1243         }
1244
1245         ret = ring->init(ring);
1246         if (ret)
1247                 goto err_unmap;
1248
1249         /* Workaround an erratum on the i830 which causes a hang if
1250          * the TAIL pointer points to within the last 2 cachelines
1251          * of the buffer.
1252          */
1253         ring->effective_size = ring->size;
1254         if (IS_I830(ring->dev) || IS_845G(ring->dev))
1255                 ring->effective_size -= 128;
1256
1257         return 0;
1258
1259 err_unmap:
1260         iounmap(ring->virtual_start);
1261 err_unpin:
1262         i915_gem_object_unpin(obj);
1263 err_unref:
1264         drm_gem_object_unreference(&obj->base);
1265         ring->obj = NULL;
1266 err_hws:
1267         cleanup_status_page(ring);
1268         return ret;
1269 }
1270
1271 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1272 {
1273         struct drm_i915_private *dev_priv;
1274         int ret;
1275
1276         if (ring->obj == NULL)
1277                 return;
1278
1279         /* Disable the ring buffer. The ring must be idle at this point */
1280         dev_priv = ring->dev->dev_private;
1281         ret = intel_ring_idle(ring);
1282         if (ret)
1283                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1284                           ring->name, ret);
1285
1286         I915_WRITE_CTL(ring, 0);
1287
1288         iounmap(ring->virtual_start);
1289
1290         i915_gem_object_unpin(ring->obj);
1291         drm_gem_object_unreference(&ring->obj->base);
1292         ring->obj = NULL;
1293
1294         if (ring->cleanup)
1295                 ring->cleanup(ring);
1296
1297         cleanup_status_page(ring);
1298 }
1299
1300 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1301 {
1302         int ret;
1303
1304         ret = i915_wait_seqno(ring, seqno);
1305         if (!ret)
1306                 i915_gem_retire_requests_ring(ring);
1307
1308         return ret;
1309 }
1310
1311 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1312 {
1313         struct drm_i915_gem_request *request;
1314         u32 seqno = 0;
1315         int ret;
1316
1317         i915_gem_retire_requests_ring(ring);
1318
1319         if (ring->last_retired_head != -1) {
1320                 ring->head = ring->last_retired_head;
1321                 ring->last_retired_head = -1;
1322                 ring->space = ring_space(ring);
1323                 if (ring->space >= n)
1324                         return 0;
1325         }
1326
1327         list_for_each_entry(request, &ring->request_list, list) {
1328                 int space;
1329
1330                 if (request->tail == -1)
1331                         continue;
1332
1333                 space = request->tail - (ring->tail + I915_RING_FREE_SPACE);
1334                 if (space < 0)
1335                         space += ring->size;
1336                 if (space >= n) {
1337                         seqno = request->seqno;
1338                         break;
1339                 }
1340
1341                 /* Consume this request in case we need more space than
1342                  * is available and so need to prevent a race between
1343                  * updating last_retired_head and direct reads of
1344                  * I915_RING_HEAD. It also provides a nice sanity check.
1345                  */
1346                 request->tail = -1;
1347         }
1348
1349         if (seqno == 0)
1350                 return -ENOSPC;
1351
1352         ret = intel_ring_wait_seqno(ring, seqno);
1353         if (ret)
1354                 return ret;
1355
1356         if (WARN_ON(ring->last_retired_head == -1))
1357                 return -ENOSPC;
1358
1359         ring->head = ring->last_retired_head;
1360         ring->last_retired_head = -1;
1361         ring->space = ring_space(ring);
1362         if (WARN_ON(ring->space < n))
1363                 return -ENOSPC;
1364
1365         return 0;
1366 }
1367
1368 static int ring_wait_for_space(struct intel_ring_buffer *ring, int n)
1369 {
1370         struct drm_device *dev = ring->dev;
1371         struct drm_i915_private *dev_priv = dev->dev_private;
1372         unsigned long end;
1373         int ret;
1374
1375         ret = intel_ring_wait_request(ring, n);
1376         if (ret != -ENOSPC)
1377                 return ret;
1378
1379         trace_i915_ring_wait_begin(ring);
1380         /* With GEM the hangcheck timer should kick us out of the loop,
1381          * leaving it early runs the risk of corrupting GEM state (due
1382          * to running on almost untested codepaths). But on resume
1383          * timers don't work yet, so prevent a complete hang in that
1384          * case by choosing an insanely large timeout. */
1385         end = jiffies + 60 * HZ;
1386
1387         do {
1388                 ring->head = I915_READ_HEAD(ring);
1389                 ring->space = ring_space(ring);
1390                 if (ring->space >= n) {
1391                         trace_i915_ring_wait_end(ring);
1392                         return 0;
1393                 }
1394
1395                 if (dev->primary->master) {
1396                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1397                         if (master_priv->sarea_priv)
1398                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1399                 }
1400
1401                 msleep(1);
1402
1403                 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1404                                            dev_priv->mm.interruptible);
1405                 if (ret)
1406                         return ret;
1407         } while (!time_after(jiffies, end));
1408         trace_i915_ring_wait_end(ring);
1409         return -EBUSY;
1410 }
1411
1412 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1413 {
1414         uint32_t __iomem *virt;
1415         int rem = ring->size - ring->tail;
1416
1417         if (ring->space < rem) {
1418                 int ret = ring_wait_for_space(ring, rem);
1419                 if (ret)
1420                         return ret;
1421         }
1422
1423         virt = ring->virtual_start + ring->tail;
1424         rem /= 4;
1425         while (rem--)
1426                 iowrite32(MI_NOOP, virt++);
1427
1428         ring->tail = 0;
1429         ring->space = ring_space(ring);
1430
1431         return 0;
1432 }
1433
1434 int intel_ring_idle(struct intel_ring_buffer *ring)
1435 {
1436         u32 seqno;
1437         int ret;
1438
1439         /* We need to add any requests required to flush the objects and ring */
1440         if (ring->outstanding_lazy_request) {
1441                 ret = i915_add_request(ring, NULL, NULL);
1442                 if (ret)
1443                         return ret;
1444         }
1445
1446         /* Wait upon the last request to be completed */
1447         if (list_empty(&ring->request_list))
1448                 return 0;
1449
1450         seqno = list_entry(ring->request_list.prev,
1451                            struct drm_i915_gem_request,
1452                            list)->seqno;
1453
1454         return i915_wait_seqno(ring, seqno);
1455 }
1456
1457 static int
1458 intel_ring_alloc_seqno(struct intel_ring_buffer *ring)
1459 {
1460         if (ring->outstanding_lazy_request)
1461                 return 0;
1462
1463         return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_request);
1464 }
1465
1466 static int __intel_ring_prepare(struct intel_ring_buffer *ring,
1467                                 int bytes)
1468 {
1469         int ret;
1470
1471         if (unlikely(ring->tail + bytes > ring->effective_size)) {
1472                 ret = intel_wrap_ring_buffer(ring);
1473                 if (unlikely(ret))
1474                         return ret;
1475         }
1476
1477         if (unlikely(ring->space < bytes)) {
1478                 ret = ring_wait_for_space(ring, bytes);
1479                 if (unlikely(ret))
1480                         return ret;
1481         }
1482
1483         return 0;
1484 }
1485
1486 int intel_ring_begin(struct intel_ring_buffer *ring,
1487                      int num_dwords)
1488 {
1489         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1490         int ret;
1491
1492         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1493                                    dev_priv->mm.interruptible);
1494         if (ret)
1495                 return ret;
1496
1497         ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
1498         if (ret)
1499                 return ret;
1500
1501         /* Preallocate the olr before touching the ring */
1502         ret = intel_ring_alloc_seqno(ring);
1503         if (ret)
1504                 return ret;
1505
1506         ring->space -= num_dwords * sizeof(uint32_t);
1507         return 0;
1508 }
1509
1510 void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno)
1511 {
1512         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1513
1514         BUG_ON(ring->outstanding_lazy_request);
1515
1516         if (INTEL_INFO(ring->dev)->gen >= 6) {
1517                 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
1518                 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
1519         }
1520
1521         ring->set_seqno(ring, seqno);
1522 }
1523
1524 void intel_ring_advance(struct intel_ring_buffer *ring)
1525 {
1526         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1527
1528         ring->tail &= ring->size - 1;
1529         if (dev_priv->gpu_error.stop_rings & intel_ring_flag(ring))
1530                 return;
1531         ring->write_tail(ring, ring->tail);
1532 }
1533
1534
1535 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1536                                      u32 value)
1537 {
1538         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1539
1540        /* Every tail move must follow the sequence below */
1541
1542         /* Disable notification that the ring is IDLE. The GT
1543          * will then assume that it is busy and bring it out of rc6.
1544          */
1545         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1546                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1547
1548         /* Clear the context id. Here be magic! */
1549         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1550
1551         /* Wait for the ring not to be idle, i.e. for it to wake up. */
1552         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1553                       GEN6_BSD_SLEEP_INDICATOR) == 0,
1554                      50))
1555                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1556
1557         /* Now that the ring is fully powered up, update the tail */
1558         I915_WRITE_TAIL(ring, value);
1559         POSTING_READ(RING_TAIL(ring->mmio_base));
1560
1561         /* Let the ring send IDLE messages to the GT again,
1562          * and so let it sleep to conserve power when idle.
1563          */
1564         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1565                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1566 }
1567
1568 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1569                            u32 invalidate, u32 flush)
1570 {
1571         uint32_t cmd;
1572         int ret;
1573
1574         ret = intel_ring_begin(ring, 4);
1575         if (ret)
1576                 return ret;
1577
1578         cmd = MI_FLUSH_DW;
1579         /*
1580          * Bspec vol 1c.5 - video engine command streamer:
1581          * "If ENABLED, all TLBs will be invalidated once the flush
1582          * operation is complete. This bit is only valid when the
1583          * Post-Sync Operation field is a value of 1h or 3h."
1584          */
1585         if (invalidate & I915_GEM_GPU_DOMAINS)
1586                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1587                         MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1588         intel_ring_emit(ring, cmd);
1589         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1590         intel_ring_emit(ring, 0);
1591         intel_ring_emit(ring, MI_NOOP);
1592         intel_ring_advance(ring);
1593         return 0;
1594 }
1595
1596 static int
1597 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1598                               u32 offset, u32 len,
1599                               unsigned flags)
1600 {
1601         int ret;
1602
1603         ret = intel_ring_begin(ring, 2);
1604         if (ret)
1605                 return ret;
1606
1607         intel_ring_emit(ring,
1608                         MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
1609                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
1610         /* bit0-7 is the length on GEN6+ */
1611         intel_ring_emit(ring, offset);
1612         intel_ring_advance(ring);
1613
1614         return 0;
1615 }
1616
1617 static int
1618 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1619                               u32 offset, u32 len,
1620                               unsigned flags)
1621 {
1622         int ret;
1623
1624         ret = intel_ring_begin(ring, 2);
1625         if (ret)
1626                 return ret;
1627
1628         intel_ring_emit(ring,
1629                         MI_BATCH_BUFFER_START |
1630                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1631         /* bit0-7 is the length on GEN6+ */
1632         intel_ring_emit(ring, offset);
1633         intel_ring_advance(ring);
1634
1635         return 0;
1636 }
1637
1638 /* Blitter support (SandyBridge+) */
1639
1640 static int blt_ring_flush(struct intel_ring_buffer *ring,
1641                           u32 invalidate, u32 flush)
1642 {
1643         uint32_t cmd;
1644         int ret;
1645
1646         ret = intel_ring_begin(ring, 4);
1647         if (ret)
1648                 return ret;
1649
1650         cmd = MI_FLUSH_DW;
1651         /*
1652          * Bspec vol 1c.3 - blitter engine command streamer:
1653          * "If ENABLED, all TLBs will be invalidated once the flush
1654          * operation is complete. This bit is only valid when the
1655          * Post-Sync Operation field is a value of 1h or 3h."
1656          */
1657         if (invalidate & I915_GEM_DOMAIN_RENDER)
1658                 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
1659                         MI_FLUSH_DW_OP_STOREDW;
1660         intel_ring_emit(ring, cmd);
1661         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1662         intel_ring_emit(ring, 0);
1663         intel_ring_emit(ring, MI_NOOP);
1664         intel_ring_advance(ring);
1665         return 0;
1666 }
1667
1668 int intel_init_render_ring_buffer(struct drm_device *dev)
1669 {
1670         drm_i915_private_t *dev_priv = dev->dev_private;
1671         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1672
1673         ring->name = "render ring";
1674         ring->id = RCS;
1675         ring->mmio_base = RENDER_RING_BASE;
1676
1677         if (INTEL_INFO(dev)->gen >= 6) {
1678                 ring->add_request = gen6_add_request;
1679                 ring->flush = gen7_render_ring_flush;
1680                 if (INTEL_INFO(dev)->gen == 6)
1681                         ring->flush = gen6_render_ring_flush;
1682                 ring->irq_get = gen6_ring_get_irq;
1683                 ring->irq_put = gen6_ring_put_irq;
1684                 ring->irq_enable_mask = GT_USER_INTERRUPT;
1685                 ring->get_seqno = gen6_ring_get_seqno;
1686                 ring->set_seqno = ring_set_seqno;
1687                 ring->sync_to = gen6_ring_sync;
1688                 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
1689                 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
1690                 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
1691                 ring->signal_mbox[0] = GEN6_VRSYNC;
1692                 ring->signal_mbox[1] = GEN6_BRSYNC;
1693         } else if (IS_GEN5(dev)) {
1694                 ring->add_request = pc_render_add_request;
1695                 ring->flush = gen4_render_ring_flush;
1696                 ring->get_seqno = pc_render_get_seqno;
1697                 ring->set_seqno = pc_render_set_seqno;
1698                 ring->irq_get = gen5_ring_get_irq;
1699                 ring->irq_put = gen5_ring_put_irq;
1700                 ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
1701         } else {
1702                 ring->add_request = i9xx_add_request;
1703                 if (INTEL_INFO(dev)->gen < 4)
1704                         ring->flush = gen2_render_ring_flush;
1705                 else
1706                         ring->flush = gen4_render_ring_flush;
1707                 ring->get_seqno = ring_get_seqno;
1708                 ring->set_seqno = ring_set_seqno;
1709                 if (IS_GEN2(dev)) {
1710                         ring->irq_get = i8xx_ring_get_irq;
1711                         ring->irq_put = i8xx_ring_put_irq;
1712                 } else {
1713                         ring->irq_get = i9xx_ring_get_irq;
1714                         ring->irq_put = i9xx_ring_put_irq;
1715                 }
1716                 ring->irq_enable_mask = I915_USER_INTERRUPT;
1717         }
1718         ring->write_tail = ring_write_tail;
1719         if (IS_HASWELL(dev))
1720                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1721         else if (INTEL_INFO(dev)->gen >= 6)
1722                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1723         else if (INTEL_INFO(dev)->gen >= 4)
1724                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1725         else if (IS_I830(dev) || IS_845G(dev))
1726                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1727         else
1728                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1729         ring->init = init_render_ring;
1730         ring->cleanup = render_ring_cleanup;
1731
1732         /* Workaround batchbuffer to combat CS tlb bug. */
1733         if (HAS_BROKEN_CS_TLB(dev)) {
1734                 struct drm_i915_gem_object *obj;
1735                 int ret;
1736
1737                 obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT);
1738                 if (obj == NULL) {
1739                         DRM_ERROR("Failed to allocate batch bo\n");
1740                         return -ENOMEM;
1741                 }
1742
1743                 ret = i915_gem_object_pin(obj, 0, true, false);
1744                 if (ret != 0) {
1745                         drm_gem_object_unreference(&obj->base);
1746                         DRM_ERROR("Failed to ping batch bo\n");
1747                         return ret;
1748                 }
1749
1750                 ring->private = obj;
1751         }
1752
1753         return intel_init_ring_buffer(dev, ring);
1754 }
1755
1756 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1757 {
1758         drm_i915_private_t *dev_priv = dev->dev_private;
1759         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1760         int ret;
1761
1762         ring->name = "render ring";
1763         ring->id = RCS;
1764         ring->mmio_base = RENDER_RING_BASE;
1765
1766         if (INTEL_INFO(dev)->gen >= 6) {
1767                 /* non-kms not supported on gen6+ */
1768                 return -ENODEV;
1769         }
1770
1771         /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1772          * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1773          * the special gen5 functions. */
1774         ring->add_request = i9xx_add_request;
1775         if (INTEL_INFO(dev)->gen < 4)
1776                 ring->flush = gen2_render_ring_flush;
1777         else
1778                 ring->flush = gen4_render_ring_flush;
1779         ring->get_seqno = ring_get_seqno;
1780         ring->set_seqno = ring_set_seqno;
1781         if (IS_GEN2(dev)) {
1782                 ring->irq_get = i8xx_ring_get_irq;
1783                 ring->irq_put = i8xx_ring_put_irq;
1784         } else {
1785                 ring->irq_get = i9xx_ring_get_irq;
1786                 ring->irq_put = i9xx_ring_put_irq;
1787         }
1788         ring->irq_enable_mask = I915_USER_INTERRUPT;
1789         ring->write_tail = ring_write_tail;
1790         if (INTEL_INFO(dev)->gen >= 4)
1791                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1792         else if (IS_I830(dev) || IS_845G(dev))
1793                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1794         else
1795                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1796         ring->init = init_render_ring;
1797         ring->cleanup = render_ring_cleanup;
1798
1799         ring->dev = dev;
1800         INIT_LIST_HEAD(&ring->active_list);
1801         INIT_LIST_HEAD(&ring->request_list);
1802
1803         ring->size = size;
1804         ring->effective_size = ring->size;
1805         if (IS_I830(ring->dev) || IS_845G(ring->dev))
1806                 ring->effective_size -= 128;
1807
1808         ring->virtual_start = ioremap_wc(start, size);
1809         if (ring->virtual_start == NULL) {
1810                 DRM_ERROR("can not ioremap virtual address for"
1811                           " ring buffer\n");
1812                 return -ENOMEM;
1813         }
1814
1815         if (!I915_NEED_GFX_HWS(dev)) {
1816                 ret = init_phys_hws_pga(ring);
1817                 if (ret)
1818                         return ret;
1819         }
1820
1821         return 0;
1822 }
1823
1824 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1825 {
1826         drm_i915_private_t *dev_priv = dev->dev_private;
1827         struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1828
1829         ring->name = "bsd ring";
1830         ring->id = VCS;
1831
1832         ring->write_tail = ring_write_tail;
1833         if (IS_GEN6(dev) || IS_GEN7(dev)) {
1834                 ring->mmio_base = GEN6_BSD_RING_BASE;
1835                 /* gen6 bsd needs a special wa for tail updates */
1836                 if (IS_GEN6(dev))
1837                         ring->write_tail = gen6_bsd_ring_write_tail;
1838                 ring->flush = gen6_ring_flush;
1839                 ring->add_request = gen6_add_request;
1840                 ring->get_seqno = gen6_ring_get_seqno;
1841                 ring->set_seqno = ring_set_seqno;
1842                 ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT;
1843                 ring->irq_get = gen6_ring_get_irq;
1844                 ring->irq_put = gen6_ring_put_irq;
1845                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1846                 ring->sync_to = gen6_ring_sync;
1847                 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
1848                 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
1849                 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
1850                 ring->signal_mbox[0] = GEN6_RVSYNC;
1851                 ring->signal_mbox[1] = GEN6_BVSYNC;
1852         } else {
1853                 ring->mmio_base = BSD_RING_BASE;
1854                 ring->flush = bsd_ring_flush;
1855                 ring->add_request = i9xx_add_request;
1856                 ring->get_seqno = ring_get_seqno;
1857                 ring->set_seqno = ring_set_seqno;
1858                 if (IS_GEN5(dev)) {
1859                         ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1860                         ring->irq_get = gen5_ring_get_irq;
1861                         ring->irq_put = gen5_ring_put_irq;
1862                 } else {
1863                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1864                         ring->irq_get = i9xx_ring_get_irq;
1865                         ring->irq_put = i9xx_ring_put_irq;
1866                 }
1867                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1868         }
1869         ring->init = init_ring_common;
1870
1871         return intel_init_ring_buffer(dev, ring);
1872 }
1873
1874 int intel_init_blt_ring_buffer(struct drm_device *dev)
1875 {
1876         drm_i915_private_t *dev_priv = dev->dev_private;
1877         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1878
1879         ring->name = "blitter ring";
1880         ring->id = BCS;
1881
1882         ring->mmio_base = BLT_RING_BASE;
1883         ring->write_tail = ring_write_tail;
1884         ring->flush = blt_ring_flush;
1885         ring->add_request = gen6_add_request;
1886         ring->get_seqno = gen6_ring_get_seqno;
1887         ring->set_seqno = ring_set_seqno;
1888         ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT;
1889         ring->irq_get = gen6_ring_get_irq;
1890         ring->irq_put = gen6_ring_put_irq;
1891         ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1892         ring->sync_to = gen6_ring_sync;
1893         ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
1894         ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
1895         ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
1896         ring->signal_mbox[0] = GEN6_RBSYNC;
1897         ring->signal_mbox[1] = GEN6_VBSYNC;
1898         ring->init = init_ring_common;
1899
1900         return intel_init_ring_buffer(dev, ring);
1901 }
1902
1903 int
1904 intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
1905 {
1906         int ret;
1907
1908         if (!ring->gpu_caches_dirty)
1909                 return 0;
1910
1911         ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
1912         if (ret)
1913                 return ret;
1914
1915         trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
1916
1917         ring->gpu_caches_dirty = false;
1918         return 0;
1919 }
1920
1921 int
1922 intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
1923 {
1924         uint32_t flush_domains;
1925         int ret;
1926
1927         flush_domains = 0;
1928         if (ring->gpu_caches_dirty)
1929                 flush_domains = I915_GEM_GPU_DOMAINS;
1930
1931         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
1932         if (ret)
1933                 return ret;
1934
1935         trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
1936
1937         ring->gpu_caches_dirty = false;
1938         return 0;
1939 }