drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include "i915_drv.h"
  32 #include <drm/i915_drm.h>
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35
  36 /*
  37  * 965+ support PIPE_CONTROL commands, which provide finer grained control
  38  * over cache flushing.
  39  */
  40 struct pipe_control {
  41         struct drm_i915_gem_object *obj;
  42         volatile u32 *cpu_page;
  43         u32 gtt_offset;
  44 };
  45
  46 static inline int ring_space(struct intel_ring_buffer *ring)
  47 {
  48         int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE);
  49         if (space < 0)
  50                 space += ring->size;
  51         return space;
  52 }
  53
  54 static int
  55 gen2_render_ring_flush(struct intel_ring_buffer *ring,
  56                        u32      invalidate_domains,
  57                        u32      flush_domains)
  58 {
  59         u32 cmd;
  60         int ret;
  61
  62         cmd = MI_FLUSH;
  63         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
  64                 cmd |= MI_NO_WRITE_FLUSH;
  65
  66         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
  67                 cmd |= MI_READ_FLUSH;
  68
  69         ret = intel_ring_begin(ring, 2);
  70         if (ret)
  71                 return ret;
  72
  73         intel_ring_emit(ring, cmd);
  74         intel_ring_emit(ring, MI_NOOP);
  75         intel_ring_advance(ring);
  76
  77         return 0;
  78 }
  79
  80 static int
  81 gen4_render_ring_flush(struct intel_ring_buffer *ring,
  82                        u32      invalidate_domains,
  83                        u32      flush_domains)
  84 {
  85         struct drm_device *dev = ring->dev;
  86         u32 cmd;
  87         int ret;
  88
  89         /*
  90          * read/write caches:
  91          *
  92          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
  93          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
  94          * also flushed at 2d versus 3d pipeline switches.
  95          *
  96          * read-only caches:
  97          *
  98          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
  99          * MI_READ_FLUSH is set, and is always flushed on 965.
 100          *
 101          * I915_GEM_DOMAIN_COMMAND may not exist?
 102          *
 103          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 104          * invalidated when MI_EXE_FLUSH is set.
 105          *
 106          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 107          * invalidated with every MI_FLUSH.
 108          *
 109          * TLBs:
 110          *
 111          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 112          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 113          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 114          * are flushed at any MI_FLUSH.
 115          */
 116
 117         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 118         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 119                 cmd &= ~MI_NO_WRITE_FLUSH;
 120         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 121                 cmd |= MI_EXE_FLUSH;
 122
 123         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 124             (IS_G4X(dev) || IS_GEN5(dev)))
 125                 cmd |= MI_INVALIDATE_ISP;
 126
 127         ret = intel_ring_begin(ring, 2);
 128         if (ret)
 129                 return ret;
 130
 131         intel_ring_emit(ring, cmd);
 132         intel_ring_emit(ring, MI_NOOP);
 133         intel_ring_advance(ring);
 134
 135         return 0;
 136 }
 137
 138 /**
 139  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 140  * implementing two workarounds on gen6.  From section 1.4.7.1
 141  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 142  *
 143  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 144  * produced by non-pipelined state commands), software needs to first
 145  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 146  * 0.
 147  *
 148  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 149  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 150  *
 151  * And the workaround for these two requires this workaround first:
 152  *
 153  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 154  * BEFORE the pipe-control with a post-sync op and no write-cache
 155  * flushes.
 156  *
 157  * And this last workaround is tricky because of the requirements on
 158  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 159  * volume 2 part 1:
 160  *
 161  *     "1 of the following must also be set:
 162  *      - Render Target Cache Flush Enable ([12] of DW1)
 163  *      - Depth Cache Flush Enable ([0] of DW1)
 164  *      - Stall at Pixel Scoreboard ([1] of DW1)
 165  *      - Depth Stall ([13] of DW1)
 166  *      - Post-Sync Operation ([13] of DW1)
 167  *      - Notify Enable ([8] of DW1)"
 168  *
 169  * The cache flushes require the workaround flush that triggered this
 170  * one, so we can't use it.  Depth stall would trigger the same.
 171  * Post-sync nonzero is what triggered this second workaround, so we
 172  * can't use that one either.  Notify enable is IRQs, which aren't
 173  * really our business.  That leaves only stall at scoreboard.
 174  */
 175 static int
 176 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
 177 {
 178         struct pipe_control *pc = ring->private;
 179         u32 scratch_addr = pc->gtt_offset + 128;
 180         int ret;
 181
 182
 183         ret = intel_ring_begin(ring, 6);
 184         if (ret)
 185                 return ret;
 186
 187         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 188         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 189                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 190         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 191         intel_ring_emit(ring, 0); /* low dword */
 192         intel_ring_emit(ring, 0); /* high dword */
 193         intel_ring_emit(ring, MI_NOOP);
 194         intel_ring_advance(ring);
 195
 196         ret = intel_ring_begin(ring, 6);
 197         if (ret)
 198                 return ret;
 199
 200         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 201         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 202         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 203         intel_ring_emit(ring, 0);
 204         intel_ring_emit(ring, 0);
 205         intel_ring_emit(ring, MI_NOOP);
 206         intel_ring_advance(ring);
 207
 208         return 0;
 209 }
 210
 211 static int
 212 gen6_render_ring_flush(struct intel_ring_buffer *ring,
 213                          u32 invalidate_domains, u32 flush_domains)
 214 {
 215         u32 flags = 0;
 216         struct pipe_control *pc = ring->private;
 217         u32 scratch_addr = pc->gtt_offset + 128;
 218         int ret;
 219
 220         /* Force SNB workarounds for PIPE_CONTROL flushes */
 221         ret = intel_emit_post_sync_nonzero_flush(ring);
 222         if (ret)
 223                 return ret;
 224
 225         /* Just flush everything.  Experiments have shown that reducing the
 226          * number of bits based on the write domains has little performance
 227          * impact.
 228          */
 229         if (flush_domains) {
 230                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 231                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 232                 /*
 233                  * Ensure that any following seqno writes only happen
 234                  * when the render cache is indeed flushed.
 235                  */
 236                 flags |= PIPE_CONTROL_CS_STALL;
 237         }
 238         if (invalidate_domains) {
 239                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 240                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 241                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 242                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 243                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 244                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 245                 /*
 246                  * TLB invalidate requires a post-sync write.
 247                  */
 248                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 249         }
 250
 251         ret = intel_ring_begin(ring, 4);
 252         if (ret)
 253                 return ret;
 254
 255         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 256         intel_ring_emit(ring, flags);
 257         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 258         intel_ring_emit(ring, 0);
 259         intel_ring_advance(ring);
 260
 261         return 0;
 262 }
 263
 264 static int
 265 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
 266 {
 267         int ret;
 268
 269         ret = intel_ring_begin(ring, 4);
 270         if (ret)
 271                 return ret;
 272
 273         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 274         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 275                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 276         intel_ring_emit(ring, 0);
 277         intel_ring_emit(ring, 0);
 278         intel_ring_advance(ring);
 279
 280         return 0;
 281 }
 282
 283 static int
 284 gen7_render_ring_flush(struct intel_ring_buffer *ring,
 285                        u32 invalidate_domains, u32 flush_domains)
 286 {
 287         u32 flags = 0;
 288         struct pipe_control *pc = ring->private;
 289         u32 scratch_addr = pc->gtt_offset + 128;
 290         int ret;
 291
 292         /*
 293          * Ensure that any following seqno writes only happen when the render
 294          * cache is indeed flushed.
 295          *
 296          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 297          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 298          * don't try to be clever and just set it unconditionally.
 299          */
 300         flags |= PIPE_CONTROL_CS_STALL;
 301
 302         /* Just flush everything.  Experiments have shown that reducing the
 303          * number of bits based on the write domains has little performance
 304          * impact.
 305          */
 306         if (flush_domains) {
 307                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 308                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 309         }
 310         if (invalidate_domains) {
 311                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 312                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 313                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 314                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 315                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 316                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 317                 /*
 318                  * TLB invalidate requires a post-sync write.
 319                  */
 320                 flags |= PIPE_CONTROL_QW_WRITE;
 321                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 322
 323                 /* Workaround: we must issue a pipe_control with CS-stall bit
 324                  * set before a pipe_control command that has the state cache
 325                  * invalidate bit set. */
 326                 gen7_render_ring_cs_stall_wa(ring);
 327         }
 328
 329         ret = intel_ring_begin(ring, 4);
 330         if (ret)
 331                 return ret;
 332
 333         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 334         intel_ring_emit(ring, flags);
 335         intel_ring_emit(ring, scratch_addr);
 336         intel_ring_emit(ring, 0);
 337         intel_ring_advance(ring);
 338
 339         return 0;
 340 }
 341
 342 static void ring_write_tail(struct intel_ring_buffer *ring,
 343                             u32 value)
 344 {
 345         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 346         I915_WRITE_TAIL(ring, value);
 347 }
 348
 349 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
 350 {
 351         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 352         u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
 353                         RING_ACTHD(ring->mmio_base) : ACTHD;
 354
 355         return I915_READ(acthd_reg);
 356 }
 357
 358 static int init_ring_common(struct intel_ring_buffer *ring)
 359 {
 360         struct drm_device *dev = ring->dev;
 361         drm_i915_private_t *dev_priv = dev->dev_private;
 362         struct drm_i915_gem_object *obj = ring->obj;
 363         int ret = 0;
 364         u32 head;
 365
 366         if (HAS_FORCE_WAKE(dev))
 367                 gen6_gt_force_wake_get(dev_priv);
 368
 369         /* Stop the ring if it's running. */
 370         I915_WRITE_CTL(ring, 0);
 371         I915_WRITE_HEAD(ring, 0);
 372         ring->write_tail(ring, 0);
 373
 374         head = I915_READ_HEAD(ring) & HEAD_ADDR;
 375
 376         /* G45 ring initialization fails to reset head to zero */
 377         if (head != 0) {
 378                 DRM_DEBUG_KMS("%s head not reset to zero "
 379                               "ctl %08x head %08x tail %08x start %08x\n",
 380                               ring->name,
 381                               I915_READ_CTL(ring),
 382                               I915_READ_HEAD(ring),
 383                               I915_READ_TAIL(ring),
 384                               I915_READ_START(ring));
 385
 386                 I915_WRITE_HEAD(ring, 0);
 387
 388                 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
 389                         DRM_ERROR("failed to set %s head to zero "
 390                                   "ctl %08x head %08x tail %08x start %08x\n",
 391                                   ring->name,
 392                                   I915_READ_CTL(ring),
 393                                   I915_READ_HEAD(ring),
 394                                   I915_READ_TAIL(ring),
 395                                   I915_READ_START(ring));
 396                 }
 397         }
 398
 399         /* Enforce ordering by reading HEAD register back */
 400         I915_READ_HEAD(ring);
 401
 402         /* Initialize the ring. This must happen _after_ we've cleared the ring
 403          * registers with the above sequence (the readback of the HEAD registers
 404          * also enforces ordering), otherwise the hw might lose the new ring
 405          * register values. */
 406         I915_WRITE_START(ring, obj->gtt_offset);
 407         I915_WRITE_CTL(ring,
 408                         ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
 409                         | RING_VALID);
 410
 411         /* If the head is still not zero, the ring is dead */
 412         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 413                      I915_READ_START(ring) == obj->gtt_offset &&
 414                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 415                 DRM_ERROR("%s initialization failed "
 416                                 "ctl %08x head %08x tail %08x start %08x\n",
 417                                 ring->name,
 418                                 I915_READ_CTL(ring),
 419                                 I915_READ_HEAD(ring),
 420                                 I915_READ_TAIL(ring),
 421                                 I915_READ_START(ring));
 422                 ret = -EIO;
 423                 goto out;
 424         }
 425
 426         if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
 427                 i915_kernel_lost_context(ring->dev);
 428         else {
 429                 ring->head = I915_READ_HEAD(ring);
 430                 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 431                 ring->space = ring_space(ring);
 432                 ring->last_retired_head = -1;
 433         }
 434
 435 out:
 436         if (HAS_FORCE_WAKE(dev))
 437                 gen6_gt_force_wake_put(dev_priv);
 438
 439         return ret;
 440 }
 441
 442 static int
 443 init_pipe_control(struct intel_ring_buffer *ring)
 444 {
 445         struct pipe_control *pc;
 446         struct drm_i915_gem_object *obj;
 447         int ret;
 448
 449         if (ring->private)
 450                 return 0;
 451
 452         pc = kmalloc(sizeof(*pc), GFP_KERNEL);
 453         if (!pc)
 454                 return -ENOMEM;
 455
 456         obj = i915_gem_alloc_object(ring->dev, 4096);
 457         if (obj == NULL) {
 458                 DRM_ERROR("Failed to allocate seqno page\n");
 459                 ret = -ENOMEM;
 460                 goto err;
 461         }
 462
 463         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
 464
 465         ret = i915_gem_object_pin(obj, 4096, true, false);
 466         if (ret)
 467                 goto err_unref;
 468
 469         pc->gtt_offset = obj->gtt_offset;
 470         pc->cpu_page =  kmap(sg_page(obj->pages->sgl));
 471         if (pc->cpu_page == NULL)
 472                 goto err_unpin;
 473
 474         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 475                          ring->name, pc->gtt_offset);
 476
 477         pc->obj = obj;
 478         ring->private = pc;
 479         return 0;
 480
 481 err_unpin:
 482         i915_gem_object_unpin(obj);
 483 err_unref:
 484         drm_gem_object_unreference(&obj->base);
 485 err:
 486         kfree(pc);
 487         return ret;
 488 }
 489
 490 static void
 491 cleanup_pipe_control(struct intel_ring_buffer *ring)
 492 {
 493         struct pipe_control *pc = ring->private;
 494         struct drm_i915_gem_object *obj;
 495
 496         obj = pc->obj;
 497
 498         kunmap(sg_page(obj->pages->sgl));
 499         i915_gem_object_unpin(obj);
 500         drm_gem_object_unreference(&obj->base);
 501
 502         kfree(pc);
 503 }
 504
 505 static int init_render_ring(struct intel_ring_buffer *ring)
 506 {
 507         struct drm_device *dev = ring->dev;
 508         struct drm_i915_private *dev_priv = dev->dev_private;
 509         int ret = init_ring_common(ring);
 510
 511         if (INTEL_INFO(dev)->gen > 3)
 512                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
 513
 514         /* We need to disable the AsyncFlip performance optimisations in order
 515          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
 516          * programmed to '1' on all products.
 517          */
 518         if (INTEL_INFO(dev)->gen >= 6)
 519                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
 520
 521         /* Required for the hardware to program scanline values for waiting */
 522         if (INTEL_INFO(dev)->gen == 6)
 523                 I915_WRITE(GFX_MODE,
 524                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
 525
 526         if (IS_GEN7(dev))
 527                 I915_WRITE(GFX_MODE_GEN7,
 528                            _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
 529                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
 530
 531         if (INTEL_INFO(dev)->gen >= 5) {
 532                 ret = init_pipe_control(ring);
 533                 if (ret)
 534                         return ret;
 535         }
 536
 537         if (IS_GEN6(dev)) {
 538                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
 539                  * "If this bit is set, STCunit will have LRA as replacement
 540                  *  policy. [...] This bit must be reset.  LRA replacement
 541                  *  policy is not supported."
 542                  */
 543                 I915_WRITE(CACHE_MODE_0,
 544                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
 545
 546                 /* This is not explicitly set for GEN6, so read the register.
 547                  * see intel_ring_mi_set_context() for why we care.
 548                  * TODO: consider explicitly setting the bit for GEN5
 549                  */
 550                 ring->itlb_before_ctx_switch =
 551                         !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
 552         }
 553
 554         if (INTEL_INFO(dev)->gen >= 6)
 555                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 556
 557         if (HAS_L3_GPU_CACHE(dev))
 558                 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
 559
 560         return ret;
 561 }
 562
 563 static void render_ring_cleanup(struct intel_ring_buffer *ring)
 564 {
 565         struct drm_device *dev = ring->dev;
 566
 567         if (!ring->private)
 568                 return;
 569
 570         if (HAS_BROKEN_CS_TLB(dev))
 571                 drm_gem_object_unreference(to_gem_object(ring->private));
 572
 573         if (INTEL_INFO(dev)->gen >= 5)
 574                 cleanup_pipe_control(ring);
 575
 576         ring->private = NULL;
 577 }
 578
 579 static void
 580 update_mboxes(struct intel_ring_buffer *ring,
 581               u32 mmio_offset)
 582 {
 583         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 584         intel_ring_emit(ring, mmio_offset);
 585         intel_ring_emit(ring, ring->outstanding_lazy_request);
 586 }
 587
 588 /**
 589  * gen6_add_request - Update the semaphore mailbox registers
 590  *
 591  * @ring - ring that is adding a request
 592  * @seqno - return seqno stuck into the ring
 593  *
 594  * Update the mailbox registers in the *other* rings with the current seqno.
 595  * This acts like a signal in the canonical semaphore.
 596  */
 597 static int
 598 gen6_add_request(struct intel_ring_buffer *ring)
 599 {
 600         u32 mbox1_reg;
 601         u32 mbox2_reg;
 602         int ret;
 603
 604         ret = intel_ring_begin(ring, 10);
 605         if (ret)
 606                 return ret;
 607
 608         mbox1_reg = ring->signal_mbox[0];
 609         mbox2_reg = ring->signal_mbox[1];
 610
 611         update_mboxes(ring, mbox1_reg);
 612         update_mboxes(ring, mbox2_reg);
 613         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 614         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 615         intel_ring_emit(ring, ring->outstanding_lazy_request);
 616         intel_ring_emit(ring, MI_USER_INTERRUPT);
 617         intel_ring_advance(ring);
 618
 619         return 0;
 620 }
 621
 622 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
 623                                               u32 seqno)
 624 {
 625         struct drm_i915_private *dev_priv = dev->dev_private;
 626         return dev_priv->last_seqno < seqno;
 627 }
 628
 629 /**
 630  * intel_ring_sync - sync the waiter to the signaller on seqno
 631  *
 632  * @waiter - ring that is waiting
 633  * @signaller - ring which has, or will signal
 634  * @seqno - seqno which the waiter will block on
 635  */
 636 static int
 637 gen6_ring_sync(struct intel_ring_buffer *waiter,
 638                struct intel_ring_buffer *signaller,
 639                u32 seqno)
 640 {
 641         int ret;
 642         u32 dw1 = MI_SEMAPHORE_MBOX |
 643                   MI_SEMAPHORE_COMPARE |
 644                   MI_SEMAPHORE_REGISTER;
 645
 646         /* Throughout all of the GEM code, seqno passed implies our current
 647          * seqno is >= the last seqno executed. However for hardware the
 648          * comparison is strictly greater than.
 649          */
 650         seqno -= 1;
 651
 652         WARN_ON(signaller->semaphore_register[waiter->id] ==
 653                 MI_SEMAPHORE_SYNC_INVALID);
 654
 655         ret = intel_ring_begin(waiter, 4);
 656         if (ret)
 657                 return ret;
 658
 659         /* If seqno wrap happened, omit the wait with no-ops */
 660         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
 661                 intel_ring_emit(waiter,
 662                                 dw1 |
 663                                 signaller->semaphore_register[waiter->id]);
 664                 intel_ring_emit(waiter, seqno);
 665                 intel_ring_emit(waiter, 0);
 666                 intel_ring_emit(waiter, MI_NOOP);
 667         } else {
 668                 intel_ring_emit(waiter, MI_NOOP);
 669                 intel_ring_emit(waiter, MI_NOOP);
 670                 intel_ring_emit(waiter, MI_NOOP);
 671                 intel_ring_emit(waiter, MI_NOOP);
 672         }
 673         intel_ring_advance(waiter);
 674
 675         return 0;
 676 }
 677
 678 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
 679 do {                                                                    \
 680         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
 681                  PIPE_CONTROL_DEPTH_STALL);                             \
 682         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
 683         intel_ring_emit(ring__, 0);                                                     \
 684         intel_ring_emit(ring__, 0);                                                     \
 685 } while (0)
 686
 687 static int
 688 pc_render_add_request(struct intel_ring_buffer *ring)
 689 {
 690         struct pipe_control *pc = ring->private;
 691         u32 scratch_addr = pc->gtt_offset + 128;
 692         int ret;
 693
 694         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
 695          * incoherent with writes to memory, i.e. completely fubar,
 696          * so we need to use PIPE_NOTIFY instead.
 697          *
 698          * However, we also need to workaround the qword write
 699          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
 700          * memory before requesting an interrupt.
 701          */
 702         ret = intel_ring_begin(ring, 32);
 703         if (ret)
 704                 return ret;
 705
 706         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 707                         PIPE_CONTROL_WRITE_FLUSH |
 708                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
 709         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 710         intel_ring_emit(ring, ring->outstanding_lazy_request);
 711         intel_ring_emit(ring, 0);
 712         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 713         scratch_addr += 128; /* write to separate cachelines */
 714         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 715         scratch_addr += 128;
 716         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 717         scratch_addr += 128;
 718         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 719         scratch_addr += 128;
 720         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 721         scratch_addr += 128;
 722         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 723
 724         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 725                         PIPE_CONTROL_WRITE_FLUSH |
 726                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
 727                         PIPE_CONTROL_NOTIFY);
 728         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 729         intel_ring_emit(ring, ring->outstanding_lazy_request);
 730         intel_ring_emit(ring, 0);
 731         intel_ring_advance(ring);
 732
 733         return 0;
 734 }
 735
 736 static u32
 737 gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 738 {
 739         /* Workaround to force correct ordering between irq and seqno writes on
 740          * ivb (and maybe also on snb) by reading from a CS register (like
 741          * ACTHD) before reading the status page. */
 742         if (!lazy_coherency)
 743                 intel_ring_get_active_head(ring);
 744         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 745 }
 746
 747 static u32
 748 ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 749 {
 750         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 751 }
 752
 753 static void
 754 ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
 755 {
 756         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
 757 }
 758
 759 static u32
 760 pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 761 {
 762         struct pipe_control *pc = ring->private;
 763         return pc->cpu_page[0];
 764 }
 765
 766 static void
 767 pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
 768 {
 769         struct pipe_control *pc = ring->private;
 770         pc->cpu_page[0] = seqno;
 771 }
 772
 773 static bool
 774 gen5_ring_get_irq(struct intel_ring_buffer *ring)
 775 {
 776         struct drm_device *dev = ring->dev;
 777         drm_i915_private_t *dev_priv = dev->dev_private;
 778         unsigned long flags;
 779
 780         if (!dev->irq_enabled)
 781                 return false;
 782
 783         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 784         if (ring->irq_refcount++ == 0) {
 785                 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
 786                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 787                 POSTING_READ(GTIMR);
 788         }
 789         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 790
 791         return true;
 792 }
 793
 794 static void
 795 gen5_ring_put_irq(struct intel_ring_buffer *ring)
 796 {
 797         struct drm_device *dev = ring->dev;
 798         drm_i915_private_t *dev_priv = dev->dev_private;
 799         unsigned long flags;
 800
 801         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 802         if (--ring->irq_refcount == 0) {
 803                 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
 804                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 805                 POSTING_READ(GTIMR);
 806         }
 807         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 808 }
 809
 810 static bool
 811 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
 812 {
 813         struct drm_device *dev = ring->dev;
 814         drm_i915_private_t *dev_priv = dev->dev_private;
 815         unsigned long flags;
 816
 817         if (!dev->irq_enabled)
 818                 return false;
 819
 820         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 821         if (ring->irq_refcount++ == 0) {
 822                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
 823                 I915_WRITE(IMR, dev_priv->irq_mask);
 824                 POSTING_READ(IMR);
 825         }
 826         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 827
 828         return true;
 829 }
 830
 831 static void
 832 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
 833 {
 834         struct drm_device *dev = ring->dev;
 835         drm_i915_private_t *dev_priv = dev->dev_private;
 836         unsigned long flags;
 837
 838         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 839         if (--ring->irq_refcount == 0) {
 840                 dev_priv->irq_mask |= ring->irq_enable_mask;
 841                 I915_WRITE(IMR, dev_priv->irq_mask);
 842                 POSTING_READ(IMR);
 843         }
 844         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 845 }
 846
 847 static bool
 848 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
 849 {
 850         struct drm_device *dev = ring->dev;
 851         drm_i915_private_t *dev_priv = dev->dev_private;
 852         unsigned long flags;
 853
 854         if (!dev->irq_enabled)
 855                 return false;
 856
 857         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 858         if (ring->irq_refcount++ == 0) {
 859                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
 860                 I915_WRITE16(IMR, dev_priv->irq_mask);
 861                 POSTING_READ16(IMR);
 862         }
 863         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 864
 865         return true;
 866 }
 867
 868 static void
 869 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
 870 {
 871         struct drm_device *dev = ring->dev;
 872         drm_i915_private_t *dev_priv = dev->dev_private;
 873         unsigned long flags;
 874
 875         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 876         if (--ring->irq_refcount == 0) {
 877                 dev_priv->irq_mask |= ring->irq_enable_mask;
 878                 I915_WRITE16(IMR, dev_priv->irq_mask);
 879                 POSTING_READ16(IMR);
 880         }
 881         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 882 }
 883
 884 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
 885 {
 886         struct drm_device *dev = ring->dev;
 887         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 888         u32 mmio = 0;
 889
 890         /* The ring status page addresses are no longer next to the rest of
 891          * the ring registers as of gen7.
 892          */
 893         if (IS_GEN7(dev)) {
 894                 switch (ring->id) {
 895                 case RCS:
 896                         mmio = RENDER_HWS_PGA_GEN7;
 897                         break;
 898                 case BCS:
 899                         mmio = BLT_HWS_PGA_GEN7;
 900                         break;
 901                 case VCS:
 902                         mmio = BSD_HWS_PGA_GEN7;
 903                         break;
 904                 }
 905         } else if (IS_GEN6(ring->dev)) {
 906                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 907         } else {
 908                 mmio = RING_HWS_PGA(ring->mmio_base);
 909         }
 910
 911         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 912         POSTING_READ(mmio);
 913
 914         /* Flush the TLB for this page */
 915         if (INTEL_INFO(dev)->gen >= 6) {
 916                 u32 reg = RING_INSTPM(ring->mmio_base);
 917                 I915_WRITE(reg,
 918                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
 919                                               INSTPM_SYNC_FLUSH));
 920                 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
 921                              1000))
 922                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
 923                                   ring->name);
 924         }
 925 }
 926
 927 static int
 928 bsd_ring_flush(struct intel_ring_buffer *ring,
 929                u32     invalidate_domains,
 930                u32     flush_domains)
 931 {
 932         int ret;
 933
 934         ret = intel_ring_begin(ring, 2);
 935         if (ret)
 936                 return ret;
 937
 938         intel_ring_emit(ring, MI_FLUSH);
 939         intel_ring_emit(ring, MI_NOOP);
 940         intel_ring_advance(ring);
 941         return 0;
 942 }
 943
 944 static int
 945 i9xx_add_request(struct intel_ring_buffer *ring)
 946 {
 947         int ret;
 948
 949         ret = intel_ring_begin(ring, 4);
 950         if (ret)
 951                 return ret;
 952
 953         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 954         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 955         intel_ring_emit(ring, ring->outstanding_lazy_request);
 956         intel_ring_emit(ring, MI_USER_INTERRUPT);
 957         intel_ring_advance(ring);
 958
 959         return 0;
 960 }
 961
 962 static bool
 963 gen6_ring_get_irq(struct intel_ring_buffer *ring)
 964 {
 965         struct drm_device *dev = ring->dev;
 966         drm_i915_private_t *dev_priv = dev->dev_private;
 967         unsigned long flags;
 968
 969         if (!dev->irq_enabled)
 970                return false;
 971
 972         /* It looks like we need to prevent the gt from suspending while waiting
 973          * for an notifiy irq, otherwise irqs seem to get lost on at least the
 974          * blt/bsd rings on ivb. */
 975         gen6_gt_force_wake_get(dev_priv);
 976
 977         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 978         if (ring->irq_refcount++ == 0) {
 979                 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
 980                         I915_WRITE_IMR(ring, ~(ring->irq_enable_mask |
 981                                                 GEN6_RENDER_L3_PARITY_ERROR));
 982                 else
 983                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
 984                 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
 985                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 986                 POSTING_READ(GTIMR);
 987         }
 988         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 989
 990         return true;
 991 }
 992
 993 static void
 994 gen6_ring_put_irq(struct intel_ring_buffer *ring)
 995 {
 996         struct drm_device *dev = ring->dev;
 997         drm_i915_private_t *dev_priv = dev->dev_private;
 998         unsigned long flags;
 999
1000         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1001         if (--ring->irq_refcount == 0) {
1002                 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
1003                         I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
1004                 else
1005                         I915_WRITE_IMR(ring, ~0);
1006                 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
1007                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1008                 POSTING_READ(GTIMR);
1009         }
1010         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1011
1012         gen6_gt_force_wake_put(dev_priv);
1013 }
1014
1015 static int
1016 i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
1017                          u32 offset, u32 length,
1018                          unsigned flags)
1019 {
1020         int ret;
1021
1022         ret = intel_ring_begin(ring, 2);
1023         if (ret)
1024                 return ret;
1025
1026         intel_ring_emit(ring,
1027                         MI_BATCH_BUFFER_START |
1028                         MI_BATCH_GTT |
1029                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1030         intel_ring_emit(ring, offset);
1031         intel_ring_advance(ring);
1032
1033         return 0;
1034 }
1035
1036 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1037 #define I830_BATCH_LIMIT (256*1024)
1038 static int
1039 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
1040                                 u32 offset, u32 len,
1041                                 unsigned flags)
1042 {
1043         int ret;
1044
1045         if (flags & I915_DISPATCH_PINNED) {
1046                 ret = intel_ring_begin(ring, 4);
1047                 if (ret)
1048                         return ret;
1049
1050                 intel_ring_emit(ring, MI_BATCH_BUFFER);
1051                 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1052                 intel_ring_emit(ring, offset + len - 8);
1053                 intel_ring_emit(ring, MI_NOOP);
1054                 intel_ring_advance(ring);
1055         } else {
1056                 struct drm_i915_gem_object *obj = ring->private;
1057                 u32 cs_offset = obj->gtt_offset;
1058
1059                 if (len > I830_BATCH_LIMIT)
1060                         return -ENOSPC;
1061
1062                 ret = intel_ring_begin(ring, 9+3);
1063                 if (ret)
1064                         return ret;
1065                 /* Blit the batch (which has now all relocs applied) to the stable batch
1066                  * scratch bo area (so that the CS never stumbles over its tlb
1067                  * invalidation bug) ... */
1068                 intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD |
1069                                 XY_SRC_COPY_BLT_WRITE_ALPHA |
1070                                 XY_SRC_COPY_BLT_WRITE_RGB);
1071                 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096);
1072                 intel_ring_emit(ring, 0);
1073                 intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024);
1074                 intel_ring_emit(ring, cs_offset);
1075                 intel_ring_emit(ring, 0);
1076                 intel_ring_emit(ring, 4096);
1077                 intel_ring_emit(ring, offset);
1078                 intel_ring_emit(ring, MI_FLUSH);
1079
1080                 /* ... and execute it. */
1081                 intel_ring_emit(ring, MI_BATCH_BUFFER);
1082                 intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1083                 intel_ring_emit(ring, cs_offset + len - 8);
1084                 intel_ring_advance(ring);
1085         }
1086
1087         return 0;
1088 }
1089
1090 static int
1091 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
1092                          u32 offset, u32 len,
1093                          unsigned flags)
1094 {
1095         int ret;
1096
1097         ret = intel_ring_begin(ring, 2);
1098         if (ret)
1099                 return ret;
1100
1101         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1102         intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1103         intel_ring_advance(ring);
1104
1105         return 0;
1106 }
1107
1108 static void cleanup_status_page(struct intel_ring_buffer *ring)
1109 {
1110         struct drm_i915_gem_object *obj;
1111
1112         obj = ring->status_page.obj;
1113         if (obj == NULL)
1114                 return;
1115
1116         kunmap(sg_page(obj->pages->sgl));
1117         i915_gem_object_unpin(obj);
1118         drm_gem_object_unreference(&obj->base);
1119         ring->status_page.obj = NULL;
1120 }
1121
1122 static int init_status_page(struct intel_ring_buffer *ring)
1123 {
1124         struct drm_device *dev = ring->dev;
1125         struct drm_i915_gem_object *obj;
1126         int ret;
1127
1128         obj = i915_gem_alloc_object(dev, 4096);
1129         if (obj == NULL) {
1130                 DRM_ERROR("Failed to allocate status page\n");
1131                 ret = -ENOMEM;
1132                 goto err;
1133         }
1134
1135         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1136
1137         ret = i915_gem_object_pin(obj, 4096, true, false);
1138         if (ret != 0) {
1139                 goto err_unref;
1140         }
1141
1142         ring->status_page.gfx_addr = obj->gtt_offset;
1143         ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1144         if (ring->status_page.page_addr == NULL) {
1145                 ret = -ENOMEM;
1146                 goto err_unpin;
1147         }
1148         ring->status_page.obj = obj;
1149         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1150
1151         intel_ring_setup_status_page(ring);
1152         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1153                         ring->name, ring->status_page.gfx_addr);
1154
1155         return 0;
1156
1157 err_unpin:
1158         i915_gem_object_unpin(obj);
1159 err_unref:
1160         drm_gem_object_unreference(&obj->base);
1161 err:
1162         return ret;
1163 }
1164
1165 static int init_phys_hws_pga(struct intel_ring_buffer *ring)
1166 {
1167         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1168         u32 addr;
1169
1170         if (!dev_priv->status_page_dmah) {
1171                 dev_priv->status_page_dmah =
1172                         drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1173                 if (!dev_priv->status_page_dmah)
1174                         return -ENOMEM;
1175         }
1176
1177         addr = dev_priv->status_page_dmah->busaddr;
1178         if (INTEL_INFO(ring->dev)->gen >= 4)
1179                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
1180         I915_WRITE(HWS_PGA, addr);
1181
1182         ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1183         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1184
1185         return 0;
1186 }
1187
1188 static int intel_init_ring_buffer(struct drm_device *dev,
1189                                   struct intel_ring_buffer *ring)
1190 {
1191         struct drm_i915_gem_object *obj;
1192         struct drm_i915_private *dev_priv = dev->dev_private;
1193         int ret;
1194
1195         ring->dev = dev;
1196         INIT_LIST_HEAD(&ring->active_list);
1197         INIT_LIST_HEAD(&ring->request_list);
1198         ring->size = 32 * PAGE_SIZE;
1199         memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno));
1200
1201         init_waitqueue_head(&ring->irq_queue);
1202
1203         if (I915_NEED_GFX_HWS(dev)) {
1204                 ret = init_status_page(ring);
1205                 if (ret)
1206                         return ret;
1207         } else {
1208                 BUG_ON(ring->id != RCS);
1209                 ret = init_phys_hws_pga(ring);
1210                 if (ret)
1211                         return ret;
1212         }
1213
1214         obj = NULL;
1215         if (!HAS_LLC(dev))
1216                 obj = i915_gem_object_create_stolen(dev, ring->size);
1217         if (obj == NULL)
1218                 obj = i915_gem_alloc_object(dev, ring->size);
1219         if (obj == NULL) {
1220                 DRM_ERROR("Failed to allocate ringbuffer\n");
1221                 ret = -ENOMEM;
1222                 goto err_hws;
1223         }
1224
1225         ring->obj = obj;
1226
1227         ret = i915_gem_object_pin(obj, PAGE_SIZE, true, false);
1228         if (ret)
1229                 goto err_unref;
1230
1231         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1232         if (ret)
1233                 goto err_unpin;
1234
1235         ring->virtual_start =
1236                 ioremap_wc(dev_priv->gtt.mappable_base + obj->gtt_offset,
1237                            ring->size);
1238         if (ring->virtual_start == NULL) {
1239                 DRM_ERROR("Failed to map ringbuffer.\n");
1240                 ret = -EINVAL;
1241                 goto err_unpin;
1242         }
1243
1244         ret = ring->init(ring);
1245         if (ret)
1246                 goto err_unmap;
1247
1248         /* Workaround an erratum on the i830 which causes a hang if
1249          * the TAIL pointer points to within the last 2 cachelines
1250          * of the buffer.
1251          */
1252         ring->effective_size = ring->size;
1253         if (IS_I830(ring->dev) || IS_845G(ring->dev))
1254                 ring->effective_size -= 128;
1255
1256         return 0;
1257
1258 err_unmap:
1259         iounmap(ring->virtual_start);
1260 err_unpin:
1261         i915_gem_object_unpin(obj);
1262 err_unref:
1263         drm_gem_object_unreference(&obj->base);
1264         ring->obj = NULL;
1265 err_hws:
1266         cleanup_status_page(ring);
1267         return ret;
1268 }
1269
1270 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1271 {
1272         struct drm_i915_private *dev_priv;
1273         int ret;
1274
1275         if (ring->obj == NULL)
1276                 return;
1277
1278         /* Disable the ring buffer. The ring must be idle at this point */
1279         dev_priv = ring->dev->dev_private;
1280         ret = intel_ring_idle(ring);
1281         if (ret)
1282                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1283                           ring->name, ret);
1284
1285         I915_WRITE_CTL(ring, 0);
1286
1287         iounmap(ring->virtual_start);
1288
1289         i915_gem_object_unpin(ring->obj);
1290         drm_gem_object_unreference(&ring->obj->base);
1291         ring->obj = NULL;
1292
1293         if (ring->cleanup)
1294                 ring->cleanup(ring);
1295
1296         cleanup_status_page(ring);
1297 }
1298
1299 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1300 {
1301         int ret;
1302
1303         ret = i915_wait_seqno(ring, seqno);
1304         if (!ret)
1305                 i915_gem_retire_requests_ring(ring);
1306
1307         return ret;
1308 }
1309
1310 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1311 {
1312         struct drm_i915_gem_request *request;
1313         u32 seqno = 0;
1314         int ret;
1315
1316         i915_gem_retire_requests_ring(ring);
1317
1318         if (ring->last_retired_head != -1) {
1319                 ring->head = ring->last_retired_head;
1320                 ring->last_retired_head = -1;
1321                 ring->space = ring_space(ring);
1322                 if (ring->space >= n)
1323                         return 0;
1324         }
1325
1326         list_for_each_entry(request, &ring->request_list, list) {
1327                 int space;
1328
1329                 if (request->tail == -1)
1330                         continue;
1331
1332                 space = request->tail - (ring->tail + I915_RING_FREE_SPACE);
1333                 if (space < 0)
1334                         space += ring->size;
1335                 if (space >= n) {
1336                         seqno = request->seqno;
1337                         break;
1338                 }
1339
1340                 /* Consume this request in case we need more space than
1341                  * is available and so need to prevent a race between
1342                  * updating last_retired_head and direct reads of
1343                  * I915_RING_HEAD. It also provides a nice sanity check.
1344                  */
1345                 request->tail = -1;
1346         }
1347
1348         if (seqno == 0)
1349                 return -ENOSPC;
1350
1351         ret = intel_ring_wait_seqno(ring, seqno);
1352         if (ret)
1353                 return ret;
1354
1355         if (WARN_ON(ring->last_retired_head == -1))
1356                 return -ENOSPC;
1357
1358         ring->head = ring->last_retired_head;
1359         ring->last_retired_head = -1;
1360         ring->space = ring_space(ring);
1361         if (WARN_ON(ring->space < n))
1362                 return -ENOSPC;
1363
1364         return 0;
1365 }
1366
1367 static int ring_wait_for_space(struct intel_ring_buffer *ring, int n)
1368 {
1369         struct drm_device *dev = ring->dev;
1370         struct drm_i915_private *dev_priv = dev->dev_private;
1371         unsigned long end;
1372         int ret;
1373
1374         ret = intel_ring_wait_request(ring, n);
1375         if (ret != -ENOSPC)
1376                 return ret;
1377
1378         trace_i915_ring_wait_begin(ring);
1379         /* With GEM the hangcheck timer should kick us out of the loop,
1380          * leaving it early runs the risk of corrupting GEM state (due
1381          * to running on almost untested codepaths). But on resume
1382          * timers don't work yet, so prevent a complete hang in that
1383          * case by choosing an insanely large timeout. */
1384         end = jiffies + 60 * HZ;
1385
1386         do {
1387                 ring->head = I915_READ_HEAD(ring);
1388                 ring->space = ring_space(ring);
1389                 if (ring->space >= n) {
1390                         trace_i915_ring_wait_end(ring);
1391                         return 0;
1392                 }
1393
1394                 if (dev->primary->master) {
1395                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1396                         if (master_priv->sarea_priv)
1397                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1398                 }
1399
1400                 msleep(1);
1401
1402                 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1403                                            dev_priv->mm.interruptible);
1404                 if (ret)
1405                         return ret;
1406         } while (!time_after(jiffies, end));
1407         trace_i915_ring_wait_end(ring);
1408         return -EBUSY;
1409 }
1410
1411 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1412 {
1413         uint32_t __iomem *virt;
1414         int rem = ring->size - ring->tail;
1415
1416         if (ring->space < rem) {
1417                 int ret = ring_wait_for_space(ring, rem);
1418                 if (ret)
1419                         return ret;
1420         }
1421
1422         virt = ring->virtual_start + ring->tail;
1423         rem /= 4;
1424         while (rem--)
1425                 iowrite32(MI_NOOP, virt++);
1426
1427         ring->tail = 0;
1428         ring->space = ring_space(ring);
1429
1430         return 0;
1431 }
1432
1433 int intel_ring_idle(struct intel_ring_buffer *ring)
1434 {
1435         u32 seqno;
1436         int ret;
1437
1438         /* We need to add any requests required to flush the objects and ring */
1439         if (ring->outstanding_lazy_request) {
1440                 ret = i915_add_request(ring, NULL, NULL);
1441                 if (ret)
1442                         return ret;
1443         }
1444
1445         /* Wait upon the last request to be completed */
1446         if (list_empty(&ring->request_list))
1447                 return 0;
1448
1449         seqno = list_entry(ring->request_list.prev,
1450                            struct drm_i915_gem_request,
1451                            list)->seqno;
1452
1453         return i915_wait_seqno(ring, seqno);
1454 }
1455
1456 static int
1457 intel_ring_alloc_seqno(struct intel_ring_buffer *ring)
1458 {
1459         if (ring->outstanding_lazy_request)
1460                 return 0;
1461
1462         return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_request);
1463 }
1464
1465 static int __intel_ring_prepare(struct intel_ring_buffer *ring,
1466                                 int bytes)
1467 {
1468         int ret;
1469
1470         if (unlikely(ring->tail + bytes > ring->effective_size)) {
1471                 ret = intel_wrap_ring_buffer(ring);
1472                 if (unlikely(ret))
1473                         return ret;
1474         }
1475
1476         if (unlikely(ring->space < bytes)) {
1477                 ret = ring_wait_for_space(ring, bytes);
1478                 if (unlikely(ret))
1479                         return ret;
1480         }
1481
1482         return 0;
1483 }
1484
1485 int intel_ring_begin(struct intel_ring_buffer *ring,
1486                      int num_dwords)
1487 {
1488         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1489         int ret;
1490
1491         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1492                                    dev_priv->mm.interruptible);
1493         if (ret)
1494                 return ret;
1495
1496         ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
1497         if (ret)
1498                 return ret;
1499
1500         /* Preallocate the olr before touching the ring */
1501         ret = intel_ring_alloc_seqno(ring);
1502         if (ret)
1503                 return ret;
1504
1505         ring->space -= num_dwords * sizeof(uint32_t);
1506         return 0;
1507 }
1508
1509 void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno)
1510 {
1511         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1512
1513         BUG_ON(ring->outstanding_lazy_request);
1514
1515         if (INTEL_INFO(ring->dev)->gen >= 6) {
1516                 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
1517                 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
1518         }
1519
1520         ring->set_seqno(ring, seqno);
1521 }
1522
1523 void intel_ring_advance(struct intel_ring_buffer *ring)
1524 {
1525         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1526
1527         ring->tail &= ring->size - 1;
1528         if (dev_priv->gpu_error.stop_rings & intel_ring_flag(ring))
1529                 return;
1530         ring->write_tail(ring, ring->tail);
1531 }
1532
1533
1534 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1535                                      u32 value)
1536 {
1537         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1538
1539        /* Every tail move must follow the sequence below */
1540
1541         /* Disable notification that the ring is IDLE. The GT
1542          * will then assume that it is busy and bring it out of rc6.
1543          */
1544         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1545                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1546
1547         /* Clear the context id. Here be magic! */
1548         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1549
1550         /* Wait for the ring not to be idle, i.e. for it to wake up. */
1551         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1552                       GEN6_BSD_SLEEP_INDICATOR) == 0,
1553                      50))
1554                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1555
1556         /* Now that the ring is fully powered up, update the tail */
1557         I915_WRITE_TAIL(ring, value);
1558         POSTING_READ(RING_TAIL(ring->mmio_base));
1559
1560         /* Let the ring send IDLE messages to the GT again,
1561          * and so let it sleep to conserve power when idle.
1562          */
1563         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1564                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1565 }
1566
1567 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1568                            u32 invalidate, u32 flush)
1569 {
1570         uint32_t cmd;
1571         int ret;
1572
1573         ret = intel_ring_begin(ring, 4);
1574         if (ret)
1575                 return ret;
1576
1577         cmd = MI_FLUSH_DW;
1578         /*
1579          * Bspec vol 1c.5 - video engine command streamer:
1580          * "If ENABLED, all TLBs will be invalidated once the flush
1581          * operation is complete. This bit is only valid when the
1582          * Post-Sync Operation field is a value of 1h or 3h."
1583          */
1584         if (invalidate & I915_GEM_GPU_DOMAINS)
1585                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1586                         MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1587         intel_ring_emit(ring, cmd);
1588         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1589         intel_ring_emit(ring, 0);
1590         intel_ring_emit(ring, MI_NOOP);
1591         intel_ring_advance(ring);
1592         return 0;
1593 }
1594
1595 static int
1596 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1597                               u32 offset, u32 len,
1598                               unsigned flags)
1599 {
1600         int ret;
1601
1602         ret = intel_ring_begin(ring, 2);
1603         if (ret)
1604                 return ret;
1605
1606         intel_ring_emit(ring,
1607                         MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
1608                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
1609         /* bit0-7 is the length on GEN6+ */
1610         intel_ring_emit(ring, offset);
1611         intel_ring_advance(ring);
1612
1613         return 0;
1614 }
1615
1616 static int
1617 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1618                               u32 offset, u32 len,
1619                               unsigned flags)
1620 {
1621         int ret;
1622
1623         ret = intel_ring_begin(ring, 2);
1624         if (ret)
1625                 return ret;
1626
1627         intel_ring_emit(ring,
1628                         MI_BATCH_BUFFER_START |
1629                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1630         /* bit0-7 is the length on GEN6+ */
1631         intel_ring_emit(ring, offset);
1632         intel_ring_advance(ring);
1633
1634         return 0;
1635 }
1636
1637 /* Blitter support (SandyBridge+) */
1638
1639 static int blt_ring_flush(struct intel_ring_buffer *ring,
1640                           u32 invalidate, u32 flush)
1641 {
1642         uint32_t cmd;
1643         int ret;
1644
1645         ret = intel_ring_begin(ring, 4);
1646         if (ret)
1647                 return ret;
1648
1649         cmd = MI_FLUSH_DW;
1650         /*
1651          * Bspec vol 1c.3 - blitter engine command streamer:
1652          * "If ENABLED, all TLBs will be invalidated once the flush
1653          * operation is complete. This bit is only valid when the
1654          * Post-Sync Operation field is a value of 1h or 3h."
1655          */
1656         if (invalidate & I915_GEM_DOMAIN_RENDER)
1657                 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
1658                         MI_FLUSH_DW_OP_STOREDW;
1659         intel_ring_emit(ring, cmd);
1660         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1661         intel_ring_emit(ring, 0);
1662         intel_ring_emit(ring, MI_NOOP);
1663         intel_ring_advance(ring);
1664         return 0;
1665 }
1666
1667 int intel_init_render_ring_buffer(struct drm_device *dev)
1668 {
1669         drm_i915_private_t *dev_priv = dev->dev_private;
1670         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1671
1672         ring->name = "render ring";
1673         ring->id = RCS;
1674         ring->mmio_base = RENDER_RING_BASE;
1675
1676         if (INTEL_INFO(dev)->gen >= 6) {
1677                 ring->add_request = gen6_add_request;
1678                 ring->flush = gen7_render_ring_flush;
1679                 if (INTEL_INFO(dev)->gen == 6)
1680                         ring->flush = gen6_render_ring_flush;
1681                 ring->irq_get = gen6_ring_get_irq;
1682                 ring->irq_put = gen6_ring_put_irq;
1683                 ring->irq_enable_mask = GT_USER_INTERRUPT;
1684                 ring->get_seqno = gen6_ring_get_seqno;
1685                 ring->set_seqno = ring_set_seqno;
1686                 ring->sync_to = gen6_ring_sync;
1687                 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
1688                 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
1689                 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
1690                 ring->signal_mbox[0] = GEN6_VRSYNC;
1691                 ring->signal_mbox[1] = GEN6_BRSYNC;
1692         } else if (IS_GEN5(dev)) {
1693                 ring->add_request = pc_render_add_request;
1694                 ring->flush = gen4_render_ring_flush;
1695                 ring->get_seqno = pc_render_get_seqno;
1696                 ring->set_seqno = pc_render_set_seqno;
1697                 ring->irq_get = gen5_ring_get_irq;
1698                 ring->irq_put = gen5_ring_put_irq;
1699                 ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
1700         } else {
1701                 ring->add_request = i9xx_add_request;
1702                 if (INTEL_INFO(dev)->gen < 4)
1703                         ring->flush = gen2_render_ring_flush;
1704                 else
1705                         ring->flush = gen4_render_ring_flush;
1706                 ring->get_seqno = ring_get_seqno;
1707                 ring->set_seqno = ring_set_seqno;
1708                 if (IS_GEN2(dev)) {
1709                         ring->irq_get = i8xx_ring_get_irq;
1710                         ring->irq_put = i8xx_ring_put_irq;
1711                 } else {
1712                         ring->irq_get = i9xx_ring_get_irq;
1713                         ring->irq_put = i9xx_ring_put_irq;
1714                 }
1715                 ring->irq_enable_mask = I915_USER_INTERRUPT;
1716         }
1717         ring->write_tail = ring_write_tail;
1718         if (IS_HASWELL(dev))
1719                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1720         else if (INTEL_INFO(dev)->gen >= 6)
1721                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1722         else if (INTEL_INFO(dev)->gen >= 4)
1723                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1724         else if (IS_I830(dev) || IS_845G(dev))
1725                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1726         else
1727                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1728         ring->init = init_render_ring;
1729         ring->cleanup = render_ring_cleanup;
1730
1731         /* Workaround batchbuffer to combat CS tlb bug. */
1732         if (HAS_BROKEN_CS_TLB(dev)) {
1733                 struct drm_i915_gem_object *obj;
1734                 int ret;
1735
1736                 obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT);
1737                 if (obj == NULL) {
1738                         DRM_ERROR("Failed to allocate batch bo\n");
1739                         return -ENOMEM;
1740                 }
1741
1742                 ret = i915_gem_object_pin(obj, 0, true, false);
1743                 if (ret != 0) {
1744                         drm_gem_object_unreference(&obj->base);
1745                         DRM_ERROR("Failed to ping batch bo\n");
1746                         return ret;
1747                 }
1748
1749                 ring->private = obj;
1750         }
1751
1752         return intel_init_ring_buffer(dev, ring);
1753 }
1754
1755 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1756 {
1757         drm_i915_private_t *dev_priv = dev->dev_private;
1758         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1759         int ret;
1760
1761         ring->name = "render ring";
1762         ring->id = RCS;
1763         ring->mmio_base = RENDER_RING_BASE;
1764
1765         if (INTEL_INFO(dev)->gen >= 6) {
1766                 /* non-kms not supported on gen6+ */
1767                 return -ENODEV;
1768         }
1769
1770         /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1771          * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1772          * the special gen5 functions. */
1773         ring->add_request = i9xx_add_request;
1774         if (INTEL_INFO(dev)->gen < 4)
1775                 ring->flush = gen2_render_ring_flush;
1776         else
1777                 ring->flush = gen4_render_ring_flush;
1778         ring->get_seqno = ring_get_seqno;
1779         ring->set_seqno = ring_set_seqno;
1780         if (IS_GEN2(dev)) {
1781                 ring->irq_get = i8xx_ring_get_irq;
1782                 ring->irq_put = i8xx_ring_put_irq;
1783         } else {
1784                 ring->irq_get = i9xx_ring_get_irq;
1785                 ring->irq_put = i9xx_ring_put_irq;
1786         }
1787         ring->irq_enable_mask = I915_USER_INTERRUPT;
1788         ring->write_tail = ring_write_tail;
1789         if (INTEL_INFO(dev)->gen >= 4)
1790                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1791         else if (IS_I830(dev) || IS_845G(dev))
1792                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1793         else
1794                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1795         ring->init = init_render_ring;
1796         ring->cleanup = render_ring_cleanup;
1797
1798         ring->dev = dev;
1799         INIT_LIST_HEAD(&ring->active_list);
1800         INIT_LIST_HEAD(&ring->request_list);
1801
1802         ring->size = size;
1803         ring->effective_size = ring->size;
1804         if (IS_I830(ring->dev) || IS_845G(ring->dev))
1805                 ring->effective_size -= 128;
1806
1807         ring->virtual_start = ioremap_wc(start, size);
1808         if (ring->virtual_start == NULL) {
1809                 DRM_ERROR("can not ioremap virtual address for"
1810                           " ring buffer\n");
1811                 return -ENOMEM;
1812         }
1813
1814         if (!I915_NEED_GFX_HWS(dev)) {
1815                 ret = init_phys_hws_pga(ring);
1816                 if (ret)
1817                         return ret;
1818         }
1819
1820         return 0;
1821 }
1822
1823 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1824 {
1825         drm_i915_private_t *dev_priv = dev->dev_private;
1826         struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1827
1828         ring->name = "bsd ring";
1829         ring->id = VCS;
1830
1831         ring->write_tail = ring_write_tail;
1832         if (IS_GEN6(dev) || IS_GEN7(dev)) {
1833                 ring->mmio_base = GEN6_BSD_RING_BASE;
1834                 /* gen6 bsd needs a special wa for tail updates */
1835                 if (IS_GEN6(dev))
1836                         ring->write_tail = gen6_bsd_ring_write_tail;
1837                 ring->flush = gen6_ring_flush;
1838                 ring->add_request = gen6_add_request;
1839                 ring->get_seqno = gen6_ring_get_seqno;
1840                 ring->set_seqno = ring_set_seqno;
1841                 ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT;
1842                 ring->irq_get = gen6_ring_get_irq;
1843                 ring->irq_put = gen6_ring_put_irq;
1844                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1845                 ring->sync_to = gen6_ring_sync;
1846                 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
1847                 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
1848                 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
1849                 ring->signal_mbox[0] = GEN6_RVSYNC;
1850                 ring->signal_mbox[1] = GEN6_BVSYNC;
1851         } else {
1852                 ring->mmio_base = BSD_RING_BASE;
1853                 ring->flush = bsd_ring_flush;
1854                 ring->add_request = i9xx_add_request;
1855                 ring->get_seqno = ring_get_seqno;
1856                 ring->set_seqno = ring_set_seqno;
1857                 if (IS_GEN5(dev)) {
1858                         ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1859                         ring->irq_get = gen5_ring_get_irq;
1860                         ring->irq_put = gen5_ring_put_irq;
1861                 } else {
1862                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1863                         ring->irq_get = i9xx_ring_get_irq;
1864                         ring->irq_put = i9xx_ring_put_irq;
1865                 }
1866                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1867         }
1868         ring->init = init_ring_common;
1869
1870         return intel_init_ring_buffer(dev, ring);
1871 }
1872
1873 int intel_init_blt_ring_buffer(struct drm_device *dev)
1874 {
1875         drm_i915_private_t *dev_priv = dev->dev_private;
1876         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1877
1878         ring->name = "blitter ring";
1879         ring->id = BCS;
1880
1881         ring->mmio_base = BLT_RING_BASE;
1882         ring->write_tail = ring_write_tail;
1883         ring->flush = blt_ring_flush;
1884         ring->add_request = gen6_add_request;
1885         ring->get_seqno = gen6_ring_get_seqno;
1886         ring->set_seqno = ring_set_seqno;
1887         ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT;
1888         ring->irq_get = gen6_ring_get_irq;
1889         ring->irq_put = gen6_ring_put_irq;
1890         ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1891         ring->sync_to = gen6_ring_sync;
1892         ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
1893         ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
1894         ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
1895         ring->signal_mbox[0] = GEN6_RBSYNC;
1896         ring->signal_mbox[1] = GEN6_VBSYNC;
1897         ring->init = init_ring_common;
1898
1899         return intel_init_ring_buffer(dev, ring);
1900 }
1901
1902 int
1903 intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
1904 {
1905         int ret;
1906
1907         if (!ring->gpu_caches_dirty)
1908                 return 0;
1909
1910         ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
1911         if (ret)
1912                 return ret;
1913
1914         trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
1915
1916         ring->gpu_caches_dirty = false;
1917         return 0;
1918 }
1919
1920 int
1921 intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
1922 {
1923         uint32_t flush_domains;
1924         int ret;
1925
1926         flush_domains = 0;
1927         if (ring->gpu_caches_dirty)
1928                 flush_domains = I915_GEM_GPU_DOMAINS;
1929
1930         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
1931         if (ret)
1932                 return ret;
1933
1934         trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
1935
1936         ring->gpu_caches_dirty = false;
1937         return 0;
1938 }