2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
37 intel_ring_initialized(struct intel_engine_cs *ring)
39 struct drm_device *dev = ring->dev;
44 if (i915.enable_execlists) {
45 struct intel_context *dctx = ring->default_context;
46 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
50 return ring->buffer && ring->buffer->obj;
53 int __intel_ring_space(int head, int tail, int size)
55 int space = head - tail;
58 return space - I915_RING_FREE_SPACE;
61 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
63 if (ringbuf->last_retired_head != -1) {
64 ringbuf->head = ringbuf->last_retired_head;
65 ringbuf->last_retired_head = -1;
68 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
69 ringbuf->tail, ringbuf->size);
72 int intel_ring_space(struct intel_ringbuffer *ringbuf)
74 intel_ring_update_space(ringbuf);
75 return ringbuf->space;
78 bool intel_ring_stopped(struct intel_engine_cs *ring)
80 struct drm_i915_private *dev_priv = ring->dev->dev_private;
81 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
84 static void __intel_ring_advance(struct intel_engine_cs *ring)
86 struct intel_ringbuffer *ringbuf = ring->buffer;
87 ringbuf->tail &= ringbuf->size - 1;
88 if (intel_ring_stopped(ring))
90 ring->write_tail(ring, ringbuf->tail);
94 gen2_render_ring_flush(struct drm_i915_gem_request *req,
95 u32 invalidate_domains,
98 struct intel_engine_cs *ring = req->ring;
103 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
104 cmd |= MI_NO_WRITE_FLUSH;
106 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
107 cmd |= MI_READ_FLUSH;
109 ret = intel_ring_begin(req, 2);
113 intel_ring_emit(ring, cmd);
114 intel_ring_emit(ring, MI_NOOP);
115 intel_ring_advance(ring);
121 gen4_render_ring_flush(struct drm_i915_gem_request *req,
122 u32 invalidate_domains,
125 struct intel_engine_cs *ring = req->ring;
126 struct drm_device *dev = ring->dev;
133 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
134 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
135 * also flushed at 2d versus 3d pipeline switches.
139 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
140 * MI_READ_FLUSH is set, and is always flushed on 965.
142 * I915_GEM_DOMAIN_COMMAND may not exist?
144 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
145 * invalidated when MI_EXE_FLUSH is set.
147 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
148 * invalidated with every MI_FLUSH.
152 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
153 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
154 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
155 * are flushed at any MI_FLUSH.
158 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
159 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
160 cmd &= ~MI_NO_WRITE_FLUSH;
161 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
164 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
165 (IS_G4X(dev) || IS_GEN5(dev)))
166 cmd |= MI_INVALIDATE_ISP;
168 ret = intel_ring_begin(req, 2);
172 intel_ring_emit(ring, cmd);
173 intel_ring_emit(ring, MI_NOOP);
174 intel_ring_advance(ring);
180 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
181 * implementing two workarounds on gen6. From section 1.4.7.1
182 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
184 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
185 * produced by non-pipelined state commands), software needs to first
186 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
189 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
190 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
192 * And the workaround for these two requires this workaround first:
194 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
195 * BEFORE the pipe-control with a post-sync op and no write-cache
198 * And this last workaround is tricky because of the requirements on
199 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
202 * "1 of the following must also be set:
203 * - Render Target Cache Flush Enable ([12] of DW1)
204 * - Depth Cache Flush Enable ([0] of DW1)
205 * - Stall at Pixel Scoreboard ([1] of DW1)
206 * - Depth Stall ([13] of DW1)
207 * - Post-Sync Operation ([13] of DW1)
208 * - Notify Enable ([8] of DW1)"
210 * The cache flushes require the workaround flush that triggered this
211 * one, so we can't use it. Depth stall would trigger the same.
212 * Post-sync nonzero is what triggered this second workaround, so we
213 * can't use that one either. Notify enable is IRQs, which aren't
214 * really our business. That leaves only stall at scoreboard.
217 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
219 struct intel_engine_cs *ring = req->ring;
220 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
223 ret = intel_ring_begin(req, 6);
227 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
228 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
229 PIPE_CONTROL_STALL_AT_SCOREBOARD);
230 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
231 intel_ring_emit(ring, 0); /* low dword */
232 intel_ring_emit(ring, 0); /* high dword */
233 intel_ring_emit(ring, MI_NOOP);
234 intel_ring_advance(ring);
236 ret = intel_ring_begin(req, 6);
240 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
241 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
242 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
243 intel_ring_emit(ring, 0);
244 intel_ring_emit(ring, 0);
245 intel_ring_emit(ring, MI_NOOP);
246 intel_ring_advance(ring);
252 gen6_render_ring_flush(struct drm_i915_gem_request *req,
253 u32 invalidate_domains, u32 flush_domains)
255 struct intel_engine_cs *ring = req->ring;
257 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
260 /* Force SNB workarounds for PIPE_CONTROL flushes */
261 ret = intel_emit_post_sync_nonzero_flush(req);
265 /* Just flush everything. Experiments have shown that reducing the
266 * number of bits based on the write domains has little performance
270 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
271 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
273 * Ensure that any following seqno writes only happen
274 * when the render cache is indeed flushed.
276 flags |= PIPE_CONTROL_CS_STALL;
278 if (invalidate_domains) {
279 flags |= PIPE_CONTROL_TLB_INVALIDATE;
280 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
281 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
282 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
283 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
284 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
286 * TLB invalidate requires a post-sync write.
288 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
291 ret = intel_ring_begin(req, 4);
295 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
296 intel_ring_emit(ring, flags);
297 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
298 intel_ring_emit(ring, 0);
299 intel_ring_advance(ring);
305 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
307 struct intel_engine_cs *ring = req->ring;
310 ret = intel_ring_begin(req, 4);
314 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
315 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
316 PIPE_CONTROL_STALL_AT_SCOREBOARD);
317 intel_ring_emit(ring, 0);
318 intel_ring_emit(ring, 0);
319 intel_ring_advance(ring);
325 gen7_render_ring_flush(struct drm_i915_gem_request *req,
326 u32 invalidate_domains, u32 flush_domains)
328 struct intel_engine_cs *ring = req->ring;
330 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
334 * Ensure that any following seqno writes only happen when the render
335 * cache is indeed flushed.
337 * Workaround: 4th PIPE_CONTROL command (except the ones with only
338 * read-cache invalidate bits set) must have the CS_STALL bit set. We
339 * don't try to be clever and just set it unconditionally.
341 flags |= PIPE_CONTROL_CS_STALL;
343 /* Just flush everything. Experiments have shown that reducing the
344 * number of bits based on the write domains has little performance
348 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
349 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
351 if (invalidate_domains) {
352 flags |= PIPE_CONTROL_TLB_INVALIDATE;
353 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
354 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
355 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
356 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
357 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
358 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
360 * TLB invalidate requires a post-sync write.
362 flags |= PIPE_CONTROL_QW_WRITE;
363 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
365 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
367 /* Workaround: we must issue a pipe_control with CS-stall bit
368 * set before a pipe_control command that has the state cache
369 * invalidate bit set. */
370 gen7_render_ring_cs_stall_wa(req);
373 ret = intel_ring_begin(req, 4);
377 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
378 intel_ring_emit(ring, flags);
379 intel_ring_emit(ring, scratch_addr);
380 intel_ring_emit(ring, 0);
381 intel_ring_advance(ring);
387 gen8_emit_pipe_control(struct drm_i915_gem_request *req,
388 u32 flags, u32 scratch_addr)
390 struct intel_engine_cs *ring = req->ring;
393 ret = intel_ring_begin(req, 6);
397 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
398 intel_ring_emit(ring, flags);
399 intel_ring_emit(ring, scratch_addr);
400 intel_ring_emit(ring, 0);
401 intel_ring_emit(ring, 0);
402 intel_ring_emit(ring, 0);
403 intel_ring_advance(ring);
409 gen8_render_ring_flush(struct drm_i915_gem_request *req,
410 u32 invalidate_domains, u32 flush_domains)
413 u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
416 flags |= PIPE_CONTROL_CS_STALL;
419 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
420 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
422 if (invalidate_domains) {
423 flags |= PIPE_CONTROL_TLB_INVALIDATE;
424 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
425 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
426 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
427 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
428 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
429 flags |= PIPE_CONTROL_QW_WRITE;
430 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
432 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
433 ret = gen8_emit_pipe_control(req,
434 PIPE_CONTROL_CS_STALL |
435 PIPE_CONTROL_STALL_AT_SCOREBOARD,
441 return gen8_emit_pipe_control(req, flags, scratch_addr);
444 static void ring_write_tail(struct intel_engine_cs *ring,
447 struct drm_i915_private *dev_priv = ring->dev->dev_private;
448 I915_WRITE_TAIL(ring, value);
451 u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
453 struct drm_i915_private *dev_priv = ring->dev->dev_private;
456 if (INTEL_INFO(ring->dev)->gen >= 8)
457 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
458 RING_ACTHD_UDW(ring->mmio_base));
459 else if (INTEL_INFO(ring->dev)->gen >= 4)
460 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
462 acthd = I915_READ(ACTHD);
467 static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
469 struct drm_i915_private *dev_priv = ring->dev->dev_private;
472 addr = dev_priv->status_page_dmah->busaddr;
473 if (INTEL_INFO(ring->dev)->gen >= 4)
474 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
475 I915_WRITE(HWS_PGA, addr);
478 static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
480 struct drm_device *dev = ring->dev;
481 struct drm_i915_private *dev_priv = ring->dev->dev_private;
484 /* The ring status page addresses are no longer next to the rest of
485 * the ring registers as of gen7.
490 mmio = RENDER_HWS_PGA_GEN7;
493 mmio = BLT_HWS_PGA_GEN7;
496 * VCS2 actually doesn't exist on Gen7. Only shut up
497 * gcc switch check warning
501 mmio = BSD_HWS_PGA_GEN7;
504 mmio = VEBOX_HWS_PGA_GEN7;
507 } else if (IS_GEN6(ring->dev)) {
508 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
510 /* XXX: gen8 returns to sanity */
511 mmio = RING_HWS_PGA(ring->mmio_base);
514 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
518 * Flush the TLB for this page
520 * FIXME: These two bits have disappeared on gen8, so a question
521 * arises: do we still need this and if so how should we go about
522 * invalidating the TLB?
524 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
525 u32 reg = RING_INSTPM(ring->mmio_base);
527 /* ring should be idle before issuing a sync flush*/
528 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
531 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
533 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
535 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
540 static bool stop_ring(struct intel_engine_cs *ring)
542 struct drm_i915_private *dev_priv = to_i915(ring->dev);
544 if (!IS_GEN2(ring->dev)) {
545 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
546 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
547 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
548 /* Sometimes we observe that the idle flag is not
549 * set even though the ring is empty. So double
550 * check before giving up.
552 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
557 I915_WRITE_CTL(ring, 0);
558 I915_WRITE_HEAD(ring, 0);
559 ring->write_tail(ring, 0);
561 if (!IS_GEN2(ring->dev)) {
562 (void)I915_READ_CTL(ring);
563 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
566 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
569 static int init_ring_common(struct intel_engine_cs *ring)
571 struct drm_device *dev = ring->dev;
572 struct drm_i915_private *dev_priv = dev->dev_private;
573 struct intel_ringbuffer *ringbuf = ring->buffer;
574 struct drm_i915_gem_object *obj = ringbuf->obj;
577 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
579 if (!stop_ring(ring)) {
580 /* G45 ring initialization often fails to reset head to zero */
581 DRM_DEBUG_KMS("%s head not reset to zero "
582 "ctl %08x head %08x tail %08x start %08x\n",
585 I915_READ_HEAD(ring),
586 I915_READ_TAIL(ring),
587 I915_READ_START(ring));
589 if (!stop_ring(ring)) {
590 DRM_ERROR("failed to set %s head to zero "
591 "ctl %08x head %08x tail %08x start %08x\n",
594 I915_READ_HEAD(ring),
595 I915_READ_TAIL(ring),
596 I915_READ_START(ring));
602 if (I915_NEED_GFX_HWS(dev))
603 intel_ring_setup_status_page(ring);
605 ring_setup_phys_status_page(ring);
607 /* Enforce ordering by reading HEAD register back */
608 I915_READ_HEAD(ring);
610 /* Initialize the ring. This must happen _after_ we've cleared the ring
611 * registers with the above sequence (the readback of the HEAD registers
612 * also enforces ordering), otherwise the hw might lose the new ring
613 * register values. */
614 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
616 /* WaClearRingBufHeadRegAtInit:ctg,elk */
617 if (I915_READ_HEAD(ring))
618 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
619 ring->name, I915_READ_HEAD(ring));
620 I915_WRITE_HEAD(ring, 0);
621 (void)I915_READ_HEAD(ring);
624 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
627 /* If the head is still not zero, the ring is dead */
628 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
629 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
630 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
631 DRM_ERROR("%s initialization failed "
632 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
634 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
635 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
636 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
641 ringbuf->last_retired_head = -1;
642 ringbuf->head = I915_READ_HEAD(ring);
643 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
644 intel_ring_update_space(ringbuf);
646 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
649 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
655 intel_fini_pipe_control(struct intel_engine_cs *ring)
657 struct drm_device *dev = ring->dev;
659 if (ring->scratch.obj == NULL)
662 if (INTEL_INFO(dev)->gen >= 5) {
663 kunmap(sg_page(ring->scratch.obj->pages->sgl));
664 i915_gem_object_ggtt_unpin(ring->scratch.obj);
667 drm_gem_object_unreference(&ring->scratch.obj->base);
668 ring->scratch.obj = NULL;
672 intel_init_pipe_control(struct intel_engine_cs *ring)
676 WARN_ON(ring->scratch.obj);
678 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
679 if (ring->scratch.obj == NULL) {
680 DRM_ERROR("Failed to allocate seqno page\n");
685 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
689 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
693 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
694 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
695 if (ring->scratch.cpu_page == NULL) {
700 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
701 ring->name, ring->scratch.gtt_offset);
705 i915_gem_object_ggtt_unpin(ring->scratch.obj);
707 drm_gem_object_unreference(&ring->scratch.obj->base);
712 static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
715 struct intel_engine_cs *ring = req->ring;
716 struct drm_device *dev = ring->dev;
717 struct drm_i915_private *dev_priv = dev->dev_private;
718 struct i915_workarounds *w = &dev_priv->workarounds;
720 if (WARN_ON_ONCE(w->count == 0))
723 ring->gpu_caches_dirty = true;
724 ret = intel_ring_flush_all_caches(req);
728 ret = intel_ring_begin(req, (w->count * 2 + 2));
732 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
733 for (i = 0; i < w->count; i++) {
734 intel_ring_emit(ring, w->reg[i].addr);
735 intel_ring_emit(ring, w->reg[i].value);
737 intel_ring_emit(ring, MI_NOOP);
739 intel_ring_advance(ring);
741 ring->gpu_caches_dirty = true;
742 ret = intel_ring_flush_all_caches(req);
746 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
751 static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
755 ret = intel_ring_workarounds_emit(req);
759 ret = i915_gem_render_state_init(req);
761 DRM_ERROR("init render state: %d\n", ret);
766 static int wa_add(struct drm_i915_private *dev_priv,
767 const u32 addr, const u32 mask, const u32 val)
769 const u32 idx = dev_priv->workarounds.count;
771 if (WARN_ON(idx >= I915_MAX_WA_REGS))
774 dev_priv->workarounds.reg[idx].addr = addr;
775 dev_priv->workarounds.reg[idx].value = val;
776 dev_priv->workarounds.reg[idx].mask = mask;
778 dev_priv->workarounds.count++;
783 #define WA_REG(addr, mask, val) do { \
784 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
789 #define WA_SET_BIT_MASKED(addr, mask) \
790 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
792 #define WA_CLR_BIT_MASKED(addr, mask) \
793 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
795 #define WA_SET_FIELD_MASKED(addr, mask, value) \
796 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
798 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
799 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
801 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
803 static int gen8_init_workarounds(struct intel_engine_cs *ring)
805 struct drm_device *dev = ring->dev;
806 struct drm_i915_private *dev_priv = dev->dev_private;
808 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
810 /* WaDisableAsyncFlipPerfMode:bdw,chv */
811 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
813 /* WaDisablePartialInstShootdown:bdw,chv */
814 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
815 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
817 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
818 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
819 * polygons in the same 8x4 pixel/sample area to be processed without
820 * stalling waiting for the earlier ones to write to Hierarchical Z
823 * This optimization is off by default for BDW and CHV; turn it on.
825 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
827 /* Wa4x4STCOptimizationDisable:bdw,chv */
828 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
831 * BSpec recommends 8x4 when MSAA is used,
832 * however in practice 16x4 seems fastest.
834 * Note that PS/WM thread counts depend on the WIZ hashing
835 * disable bit, which we don't touch here, but it's good
836 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
838 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
839 GEN6_WIZ_HASHING_MASK,
840 GEN6_WIZ_HASHING_16x4);
845 static int bdw_init_workarounds(struct intel_engine_cs *ring)
848 struct drm_device *dev = ring->dev;
849 struct drm_i915_private *dev_priv = dev->dev_private;
851 ret = gen8_init_workarounds(ring);
855 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
856 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
858 /* WaDisableDopClockGating:bdw */
859 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
860 DOP_CLOCK_GATING_DISABLE);
862 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
863 GEN8_SAMPLER_POWER_BYPASS_DIS);
865 /* Use Force Non-Coherent whenever executing a 3D context. This is a
866 * workaround for for a possible hang in the unlikely event a TLB
867 * invalidation occurs during a PSD flush.
869 WA_SET_BIT_MASKED(HDC_CHICKEN0,
870 /* WaForceEnableNonCoherent:bdw */
871 HDC_FORCE_NON_COHERENT |
872 /* WaForceContextSaveRestoreNonCoherent:bdw */
873 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
874 /* WaHdcDisableFetchWhenMasked:bdw */
875 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
876 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
877 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
882 static int chv_init_workarounds(struct intel_engine_cs *ring)
885 struct drm_device *dev = ring->dev;
886 struct drm_i915_private *dev_priv = dev->dev_private;
888 ret = gen8_init_workarounds(ring);
892 /* WaDisableThreadStallDopClockGating:chv */
893 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
895 /* Use Force Non-Coherent whenever executing a 3D context. This is a
896 * workaround for a possible hang in the unlikely event a TLB
897 * invalidation occurs during a PSD flush.
899 /* WaForceEnableNonCoherent:chv */
900 /* WaHdcDisableFetchWhenMasked:chv */
901 WA_SET_BIT_MASKED(HDC_CHICKEN0,
902 HDC_FORCE_NON_COHERENT |
903 HDC_DONOT_FETCH_MEM_WHEN_MASKED);
905 /* Improve HiZ throughput on CHV. */
906 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
911 static int gen9_init_workarounds(struct intel_engine_cs *ring)
913 struct drm_device *dev = ring->dev;
914 struct drm_i915_private *dev_priv = dev->dev_private;
917 /* WaDisablePartialInstShootdown:skl,bxt */
918 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
919 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
921 /* Syncing dependencies between camera and graphics:skl,bxt */
922 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
923 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
925 if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 ||
926 INTEL_REVID(dev) == SKL_REVID_B0)) ||
927 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
928 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
929 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
930 GEN9_DG_MIRROR_FIX_ENABLE);
933 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
934 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
935 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
936 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
937 GEN9_RHWO_OPTIMIZATION_DISABLE);
939 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
940 * but we do that in per ctx batchbuffer as there is an issue
941 * with this register not getting restored on ctx restore
945 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) ||
947 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
948 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
949 GEN9_ENABLE_YV12_BUGFIX);
952 /* Wa4x4STCOptimizationDisable:skl,bxt */
953 /* WaDisablePartialResolveInVc:skl,bxt */
954 WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
955 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
957 /* WaCcsTlbPrefetchDisable:skl,bxt */
958 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
959 GEN9_CCS_TLB_PREFETCH_ENABLE);
961 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
962 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) ||
963 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0))
964 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
965 PIXEL_MASK_CAMMING_DISABLE);
967 /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
968 tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
969 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_F0) ||
970 (IS_BROXTON(dev) && INTEL_REVID(dev) >= BXT_REVID_B0))
971 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
972 WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
974 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
975 if (IS_SKYLAKE(dev) ||
976 (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_B0)) {
977 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
978 GEN8_SAMPLER_POWER_BYPASS_DIS);
981 /* WaDisableSTUnitPowerOptimization:skl,bxt */
982 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
987 static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
989 struct drm_device *dev = ring->dev;
990 struct drm_i915_private *dev_priv = dev->dev_private;
991 u8 vals[3] = { 0, 0, 0 };
994 for (i = 0; i < 3; i++) {
998 * Only consider slices where one, and only one, subslice has 7
1001 if (hweight8(dev_priv->info.subslice_7eu[i]) != 1)
1005 * subslice_7eu[i] != 0 (because of the check above) and
1006 * ss_max == 4 (maximum number of subslices possible per slice)
1010 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1014 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1017 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1018 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1019 GEN9_IZ_HASHING_MASK(2) |
1020 GEN9_IZ_HASHING_MASK(1) |
1021 GEN9_IZ_HASHING_MASK(0),
1022 GEN9_IZ_HASHING(2, vals[2]) |
1023 GEN9_IZ_HASHING(1, vals[1]) |
1024 GEN9_IZ_HASHING(0, vals[0]));
1030 static int skl_init_workarounds(struct intel_engine_cs *ring)
1033 struct drm_device *dev = ring->dev;
1034 struct drm_i915_private *dev_priv = dev->dev_private;
1036 ret = gen9_init_workarounds(ring);
1040 /* WaDisablePowerCompilerClockGating:skl */
1041 if (INTEL_REVID(dev) == SKL_REVID_B0)
1042 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1043 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1045 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
1047 *Use Force Non-Coherent whenever executing a 3D context. This
1048 * is a workaround for a possible hang in the unlikely event
1049 * a TLB invalidation occurs during a PSD flush.
1051 /* WaForceEnableNonCoherent:skl */
1052 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1053 HDC_FORCE_NON_COHERENT);
1056 if (INTEL_REVID(dev) == SKL_REVID_C0 ||
1057 INTEL_REVID(dev) == SKL_REVID_D0)
1058 /* WaBarrierPerformanceFixDisable:skl */
1059 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1060 HDC_FENCE_DEST_SLM_DISABLE |
1061 HDC_BARRIER_PERFORMANCE_DISABLE);
1063 /* WaDisableSbeCacheDispatchPortSharing:skl */
1064 if (INTEL_REVID(dev) <= SKL_REVID_F0) {
1066 GEN7_HALF_SLICE_CHICKEN1,
1067 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1070 return skl_tune_iz_hashing(ring);
1073 static int bxt_init_workarounds(struct intel_engine_cs *ring)
1076 struct drm_device *dev = ring->dev;
1077 struct drm_i915_private *dev_priv = dev->dev_private;
1079 ret = gen9_init_workarounds(ring);
1083 /* WaDisableThreadStallDopClockGating:bxt */
1084 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1085 STALL_DOP_GATING_DISABLE);
1087 /* WaDisableSbeCacheDispatchPortSharing:bxt */
1088 if (INTEL_REVID(dev) <= BXT_REVID_B0) {
1090 GEN7_HALF_SLICE_CHICKEN1,
1091 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1097 int init_workarounds_ring(struct intel_engine_cs *ring)
1099 struct drm_device *dev = ring->dev;
1100 struct drm_i915_private *dev_priv = dev->dev_private;
1102 WARN_ON(ring->id != RCS);
1104 dev_priv->workarounds.count = 0;
1106 if (IS_BROADWELL(dev))
1107 return bdw_init_workarounds(ring);
1109 if (IS_CHERRYVIEW(dev))
1110 return chv_init_workarounds(ring);
1112 if (IS_SKYLAKE(dev))
1113 return skl_init_workarounds(ring);
1115 if (IS_BROXTON(dev))
1116 return bxt_init_workarounds(ring);
1121 static int init_render_ring(struct intel_engine_cs *ring)
1123 struct drm_device *dev = ring->dev;
1124 struct drm_i915_private *dev_priv = dev->dev_private;
1125 int ret = init_ring_common(ring);
1129 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1130 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
1131 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1133 /* We need to disable the AsyncFlip performance optimisations in order
1134 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1135 * programmed to '1' on all products.
1137 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1139 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1140 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1142 /* Required for the hardware to program scanline values for waiting */
1143 /* WaEnableFlushTlbInvalidationMode:snb */
1144 if (INTEL_INFO(dev)->gen == 6)
1145 I915_WRITE(GFX_MODE,
1146 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1148 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1150 I915_WRITE(GFX_MODE_GEN7,
1151 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1152 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1155 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1156 * "If this bit is set, STCunit will have LRA as replacement
1157 * policy. [...] This bit must be reset. LRA replacement
1158 * policy is not supported."
1160 I915_WRITE(CACHE_MODE_0,
1161 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1164 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1165 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1167 if (HAS_L3_DPF(dev))
1168 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1170 return init_workarounds_ring(ring);
1173 static void render_ring_cleanup(struct intel_engine_cs *ring)
1175 struct drm_device *dev = ring->dev;
1176 struct drm_i915_private *dev_priv = dev->dev_private;
1178 if (dev_priv->semaphore_obj) {
1179 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1180 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1181 dev_priv->semaphore_obj = NULL;
1184 intel_fini_pipe_control(ring);
1187 static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
1188 unsigned int num_dwords)
1190 #define MBOX_UPDATE_DWORDS 8
1191 struct intel_engine_cs *signaller = signaller_req->ring;
1192 struct drm_device *dev = signaller->dev;
1193 struct drm_i915_private *dev_priv = dev->dev_private;
1194 struct intel_engine_cs *waiter;
1195 int i, ret, num_rings;
1197 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1198 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1199 #undef MBOX_UPDATE_DWORDS
1201 ret = intel_ring_begin(signaller_req, num_dwords);
1205 for_each_ring(waiter, dev_priv, i) {
1207 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1208 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1211 seqno = i915_gem_request_get_seqno(signaller_req);
1212 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1213 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1214 PIPE_CONTROL_QW_WRITE |
1215 PIPE_CONTROL_FLUSH_ENABLE);
1216 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1217 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1218 intel_ring_emit(signaller, seqno);
1219 intel_ring_emit(signaller, 0);
1220 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1221 MI_SEMAPHORE_TARGET(waiter->id));
1222 intel_ring_emit(signaller, 0);
1228 static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
1229 unsigned int num_dwords)
1231 #define MBOX_UPDATE_DWORDS 6
1232 struct intel_engine_cs *signaller = signaller_req->ring;
1233 struct drm_device *dev = signaller->dev;
1234 struct drm_i915_private *dev_priv = dev->dev_private;
1235 struct intel_engine_cs *waiter;
1236 int i, ret, num_rings;
1238 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1239 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1240 #undef MBOX_UPDATE_DWORDS
1242 ret = intel_ring_begin(signaller_req, num_dwords);
1246 for_each_ring(waiter, dev_priv, i) {
1248 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1249 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1252 seqno = i915_gem_request_get_seqno(signaller_req);
1253 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1254 MI_FLUSH_DW_OP_STOREDW);
1255 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1256 MI_FLUSH_DW_USE_GTT);
1257 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1258 intel_ring_emit(signaller, seqno);
1259 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1260 MI_SEMAPHORE_TARGET(waiter->id));
1261 intel_ring_emit(signaller, 0);
1267 static int gen6_signal(struct drm_i915_gem_request *signaller_req,
1268 unsigned int num_dwords)
1270 struct intel_engine_cs *signaller = signaller_req->ring;
1271 struct drm_device *dev = signaller->dev;
1272 struct drm_i915_private *dev_priv = dev->dev_private;
1273 struct intel_engine_cs *useless;
1274 int i, ret, num_rings;
1276 #define MBOX_UPDATE_DWORDS 3
1277 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1278 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1279 #undef MBOX_UPDATE_DWORDS
1281 ret = intel_ring_begin(signaller_req, num_dwords);
1285 for_each_ring(useless, dev_priv, i) {
1286 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1287 if (mbox_reg != GEN6_NOSYNC) {
1288 u32 seqno = i915_gem_request_get_seqno(signaller_req);
1289 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1290 intel_ring_emit(signaller, mbox_reg);
1291 intel_ring_emit(signaller, seqno);
1295 /* If num_dwords was rounded, make sure the tail pointer is correct */
1296 if (num_rings % 2 == 0)
1297 intel_ring_emit(signaller, MI_NOOP);
1303 * gen6_add_request - Update the semaphore mailbox registers
1305 * @request - request to write to the ring
1307 * Update the mailbox registers in the *other* rings with the current seqno.
1308 * This acts like a signal in the canonical semaphore.
1311 gen6_add_request(struct drm_i915_gem_request *req)
1313 struct intel_engine_cs *ring = req->ring;
1316 if (ring->semaphore.signal)
1317 ret = ring->semaphore.signal(req, 4);
1319 ret = intel_ring_begin(req, 4);
1324 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1325 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1326 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1327 intel_ring_emit(ring, MI_USER_INTERRUPT);
1328 __intel_ring_advance(ring);
1333 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1336 struct drm_i915_private *dev_priv = dev->dev_private;
1337 return dev_priv->last_seqno < seqno;
1341 * intel_ring_sync - sync the waiter to the signaller on seqno
1343 * @waiter - ring that is waiting
1344 * @signaller - ring which has, or will signal
1345 * @seqno - seqno which the waiter will block on
1349 gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
1350 struct intel_engine_cs *signaller,
1353 struct intel_engine_cs *waiter = waiter_req->ring;
1354 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1357 ret = intel_ring_begin(waiter_req, 4);
1361 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1362 MI_SEMAPHORE_GLOBAL_GTT |
1364 MI_SEMAPHORE_SAD_GTE_SDD);
1365 intel_ring_emit(waiter, seqno);
1366 intel_ring_emit(waiter,
1367 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1368 intel_ring_emit(waiter,
1369 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1370 intel_ring_advance(waiter);
1375 gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
1376 struct intel_engine_cs *signaller,
1379 struct intel_engine_cs *waiter = waiter_req->ring;
1380 u32 dw1 = MI_SEMAPHORE_MBOX |
1381 MI_SEMAPHORE_COMPARE |
1382 MI_SEMAPHORE_REGISTER;
1383 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1386 /* Throughout all of the GEM code, seqno passed implies our current
1387 * seqno is >= the last seqno executed. However for hardware the
1388 * comparison is strictly greater than.
1392 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1394 ret = intel_ring_begin(waiter_req, 4);
1398 /* If seqno wrap happened, omit the wait with no-ops */
1399 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1400 intel_ring_emit(waiter, dw1 | wait_mbox);
1401 intel_ring_emit(waiter, seqno);
1402 intel_ring_emit(waiter, 0);
1403 intel_ring_emit(waiter, MI_NOOP);
1405 intel_ring_emit(waiter, MI_NOOP);
1406 intel_ring_emit(waiter, MI_NOOP);
1407 intel_ring_emit(waiter, MI_NOOP);
1408 intel_ring_emit(waiter, MI_NOOP);
1410 intel_ring_advance(waiter);
1415 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
1417 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1418 PIPE_CONTROL_DEPTH_STALL); \
1419 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1420 intel_ring_emit(ring__, 0); \
1421 intel_ring_emit(ring__, 0); \
1425 pc_render_add_request(struct drm_i915_gem_request *req)
1427 struct intel_engine_cs *ring = req->ring;
1428 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1431 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1432 * incoherent with writes to memory, i.e. completely fubar,
1433 * so we need to use PIPE_NOTIFY instead.
1435 * However, we also need to workaround the qword write
1436 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1437 * memory before requesting an interrupt.
1439 ret = intel_ring_begin(req, 32);
1443 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1444 PIPE_CONTROL_WRITE_FLUSH |
1445 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1446 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1447 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1448 intel_ring_emit(ring, 0);
1449 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1450 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1451 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1452 scratch_addr += 2 * CACHELINE_BYTES;
1453 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1454 scratch_addr += 2 * CACHELINE_BYTES;
1455 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1456 scratch_addr += 2 * CACHELINE_BYTES;
1457 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1458 scratch_addr += 2 * CACHELINE_BYTES;
1459 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1461 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1462 PIPE_CONTROL_WRITE_FLUSH |
1463 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1464 PIPE_CONTROL_NOTIFY);
1465 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1466 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1467 intel_ring_emit(ring, 0);
1468 __intel_ring_advance(ring);
1474 gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1476 /* Workaround to force correct ordering between irq and seqno writes on
1477 * ivb (and maybe also on snb) by reading from a CS register (like
1478 * ACTHD) before reading the status page. */
1479 if (!lazy_coherency) {
1480 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1481 POSTING_READ(RING_ACTHD(ring->mmio_base));
1484 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1488 ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1490 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1494 ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1496 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1500 pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1502 return ring->scratch.cpu_page[0];
1506 pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1508 ring->scratch.cpu_page[0] = seqno;
1512 gen5_ring_get_irq(struct intel_engine_cs *ring)
1514 struct drm_device *dev = ring->dev;
1515 struct drm_i915_private *dev_priv = dev->dev_private;
1516 unsigned long flags;
1518 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1521 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1522 if (ring->irq_refcount++ == 0)
1523 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1524 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1530 gen5_ring_put_irq(struct intel_engine_cs *ring)
1532 struct drm_device *dev = ring->dev;
1533 struct drm_i915_private *dev_priv = dev->dev_private;
1534 unsigned long flags;
1536 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1537 if (--ring->irq_refcount == 0)
1538 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1539 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1543 i9xx_ring_get_irq(struct intel_engine_cs *ring)
1545 struct drm_device *dev = ring->dev;
1546 struct drm_i915_private *dev_priv = dev->dev_private;
1547 unsigned long flags;
1549 if (!intel_irqs_enabled(dev_priv))
1552 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1553 if (ring->irq_refcount++ == 0) {
1554 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1555 I915_WRITE(IMR, dev_priv->irq_mask);
1558 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1564 i9xx_ring_put_irq(struct intel_engine_cs *ring)
1566 struct drm_device *dev = ring->dev;
1567 struct drm_i915_private *dev_priv = dev->dev_private;
1568 unsigned long flags;
1570 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1571 if (--ring->irq_refcount == 0) {
1572 dev_priv->irq_mask |= ring->irq_enable_mask;
1573 I915_WRITE(IMR, dev_priv->irq_mask);
1576 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1580 i8xx_ring_get_irq(struct intel_engine_cs *ring)
1582 struct drm_device *dev = ring->dev;
1583 struct drm_i915_private *dev_priv = dev->dev_private;
1584 unsigned long flags;
1586 if (!intel_irqs_enabled(dev_priv))
1589 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1590 if (ring->irq_refcount++ == 0) {
1591 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1592 I915_WRITE16(IMR, dev_priv->irq_mask);
1593 POSTING_READ16(IMR);
1595 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1601 i8xx_ring_put_irq(struct intel_engine_cs *ring)
1603 struct drm_device *dev = ring->dev;
1604 struct drm_i915_private *dev_priv = dev->dev_private;
1605 unsigned long flags;
1607 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1608 if (--ring->irq_refcount == 0) {
1609 dev_priv->irq_mask |= ring->irq_enable_mask;
1610 I915_WRITE16(IMR, dev_priv->irq_mask);
1611 POSTING_READ16(IMR);
1613 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1617 bsd_ring_flush(struct drm_i915_gem_request *req,
1618 u32 invalidate_domains,
1621 struct intel_engine_cs *ring = req->ring;
1624 ret = intel_ring_begin(req, 2);
1628 intel_ring_emit(ring, MI_FLUSH);
1629 intel_ring_emit(ring, MI_NOOP);
1630 intel_ring_advance(ring);
1635 i9xx_add_request(struct drm_i915_gem_request *req)
1637 struct intel_engine_cs *ring = req->ring;
1640 ret = intel_ring_begin(req, 4);
1644 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1645 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1646 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1647 intel_ring_emit(ring, MI_USER_INTERRUPT);
1648 __intel_ring_advance(ring);
1654 gen6_ring_get_irq(struct intel_engine_cs *ring)
1656 struct drm_device *dev = ring->dev;
1657 struct drm_i915_private *dev_priv = dev->dev_private;
1658 unsigned long flags;
1660 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1663 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1664 if (ring->irq_refcount++ == 0) {
1665 if (HAS_L3_DPF(dev) && ring->id == RCS)
1666 I915_WRITE_IMR(ring,
1667 ~(ring->irq_enable_mask |
1668 GT_PARITY_ERROR(dev)));
1670 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1671 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1673 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1679 gen6_ring_put_irq(struct intel_engine_cs *ring)
1681 struct drm_device *dev = ring->dev;
1682 struct drm_i915_private *dev_priv = dev->dev_private;
1683 unsigned long flags;
1685 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1686 if (--ring->irq_refcount == 0) {
1687 if (HAS_L3_DPF(dev) && ring->id == RCS)
1688 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1690 I915_WRITE_IMR(ring, ~0);
1691 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1693 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1697 hsw_vebox_get_irq(struct intel_engine_cs *ring)
1699 struct drm_device *dev = ring->dev;
1700 struct drm_i915_private *dev_priv = dev->dev_private;
1701 unsigned long flags;
1703 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1706 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1707 if (ring->irq_refcount++ == 0) {
1708 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1709 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1711 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1717 hsw_vebox_put_irq(struct intel_engine_cs *ring)
1719 struct drm_device *dev = ring->dev;
1720 struct drm_i915_private *dev_priv = dev->dev_private;
1721 unsigned long flags;
1723 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1724 if (--ring->irq_refcount == 0) {
1725 I915_WRITE_IMR(ring, ~0);
1726 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1728 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1732 gen8_ring_get_irq(struct intel_engine_cs *ring)
1734 struct drm_device *dev = ring->dev;
1735 struct drm_i915_private *dev_priv = dev->dev_private;
1736 unsigned long flags;
1738 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1741 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1742 if (ring->irq_refcount++ == 0) {
1743 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1744 I915_WRITE_IMR(ring,
1745 ~(ring->irq_enable_mask |
1746 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1748 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1750 POSTING_READ(RING_IMR(ring->mmio_base));
1752 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1758 gen8_ring_put_irq(struct intel_engine_cs *ring)
1760 struct drm_device *dev = ring->dev;
1761 struct drm_i915_private *dev_priv = dev->dev_private;
1762 unsigned long flags;
1764 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1765 if (--ring->irq_refcount == 0) {
1766 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1767 I915_WRITE_IMR(ring,
1768 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1770 I915_WRITE_IMR(ring, ~0);
1772 POSTING_READ(RING_IMR(ring->mmio_base));
1774 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1778 i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
1779 u64 offset, u32 length,
1780 unsigned dispatch_flags)
1782 struct intel_engine_cs *ring = req->ring;
1785 ret = intel_ring_begin(req, 2);
1789 intel_ring_emit(ring,
1790 MI_BATCH_BUFFER_START |
1792 (dispatch_flags & I915_DISPATCH_SECURE ?
1793 0 : MI_BATCH_NON_SECURE_I965));
1794 intel_ring_emit(ring, offset);
1795 intel_ring_advance(ring);
1800 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1801 #define I830_BATCH_LIMIT (256*1024)
1802 #define I830_TLB_ENTRIES (2)
1803 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1805 i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
1806 u64 offset, u32 len,
1807 unsigned dispatch_flags)
1809 struct intel_engine_cs *ring = req->ring;
1810 u32 cs_offset = ring->scratch.gtt_offset;
1813 ret = intel_ring_begin(req, 6);
1817 /* Evict the invalid PTE TLBs */
1818 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1819 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1820 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1821 intel_ring_emit(ring, cs_offset);
1822 intel_ring_emit(ring, 0xdeadbeef);
1823 intel_ring_emit(ring, MI_NOOP);
1824 intel_ring_advance(ring);
1826 if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1827 if (len > I830_BATCH_LIMIT)
1830 ret = intel_ring_begin(req, 6 + 2);
1834 /* Blit the batch (which has now all relocs applied) to the
1835 * stable batch scratch bo area (so that the CS never
1836 * stumbles over its tlb invalidation bug) ...
1838 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1839 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1840 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1841 intel_ring_emit(ring, cs_offset);
1842 intel_ring_emit(ring, 4096);
1843 intel_ring_emit(ring, offset);
1845 intel_ring_emit(ring, MI_FLUSH);
1846 intel_ring_emit(ring, MI_NOOP);
1847 intel_ring_advance(ring);
1849 /* ... and execute it. */
1853 ret = intel_ring_begin(req, 4);
1857 intel_ring_emit(ring, MI_BATCH_BUFFER);
1858 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1859 0 : MI_BATCH_NON_SECURE));
1860 intel_ring_emit(ring, offset + len - 8);
1861 intel_ring_emit(ring, MI_NOOP);
1862 intel_ring_advance(ring);
1868 i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
1869 u64 offset, u32 len,
1870 unsigned dispatch_flags)
1872 struct intel_engine_cs *ring = req->ring;
1875 ret = intel_ring_begin(req, 2);
1879 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1880 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1881 0 : MI_BATCH_NON_SECURE));
1882 intel_ring_advance(ring);
1887 static void cleanup_status_page(struct intel_engine_cs *ring)
1889 struct drm_i915_gem_object *obj;
1891 obj = ring->status_page.obj;
1895 kunmap(sg_page(obj->pages->sgl));
1896 i915_gem_object_ggtt_unpin(obj);
1897 drm_gem_object_unreference(&obj->base);
1898 ring->status_page.obj = NULL;
1901 static int init_status_page(struct intel_engine_cs *ring)
1903 struct drm_i915_gem_object *obj;
1905 if ((obj = ring->status_page.obj) == NULL) {
1909 obj = i915_gem_alloc_object(ring->dev, 4096);
1911 DRM_ERROR("Failed to allocate status page\n");
1915 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1920 if (!HAS_LLC(ring->dev))
1921 /* On g33, we cannot place HWS above 256MiB, so
1922 * restrict its pinning to the low mappable arena.
1923 * Though this restriction is not documented for
1924 * gen4, gen5, or byt, they also behave similarly
1925 * and hang if the HWS is placed at the top of the
1926 * GTT. To generalise, it appears that all !llc
1927 * platforms have issues with us placing the HWS
1928 * above the mappable region (even though we never
1931 flags |= PIN_MAPPABLE;
1932 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
1935 drm_gem_object_unreference(&obj->base);
1939 ring->status_page.obj = obj;
1942 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1943 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1944 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1946 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1947 ring->name, ring->status_page.gfx_addr);
1952 static int init_phys_status_page(struct intel_engine_cs *ring)
1954 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1956 if (!dev_priv->status_page_dmah) {
1957 dev_priv->status_page_dmah =
1958 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1959 if (!dev_priv->status_page_dmah)
1963 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1964 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1969 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1971 iounmap(ringbuf->virtual_start);
1972 ringbuf->virtual_start = NULL;
1973 i915_gem_object_ggtt_unpin(ringbuf->obj);
1976 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
1977 struct intel_ringbuffer *ringbuf)
1979 struct drm_i915_private *dev_priv = to_i915(dev);
1980 struct drm_i915_gem_object *obj = ringbuf->obj;
1983 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1987 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1989 i915_gem_object_ggtt_unpin(obj);
1993 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
1994 i915_gem_obj_ggtt_offset(obj), ringbuf->size);
1995 if (ringbuf->virtual_start == NULL) {
1996 i915_gem_object_ggtt_unpin(obj);
2003 static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2005 drm_gem_object_unreference(&ringbuf->obj->base);
2006 ringbuf->obj = NULL;
2009 static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
2010 struct intel_ringbuffer *ringbuf)
2012 struct drm_i915_gem_object *obj;
2016 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
2018 obj = i915_gem_alloc_object(dev, ringbuf->size);
2022 /* mark ring buffers as read-only from GPU side by default */
2030 struct intel_ringbuffer *
2031 intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
2033 struct intel_ringbuffer *ring;
2036 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
2038 return ERR_PTR(-ENOMEM);
2040 ring->ring = engine;
2043 /* Workaround an erratum on the i830 which causes a hang if
2044 * the TAIL pointer points to within the last 2 cachelines
2047 ring->effective_size = size;
2048 if (IS_I830(engine->dev) || IS_845G(engine->dev))
2049 ring->effective_size -= 2 * CACHELINE_BYTES;
2051 ring->last_retired_head = -1;
2052 intel_ring_update_space(ring);
2054 ret = intel_alloc_ringbuffer_obj(engine->dev, ring);
2056 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
2059 return ERR_PTR(ret);
2066 intel_ringbuffer_free(struct intel_ringbuffer *ring)
2068 intel_destroy_ringbuffer_obj(ring);
2072 static int intel_init_ring_buffer(struct drm_device *dev,
2073 struct intel_engine_cs *ring)
2075 struct intel_ringbuffer *ringbuf;
2078 WARN_ON(ring->buffer);
2081 INIT_LIST_HEAD(&ring->active_list);
2082 INIT_LIST_HEAD(&ring->request_list);
2083 INIT_LIST_HEAD(&ring->execlist_queue);
2084 i915_gem_batch_pool_init(dev, &ring->batch_pool);
2085 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
2087 init_waitqueue_head(&ring->irq_queue);
2089 ringbuf = intel_engine_create_ringbuffer(ring, 32 * PAGE_SIZE);
2090 if (IS_ERR(ringbuf))
2091 return PTR_ERR(ringbuf);
2092 ring->buffer = ringbuf;
2094 if (I915_NEED_GFX_HWS(dev)) {
2095 ret = init_status_page(ring);
2099 BUG_ON(ring->id != RCS);
2100 ret = init_phys_status_page(ring);
2105 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2107 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2109 intel_destroy_ringbuffer_obj(ringbuf);
2113 ret = i915_cmd_parser_init_ring(ring);
2120 intel_ringbuffer_free(ringbuf);
2121 ring->buffer = NULL;
2125 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
2127 struct drm_i915_private *dev_priv;
2129 if (!intel_ring_initialized(ring))
2132 dev_priv = to_i915(ring->dev);
2134 intel_stop_ring_buffer(ring);
2135 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
2137 intel_unpin_ringbuffer_obj(ring->buffer);
2138 intel_ringbuffer_free(ring->buffer);
2139 ring->buffer = NULL;
2142 ring->cleanup(ring);
2144 cleanup_status_page(ring);
2146 i915_cmd_parser_fini_ring(ring);
2147 i915_gem_batch_pool_fini(&ring->batch_pool);
2150 static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
2152 struct intel_ringbuffer *ringbuf = ring->buffer;
2153 struct drm_i915_gem_request *request;
2157 if (intel_ring_space(ringbuf) >= n)
2160 /* The whole point of reserving space is to not wait! */
2161 WARN_ON(ringbuf->reserved_in_use);
2163 list_for_each_entry(request, &ring->request_list, list) {
2164 space = __intel_ring_space(request->postfix, ringbuf->tail,
2170 if (WARN_ON(&request->list == &ring->request_list))
2173 ret = i915_wait_request(request);
2177 ringbuf->space = space;
2181 static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)
2183 uint32_t __iomem *virt;
2184 int rem = ringbuf->size - ringbuf->tail;
2186 virt = ringbuf->virtual_start + ringbuf->tail;
2189 iowrite32(MI_NOOP, virt++);
2192 intel_ring_update_space(ringbuf);
2195 int intel_ring_idle(struct intel_engine_cs *ring)
2197 struct drm_i915_gem_request *req;
2199 /* Wait upon the last request to be completed */
2200 if (list_empty(&ring->request_list))
2203 req = list_entry(ring->request_list.prev,
2204 struct drm_i915_gem_request,
2207 /* Make sure we do not trigger any retires */
2208 return __i915_wait_request(req,
2209 atomic_read(&to_i915(ring->dev)->gpu_error.reset_counter),
2210 to_i915(ring->dev)->mm.interruptible,
2214 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
2216 request->ringbuf = request->ring->buffer;
2220 int intel_ring_reserve_space(struct drm_i915_gem_request *request)
2223 * The first call merely notes the reserve request and is common for
2224 * all back ends. The subsequent localised _begin() call actually
2225 * ensures that the reservation is available. Without the begin, if
2226 * the request creator immediately submitted the request without
2227 * adding any commands to it then there might not actually be
2228 * sufficient room for the submission commands.
2230 intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
2232 return intel_ring_begin(request, 0);
2235 void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size)
2237 WARN_ON(ringbuf->reserved_size);
2238 WARN_ON(ringbuf->reserved_in_use);
2240 ringbuf->reserved_size = size;
2243 void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf)
2245 WARN_ON(ringbuf->reserved_in_use);
2247 ringbuf->reserved_size = 0;
2248 ringbuf->reserved_in_use = false;
2251 void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf)
2253 WARN_ON(ringbuf->reserved_in_use);
2255 ringbuf->reserved_in_use = true;
2256 ringbuf->reserved_tail = ringbuf->tail;
2259 void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
2261 WARN_ON(!ringbuf->reserved_in_use);
2262 if (ringbuf->tail > ringbuf->reserved_tail) {
2263 WARN(ringbuf->tail > ringbuf->reserved_tail + ringbuf->reserved_size,
2264 "request reserved size too small: %d vs %d!\n",
2265 ringbuf->tail - ringbuf->reserved_tail, ringbuf->reserved_size);
2268 * The ring was wrapped while the reserved space was in use.
2269 * That means that some unknown amount of the ring tail was
2270 * no-op filled and skipped. Thus simply adding the ring size
2271 * to the tail and doing the above space check will not work.
2272 * Rather than attempt to track how much tail was skipped,
2273 * it is much simpler to say that also skipping the sanity
2274 * check every once in a while is not a big issue.
2278 ringbuf->reserved_size = 0;
2279 ringbuf->reserved_in_use = false;
2282 static int __intel_ring_prepare(struct intel_engine_cs *ring, int bytes)
2284 struct intel_ringbuffer *ringbuf = ring->buffer;
2285 int remain_usable = ringbuf->effective_size - ringbuf->tail;
2286 int remain_actual = ringbuf->size - ringbuf->tail;
2287 int ret, total_bytes, wait_bytes = 0;
2288 bool need_wrap = false;
2290 if (ringbuf->reserved_in_use)
2291 total_bytes = bytes;
2293 total_bytes = bytes + ringbuf->reserved_size;
2295 if (unlikely(bytes > remain_usable)) {
2297 * Not enough space for the basic request. So need to flush
2298 * out the remainder and then wait for base + reserved.
2300 wait_bytes = remain_actual + total_bytes;
2303 if (unlikely(total_bytes > remain_usable)) {
2305 * The base request will fit but the reserved space
2306 * falls off the end. So only need to to wait for the
2307 * reserved size after flushing out the remainder.
2309 wait_bytes = remain_actual + ringbuf->reserved_size;
2311 } else if (total_bytes > ringbuf->space) {
2312 /* No wrapping required, just waiting. */
2313 wait_bytes = total_bytes;
2318 ret = ring_wait_for_space(ring, wait_bytes);
2323 __wrap_ring_buffer(ringbuf);
2329 int intel_ring_begin(struct drm_i915_gem_request *req,
2332 struct intel_engine_cs *ring;
2333 struct drm_i915_private *dev_priv;
2336 WARN_ON(req == NULL);
2338 dev_priv = ring->dev->dev_private;
2340 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2341 dev_priv->mm.interruptible);
2345 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2349 ring->buffer->space -= num_dwords * sizeof(uint32_t);
2353 /* Align the ring tail to a cacheline boundary */
2354 int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
2356 struct intel_engine_cs *ring = req->ring;
2357 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2360 if (num_dwords == 0)
2363 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2364 ret = intel_ring_begin(req, num_dwords);
2368 while (num_dwords--)
2369 intel_ring_emit(ring, MI_NOOP);
2371 intel_ring_advance(ring);
2376 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
2378 struct drm_device *dev = ring->dev;
2379 struct drm_i915_private *dev_priv = dev->dev_private;
2381 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
2382 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2383 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
2385 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
2388 ring->set_seqno(ring, seqno);
2389 ring->hangcheck.seqno = seqno;
2392 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
2395 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2397 /* Every tail move must follow the sequence below */
2399 /* Disable notification that the ring is IDLE. The GT
2400 * will then assume that it is busy and bring it out of rc6.
2402 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2403 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2405 /* Clear the context id. Here be magic! */
2406 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2408 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2409 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2410 GEN6_BSD_SLEEP_INDICATOR) == 0,
2412 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2414 /* Now that the ring is fully powered up, update the tail */
2415 I915_WRITE_TAIL(ring, value);
2416 POSTING_READ(RING_TAIL(ring->mmio_base));
2418 /* Let the ring send IDLE messages to the GT again,
2419 * and so let it sleep to conserve power when idle.
2421 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2422 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2425 static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
2426 u32 invalidate, u32 flush)
2428 struct intel_engine_cs *ring = req->ring;
2432 ret = intel_ring_begin(req, 4);
2437 if (INTEL_INFO(ring->dev)->gen >= 8)
2440 /* We always require a command barrier so that subsequent
2441 * commands, such as breadcrumb interrupts, are strictly ordered
2442 * wrt the contents of the write cache being flushed to memory
2443 * (and thus being coherent from the CPU).
2445 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2448 * Bspec vol 1c.5 - video engine command streamer:
2449 * "If ENABLED, all TLBs will be invalidated once the flush
2450 * operation is complete. This bit is only valid when the
2451 * Post-Sync Operation field is a value of 1h or 3h."
2453 if (invalidate & I915_GEM_GPU_DOMAINS)
2454 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2456 intel_ring_emit(ring, cmd);
2457 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2458 if (INTEL_INFO(ring->dev)->gen >= 8) {
2459 intel_ring_emit(ring, 0); /* upper addr */
2460 intel_ring_emit(ring, 0); /* value */
2462 intel_ring_emit(ring, 0);
2463 intel_ring_emit(ring, MI_NOOP);
2465 intel_ring_advance(ring);
2470 gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2471 u64 offset, u32 len,
2472 unsigned dispatch_flags)
2474 struct intel_engine_cs *ring = req->ring;
2475 bool ppgtt = USES_PPGTT(ring->dev) &&
2476 !(dispatch_flags & I915_DISPATCH_SECURE);
2479 ret = intel_ring_begin(req, 4);
2483 /* FIXME(BDW): Address space and security selectors. */
2484 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
2485 (dispatch_flags & I915_DISPATCH_RS ?
2486 MI_BATCH_RESOURCE_STREAMER : 0));
2487 intel_ring_emit(ring, lower_32_bits(offset));
2488 intel_ring_emit(ring, upper_32_bits(offset));
2489 intel_ring_emit(ring, MI_NOOP);
2490 intel_ring_advance(ring);
2496 hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2497 u64 offset, u32 len,
2498 unsigned dispatch_flags)
2500 struct intel_engine_cs *ring = req->ring;
2503 ret = intel_ring_begin(req, 2);
2507 intel_ring_emit(ring,
2508 MI_BATCH_BUFFER_START |
2509 (dispatch_flags & I915_DISPATCH_SECURE ?
2510 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2511 (dispatch_flags & I915_DISPATCH_RS ?
2512 MI_BATCH_RESOURCE_STREAMER : 0));
2513 /* bit0-7 is the length on GEN6+ */
2514 intel_ring_emit(ring, offset);
2515 intel_ring_advance(ring);
2521 gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2522 u64 offset, u32 len,
2523 unsigned dispatch_flags)
2525 struct intel_engine_cs *ring = req->ring;
2528 ret = intel_ring_begin(req, 2);
2532 intel_ring_emit(ring,
2533 MI_BATCH_BUFFER_START |
2534 (dispatch_flags & I915_DISPATCH_SECURE ?
2535 0 : MI_BATCH_NON_SECURE_I965));
2536 /* bit0-7 is the length on GEN6+ */
2537 intel_ring_emit(ring, offset);
2538 intel_ring_advance(ring);
2543 /* Blitter support (SandyBridge+) */
2545 static int gen6_ring_flush(struct drm_i915_gem_request *req,
2546 u32 invalidate, u32 flush)
2548 struct intel_engine_cs *ring = req->ring;
2549 struct drm_device *dev = ring->dev;
2553 ret = intel_ring_begin(req, 4);
2558 if (INTEL_INFO(dev)->gen >= 8)
2561 /* We always require a command barrier so that subsequent
2562 * commands, such as breadcrumb interrupts, are strictly ordered
2563 * wrt the contents of the write cache being flushed to memory
2564 * (and thus being coherent from the CPU).
2566 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2569 * Bspec vol 1c.3 - blitter engine command streamer:
2570 * "If ENABLED, all TLBs will be invalidated once the flush
2571 * operation is complete. This bit is only valid when the
2572 * Post-Sync Operation field is a value of 1h or 3h."
2574 if (invalidate & I915_GEM_DOMAIN_RENDER)
2575 cmd |= MI_INVALIDATE_TLB;
2576 intel_ring_emit(ring, cmd);
2577 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2578 if (INTEL_INFO(dev)->gen >= 8) {
2579 intel_ring_emit(ring, 0); /* upper addr */
2580 intel_ring_emit(ring, 0); /* value */
2582 intel_ring_emit(ring, 0);
2583 intel_ring_emit(ring, MI_NOOP);
2585 intel_ring_advance(ring);
2590 int intel_init_render_ring_buffer(struct drm_device *dev)
2592 struct drm_i915_private *dev_priv = dev->dev_private;
2593 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2594 struct drm_i915_gem_object *obj;
2597 ring->name = "render ring";
2599 ring->mmio_base = RENDER_RING_BASE;
2601 if (INTEL_INFO(dev)->gen >= 8) {
2602 if (i915_semaphore_is_enabled(dev)) {
2603 obj = i915_gem_alloc_object(dev, 4096);
2605 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2606 i915.semaphores = 0;
2608 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2609 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2611 drm_gem_object_unreference(&obj->base);
2612 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2613 i915.semaphores = 0;
2615 dev_priv->semaphore_obj = obj;
2619 ring->init_context = intel_rcs_ctx_init;
2620 ring->add_request = gen6_add_request;
2621 ring->flush = gen8_render_ring_flush;
2622 ring->irq_get = gen8_ring_get_irq;
2623 ring->irq_put = gen8_ring_put_irq;
2624 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2625 ring->get_seqno = gen6_ring_get_seqno;
2626 ring->set_seqno = ring_set_seqno;
2627 if (i915_semaphore_is_enabled(dev)) {
2628 WARN_ON(!dev_priv->semaphore_obj);
2629 ring->semaphore.sync_to = gen8_ring_sync;
2630 ring->semaphore.signal = gen8_rcs_signal;
2631 GEN8_RING_SEMAPHORE_INIT;
2633 } else if (INTEL_INFO(dev)->gen >= 6) {
2634 ring->add_request = gen6_add_request;
2635 ring->flush = gen7_render_ring_flush;
2636 if (INTEL_INFO(dev)->gen == 6)
2637 ring->flush = gen6_render_ring_flush;
2638 ring->irq_get = gen6_ring_get_irq;
2639 ring->irq_put = gen6_ring_put_irq;
2640 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2641 ring->get_seqno = gen6_ring_get_seqno;
2642 ring->set_seqno = ring_set_seqno;
2643 if (i915_semaphore_is_enabled(dev)) {
2644 ring->semaphore.sync_to = gen6_ring_sync;
2645 ring->semaphore.signal = gen6_signal;
2647 * The current semaphore is only applied on pre-gen8
2648 * platform. And there is no VCS2 ring on the pre-gen8
2649 * platform. So the semaphore between RCS and VCS2 is
2650 * initialized as INVALID. Gen8 will initialize the
2651 * sema between VCS2 and RCS later.
2653 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2654 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2655 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2656 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2657 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2658 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2659 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2660 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2661 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2662 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2664 } else if (IS_GEN5(dev)) {
2665 ring->add_request = pc_render_add_request;
2666 ring->flush = gen4_render_ring_flush;
2667 ring->get_seqno = pc_render_get_seqno;
2668 ring->set_seqno = pc_render_set_seqno;
2669 ring->irq_get = gen5_ring_get_irq;
2670 ring->irq_put = gen5_ring_put_irq;
2671 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2672 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2674 ring->add_request = i9xx_add_request;
2675 if (INTEL_INFO(dev)->gen < 4)
2676 ring->flush = gen2_render_ring_flush;
2678 ring->flush = gen4_render_ring_flush;
2679 ring->get_seqno = ring_get_seqno;
2680 ring->set_seqno = ring_set_seqno;
2682 ring->irq_get = i8xx_ring_get_irq;
2683 ring->irq_put = i8xx_ring_put_irq;
2685 ring->irq_get = i9xx_ring_get_irq;
2686 ring->irq_put = i9xx_ring_put_irq;
2688 ring->irq_enable_mask = I915_USER_INTERRUPT;
2690 ring->write_tail = ring_write_tail;
2692 if (IS_HASWELL(dev))
2693 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2694 else if (IS_GEN8(dev))
2695 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2696 else if (INTEL_INFO(dev)->gen >= 6)
2697 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2698 else if (INTEL_INFO(dev)->gen >= 4)
2699 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2700 else if (IS_I830(dev) || IS_845G(dev))
2701 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2703 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2704 ring->init_hw = init_render_ring;
2705 ring->cleanup = render_ring_cleanup;
2707 /* Workaround batchbuffer to combat CS tlb bug. */
2708 if (HAS_BROKEN_CS_TLB(dev)) {
2709 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2711 DRM_ERROR("Failed to allocate batch bo\n");
2715 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2717 drm_gem_object_unreference(&obj->base);
2718 DRM_ERROR("Failed to ping batch bo\n");
2722 ring->scratch.obj = obj;
2723 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2726 ret = intel_init_ring_buffer(dev, ring);
2730 if (INTEL_INFO(dev)->gen >= 5) {
2731 ret = intel_init_pipe_control(ring);
2739 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2741 struct drm_i915_private *dev_priv = dev->dev_private;
2742 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2744 ring->name = "bsd ring";
2747 ring->write_tail = ring_write_tail;
2748 if (INTEL_INFO(dev)->gen >= 6) {
2749 ring->mmio_base = GEN6_BSD_RING_BASE;
2750 /* gen6 bsd needs a special wa for tail updates */
2752 ring->write_tail = gen6_bsd_ring_write_tail;
2753 ring->flush = gen6_bsd_ring_flush;
2754 ring->add_request = gen6_add_request;
2755 ring->get_seqno = gen6_ring_get_seqno;
2756 ring->set_seqno = ring_set_seqno;
2757 if (INTEL_INFO(dev)->gen >= 8) {
2758 ring->irq_enable_mask =
2759 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2760 ring->irq_get = gen8_ring_get_irq;
2761 ring->irq_put = gen8_ring_put_irq;
2762 ring->dispatch_execbuffer =
2763 gen8_ring_dispatch_execbuffer;
2764 if (i915_semaphore_is_enabled(dev)) {
2765 ring->semaphore.sync_to = gen8_ring_sync;
2766 ring->semaphore.signal = gen8_xcs_signal;
2767 GEN8_RING_SEMAPHORE_INIT;
2770 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2771 ring->irq_get = gen6_ring_get_irq;
2772 ring->irq_put = gen6_ring_put_irq;
2773 ring->dispatch_execbuffer =
2774 gen6_ring_dispatch_execbuffer;
2775 if (i915_semaphore_is_enabled(dev)) {
2776 ring->semaphore.sync_to = gen6_ring_sync;
2777 ring->semaphore.signal = gen6_signal;
2778 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2779 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2780 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2781 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2782 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2783 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2784 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2785 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2786 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2787 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2791 ring->mmio_base = BSD_RING_BASE;
2792 ring->flush = bsd_ring_flush;
2793 ring->add_request = i9xx_add_request;
2794 ring->get_seqno = ring_get_seqno;
2795 ring->set_seqno = ring_set_seqno;
2797 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2798 ring->irq_get = gen5_ring_get_irq;
2799 ring->irq_put = gen5_ring_put_irq;
2801 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2802 ring->irq_get = i9xx_ring_get_irq;
2803 ring->irq_put = i9xx_ring_put_irq;
2805 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2807 ring->init_hw = init_ring_common;
2809 return intel_init_ring_buffer(dev, ring);
2813 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2815 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2817 struct drm_i915_private *dev_priv = dev->dev_private;
2818 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2820 ring->name = "bsd2 ring";
2823 ring->write_tail = ring_write_tail;
2824 ring->mmio_base = GEN8_BSD2_RING_BASE;
2825 ring->flush = gen6_bsd_ring_flush;
2826 ring->add_request = gen6_add_request;
2827 ring->get_seqno = gen6_ring_get_seqno;
2828 ring->set_seqno = ring_set_seqno;
2829 ring->irq_enable_mask =
2830 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2831 ring->irq_get = gen8_ring_get_irq;
2832 ring->irq_put = gen8_ring_put_irq;
2833 ring->dispatch_execbuffer =
2834 gen8_ring_dispatch_execbuffer;
2835 if (i915_semaphore_is_enabled(dev)) {
2836 ring->semaphore.sync_to = gen8_ring_sync;
2837 ring->semaphore.signal = gen8_xcs_signal;
2838 GEN8_RING_SEMAPHORE_INIT;
2840 ring->init_hw = init_ring_common;
2842 return intel_init_ring_buffer(dev, ring);
2845 int intel_init_blt_ring_buffer(struct drm_device *dev)
2847 struct drm_i915_private *dev_priv = dev->dev_private;
2848 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2850 ring->name = "blitter ring";
2853 ring->mmio_base = BLT_RING_BASE;
2854 ring->write_tail = ring_write_tail;
2855 ring->flush = gen6_ring_flush;
2856 ring->add_request = gen6_add_request;
2857 ring->get_seqno = gen6_ring_get_seqno;
2858 ring->set_seqno = ring_set_seqno;
2859 if (INTEL_INFO(dev)->gen >= 8) {
2860 ring->irq_enable_mask =
2861 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2862 ring->irq_get = gen8_ring_get_irq;
2863 ring->irq_put = gen8_ring_put_irq;
2864 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2865 if (i915_semaphore_is_enabled(dev)) {
2866 ring->semaphore.sync_to = gen8_ring_sync;
2867 ring->semaphore.signal = gen8_xcs_signal;
2868 GEN8_RING_SEMAPHORE_INIT;
2871 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2872 ring->irq_get = gen6_ring_get_irq;
2873 ring->irq_put = gen6_ring_put_irq;
2874 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2875 if (i915_semaphore_is_enabled(dev)) {
2876 ring->semaphore.signal = gen6_signal;
2877 ring->semaphore.sync_to = gen6_ring_sync;
2879 * The current semaphore is only applied on pre-gen8
2880 * platform. And there is no VCS2 ring on the pre-gen8
2881 * platform. So the semaphore between BCS and VCS2 is
2882 * initialized as INVALID. Gen8 will initialize the
2883 * sema between BCS and VCS2 later.
2885 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2886 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2887 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2888 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2889 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2890 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2891 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2892 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2893 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2894 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2897 ring->init_hw = init_ring_common;
2899 return intel_init_ring_buffer(dev, ring);
2902 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2904 struct drm_i915_private *dev_priv = dev->dev_private;
2905 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2907 ring->name = "video enhancement ring";
2910 ring->mmio_base = VEBOX_RING_BASE;
2911 ring->write_tail = ring_write_tail;
2912 ring->flush = gen6_ring_flush;
2913 ring->add_request = gen6_add_request;
2914 ring->get_seqno = gen6_ring_get_seqno;
2915 ring->set_seqno = ring_set_seqno;
2917 if (INTEL_INFO(dev)->gen >= 8) {
2918 ring->irq_enable_mask =
2919 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2920 ring->irq_get = gen8_ring_get_irq;
2921 ring->irq_put = gen8_ring_put_irq;
2922 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2923 if (i915_semaphore_is_enabled(dev)) {
2924 ring->semaphore.sync_to = gen8_ring_sync;
2925 ring->semaphore.signal = gen8_xcs_signal;
2926 GEN8_RING_SEMAPHORE_INIT;
2929 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2930 ring->irq_get = hsw_vebox_get_irq;
2931 ring->irq_put = hsw_vebox_put_irq;
2932 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2933 if (i915_semaphore_is_enabled(dev)) {
2934 ring->semaphore.sync_to = gen6_ring_sync;
2935 ring->semaphore.signal = gen6_signal;
2936 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2937 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2938 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2939 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2940 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2941 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2942 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2943 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2944 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2945 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2948 ring->init_hw = init_ring_common;
2950 return intel_init_ring_buffer(dev, ring);
2954 intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
2956 struct intel_engine_cs *ring = req->ring;
2959 if (!ring->gpu_caches_dirty)
2962 ret = ring->flush(req, 0, I915_GEM_GPU_DOMAINS);
2966 trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
2968 ring->gpu_caches_dirty = false;
2973 intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
2975 struct intel_engine_cs *ring = req->ring;
2976 uint32_t flush_domains;
2980 if (ring->gpu_caches_dirty)
2981 flush_domains = I915_GEM_GPU_DOMAINS;
2983 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
2987 trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
2989 ring->gpu_caches_dirty = false;
2994 intel_stop_ring_buffer(struct intel_engine_cs *ring)
2998 if (!intel_ring_initialized(ring))
3001 ret = intel_ring_idle(ring);
3002 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
3003 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",