drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33
  34 /**
  35  * RC6 is a special power stage which allows the GPU to enter an very
  36  * low-voltage mode when idle, using down to 0V while at this stage.  This
  37  * stage is entered automatically when the GPU is idle when RC6 support is
  38  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  39  *
  40  * There are different RC6 modes available in Intel GPU, which differentiate
  41  * among each other with the latency required to enter and leave RC6 and
  42  * voltage consumed by the GPU in different states.
  43  *
  44  * The combination of the following flags define which states GPU is allowed
  45  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  46  * RC6pp is deepest RC6. Their support by hardware varies according to the
  47  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  48  * which brings the most power savings; deeper states save more power, but
  49  * require higher latency to switch to and wake up.
  50  */
  51 #define INTEL_RC6_ENABLE                        (1<<0)
  52 #define INTEL_RC6p_ENABLE                       (1<<1)
  53 #define INTEL_RC6pp_ENABLE                      (1<<2)
  54
  55 static void gen9_init_clock_gating(struct drm_device *dev)
  56 {
  57         struct drm_i915_private *dev_priv = dev->dev_private;
  58
  59         /* WaEnableLbsSlaRetryTimerDecrement:skl */
  60         I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
  61                    GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
  62
  63         /* WaDisableKillLogic:bxt,skl */
  64         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
  65                    ECOCHK_DIS_TLB);
  66 }
  67
  68 static void skl_init_clock_gating(struct drm_device *dev)
  69 {
  70         struct drm_i915_private *dev_priv = dev->dev_private;
  71
  72         gen9_init_clock_gating(dev);
  73
  74         if (INTEL_REVID(dev) <= SKL_REVID_B0) {
  75                 /*
  76                  * WaDisableSDEUnitClockGating:skl
  77                  * WaSetGAPSunitClckGateDisable:skl
  78                  */
  79                 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  80                            GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
  81                            GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
  82
  83                 /* WaDisableVFUnitClockGating:skl */
  84                 I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
  85                            GEN6_VFUNIT_CLOCK_GATE_DISABLE);
  86         }
  87
  88         if (INTEL_REVID(dev) <= SKL_REVID_D0) {
  89                 /* WaDisableHDCInvalidation:skl */
  90                 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
  91                            BDW_DISABLE_HDC_INVALIDATION);
  92
  93                 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
  94                 I915_WRITE(FF_SLICE_CS_CHICKEN2,
  95                            _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
  96         }
  97
  98         /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
  99          * involving this register should also be added to WA batch as required.
 100          */
 101         if (INTEL_REVID(dev) <= SKL_REVID_E0)
 102                 /* WaDisableLSQCROPERFforOCL:skl */
 103                 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
 104                            GEN8_LQSC_RO_PERF_DIS);
 105
 106         /* WaEnableGapsTsvCreditFix:skl */
 107         if (IS_SKYLAKE(dev) && (INTEL_REVID(dev) >= SKL_REVID_C0)) {
 108                 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
 109                                            GEN9_GAPS_TSV_CREDIT_DISABLE));
 110         }
 111 }
 112
 113 static void bxt_init_clock_gating(struct drm_device *dev)
 114 {
 115         struct drm_i915_private *dev_priv = dev->dev_private;
 116
 117         gen9_init_clock_gating(dev);
 118
 119         /*
 120          * FIXME:
 121          * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only.
 122          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
 123          */
 124          /* WaDisableSDEUnitClockGating:bxt */
 125         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
 126                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE |
 127                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
 128
 129         /* FIXME: apply on A0 only */
 130         I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
 131 }
 132
 133 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 134 {
 135         struct drm_i915_private *dev_priv = dev->dev_private;
 136         u32 tmp;
 137
 138         tmp = I915_READ(CLKCFG);
 139
 140         switch (tmp & CLKCFG_FSB_MASK) {
 141         case CLKCFG_FSB_533:
 142                 dev_priv->fsb_freq = 533; /* 133*4 */
 143                 break;
 144         case CLKCFG_FSB_800:
 145                 dev_priv->fsb_freq = 800; /* 200*4 */
 146                 break;
 147         case CLKCFG_FSB_667:
 148                 dev_priv->fsb_freq =  667; /* 167*4 */
 149                 break;
 150         case CLKCFG_FSB_400:
 151                 dev_priv->fsb_freq = 400; /* 100*4 */
 152                 break;
 153         }
 154
 155         switch (tmp & CLKCFG_MEM_MASK) {
 156         case CLKCFG_MEM_533:
 157                 dev_priv->mem_freq = 533;
 158                 break;
 159         case CLKCFG_MEM_667:
 160                 dev_priv->mem_freq = 667;
 161                 break;
 162         case CLKCFG_MEM_800:
 163                 dev_priv->mem_freq = 800;
 164                 break;
 165         }
 166
 167         /* detect pineview DDR3 setting */
 168         tmp = I915_READ(CSHRDDR3CTL);
 169         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 170 }
 171
 172 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 173 {
 174         struct drm_i915_private *dev_priv = dev->dev_private;
 175         u16 ddrpll, csipll;
 176
 177         ddrpll = I915_READ16(DDRMPLL1);
 178         csipll = I915_READ16(CSIPLL0);
 179
 180         switch (ddrpll & 0xff) {
 181         case 0xc:
 182                 dev_priv->mem_freq = 800;
 183                 break;
 184         case 0x10:
 185                 dev_priv->mem_freq = 1066;
 186                 break;
 187         case 0x14:
 188                 dev_priv->mem_freq = 1333;
 189                 break;
 190         case 0x18:
 191                 dev_priv->mem_freq = 1600;
 192                 break;
 193         default:
 194                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 195                                  ddrpll & 0xff);
 196                 dev_priv->mem_freq = 0;
 197                 break;
 198         }
 199
 200         dev_priv->ips.r_t = dev_priv->mem_freq;
 201
 202         switch (csipll & 0x3ff) {
 203         case 0x00c:
 204                 dev_priv->fsb_freq = 3200;
 205                 break;
 206         case 0x00e:
 207                 dev_priv->fsb_freq = 3733;
 208                 break;
 209         case 0x010:
 210                 dev_priv->fsb_freq = 4266;
 211                 break;
 212         case 0x012:
 213                 dev_priv->fsb_freq = 4800;
 214                 break;
 215         case 0x014:
 216                 dev_priv->fsb_freq = 5333;
 217                 break;
 218         case 0x016:
 219                 dev_priv->fsb_freq = 5866;
 220                 break;
 221         case 0x018:
 222                 dev_priv->fsb_freq = 6400;
 223                 break;
 224         default:
 225                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 226                                  csipll & 0x3ff);
 227                 dev_priv->fsb_freq = 0;
 228                 break;
 229         }
 230
 231         if (dev_priv->fsb_freq == 3200) {
 232                 dev_priv->ips.c_m = 0;
 233         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 234                 dev_priv->ips.c_m = 1;
 235         } else {
 236                 dev_priv->ips.c_m = 2;
 237         }
 238 }
 239
 240 static const struct cxsr_latency cxsr_latency_table[] = {
 241         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 242         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 243         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 244         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 245         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 246
 247         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 248         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 249         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 250         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 251         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 252
 253         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 254         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 255         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 256         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 257         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 258
 259         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 260         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 261         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 262         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 263         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 264
 265         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 266         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 267         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 268         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 269         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 270
 271         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 272         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 273         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 274         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 275         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 276 };
 277
 278 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 279                                                          int is_ddr3,
 280                                                          int fsb,
 281                                                          int mem)
 282 {
 283         const struct cxsr_latency *latency;
 284         int i;
 285
 286         if (fsb == 0 || mem == 0)
 287                 return NULL;
 288
 289         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 290                 latency = &cxsr_latency_table[i];
 291                 if (is_desktop == latency->is_desktop &&
 292                     is_ddr3 == latency->is_ddr3 &&
 293                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 294                         return latency;
 295         }
 296
 297         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 298
 299         return NULL;
 300 }
 301
 302 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 303 {
 304         u32 val;
 305
 306         mutex_lock(&dev_priv->rps.hw_lock);
 307
 308         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 309         if (enable)
 310                 val &= ~FORCE_DDR_HIGH_FREQ;
 311         else
 312                 val |= FORCE_DDR_HIGH_FREQ;
 313         val &= ~FORCE_DDR_LOW_FREQ;
 314         val |= FORCE_DDR_FREQ_REQ_ACK;
 315         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 316
 317         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 318                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 319                 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
 320
 321         mutex_unlock(&dev_priv->rps.hw_lock);
 322 }
 323
 324 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 325 {
 326         u32 val;
 327
 328         mutex_lock(&dev_priv->rps.hw_lock);
 329
 330         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 331         if (enable)
 332                 val |= DSP_MAXFIFO_PM5_ENABLE;
 333         else
 334                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 335         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 336
 337         mutex_unlock(&dev_priv->rps.hw_lock);
 338 }
 339
 340 #define FW_WM(value, plane) \
 341         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 342
 343 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 344 {
 345         struct drm_device *dev = dev_priv->dev;
 346         u32 val;
 347
 348         if (IS_VALLEYVIEW(dev)) {
 349                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 350                 POSTING_READ(FW_BLC_SELF_VLV);
 351                 dev_priv->wm.vlv.cxsr = enable;
 352         } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
 353                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 354                 POSTING_READ(FW_BLC_SELF);
 355         } else if (IS_PINEVIEW(dev)) {
 356                 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
 357                 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
 358                 I915_WRITE(DSPFW3, val);
 359                 POSTING_READ(DSPFW3);
 360         } else if (IS_I945G(dev) || IS_I945GM(dev)) {
 361                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 362                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 363                 I915_WRITE(FW_BLC_SELF, val);
 364                 POSTING_READ(FW_BLC_SELF);
 365         } else if (IS_I915GM(dev)) {
 366                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 367                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 368                 I915_WRITE(INSTPM, val);
 369                 POSTING_READ(INSTPM);
 370         } else {
 371                 return;
 372         }
 373
 374         DRM_DEBUG_KMS("memory self-refresh is %s\n",
 375                       enable ? "enabled" : "disabled");
 376 }
 377
 378
 379 /*
 380  * Latency for FIFO fetches is dependent on several factors:
 381  *   - memory configuration (speed, channels)
 382  *   - chipset
 383  *   - current MCH state
 384  * It can be fairly high in some situations, so here we assume a fairly
 385  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 386  * set this value too high, the FIFO will fetch frequently to stay full)
 387  * and power consumption (set it too low to save power and we might see
 388  * FIFO underruns and display "flicker").
 389  *
 390  * A value of 5us seems to be a good balance; safe for very low end
 391  * platforms but not overly aggressive on lower latency configs.
 392  */
 393 static const int pessimal_latency_ns = 5000;
 394
 395 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 396         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 397
 398 static int vlv_get_fifo_size(struct drm_device *dev,
 399                               enum pipe pipe, int plane)
 400 {
 401         struct drm_i915_private *dev_priv = dev->dev_private;
 402         int sprite0_start, sprite1_start, size;
 403
 404         switch (pipe) {
 405                 uint32_t dsparb, dsparb2, dsparb3;
 406         case PIPE_A:
 407                 dsparb = I915_READ(DSPARB);
 408                 dsparb2 = I915_READ(DSPARB2);
 409                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 410                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 411                 break;
 412         case PIPE_B:
 413                 dsparb = I915_READ(DSPARB);
 414                 dsparb2 = I915_READ(DSPARB2);
 415                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 416                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 417                 break;
 418         case PIPE_C:
 419                 dsparb2 = I915_READ(DSPARB2);
 420                 dsparb3 = I915_READ(DSPARB3);
 421                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 422                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 423                 break;
 424         default:
 425                 return 0;
 426         }
 427
 428         switch (plane) {
 429         case 0:
 430                 size = sprite0_start;
 431                 break;
 432         case 1:
 433                 size = sprite1_start - sprite0_start;
 434                 break;
 435         case 2:
 436                 size = 512 - 1 - sprite1_start;
 437                 break;
 438         default:
 439                 return 0;
 440         }
 441
 442         DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
 443                       pipe_name(pipe), plane == 0 ? "primary" : "sprite",
 444                       plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
 445                       size);
 446
 447         return size;
 448 }
 449
 450 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 451 {
 452         struct drm_i915_private *dev_priv = dev->dev_private;
 453         uint32_t dsparb = I915_READ(DSPARB);
 454         int size;
 455
 456         size = dsparb & 0x7f;
 457         if (plane)
 458                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 459
 460         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 461                       plane ? "B" : "A", size);
 462
 463         return size;
 464 }
 465
 466 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 467 {
 468         struct drm_i915_private *dev_priv = dev->dev_private;
 469         uint32_t dsparb = I915_READ(DSPARB);
 470         int size;
 471
 472         size = dsparb & 0x1ff;
 473         if (plane)
 474                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 475         size >>= 1; /* Convert to cachelines */
 476
 477         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 478                       plane ? "B" : "A", size);
 479
 480         return size;
 481 }
 482
 483 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 484 {
 485         struct drm_i915_private *dev_priv = dev->dev_private;
 486         uint32_t dsparb = I915_READ(DSPARB);
 487         int size;
 488
 489         size = dsparb & 0x7f;
 490         size >>= 2; /* Convert to cachelines */
 491
 492         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 493                       plane ? "B" : "A",
 494                       size);
 495
 496         return size;
 497 }
 498
 499 /* Pineview has different values for various configs */
 500 static const struct intel_watermark_params pineview_display_wm = {
 501         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 502         .max_wm = PINEVIEW_MAX_WM,
 503         .default_wm = PINEVIEW_DFT_WM,
 504         .guard_size = PINEVIEW_GUARD_WM,
 505         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 506 };
 507 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 508         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 509         .max_wm = PINEVIEW_MAX_WM,
 510         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 511         .guard_size = PINEVIEW_GUARD_WM,
 512         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 513 };
 514 static const struct intel_watermark_params pineview_cursor_wm = {
 515         .fifo_size = PINEVIEW_CURSOR_FIFO,
 516         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 517         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 518         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 519         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 520 };
 521 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 522         .fifo_size = PINEVIEW_CURSOR_FIFO,
 523         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 524         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 525         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 526         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 527 };
 528 static const struct intel_watermark_params g4x_wm_info = {
 529         .fifo_size = G4X_FIFO_SIZE,
 530         .max_wm = G4X_MAX_WM,
 531         .default_wm = G4X_MAX_WM,
 532         .guard_size = 2,
 533         .cacheline_size = G4X_FIFO_LINE_SIZE,
 534 };
 535 static const struct intel_watermark_params g4x_cursor_wm_info = {
 536         .fifo_size = I965_CURSOR_FIFO,
 537         .max_wm = I965_CURSOR_MAX_WM,
 538         .default_wm = I965_CURSOR_DFT_WM,
 539         .guard_size = 2,
 540         .cacheline_size = G4X_FIFO_LINE_SIZE,
 541 };
 542 static const struct intel_watermark_params valleyview_wm_info = {
 543         .fifo_size = VALLEYVIEW_FIFO_SIZE,
 544         .max_wm = VALLEYVIEW_MAX_WM,
 545         .default_wm = VALLEYVIEW_MAX_WM,
 546         .guard_size = 2,
 547         .cacheline_size = G4X_FIFO_LINE_SIZE,
 548 };
 549 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 550         .fifo_size = I965_CURSOR_FIFO,
 551         .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
 552         .default_wm = I965_CURSOR_DFT_WM,
 553         .guard_size = 2,
 554         .cacheline_size = G4X_FIFO_LINE_SIZE,
 555 };
 556 static const struct intel_watermark_params i965_cursor_wm_info = {
 557         .fifo_size = I965_CURSOR_FIFO,
 558         .max_wm = I965_CURSOR_MAX_WM,
 559         .default_wm = I965_CURSOR_DFT_WM,
 560         .guard_size = 2,
 561         .cacheline_size = I915_FIFO_LINE_SIZE,
 562 };
 563 static const struct intel_watermark_params i945_wm_info = {
 564         .fifo_size = I945_FIFO_SIZE,
 565         .max_wm = I915_MAX_WM,
 566         .default_wm = 1,
 567         .guard_size = 2,
 568         .cacheline_size = I915_FIFO_LINE_SIZE,
 569 };
 570 static const struct intel_watermark_params i915_wm_info = {
 571         .fifo_size = I915_FIFO_SIZE,
 572         .max_wm = I915_MAX_WM,
 573         .default_wm = 1,
 574         .guard_size = 2,
 575         .cacheline_size = I915_FIFO_LINE_SIZE,
 576 };
 577 static const struct intel_watermark_params i830_a_wm_info = {
 578         .fifo_size = I855GM_FIFO_SIZE,
 579         .max_wm = I915_MAX_WM,
 580         .default_wm = 1,
 581         .guard_size = 2,
 582         .cacheline_size = I830_FIFO_LINE_SIZE,
 583 };
 584 static const struct intel_watermark_params i830_bc_wm_info = {
 585         .fifo_size = I855GM_FIFO_SIZE,
 586         .max_wm = I915_MAX_WM/2,
 587         .default_wm = 1,
 588         .guard_size = 2,
 589         .cacheline_size = I830_FIFO_LINE_SIZE,
 590 };
 591 static const struct intel_watermark_params i845_wm_info = {
 592         .fifo_size = I830_FIFO_SIZE,
 593         .max_wm = I915_MAX_WM,
 594         .default_wm = 1,
 595         .guard_size = 2,
 596         .cacheline_size = I830_FIFO_LINE_SIZE,
 597 };
 598
 599 /**
 600  * intel_calculate_wm - calculate watermark level
 601  * @clock_in_khz: pixel clock
 602  * @wm: chip FIFO params
 603  * @pixel_size: display pixel size
 604  * @latency_ns: memory latency for the platform
 605  *
 606  * Calculate the watermark level (the level at which the display plane will
 607  * start fetching from memory again).  Each chip has a different display
 608  * FIFO size and allocation, so the caller needs to figure that out and pass
 609  * in the correct intel_watermark_params structure.
 610  *
 611  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 612  * on the pixel size.  When it reaches the watermark level, it'll start
 613  * fetching FIFO line sized based chunks from memory until the FIFO fills
 614  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 615  * will occur, and a display engine hang could result.
 616  */
 617 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 618                                         const struct intel_watermark_params *wm,
 619                                         int fifo_size,
 620                                         int pixel_size,
 621                                         unsigned long latency_ns)
 622 {
 623         long entries_required, wm_size;
 624
 625         /*
 626          * Note: we need to make sure we don't overflow for various clock &
 627          * latency values.
 628          * clocks go from a few thousand to several hundred thousand.
 629          * latency is usually a few thousand
 630          */
 631         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
 632                 1000;
 633         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 634
 635         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 636
 637         wm_size = fifo_size - (entries_required + wm->guard_size);
 638
 639         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 640
 641         /* Don't promote wm_size to unsigned... */
 642         if (wm_size > (long)wm->max_wm)
 643                 wm_size = wm->max_wm;
 644         if (wm_size <= 0)
 645                 wm_size = wm->default_wm;
 646
 647         /*
 648          * Bspec seems to indicate that the value shouldn't be lower than
 649          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 650          * Lets go for 8 which is the burst size since certain platforms
 651          * already use a hardcoded 8 (which is what the spec says should be
 652          * done).
 653          */
 654         if (wm_size <= 8)
 655                 wm_size = 8;
 656
 657         return wm_size;
 658 }
 659
 660 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
 661 {
 662         struct drm_crtc *crtc, *enabled = NULL;
 663
 664         for_each_crtc(dev, crtc) {
 665                 if (intel_crtc_active(crtc)) {
 666                         if (enabled)
 667                                 return NULL;
 668                         enabled = crtc;
 669                 }
 670         }
 671
 672         return enabled;
 673 }
 674
 675 static void pineview_update_wm(struct drm_crtc *unused_crtc)
 676 {
 677         struct drm_device *dev = unused_crtc->dev;
 678         struct drm_i915_private *dev_priv = dev->dev_private;
 679         struct drm_crtc *crtc;
 680         const struct cxsr_latency *latency;
 681         u32 reg;
 682         unsigned long wm;
 683
 684         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
 685                                          dev_priv->fsb_freq, dev_priv->mem_freq);
 686         if (!latency) {
 687                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 688                 intel_set_memory_cxsr(dev_priv, false);
 689                 return;
 690         }
 691
 692         crtc = single_enabled_crtc(dev);
 693         if (crtc) {
 694                 const struct drm_display_mode *adjusted_mode;
 695                 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
 696                 int clock;
 697
 698                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 699                 clock = adjusted_mode->crtc_clock;
 700
 701                 /* Display SR */
 702                 wm = intel_calculate_wm(clock, &pineview_display_wm,
 703                                         pineview_display_wm.fifo_size,
 704                                         pixel_size, latency->display_sr);
 705                 reg = I915_READ(DSPFW1);
 706                 reg &= ~DSPFW_SR_MASK;
 707                 reg |= FW_WM(wm, SR);
 708                 I915_WRITE(DSPFW1, reg);
 709                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 710
 711                 /* cursor SR */
 712                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 713                                         pineview_display_wm.fifo_size,
 714                                         pixel_size, latency->cursor_sr);
 715                 reg = I915_READ(DSPFW3);
 716                 reg &= ~DSPFW_CURSOR_SR_MASK;
 717                 reg |= FW_WM(wm, CURSOR_SR);
 718                 I915_WRITE(DSPFW3, reg);
 719
 720                 /* Display HPLL off SR */
 721                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 722                                         pineview_display_hplloff_wm.fifo_size,
 723                                         pixel_size, latency->display_hpll_disable);
 724                 reg = I915_READ(DSPFW3);
 725                 reg &= ~DSPFW_HPLL_SR_MASK;
 726                 reg |= FW_WM(wm, HPLL_SR);
 727                 I915_WRITE(DSPFW3, reg);
 728
 729                 /* cursor HPLL off SR */
 730                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 731                                         pineview_display_hplloff_wm.fifo_size,
 732                                         pixel_size, latency->cursor_hpll_disable);
 733                 reg = I915_READ(DSPFW3);
 734                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 735                 reg |= FW_WM(wm, HPLL_CURSOR);
 736                 I915_WRITE(DSPFW3, reg);
 737                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 738
 739                 intel_set_memory_cxsr(dev_priv, true);
 740         } else {
 741                 intel_set_memory_cxsr(dev_priv, false);
 742         }
 743 }
 744
 745 static bool g4x_compute_wm0(struct drm_device *dev,
 746                             int plane,
 747                             const struct intel_watermark_params *display,
 748                             int display_latency_ns,
 749                             const struct intel_watermark_params *cursor,
 750                             int cursor_latency_ns,
 751                             int *plane_wm,
 752                             int *cursor_wm)
 753 {
 754         struct drm_crtc *crtc;
 755         const struct drm_display_mode *adjusted_mode;
 756         int htotal, hdisplay, clock, pixel_size;
 757         int line_time_us, line_count;
 758         int entries, tlb_miss;
 759
 760         crtc = intel_get_crtc_for_plane(dev, plane);
 761         if (!intel_crtc_active(crtc)) {
 762                 *cursor_wm = cursor->guard_size;
 763                 *plane_wm = display->guard_size;
 764                 return false;
 765         }
 766
 767         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 768         clock = adjusted_mode->crtc_clock;
 769         htotal = adjusted_mode->crtc_htotal;
 770         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 771         pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
 772
 773         /* Use the small buffer method to calculate plane watermark */
 774         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
 775         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
 776         if (tlb_miss > 0)
 777                 entries += tlb_miss;
 778         entries = DIV_ROUND_UP(entries, display->cacheline_size);
 779         *plane_wm = entries + display->guard_size;
 780         if (*plane_wm > (int)display->max_wm)
 781                 *plane_wm = display->max_wm;
 782
 783         /* Use the large buffer method to calculate cursor watermark */
 784         line_time_us = max(htotal * 1000 / clock, 1);
 785         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
 786         entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
 787         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
 788         if (tlb_miss > 0)
 789                 entries += tlb_miss;
 790         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 791         *cursor_wm = entries + cursor->guard_size;
 792         if (*cursor_wm > (int)cursor->max_wm)
 793                 *cursor_wm = (int)cursor->max_wm;
 794
 795         return true;
 796 }
 797
 798 /*
 799  * Check the wm result.
 800  *
 801  * If any calculated watermark values is larger than the maximum value that
 802  * can be programmed into the associated watermark register, that watermark
 803  * must be disabled.
 804  */
 805 static bool g4x_check_srwm(struct drm_device *dev,
 806                            int display_wm, int cursor_wm,
 807                            const struct intel_watermark_params *display,
 808                            const struct intel_watermark_params *cursor)
 809 {
 810         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
 811                       display_wm, cursor_wm);
 812
 813         if (display_wm > display->max_wm) {
 814                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
 815                               display_wm, display->max_wm);
 816                 return false;
 817         }
 818
 819         if (cursor_wm > cursor->max_wm) {
 820                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
 821                               cursor_wm, cursor->max_wm);
 822                 return false;
 823         }
 824
 825         if (!(display_wm || cursor_wm)) {
 826                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
 827                 return false;
 828         }
 829
 830         return true;
 831 }
 832
 833 static bool g4x_compute_srwm(struct drm_device *dev,
 834                              int plane,
 835                              int latency_ns,
 836                              const struct intel_watermark_params *display,
 837                              const struct intel_watermark_params *cursor,
 838                              int *display_wm, int *cursor_wm)
 839 {
 840         struct drm_crtc *crtc;
 841         const struct drm_display_mode *adjusted_mode;
 842         int hdisplay, htotal, pixel_size, clock;
 843         unsigned long line_time_us;
 844         int line_count, line_size;
 845         int small, large;
 846         int entries;
 847
 848         if (!latency_ns) {
 849                 *display_wm = *cursor_wm = 0;
 850                 return false;
 851         }
 852
 853         crtc = intel_get_crtc_for_plane(dev, plane);
 854         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 855         clock = adjusted_mode->crtc_clock;
 856         htotal = adjusted_mode->crtc_htotal;
 857         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 858         pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
 859
 860         line_time_us = max(htotal * 1000 / clock, 1);
 861         line_count = (latency_ns / line_time_us + 1000) / 1000;
 862         line_size = hdisplay * pixel_size;
 863
 864         /* Use the minimum of the small and large buffer method for primary */
 865         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
 866         large = line_count * line_size;
 867
 868         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
 869         *display_wm = entries + display->guard_size;
 870
 871         /* calculate the self-refresh watermark for display cursor */
 872         entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
 873         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 874         *cursor_wm = entries + cursor->guard_size;
 875
 876         return g4x_check_srwm(dev,
 877                               *display_wm, *cursor_wm,
 878                               display, cursor);
 879 }
 880
 881 #define FW_WM_VLV(value, plane) \
 882         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
 883
 884 static void vlv_write_wm_values(struct intel_crtc *crtc,
 885                                 const struct vlv_wm_values *wm)
 886 {
 887         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 888         enum pipe pipe = crtc->pipe;
 889
 890         I915_WRITE(VLV_DDL(pipe),
 891                    (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
 892                    (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
 893                    (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
 894                    (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
 895
 896         I915_WRITE(DSPFW1,
 897                    FW_WM(wm->sr.plane, SR) |
 898                    FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
 899                    FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
 900                    FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
 901         I915_WRITE(DSPFW2,
 902                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
 903                    FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
 904                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
 905         I915_WRITE(DSPFW3,
 906                    FW_WM(wm->sr.cursor, CURSOR_SR));
 907
 908         if (IS_CHERRYVIEW(dev_priv)) {
 909                 I915_WRITE(DSPFW7_CHV,
 910                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 911                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 912                 I915_WRITE(DSPFW8_CHV,
 913                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
 914                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
 915                 I915_WRITE(DSPFW9_CHV,
 916                            FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
 917                            FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
 918                 I915_WRITE(DSPHOWM,
 919                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 920                            FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
 921                            FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
 922                            FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
 923                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 924                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 925                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 926                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 927                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 928                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 929         } else {
 930                 I915_WRITE(DSPFW7,
 931                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 932                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 933                 I915_WRITE(DSPHOWM,
 934                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 935                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 936                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 937                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 938                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 939                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 940                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 941         }
 942
 943         /* zero (unused) WM1 watermarks */
 944         I915_WRITE(DSPFW4, 0);
 945         I915_WRITE(DSPFW5, 0);
 946         I915_WRITE(DSPFW6, 0);
 947         I915_WRITE(DSPHOWM1, 0);
 948
 949         POSTING_READ(DSPFW1);
 950 }
 951
 952 #undef FW_WM_VLV
 953
 954 enum vlv_wm_level {
 955         VLV_WM_LEVEL_PM2,
 956         VLV_WM_LEVEL_PM5,
 957         VLV_WM_LEVEL_DDR_DVFS,
 958         CHV_WM_NUM_LEVELS,
 959         VLV_WM_NUM_LEVELS = 1,
 960 };
 961
 962 /* latency must be in 0.1us units. */
 963 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
 964                                    unsigned int pipe_htotal,
 965                                    unsigned int horiz_pixels,
 966                                    unsigned int bytes_per_pixel,
 967                                    unsigned int latency)
 968 {
 969         unsigned int ret;
 970
 971         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
 972         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
 973         ret = DIV_ROUND_UP(ret, 64);
 974
 975         return ret;
 976 }
 977
 978 static void vlv_setup_wm_latency(struct drm_device *dev)
 979 {
 980         struct drm_i915_private *dev_priv = dev->dev_private;
 981
 982         /* all latencies in usec */
 983         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
 984
 985         if (IS_CHERRYVIEW(dev_priv)) {
 986                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
 987                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
 988         }
 989 }
 990
 991 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
 992                                      struct intel_crtc *crtc,
 993                                      const struct intel_plane_state *state,
 994                                      int level)
 995 {
 996         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 997         int clock, htotal, pixel_size, width, wm;
 998
 999         if (dev_priv->wm.pri_latency[level] == 0)
1000                 return USHRT_MAX;
1001
1002         if (!state->visible)
1003                 return 0;
1004
1005         pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1006         clock = crtc->config->base.adjusted_mode.crtc_clock;
1007         htotal = crtc->config->base.adjusted_mode.crtc_htotal;
1008         width = crtc->config->pipe_src_w;
1009         if (WARN_ON(htotal == 0))
1010                 htotal = 1;
1011
1012         if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1013                 /*
1014                  * FIXME the formula gives values that are
1015                  * too big for the cursor FIFO, and hence we
1016                  * would never be able to use cursors. For
1017                  * now just hardcode the watermark.
1018                  */
1019                 wm = 63;
1020         } else {
1021                 wm = vlv_wm_method2(clock, htotal, width, pixel_size,
1022                                     dev_priv->wm.pri_latency[level] * 10);
1023         }
1024
1025         return min_t(int, wm, USHRT_MAX);
1026 }
1027
1028 static void vlv_compute_fifo(struct intel_crtc *crtc)
1029 {
1030         struct drm_device *dev = crtc->base.dev;
1031         struct vlv_wm_state *wm_state = &crtc->wm_state;
1032         struct intel_plane *plane;
1033         unsigned int total_rate = 0;
1034         const int fifo_size = 512 - 1;
1035         int fifo_extra, fifo_left = fifo_size;
1036
1037         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1038                 struct intel_plane_state *state =
1039                         to_intel_plane_state(plane->base.state);
1040
1041                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1042                         continue;
1043
1044                 if (state->visible) {
1045                         wm_state->num_active_planes++;
1046                         total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1047                 }
1048         }
1049
1050         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1051                 struct intel_plane_state *state =
1052                         to_intel_plane_state(plane->base.state);
1053                 unsigned int rate;
1054
1055                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1056                         plane->wm.fifo_size = 63;
1057                         continue;
1058                 }
1059
1060                 if (!state->visible) {
1061                         plane->wm.fifo_size = 0;
1062                         continue;
1063                 }
1064
1065                 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1066                 plane->wm.fifo_size = fifo_size * rate / total_rate;
1067                 fifo_left -= plane->wm.fifo_size;
1068         }
1069
1070         fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1071
1072         /* spread the remainder evenly */
1073         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1074                 int plane_extra;
1075
1076                 if (fifo_left == 0)
1077                         break;
1078
1079                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1080                         continue;
1081
1082                 /* give it all to the first plane if none are active */
1083                 if (plane->wm.fifo_size == 0 &&
1084                     wm_state->num_active_planes)
1085                         continue;
1086
1087                 plane_extra = min(fifo_extra, fifo_left);
1088                 plane->wm.fifo_size += plane_extra;
1089                 fifo_left -= plane_extra;
1090         }
1091
1092         WARN_ON(fifo_left != 0);
1093 }
1094
1095 static void vlv_invert_wms(struct intel_crtc *crtc)
1096 {
1097         struct vlv_wm_state *wm_state = &crtc->wm_state;
1098         int level;
1099
1100         for (level = 0; level < wm_state->num_levels; level++) {
1101                 struct drm_device *dev = crtc->base.dev;
1102                 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1103                 struct intel_plane *plane;
1104
1105                 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1106                 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1107
1108                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1109                         switch (plane->base.type) {
1110                                 int sprite;
1111                         case DRM_PLANE_TYPE_CURSOR:
1112                                 wm_state->wm[level].cursor = plane->wm.fifo_size -
1113                                         wm_state->wm[level].cursor;
1114                                 break;
1115                         case DRM_PLANE_TYPE_PRIMARY:
1116                                 wm_state->wm[level].primary = plane->wm.fifo_size -
1117                                         wm_state->wm[level].primary;
1118                                 break;
1119                         case DRM_PLANE_TYPE_OVERLAY:
1120                                 sprite = plane->plane;
1121                                 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1122                                         wm_state->wm[level].sprite[sprite];
1123                                 break;
1124                         }
1125                 }
1126         }
1127 }
1128
1129 static void vlv_compute_wm(struct intel_crtc *crtc)
1130 {
1131         struct drm_device *dev = crtc->base.dev;
1132         struct vlv_wm_state *wm_state = &crtc->wm_state;
1133         struct intel_plane *plane;
1134         int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1135         int level;
1136
1137         memset(wm_state, 0, sizeof(*wm_state));
1138
1139         wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1140         if (IS_CHERRYVIEW(dev))
1141                 wm_state->num_levels = CHV_WM_NUM_LEVELS;
1142         else
1143                 wm_state->num_levels = VLV_WM_NUM_LEVELS;
1144
1145         wm_state->num_active_planes = 0;
1146
1147         vlv_compute_fifo(crtc);
1148
1149         if (wm_state->num_active_planes != 1)
1150                 wm_state->cxsr = false;
1151
1152         if (wm_state->cxsr) {
1153                 for (level = 0; level < wm_state->num_levels; level++) {
1154                         wm_state->sr[level].plane = sr_fifo_size;
1155                         wm_state->sr[level].cursor = 63;
1156                 }
1157         }
1158
1159         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1160                 struct intel_plane_state *state =
1161                         to_intel_plane_state(plane->base.state);
1162
1163                 if (!state->visible)
1164                         continue;
1165
1166                 /* normal watermarks */
1167                 for (level = 0; level < wm_state->num_levels; level++) {
1168                         int wm = vlv_compute_wm_level(plane, crtc, state, level);
1169                         int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1170
1171                         /* hack */
1172                         if (WARN_ON(level == 0 && wm > max_wm))
1173                                 wm = max_wm;
1174
1175                         if (wm > plane->wm.fifo_size)
1176                                 break;
1177
1178                         switch (plane->base.type) {
1179                                 int sprite;
1180                         case DRM_PLANE_TYPE_CURSOR:
1181                                 wm_state->wm[level].cursor = wm;
1182                                 break;
1183                         case DRM_PLANE_TYPE_PRIMARY:
1184                                 wm_state->wm[level].primary = wm;
1185                                 break;
1186                         case DRM_PLANE_TYPE_OVERLAY:
1187                                 sprite = plane->plane;
1188                                 wm_state->wm[level].sprite[sprite] = wm;
1189                                 break;
1190                         }
1191                 }
1192
1193                 wm_state->num_levels = level;
1194
1195                 if (!wm_state->cxsr)
1196                         continue;
1197
1198                 /* maxfifo watermarks */
1199                 switch (plane->base.type) {
1200                         int sprite, level;
1201                 case DRM_PLANE_TYPE_CURSOR:
1202                         for (level = 0; level < wm_state->num_levels; level++)
1203                                 wm_state->sr[level].cursor =
1204                                         wm_state->sr[level].cursor;
1205                         break;
1206                 case DRM_PLANE_TYPE_PRIMARY:
1207                         for (level = 0; level < wm_state->num_levels; level++)
1208                                 wm_state->sr[level].plane =
1209                                         min(wm_state->sr[level].plane,
1210                                             wm_state->wm[level].primary);
1211                         break;
1212                 case DRM_PLANE_TYPE_OVERLAY:
1213                         sprite = plane->plane;
1214                         for (level = 0; level < wm_state->num_levels; level++)
1215                                 wm_state->sr[level].plane =
1216                                         min(wm_state->sr[level].plane,
1217                                             wm_state->wm[level].sprite[sprite]);
1218                         break;
1219                 }
1220         }
1221
1222         /* clear any (partially) filled invalid levels */
1223         for (level = wm_state->num_levels; level < CHV_WM_NUM_LEVELS; level++) {
1224                 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1225                 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1226         }
1227
1228         vlv_invert_wms(crtc);
1229 }
1230
1231 #define VLV_FIFO(plane, value) \
1232         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1233
1234 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1235 {
1236         struct drm_device *dev = crtc->base.dev;
1237         struct drm_i915_private *dev_priv = to_i915(dev);
1238         struct intel_plane *plane;
1239         int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1240
1241         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1242                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1243                         WARN_ON(plane->wm.fifo_size != 63);
1244                         continue;
1245                 }
1246
1247                 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1248                         sprite0_start = plane->wm.fifo_size;
1249                 else if (plane->plane == 0)
1250                         sprite1_start = sprite0_start + plane->wm.fifo_size;
1251                 else
1252                         fifo_size = sprite1_start + plane->wm.fifo_size;
1253         }
1254
1255         WARN_ON(fifo_size != 512 - 1);
1256
1257         DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1258                       pipe_name(crtc->pipe), sprite0_start,
1259                       sprite1_start, fifo_size);
1260
1261         switch (crtc->pipe) {
1262                 uint32_t dsparb, dsparb2, dsparb3;
1263         case PIPE_A:
1264                 dsparb = I915_READ(DSPARB);
1265                 dsparb2 = I915_READ(DSPARB2);
1266
1267                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1268                             VLV_FIFO(SPRITEB, 0xff));
1269                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1270                            VLV_FIFO(SPRITEB, sprite1_start));
1271
1272                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1273                              VLV_FIFO(SPRITEB_HI, 0x1));
1274                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1275                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1276
1277                 I915_WRITE(DSPARB, dsparb);
1278                 I915_WRITE(DSPARB2, dsparb2);
1279                 break;
1280         case PIPE_B:
1281                 dsparb = I915_READ(DSPARB);
1282                 dsparb2 = I915_READ(DSPARB2);
1283
1284                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1285                             VLV_FIFO(SPRITED, 0xff));
1286                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1287                            VLV_FIFO(SPRITED, sprite1_start));
1288
1289                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1290                              VLV_FIFO(SPRITED_HI, 0xff));
1291                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1292                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1293
1294                 I915_WRITE(DSPARB, dsparb);
1295                 I915_WRITE(DSPARB2, dsparb2);
1296                 break;
1297         case PIPE_C:
1298                 dsparb3 = I915_READ(DSPARB3);
1299                 dsparb2 = I915_READ(DSPARB2);
1300
1301                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1302                              VLV_FIFO(SPRITEF, 0xff));
1303                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1304                             VLV_FIFO(SPRITEF, sprite1_start));
1305
1306                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1307                              VLV_FIFO(SPRITEF_HI, 0xff));
1308                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1309                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1310
1311                 I915_WRITE(DSPARB3, dsparb3);
1312                 I915_WRITE(DSPARB2, dsparb2);
1313                 break;
1314         default:
1315                 break;
1316         }
1317 }
1318
1319 #undef VLV_FIFO
1320
1321 static void vlv_merge_wm(struct drm_device *dev,
1322                          struct vlv_wm_values *wm)
1323 {
1324         struct intel_crtc *crtc;
1325         int num_active_crtcs = 0;
1326
1327         if (IS_CHERRYVIEW(dev))
1328                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
1329         else
1330                 wm->level = VLV_WM_LEVEL_PM2;
1331         wm->cxsr = true;
1332
1333         for_each_intel_crtc(dev, crtc) {
1334                 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1335
1336                 if (!crtc->active)
1337                         continue;
1338
1339                 if (!wm_state->cxsr)
1340                         wm->cxsr = false;
1341
1342                 num_active_crtcs++;
1343                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1344         }
1345
1346         if (num_active_crtcs != 1)
1347                 wm->cxsr = false;
1348
1349         if (num_active_crtcs > 1)
1350                 wm->level = VLV_WM_LEVEL_PM2;
1351
1352         for_each_intel_crtc(dev, crtc) {
1353                 struct vlv_wm_state *wm_state = &crtc->wm_state;
1354                 enum pipe pipe = crtc->pipe;
1355
1356                 if (!crtc->active)
1357                         continue;
1358
1359                 wm->pipe[pipe] = wm_state->wm[wm->level];
1360                 if (wm->cxsr)
1361                         wm->sr = wm_state->sr[wm->level];
1362
1363                 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1364                 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1365                 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1366                 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1367         }
1368 }
1369
1370 static void vlv_update_wm(struct drm_crtc *crtc)
1371 {
1372         struct drm_device *dev = crtc->dev;
1373         struct drm_i915_private *dev_priv = dev->dev_private;
1374         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1375         enum pipe pipe = intel_crtc->pipe;
1376         struct vlv_wm_values wm = {};
1377
1378         vlv_compute_wm(intel_crtc);
1379         vlv_merge_wm(dev, &wm);
1380
1381         if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1382                 /* FIXME should be part of crtc atomic commit */
1383                 vlv_pipe_set_fifo_size(intel_crtc);
1384                 return;
1385         }
1386
1387         if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1388             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1389                 chv_set_memory_dvfs(dev_priv, false);
1390
1391         if (wm.level < VLV_WM_LEVEL_PM5 &&
1392             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1393                 chv_set_memory_pm5(dev_priv, false);
1394
1395         if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1396                 intel_set_memory_cxsr(dev_priv, false);
1397
1398         /* FIXME should be part of crtc atomic commit */
1399         vlv_pipe_set_fifo_size(intel_crtc);
1400
1401         vlv_write_wm_values(intel_crtc, &wm);
1402
1403         DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1404                       "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1405                       pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1406                       wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1407                       wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1408
1409         if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1410                 intel_set_memory_cxsr(dev_priv, true);
1411
1412         if (wm.level >= VLV_WM_LEVEL_PM5 &&
1413             dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1414                 chv_set_memory_pm5(dev_priv, true);
1415
1416         if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1417             dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1418                 chv_set_memory_dvfs(dev_priv, true);
1419
1420         dev_priv->wm.vlv = wm;
1421 }
1422
1423 #define single_plane_enabled(mask) is_power_of_2(mask)
1424
1425 static void g4x_update_wm(struct drm_crtc *crtc)
1426 {
1427         struct drm_device *dev = crtc->dev;
1428         static const int sr_latency_ns = 12000;
1429         struct drm_i915_private *dev_priv = dev->dev_private;
1430         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1431         int plane_sr, cursor_sr;
1432         unsigned int enabled = 0;
1433         bool cxsr_enabled;
1434
1435         if (g4x_compute_wm0(dev, PIPE_A,
1436                             &g4x_wm_info, pessimal_latency_ns,
1437                             &g4x_cursor_wm_info, pessimal_latency_ns,
1438                             &planea_wm, &cursora_wm))
1439                 enabled |= 1 << PIPE_A;
1440
1441         if (g4x_compute_wm0(dev, PIPE_B,
1442                             &g4x_wm_info, pessimal_latency_ns,
1443                             &g4x_cursor_wm_info, pessimal_latency_ns,
1444                             &planeb_wm, &cursorb_wm))
1445                 enabled |= 1 << PIPE_B;
1446
1447         if (single_plane_enabled(enabled) &&
1448             g4x_compute_srwm(dev, ffs(enabled) - 1,
1449                              sr_latency_ns,
1450                              &g4x_wm_info,
1451                              &g4x_cursor_wm_info,
1452                              &plane_sr, &cursor_sr)) {
1453                 cxsr_enabled = true;
1454         } else {
1455                 cxsr_enabled = false;
1456                 intel_set_memory_cxsr(dev_priv, false);
1457                 plane_sr = cursor_sr = 0;
1458         }
1459
1460         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1461                       "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1462                       planea_wm, cursora_wm,
1463                       planeb_wm, cursorb_wm,
1464                       plane_sr, cursor_sr);
1465
1466         I915_WRITE(DSPFW1,
1467                    FW_WM(plane_sr, SR) |
1468                    FW_WM(cursorb_wm, CURSORB) |
1469                    FW_WM(planeb_wm, PLANEB) |
1470                    FW_WM(planea_wm, PLANEA));
1471         I915_WRITE(DSPFW2,
1472                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1473                    FW_WM(cursora_wm, CURSORA));
1474         /* HPLL off in SR has some issues on G4x... disable it */
1475         I915_WRITE(DSPFW3,
1476                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1477                    FW_WM(cursor_sr, CURSOR_SR));
1478
1479         if (cxsr_enabled)
1480                 intel_set_memory_cxsr(dev_priv, true);
1481 }
1482
1483 static void i965_update_wm(struct drm_crtc *unused_crtc)
1484 {
1485         struct drm_device *dev = unused_crtc->dev;
1486         struct drm_i915_private *dev_priv = dev->dev_private;
1487         struct drm_crtc *crtc;
1488         int srwm = 1;
1489         int cursor_sr = 16;
1490         bool cxsr_enabled;
1491
1492         /* Calc sr entries for one plane configs */
1493         crtc = single_enabled_crtc(dev);
1494         if (crtc) {
1495                 /* self-refresh has much higher latency */
1496                 static const int sr_latency_ns = 12000;
1497                 const struct drm_display_mode *adjusted_mode =
1498                         &to_intel_crtc(crtc)->config->base.adjusted_mode;
1499                 int clock = adjusted_mode->crtc_clock;
1500                 int htotal = adjusted_mode->crtc_htotal;
1501                 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1502                 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
1503                 unsigned long line_time_us;
1504                 int entries;
1505
1506                 line_time_us = max(htotal * 1000 / clock, 1);
1507
1508                 /* Use ns/us then divide to preserve precision */
1509                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1510                         pixel_size * hdisplay;
1511                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1512                 srwm = I965_FIFO_SIZE - entries;
1513                 if (srwm < 0)
1514                         srwm = 1;
1515                 srwm &= 0x1ff;
1516                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1517                               entries, srwm);
1518
1519                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1520                         pixel_size * crtc->cursor->state->crtc_w;
1521                 entries = DIV_ROUND_UP(entries,
1522                                           i965_cursor_wm_info.cacheline_size);
1523                 cursor_sr = i965_cursor_wm_info.fifo_size -
1524                         (entries + i965_cursor_wm_info.guard_size);
1525
1526                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1527                         cursor_sr = i965_cursor_wm_info.max_wm;
1528
1529                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1530                               "cursor %d\n", srwm, cursor_sr);
1531
1532                 cxsr_enabled = true;
1533         } else {
1534                 cxsr_enabled = false;
1535                 /* Turn off self refresh if both pipes are enabled */
1536                 intel_set_memory_cxsr(dev_priv, false);
1537         }
1538
1539         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1540                       srwm);
1541
1542         /* 965 has limitations... */
1543         I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1544                    FW_WM(8, CURSORB) |
1545                    FW_WM(8, PLANEB) |
1546                    FW_WM(8, PLANEA));
1547         I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1548                    FW_WM(8, PLANEC_OLD));
1549         /* update cursor SR watermark */
1550         I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1551
1552         if (cxsr_enabled)
1553                 intel_set_memory_cxsr(dev_priv, true);
1554 }
1555
1556 #undef FW_WM
1557
1558 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1559 {
1560         struct drm_device *dev = unused_crtc->dev;
1561         struct drm_i915_private *dev_priv = dev->dev_private;
1562         const struct intel_watermark_params *wm_info;
1563         uint32_t fwater_lo;
1564         uint32_t fwater_hi;
1565         int cwm, srwm = 1;
1566         int fifo_size;
1567         int planea_wm, planeb_wm;
1568         struct drm_crtc *crtc, *enabled = NULL;
1569
1570         if (IS_I945GM(dev))
1571                 wm_info = &i945_wm_info;
1572         else if (!IS_GEN2(dev))
1573                 wm_info = &i915_wm_info;
1574         else
1575                 wm_info = &i830_a_wm_info;
1576
1577         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1578         crtc = intel_get_crtc_for_plane(dev, 0);
1579         if (intel_crtc_active(crtc)) {
1580                 const struct drm_display_mode *adjusted_mode;
1581                 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1582                 if (IS_GEN2(dev))
1583                         cpp = 4;
1584
1585                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1586                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1587                                                wm_info, fifo_size, cpp,
1588                                                pessimal_latency_ns);
1589                 enabled = crtc;
1590         } else {
1591                 planea_wm = fifo_size - wm_info->guard_size;
1592                 if (planea_wm > (long)wm_info->max_wm)
1593                         planea_wm = wm_info->max_wm;
1594         }
1595
1596         if (IS_GEN2(dev))
1597                 wm_info = &i830_bc_wm_info;
1598
1599         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1600         crtc = intel_get_crtc_for_plane(dev, 1);
1601         if (intel_crtc_active(crtc)) {
1602                 const struct drm_display_mode *adjusted_mode;
1603                 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1604                 if (IS_GEN2(dev))
1605                         cpp = 4;
1606
1607                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1608                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1609                                                wm_info, fifo_size, cpp,
1610                                                pessimal_latency_ns);
1611                 if (enabled == NULL)
1612                         enabled = crtc;
1613                 else
1614                         enabled = NULL;
1615         } else {
1616                 planeb_wm = fifo_size - wm_info->guard_size;
1617                 if (planeb_wm > (long)wm_info->max_wm)
1618                         planeb_wm = wm_info->max_wm;
1619         }
1620
1621         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1622
1623         if (IS_I915GM(dev) && enabled) {
1624                 struct drm_i915_gem_object *obj;
1625
1626                 obj = intel_fb_obj(enabled->primary->state->fb);
1627
1628                 /* self-refresh seems busted with untiled */
1629                 if (obj->tiling_mode == I915_TILING_NONE)
1630                         enabled = NULL;
1631         }
1632
1633         /*
1634          * Overlay gets an aggressive default since video jitter is bad.
1635          */
1636         cwm = 2;
1637
1638         /* Play safe and disable self-refresh before adjusting watermarks. */
1639         intel_set_memory_cxsr(dev_priv, false);
1640
1641         /* Calc sr entries for one plane configs */
1642         if (HAS_FW_BLC(dev) && enabled) {
1643                 /* self-refresh has much higher latency */
1644                 static const int sr_latency_ns = 6000;
1645                 const struct drm_display_mode *adjusted_mode =
1646                         &to_intel_crtc(enabled)->config->base.adjusted_mode;
1647                 int clock = adjusted_mode->crtc_clock;
1648                 int htotal = adjusted_mode->crtc_htotal;
1649                 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1650                 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
1651                 unsigned long line_time_us;
1652                 int entries;
1653
1654                 line_time_us = max(htotal * 1000 / clock, 1);
1655
1656                 /* Use ns/us then divide to preserve precision */
1657                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1658                         pixel_size * hdisplay;
1659                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1660                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1661                 srwm = wm_info->fifo_size - entries;
1662                 if (srwm < 0)
1663                         srwm = 1;
1664
1665                 if (IS_I945G(dev) || IS_I945GM(dev))
1666                         I915_WRITE(FW_BLC_SELF,
1667                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1668                 else if (IS_I915GM(dev))
1669                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1670         }
1671
1672         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1673                       planea_wm, planeb_wm, cwm, srwm);
1674
1675         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1676         fwater_hi = (cwm & 0x1f);
1677
1678         /* Set request length to 8 cachelines per fetch */
1679         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1680         fwater_hi = fwater_hi | (1 << 8);
1681
1682         I915_WRITE(FW_BLC, fwater_lo);
1683         I915_WRITE(FW_BLC2, fwater_hi);
1684
1685         if (enabled)
1686                 intel_set_memory_cxsr(dev_priv, true);
1687 }
1688
1689 static void i845_update_wm(struct drm_crtc *unused_crtc)
1690 {
1691         struct drm_device *dev = unused_crtc->dev;
1692         struct drm_i915_private *dev_priv = dev->dev_private;
1693         struct drm_crtc *crtc;
1694         const struct drm_display_mode *adjusted_mode;
1695         uint32_t fwater_lo;
1696         int planea_wm;
1697
1698         crtc = single_enabled_crtc(dev);
1699         if (crtc == NULL)
1700                 return;
1701
1702         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1703         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1704                                        &i845_wm_info,
1705                                        dev_priv->display.get_fifo_size(dev, 0),
1706                                        4, pessimal_latency_ns);
1707         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1708         fwater_lo |= (3<<8) | planea_wm;
1709
1710         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1711
1712         I915_WRITE(FW_BLC, fwater_lo);
1713 }
1714
1715 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1716 {
1717         uint32_t pixel_rate;
1718
1719         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1720
1721         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1722          * adjust the pixel_rate here. */
1723
1724         if (pipe_config->pch_pfit.enabled) {
1725                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1726                 uint32_t pfit_size = pipe_config->pch_pfit.size;
1727
1728                 pipe_w = pipe_config->pipe_src_w;
1729                 pipe_h = pipe_config->pipe_src_h;
1730
1731                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1732                 pfit_h = pfit_size & 0xFFFF;
1733                 if (pipe_w < pfit_w)
1734                         pipe_w = pfit_w;
1735                 if (pipe_h < pfit_h)
1736                         pipe_h = pfit_h;
1737
1738                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1739                                      pfit_w * pfit_h);
1740         }
1741
1742         return pixel_rate;
1743 }
1744
1745 /* latency must be in 0.1us units. */
1746 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1747                                uint32_t latency)
1748 {
1749         uint64_t ret;
1750
1751         if (WARN(latency == 0, "Latency value missing\n"))
1752                 return UINT_MAX;
1753
1754         ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1755         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1756
1757         return ret;
1758 }
1759
1760 /* latency must be in 0.1us units. */
1761 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1762                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1763                                uint32_t latency)
1764 {
1765         uint32_t ret;
1766
1767         if (WARN(latency == 0, "Latency value missing\n"))
1768                 return UINT_MAX;
1769
1770         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1771         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1772         ret = DIV_ROUND_UP(ret, 64) + 2;
1773         return ret;
1774 }
1775
1776 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1777                            uint8_t bytes_per_pixel)
1778 {
1779         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1780 }
1781
1782 struct skl_pipe_wm_parameters {
1783         bool active;
1784         uint32_t pipe_htotal;
1785         uint32_t pixel_rate; /* in KHz */
1786         struct intel_plane_wm_parameters plane[I915_MAX_PLANES];
1787         struct intel_plane_wm_parameters cursor;
1788 };
1789
1790 struct ilk_pipe_wm_parameters {
1791         bool active;
1792         uint32_t pipe_htotal;
1793         uint32_t pixel_rate;
1794         struct intel_plane_wm_parameters pri;
1795         struct intel_plane_wm_parameters spr;
1796         struct intel_plane_wm_parameters cur;
1797 };
1798
1799 struct ilk_wm_maximums {
1800         uint16_t pri;
1801         uint16_t spr;
1802         uint16_t cur;
1803         uint16_t fbc;
1804 };
1805
1806 /* used in computing the new watermarks state */
1807 struct intel_wm_config {
1808         unsigned int num_pipes_active;
1809         bool sprites_enabled;
1810         bool sprites_scaled;
1811 };
1812
1813 /*
1814  * For both WM_PIPE and WM_LP.
1815  * mem_value must be in 0.1us units.
1816  */
1817 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
1818                                    uint32_t mem_value,
1819                                    bool is_lp)
1820 {
1821         uint32_t method1, method2;
1822
1823         if (!params->active || !params->pri.enabled)
1824                 return 0;
1825
1826         method1 = ilk_wm_method1(params->pixel_rate,
1827                                  params->pri.bytes_per_pixel,
1828                                  mem_value);
1829
1830         if (!is_lp)
1831                 return method1;
1832
1833         method2 = ilk_wm_method2(params->pixel_rate,
1834                                  params->pipe_htotal,
1835                                  params->pri.horiz_pixels,
1836                                  params->pri.bytes_per_pixel,
1837                                  mem_value);
1838
1839         return min(method1, method2);
1840 }
1841
1842 /*
1843  * For both WM_PIPE and WM_LP.
1844  * mem_value must be in 0.1us units.
1845  */
1846 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
1847                                    uint32_t mem_value)
1848 {
1849         uint32_t method1, method2;
1850
1851         if (!params->active || !params->spr.enabled)
1852                 return 0;
1853
1854         method1 = ilk_wm_method1(params->pixel_rate,
1855                                  params->spr.bytes_per_pixel,
1856                                  mem_value);
1857         method2 = ilk_wm_method2(params->pixel_rate,
1858                                  params->pipe_htotal,
1859                                  params->spr.horiz_pixels,
1860                                  params->spr.bytes_per_pixel,
1861                                  mem_value);
1862         return min(method1, method2);
1863 }
1864
1865 /*
1866  * For both WM_PIPE and WM_LP.
1867  * mem_value must be in 0.1us units.
1868  */
1869 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
1870                                    uint32_t mem_value)
1871 {
1872         if (!params->active || !params->cur.enabled)
1873                 return 0;
1874
1875         return ilk_wm_method2(params->pixel_rate,
1876                               params->pipe_htotal,
1877                               params->cur.horiz_pixels,
1878                               params->cur.bytes_per_pixel,
1879                               mem_value);
1880 }
1881
1882 /* Only for WM_LP. */
1883 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1884                                    uint32_t pri_val)
1885 {
1886         if (!params->active || !params->pri.enabled)
1887                 return 0;
1888
1889         return ilk_wm_fbc(pri_val,
1890                           params->pri.horiz_pixels,
1891                           params->pri.bytes_per_pixel);
1892 }
1893
1894 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1895 {
1896         if (INTEL_INFO(dev)->gen >= 8)
1897                 return 3072;
1898         else if (INTEL_INFO(dev)->gen >= 7)
1899                 return 768;
1900         else
1901                 return 512;
1902 }
1903
1904 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1905                                          int level, bool is_sprite)
1906 {
1907         if (INTEL_INFO(dev)->gen >= 8)
1908                 /* BDW primary/sprite plane watermarks */
1909                 return level == 0 ? 255 : 2047;
1910         else if (INTEL_INFO(dev)->gen >= 7)
1911                 /* IVB/HSW primary/sprite plane watermarks */
1912                 return level == 0 ? 127 : 1023;
1913         else if (!is_sprite)
1914                 /* ILK/SNB primary plane watermarks */
1915                 return level == 0 ? 127 : 511;
1916         else
1917                 /* ILK/SNB sprite plane watermarks */
1918                 return level == 0 ? 63 : 255;
1919 }
1920
1921 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1922                                           int level)
1923 {
1924         if (INTEL_INFO(dev)->gen >= 7)
1925                 return level == 0 ? 63 : 255;
1926         else
1927                 return level == 0 ? 31 : 63;
1928 }
1929
1930 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1931 {
1932         if (INTEL_INFO(dev)->gen >= 8)
1933                 return 31;
1934         else
1935                 return 15;
1936 }
1937
1938 /* Calculate the maximum primary/sprite plane watermark */
1939 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1940                                      int level,
1941                                      const struct intel_wm_config *config,
1942                                      enum intel_ddb_partitioning ddb_partitioning,
1943                                      bool is_sprite)
1944 {
1945         unsigned int fifo_size = ilk_display_fifo_size(dev);
1946
1947         /* if sprites aren't enabled, sprites get nothing */
1948         if (is_sprite && !config->sprites_enabled)
1949                 return 0;
1950
1951         /* HSW allows LP1+ watermarks even with multiple pipes */
1952         if (level == 0 || config->num_pipes_active > 1) {
1953                 fifo_size /= INTEL_INFO(dev)->num_pipes;
1954
1955                 /*
1956                  * For some reason the non self refresh
1957                  * FIFO size is only half of the self
1958                  * refresh FIFO size on ILK/SNB.
1959                  */
1960                 if (INTEL_INFO(dev)->gen <= 6)
1961                         fifo_size /= 2;
1962         }
1963
1964         if (config->sprites_enabled) {
1965                 /* level 0 is always calculated with 1:1 split */
1966                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1967                         if (is_sprite)
1968                                 fifo_size *= 5;
1969                         fifo_size /= 6;
1970                 } else {
1971                         fifo_size /= 2;
1972                 }
1973         }
1974
1975         /* clamp to max that the registers can hold */
1976         return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1977 }
1978
1979 /* Calculate the maximum cursor plane watermark */
1980 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1981                                       int level,
1982                                       const struct intel_wm_config *config)
1983 {
1984         /* HSW LP1+ watermarks w/ multiple pipes */
1985         if (level > 0 && config->num_pipes_active > 1)
1986                 return 64;
1987
1988         /* otherwise just report max that registers can hold */
1989         return ilk_cursor_wm_reg_max(dev, level);
1990 }
1991
1992 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1993                                     int level,
1994                                     const struct intel_wm_config *config,
1995                                     enum intel_ddb_partitioning ddb_partitioning,
1996                                     struct ilk_wm_maximums *max)
1997 {
1998         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1999         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2000         max->cur = ilk_cursor_wm_max(dev, level, config);
2001         max->fbc = ilk_fbc_wm_reg_max(dev);
2002 }
2003
2004 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
2005                                         int level,
2006                                         struct ilk_wm_maximums *max)
2007 {
2008         max->pri = ilk_plane_wm_reg_max(dev, level, false);
2009         max->spr = ilk_plane_wm_reg_max(dev, level, true);
2010         max->cur = ilk_cursor_wm_reg_max(dev, level);
2011         max->fbc = ilk_fbc_wm_reg_max(dev);
2012 }
2013
2014 static bool ilk_validate_wm_level(int level,
2015                                   const struct ilk_wm_maximums *max,
2016                                   struct intel_wm_level *result)
2017 {
2018         bool ret;
2019
2020         /* already determined to be invalid? */
2021         if (!result->enable)
2022                 return false;
2023
2024         result->enable = result->pri_val <= max->pri &&
2025                          result->spr_val <= max->spr &&
2026                          result->cur_val <= max->cur;
2027
2028         ret = result->enable;
2029
2030         /*
2031          * HACK until we can pre-compute everything,
2032          * and thus fail gracefully if LP0 watermarks
2033          * are exceeded...
2034          */
2035         if (level == 0 && !result->enable) {
2036                 if (result->pri_val > max->pri)
2037                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2038                                       level, result->pri_val, max->pri);
2039                 if (result->spr_val > max->spr)
2040                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2041                                       level, result->spr_val, max->spr);
2042                 if (result->cur_val > max->cur)
2043                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2044                                       level, result->cur_val, max->cur);
2045
2046                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2047                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2048                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2049                 result->enable = true;
2050         }
2051
2052         return ret;
2053 }
2054
2055 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2056                                  int level,
2057                                  const struct ilk_pipe_wm_parameters *p,
2058                                  struct intel_wm_level *result)
2059 {
2060         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2061         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2062         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2063
2064         /* WM1+ latency values stored in 0.5us units */
2065         if (level > 0) {
2066                 pri_latency *= 5;
2067                 spr_latency *= 5;
2068                 cur_latency *= 5;
2069         }
2070
2071         result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2072         result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2073         result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2074         result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2075         result->enable = true;
2076 }
2077
2078 static uint32_t
2079 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2080 {
2081         struct drm_i915_private *dev_priv = dev->dev_private;
2082         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2083         struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
2084         u32 linetime, ips_linetime;
2085
2086         if (!intel_crtc->active)
2087                 return 0;
2088
2089         /* The WM are computed with base on how long it takes to fill a single
2090          * row at the given clock rate, multiplied by 8.
2091          * */
2092         linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2093                                      mode->crtc_clock);
2094         ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2095                                          dev_priv->cdclk_freq);
2096
2097         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2098                PIPE_WM_LINETIME_TIME(linetime);
2099 }
2100
2101 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2102 {
2103         struct drm_i915_private *dev_priv = dev->dev_private;
2104
2105         if (IS_GEN9(dev)) {
2106                 uint32_t val;
2107                 int ret, i;
2108                 int level, max_level = ilk_wm_max_level(dev);
2109
2110                 /* read the first set of memory latencies[0:3] */
2111                 val = 0; /* data0 to be programmed to 0 for first set */
2112                 mutex_lock(&dev_priv->rps.hw_lock);
2113                 ret = sandybridge_pcode_read(dev_priv,
2114                                              GEN9_PCODE_READ_MEM_LATENCY,
2115                                              &val);
2116                 mutex_unlock(&dev_priv->rps.hw_lock);
2117
2118                 if (ret) {
2119                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2120                         return;
2121                 }
2122
2123                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2124                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2125                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2126                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2127                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2128                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2129                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2130
2131                 /* read the second set of memory latencies[4:7] */
2132                 val = 1; /* data0 to be programmed to 1 for second set */
2133                 mutex_lock(&dev_priv->rps.hw_lock);
2134                 ret = sandybridge_pcode_read(dev_priv,
2135                                              GEN9_PCODE_READ_MEM_LATENCY,
2136                                              &val);
2137                 mutex_unlock(&dev_priv->rps.hw_lock);
2138                 if (ret) {
2139                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2140                         return;
2141                 }
2142
2143                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2144                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2145                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2146                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2147                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2148                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2149                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2150
2151                 /*
2152                  * WaWmMemoryReadLatency:skl
2153                  *
2154                  * punit doesn't take into account the read latency so we need
2155                  * to add 2us to the various latency levels we retrieve from
2156                  * the punit.
2157                  *   - W0 is a bit special in that it's the only level that
2158                  *   can't be disabled if we want to have display working, so
2159                  *   we always add 2us there.
2160                  *   - For levels >=1, punit returns 0us latency when they are
2161                  *   disabled, so we respect that and don't add 2us then
2162                  *
2163                  * Additionally, if a level n (n > 1) has a 0us latency, all
2164                  * levels m (m >= n) need to be disabled. We make sure to
2165                  * sanitize the values out of the punit to satisfy this
2166                  * requirement.
2167                  */
2168                 wm[0] += 2;
2169                 for (level = 1; level <= max_level; level++)
2170                         if (wm[level] != 0)
2171                                 wm[level] += 2;
2172                         else {
2173                                 for (i = level + 1; i <= max_level; i++)
2174                                         wm[i] = 0;
2175
2176                                 break;
2177                         }
2178         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2179                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2180
2181                 wm[0] = (sskpd >> 56) & 0xFF;
2182                 if (wm[0] == 0)
2183                         wm[0] = sskpd & 0xF;
2184                 wm[1] = (sskpd >> 4) & 0xFF;
2185                 wm[2] = (sskpd >> 12) & 0xFF;
2186                 wm[3] = (sskpd >> 20) & 0x1FF;
2187                 wm[4] = (sskpd >> 32) & 0x1FF;
2188         } else if (INTEL_INFO(dev)->gen >= 6) {
2189                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2190
2191                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2192                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2193                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2194                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2195         } else if (INTEL_INFO(dev)->gen >= 5) {
2196                 uint32_t mltr = I915_READ(MLTR_ILK);
2197
2198                 /* ILK primary LP0 latency is 700 ns */
2199                 wm[0] = 7;
2200                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2201                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2202         }
2203 }
2204
2205 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2206 {
2207         /* ILK sprite LP0 latency is 1300 ns */
2208         if (INTEL_INFO(dev)->gen == 5)
2209                 wm[0] = 13;
2210 }
2211
2212 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2213 {
2214         /* ILK cursor LP0 latency is 1300 ns */
2215         if (INTEL_INFO(dev)->gen == 5)
2216                 wm[0] = 13;
2217
2218         /* WaDoubleCursorLP3Latency:ivb */
2219         if (IS_IVYBRIDGE(dev))
2220                 wm[3] *= 2;
2221 }
2222
2223 int ilk_wm_max_level(const struct drm_device *dev)
2224 {
2225         /* how many WM levels are we expecting */
2226         if (INTEL_INFO(dev)->gen >= 9)
2227                 return 7;
2228         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2229                 return 4;
2230         else if (INTEL_INFO(dev)->gen >= 6)
2231                 return 3;
2232         else
2233                 return 2;
2234 }
2235
2236 static void intel_print_wm_latency(struct drm_device *dev,
2237                                    const char *name,
2238                                    const uint16_t wm[8])
2239 {
2240         int level, max_level = ilk_wm_max_level(dev);
2241
2242         for (level = 0; level <= max_level; level++) {
2243                 unsigned int latency = wm[level];
2244
2245                 if (latency == 0) {
2246                         DRM_ERROR("%s WM%d latency not provided\n",
2247                                   name, level);
2248                         continue;
2249                 }
2250
2251                 /*
2252                  * - latencies are in us on gen9.
2253                  * - before then, WM1+ latency values are in 0.5us units
2254                  */
2255                 if (IS_GEN9(dev))
2256                         latency *= 10;
2257                 else if (level > 0)
2258                         latency *= 5;
2259
2260                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2261                               name, level, wm[level],
2262                               latency / 10, latency % 10);
2263         }
2264 }
2265
2266 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2267                                     uint16_t wm[5], uint16_t min)
2268 {
2269         int level, max_level = ilk_wm_max_level(dev_priv->dev);
2270
2271         if (wm[0] >= min)
2272                 return false;
2273
2274         wm[0] = max(wm[0], min);
2275         for (level = 1; level <= max_level; level++)
2276                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2277
2278         return true;
2279 }
2280
2281 static void snb_wm_latency_quirk(struct drm_device *dev)
2282 {
2283         struct drm_i915_private *dev_priv = dev->dev_private;
2284         bool changed;
2285
2286         /*
2287          * The BIOS provided WM memory latency values are often
2288          * inadequate for high resolution displays. Adjust them.
2289          */
2290         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2291                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2292                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2293
2294         if (!changed)
2295                 return;
2296
2297         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2298         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2299         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2300         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2301 }
2302
2303 static void ilk_setup_wm_latency(struct drm_device *dev)
2304 {
2305         struct drm_i915_private *dev_priv = dev->dev_private;
2306
2307         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2308
2309         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2310                sizeof(dev_priv->wm.pri_latency));
2311         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2312                sizeof(dev_priv->wm.pri_latency));
2313
2314         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2315         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2316
2317         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2318         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2319         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2320
2321         if (IS_GEN6(dev))
2322                 snb_wm_latency_quirk(dev);
2323 }
2324
2325 static void skl_setup_wm_latency(struct drm_device *dev)
2326 {
2327         struct drm_i915_private *dev_priv = dev->dev_private;
2328
2329         intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2330         intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2331 }
2332
2333 static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2334                                       struct ilk_pipe_wm_parameters *p)
2335 {
2336         struct drm_device *dev = crtc->dev;
2337         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2338         enum pipe pipe = intel_crtc->pipe;
2339         struct drm_plane *plane;
2340
2341         if (!intel_crtc->active)
2342                 return;
2343
2344         p->active = true;
2345         p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
2346         p->pixel_rate = ilk_pipe_pixel_rate(intel_crtc->config);
2347
2348         if (crtc->primary->state->fb)
2349                 p->pri.bytes_per_pixel =
2350                         crtc->primary->state->fb->bits_per_pixel / 8;
2351         else
2352                 p->pri.bytes_per_pixel = 4;
2353
2354         p->cur.bytes_per_pixel = 4;
2355         /*
2356          * TODO: for now, assume primary and cursor planes are always enabled.
2357          * Setting them to false makes the screen flicker.
2358          */
2359         p->pri.enabled = true;
2360         p->cur.enabled = true;
2361
2362         p->pri.horiz_pixels = intel_crtc->config->pipe_src_w;
2363         p->cur.horiz_pixels = intel_crtc->base.cursor->state->crtc_w;
2364
2365         drm_for_each_legacy_plane(plane, dev) {
2366                 struct intel_plane *intel_plane = to_intel_plane(plane);
2367
2368                 if (intel_plane->pipe == pipe) {
2369                         p->spr = intel_plane->wm;
2370                         break;
2371                 }
2372         }
2373 }
2374
2375 static void ilk_compute_wm_config(struct drm_device *dev,
2376                                   struct intel_wm_config *config)
2377 {
2378         struct intel_crtc *intel_crtc;
2379
2380         /* Compute the currently _active_ config */
2381         for_each_intel_crtc(dev, intel_crtc) {
2382                 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
2383
2384                 if (!wm->pipe_enabled)
2385                         continue;
2386
2387                 config->sprites_enabled |= wm->sprites_enabled;
2388                 config->sprites_scaled |= wm->sprites_scaled;
2389                 config->num_pipes_active++;
2390         }
2391 }
2392
2393 /* Compute new watermarks for the pipe */
2394 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2395                                   const struct ilk_pipe_wm_parameters *params,
2396                                   struct intel_pipe_wm *pipe_wm)
2397 {
2398         struct drm_device *dev = crtc->dev;
2399         const struct drm_i915_private *dev_priv = dev->dev_private;
2400         int level, max_level = ilk_wm_max_level(dev);
2401         /* LP0 watermark maximums depend on this pipe alone */
2402         struct intel_wm_config config = {
2403                 .num_pipes_active = 1,
2404                 .sprites_enabled = params->spr.enabled,
2405                 .sprites_scaled = params->spr.scaled,
2406         };
2407         struct ilk_wm_maximums max;
2408
2409         pipe_wm->pipe_enabled = params->active;
2410         pipe_wm->sprites_enabled = params->spr.enabled;
2411         pipe_wm->sprites_scaled = params->spr.scaled;
2412
2413         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2414         if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2415                 max_level = 1;
2416
2417         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2418         if (params->spr.scaled)
2419                 max_level = 0;
2420
2421         ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
2422
2423         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2424                 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2425
2426         /* LP0 watermarks always use 1/2 DDB partitioning */
2427         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2428
2429         /* At least LP0 must be valid */
2430         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2431                 return false;
2432
2433         ilk_compute_wm_reg_maximums(dev, 1, &max);
2434
2435         for (level = 1; level <= max_level; level++) {
2436                 struct intel_wm_level wm = {};
2437
2438                 ilk_compute_wm_level(dev_priv, level, params, &wm);
2439
2440                 /*
2441                  * Disable any watermark level that exceeds the
2442                  * register maximums since such watermarks are
2443                  * always invalid.
2444                  */
2445                 if (!ilk_validate_wm_level(level, &max, &wm))
2446                         break;
2447
2448                 pipe_wm->wm[level] = wm;
2449         }
2450
2451         return true;
2452 }
2453
2454 /*
2455  * Merge the watermarks from all active pipes for a specific level.
2456  */
2457 static void ilk_merge_wm_level(struct drm_device *dev,
2458                                int level,
2459                                struct intel_wm_level *ret_wm)
2460 {
2461         const struct intel_crtc *intel_crtc;
2462
2463         ret_wm->enable = true;
2464
2465         for_each_intel_crtc(dev, intel_crtc) {
2466                 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2467                 const struct intel_wm_level *wm = &active->wm[level];
2468
2469                 if (!active->pipe_enabled)
2470                         continue;
2471
2472                 /*
2473                  * The watermark values may have been used in the past,
2474                  * so we must maintain them in the registers for some
2475                  * time even if the level is now disabled.
2476                  */
2477                 if (!wm->enable)
2478                         ret_wm->enable = false;
2479
2480                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2481                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2482                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2483                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2484         }
2485 }
2486
2487 /*
2488  * Merge all low power watermarks for all active pipes.
2489  */
2490 static void ilk_wm_merge(struct drm_device *dev,
2491                          const struct intel_wm_config *config,
2492                          const struct ilk_wm_maximums *max,
2493                          struct intel_pipe_wm *merged)
2494 {
2495         struct drm_i915_private *dev_priv = dev->dev_private;
2496         int level, max_level = ilk_wm_max_level(dev);
2497         int last_enabled_level = max_level;
2498
2499         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2500         if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2501             config->num_pipes_active > 1)
2502                 return;
2503
2504         /* ILK: FBC WM must be disabled always */
2505         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2506
2507         /* merge each WM1+ level */
2508         for (level = 1; level <= max_level; level++) {
2509                 struct intel_wm_level *wm = &merged->wm[level];
2510
2511                 ilk_merge_wm_level(dev, level, wm);
2512
2513                 if (level > last_enabled_level)
2514                         wm->enable = false;
2515                 else if (!ilk_validate_wm_level(level, max, wm))
2516                         /* make sure all following levels get disabled */
2517                         last_enabled_level = level - 1;
2518
2519                 /*
2520                  * The spec says it is preferred to disable
2521                  * FBC WMs instead of disabling a WM level.
2522                  */
2523                 if (wm->fbc_val > max->fbc) {
2524                         if (wm->enable)
2525                                 merged->fbc_wm_enabled = false;
2526                         wm->fbc_val = 0;
2527                 }
2528         }
2529
2530         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2531         /*
2532          * FIXME this is racy. FBC might get enabled later.
2533          * What we should check here is whether FBC can be
2534          * enabled sometime later.
2535          */
2536         if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2537             intel_fbc_enabled(dev_priv)) {
2538                 for (level = 2; level <= max_level; level++) {
2539                         struct intel_wm_level *wm = &merged->wm[level];
2540
2541                         wm->enable = false;
2542                 }
2543         }
2544 }
2545
2546 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2547 {
2548         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2549         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2550 }
2551
2552 /* The value we need to program into the WM_LPx latency field */
2553 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2554 {
2555         struct drm_i915_private *dev_priv = dev->dev_private;
2556
2557         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2558                 return 2 * level;
2559         else
2560                 return dev_priv->wm.pri_latency[level];
2561 }
2562
2563 static void ilk_compute_wm_results(struct drm_device *dev,
2564                                    const struct intel_pipe_wm *merged,
2565                                    enum intel_ddb_partitioning partitioning,
2566                                    struct ilk_wm_values *results)
2567 {
2568         struct intel_crtc *intel_crtc;
2569         int level, wm_lp;
2570
2571         results->enable_fbc_wm = merged->fbc_wm_enabled;
2572         results->partitioning = partitioning;
2573
2574         /* LP1+ register values */
2575         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2576                 const struct intel_wm_level *r;
2577
2578                 level = ilk_wm_lp_to_level(wm_lp, merged);
2579
2580                 r = &merged->wm[level];
2581
2582                 /*
2583                  * Maintain the watermark values even if the level is
2584                  * disabled. Doing otherwise could cause underruns.
2585                  */
2586                 results->wm_lp[wm_lp - 1] =
2587                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2588                         (r->pri_val << WM1_LP_SR_SHIFT) |
2589                         r->cur_val;
2590
2591                 if (r->enable)
2592                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2593
2594                 if (INTEL_INFO(dev)->gen >= 8)
2595                         results->wm_lp[wm_lp - 1] |=
2596                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2597                 else
2598                         results->wm_lp[wm_lp - 1] |=
2599                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2600
2601                 /*
2602                  * Always set WM1S_LP_EN when spr_val != 0, even if the
2603                  * level is disabled. Doing otherwise could cause underruns.
2604                  */
2605                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2606                         WARN_ON(wm_lp != 1);
2607                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2608                 } else
2609                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2610         }
2611
2612         /* LP0 register values */
2613         for_each_intel_crtc(dev, intel_crtc) {
2614                 enum pipe pipe = intel_crtc->pipe;
2615                 const struct intel_wm_level *r =
2616                         &intel_crtc->wm.active.wm[0];
2617
2618                 if (WARN_ON(!r->enable))
2619                         continue;
2620
2621                 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2622
2623                 results->wm_pipe[pipe] =
2624                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2625                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2626                         r->cur_val;
2627         }
2628 }
2629
2630 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2631  * case both are at the same level. Prefer r1 in case they're the same. */
2632 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2633                                                   struct intel_pipe_wm *r1,
2634                                                   struct intel_pipe_wm *r2)
2635 {
2636         int level, max_level = ilk_wm_max_level(dev);
2637         int level1 = 0, level2 = 0;
2638
2639         for (level = 1; level <= max_level; level++) {
2640                 if (r1->wm[level].enable)
2641                         level1 = level;
2642                 if (r2->wm[level].enable)
2643                         level2 = level;
2644         }
2645
2646         if (level1 == level2) {
2647                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2648                         return r2;
2649                 else
2650                         return r1;
2651         } else if (level1 > level2) {
2652                 return r1;
2653         } else {
2654                 return r2;
2655         }
2656 }
2657
2658 /* dirty bits used to track which watermarks need changes */
2659 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2660 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2661 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2662 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2663 #define WM_DIRTY_FBC (1 << 24)
2664 #define WM_DIRTY_DDB (1 << 25)
2665
2666 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2667                                          const struct ilk_wm_values *old,
2668                                          const struct ilk_wm_values *new)
2669 {
2670         unsigned int dirty = 0;
2671         enum pipe pipe;
2672         int wm_lp;
2673
2674         for_each_pipe(dev_priv, pipe) {
2675                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2676                         dirty |= WM_DIRTY_LINETIME(pipe);
2677                         /* Must disable LP1+ watermarks too */
2678                         dirty |= WM_DIRTY_LP_ALL;
2679                 }
2680
2681                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2682                         dirty |= WM_DIRTY_PIPE(pipe);
2683                         /* Must disable LP1+ watermarks too */
2684                         dirty |= WM_DIRTY_LP_ALL;
2685                 }
2686         }
2687
2688         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2689                 dirty |= WM_DIRTY_FBC;
2690                 /* Must disable LP1+ watermarks too */
2691                 dirty |= WM_DIRTY_LP_ALL;
2692         }
2693
2694         if (old->partitioning != new->partitioning) {
2695                 dirty |= WM_DIRTY_DDB;
2696                 /* Must disable LP1+ watermarks too */
2697                 dirty |= WM_DIRTY_LP_ALL;
2698         }
2699
2700         /* LP1+ watermarks already deemed dirty, no need to continue */
2701         if (dirty & WM_DIRTY_LP_ALL)
2702                 return dirty;
2703
2704         /* Find the lowest numbered LP1+ watermark in need of an update... */
2705         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2706                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2707                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2708                         break;
2709         }
2710
2711         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2712         for (; wm_lp <= 3; wm_lp++)
2713                 dirty |= WM_DIRTY_LP(wm_lp);
2714
2715         return dirty;
2716 }
2717
2718 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2719                                unsigned int dirty)
2720 {
2721         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2722         bool changed = false;
2723
2724         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2725                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2726                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2727                 changed = true;
2728         }
2729         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2730                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2731                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2732                 changed = true;
2733         }
2734         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2735                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2736                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2737                 changed = true;
2738         }
2739
2740         /*
2741          * Don't touch WM1S_LP_EN here.
2742          * Doing so could cause underruns.
2743          */
2744
2745         return changed;
2746 }
2747
2748 /*
2749  * The spec says we shouldn't write when we don't need, because every write
2750  * causes WMs to be re-evaluated, expending some power.
2751  */
2752 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2753                                 struct ilk_wm_values *results)
2754 {
2755         struct drm_device *dev = dev_priv->dev;
2756         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2757         unsigned int dirty;
2758         uint32_t val;
2759
2760         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2761         if (!dirty)
2762                 return;
2763
2764         _ilk_disable_lp_wm(dev_priv, dirty);
2765
2766         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2767                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2768         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2769                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2770         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2771                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2772
2773         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2774                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2775         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2776                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2777         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2778                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2779
2780         if (dirty & WM_DIRTY_DDB) {
2781                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2782                         val = I915_READ(WM_MISC);
2783                         if (results->partitioning == INTEL_DDB_PART_1_2)
2784                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2785                         else
2786                                 val |= WM_MISC_DATA_PARTITION_5_6;
2787                         I915_WRITE(WM_MISC, val);
2788                 } else {
2789                         val = I915_READ(DISP_ARB_CTL2);
2790                         if (results->partitioning == INTEL_DDB_PART_1_2)
2791                                 val &= ~DISP_DATA_PARTITION_5_6;
2792                         else
2793                                 val |= DISP_DATA_PARTITION_5_6;
2794                         I915_WRITE(DISP_ARB_CTL2, val);
2795                 }
2796         }
2797
2798         if (dirty & WM_DIRTY_FBC) {
2799                 val = I915_READ(DISP_ARB_CTL);
2800                 if (results->enable_fbc_wm)
2801                         val &= ~DISP_FBC_WM_DIS;
2802                 else
2803                         val |= DISP_FBC_WM_DIS;
2804                 I915_WRITE(DISP_ARB_CTL, val);
2805         }
2806
2807         if (dirty & WM_DIRTY_LP(1) &&
2808             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2809                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2810
2811         if (INTEL_INFO(dev)->gen >= 7) {
2812                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2813                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2814                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2815                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2816         }
2817
2818         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2819                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2820         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2821                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2822         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2823                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2824
2825         dev_priv->wm.hw = *results;
2826 }
2827
2828 static bool ilk_disable_lp_wm(struct drm_device *dev)
2829 {
2830         struct drm_i915_private *dev_priv = dev->dev_private;
2831
2832         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2833 }
2834
2835 /*
2836  * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2837  * different active planes.
2838  */
2839
2840 #define SKL_DDB_SIZE            896     /* in blocks */
2841 #define BXT_DDB_SIZE            512
2842
2843 static void
2844 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2845                                    struct drm_crtc *for_crtc,
2846                                    const struct intel_wm_config *config,
2847                                    const struct skl_pipe_wm_parameters *params,
2848                                    struct skl_ddb_entry *alloc /* out */)
2849 {
2850         struct drm_crtc *crtc;
2851         unsigned int pipe_size, ddb_size;
2852         int nth_active_pipe;
2853
2854         if (!params->active) {
2855                 alloc->start = 0;
2856                 alloc->end = 0;
2857                 return;
2858         }
2859
2860         if (IS_BROXTON(dev))
2861                 ddb_size = BXT_DDB_SIZE;
2862         else
2863                 ddb_size = SKL_DDB_SIZE;
2864
2865         ddb_size -= 4; /* 4 blocks for bypass path allocation */
2866
2867         nth_active_pipe = 0;
2868         for_each_crtc(dev, crtc) {
2869                 if (!to_intel_crtc(crtc)->active)
2870                         continue;
2871
2872                 if (crtc == for_crtc)
2873                         break;
2874
2875                 nth_active_pipe++;
2876         }
2877
2878         pipe_size = ddb_size / config->num_pipes_active;
2879         alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
2880         alloc->end = alloc->start + pipe_size;
2881 }
2882
2883 static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2884 {
2885         if (config->num_pipes_active == 1)
2886                 return 32;
2887
2888         return 8;
2889 }
2890
2891 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2892 {
2893         entry->start = reg & 0x3ff;
2894         entry->end = (reg >> 16) & 0x3ff;
2895         if (entry->end)
2896                 entry->end += 1;
2897 }
2898
2899 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2900                           struct skl_ddb_allocation *ddb /* out */)
2901 {
2902         enum pipe pipe;
2903         int plane;
2904         u32 val;
2905
2906         for_each_pipe(dev_priv, pipe) {
2907                 for_each_plane(dev_priv, pipe, plane) {
2908                         val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2909                         skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2910                                                    val);
2911                 }
2912
2913                 val = I915_READ(CUR_BUF_CFG(pipe));
2914                 skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val);
2915         }
2916 }
2917
2918 static unsigned int
2919 skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p, int y)
2920 {
2921
2922         /* for planar format */
2923         if (p->y_bytes_per_pixel) {
2924                 if (y)  /* y-plane data rate */
2925                         return p->horiz_pixels * p->vert_pixels * p->y_bytes_per_pixel;
2926                 else    /* uv-plane data rate */
2927                         return (p->horiz_pixels/2) * (p->vert_pixels/2) * p->bytes_per_pixel;
2928         }
2929
2930         /* for packed formats */
2931         return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel;
2932 }
2933
2934 /*
2935  * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2936  * a 8192x4096@32bpp framebuffer:
2937  *   3 * 4096 * 8192  * 4 < 2^32
2938  */
2939 static unsigned int
2940 skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
2941                                  const struct skl_pipe_wm_parameters *params)
2942 {
2943         unsigned int total_data_rate = 0;
2944         int plane;
2945
2946         for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2947                 const struct intel_plane_wm_parameters *p;
2948
2949                 p = &params->plane[plane];
2950                 if (!p->enabled)
2951                         continue;
2952
2953                 total_data_rate += skl_plane_relative_data_rate(p, 0); /* packed/uv */
2954                 if (p->y_bytes_per_pixel) {
2955                         total_data_rate += skl_plane_relative_data_rate(p, 1); /* y-plane */
2956                 }
2957         }
2958
2959         return total_data_rate;
2960 }
2961
2962 static void
2963 skl_allocate_pipe_ddb(struct drm_crtc *crtc,
2964                       const struct intel_wm_config *config,
2965                       const struct skl_pipe_wm_parameters *params,
2966                       struct skl_ddb_allocation *ddb /* out */)
2967 {
2968         struct drm_device *dev = crtc->dev;
2969         struct drm_i915_private *dev_priv = dev->dev_private;
2970         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2971         enum pipe pipe = intel_crtc->pipe;
2972         struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
2973         uint16_t alloc_size, start, cursor_blocks;
2974         uint16_t minimum[I915_MAX_PLANES];
2975         uint16_t y_minimum[I915_MAX_PLANES];
2976         unsigned int total_data_rate;
2977         int plane;
2978
2979         skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc);
2980         alloc_size = skl_ddb_entry_size(alloc);
2981         if (alloc_size == 0) {
2982                 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2983                 memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe]));
2984                 return;
2985         }
2986
2987         cursor_blocks = skl_cursor_allocation(config);
2988         ddb->cursor[pipe].start = alloc->end - cursor_blocks;
2989         ddb->cursor[pipe].end = alloc->end;
2990
2991         alloc_size -= cursor_blocks;
2992         alloc->end -= cursor_blocks;
2993
2994         /* 1. Allocate the mininum required blocks for each active plane */
2995         for_each_plane(dev_priv, pipe, plane) {
2996                 const struct intel_plane_wm_parameters *p;
2997
2998                 p = &params->plane[plane];
2999                 if (!p->enabled)
3000                         continue;
3001
3002                 minimum[plane] = 8;
3003                 alloc_size -= minimum[plane];
3004                 y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0;
3005                 alloc_size -= y_minimum[plane];
3006         }
3007
3008         /*
3009          * 2. Distribute the remaining space in proportion to the amount of
3010          * data each plane needs to fetch from memory.
3011          *
3012          * FIXME: we may not allocate every single block here.
3013          */
3014         total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
3015
3016         start = alloc->start;
3017         for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
3018                 const struct intel_plane_wm_parameters *p;
3019                 unsigned int data_rate, y_data_rate;
3020                 uint16_t plane_blocks, y_plane_blocks = 0;
3021
3022                 p = &params->plane[plane];
3023                 if (!p->enabled)
3024                         continue;
3025
3026                 data_rate = skl_plane_relative_data_rate(p, 0);
3027
3028                 /*
3029                  * allocation for (packed formats) or (uv-plane part of planar format):
3030                  * promote the expression to 64 bits to avoid overflowing, the
3031                  * result is < available as data_rate / total_data_rate < 1
3032                  */
3033                 plane_blocks = minimum[plane];
3034                 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3035                                         total_data_rate);
3036
3037                 ddb->plane[pipe][plane].start = start;
3038                 ddb->plane[pipe][plane].end = start + plane_blocks;
3039
3040                 start += plane_blocks;
3041
3042                 /*
3043                  * allocation for y_plane part of planar format:
3044                  */
3045                 if (p->y_bytes_per_pixel) {
3046                         y_data_rate = skl_plane_relative_data_rate(p, 1);
3047                         y_plane_blocks = y_minimum[plane];
3048                         y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3049                                                 total_data_rate);
3050
3051                         ddb->y_plane[pipe][plane].start = start;
3052                         ddb->y_plane[pipe][plane].end = start + y_plane_blocks;
3053
3054                         start += y_plane_blocks;
3055                 }
3056
3057         }
3058
3059 }
3060
3061 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
3062 {
3063         /* TODO: Take into account the scalers once we support them */
3064         return config->base.adjusted_mode.crtc_clock;
3065 }
3066
3067 /*
3068  * The max latency should be 257 (max the punit can code is 255 and we add 2us
3069  * for the read latency) and bytes_per_pixel should always be <= 8, so that
3070  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3071  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3072 */
3073 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
3074                                uint32_t latency)
3075 {
3076         uint32_t wm_intermediate_val, ret;
3077
3078         if (latency == 0)
3079                 return UINT_MAX;
3080
3081         wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
3082         ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3083
3084         return ret;
3085 }
3086
3087 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3088                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
3089                                uint64_t tiling, uint32_t latency)
3090 {
3091         uint32_t ret;
3092         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3093         uint32_t wm_intermediate_val;
3094
3095         if (latency == 0)
3096                 return UINT_MAX;
3097
3098         plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
3099
3100         if (tiling == I915_FORMAT_MOD_Y_TILED ||
3101             tiling == I915_FORMAT_MOD_Yf_TILED) {
3102                 plane_bytes_per_line *= 4;
3103                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3104                 plane_blocks_per_line /= 4;
3105         } else {
3106                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3107         }
3108
3109         wm_intermediate_val = latency * pixel_rate;
3110         ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3111                                 plane_blocks_per_line;
3112
3113         return ret;
3114 }
3115
3116 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3117                                        const struct intel_crtc *intel_crtc)
3118 {
3119         struct drm_device *dev = intel_crtc->base.dev;
3120         struct drm_i915_private *dev_priv = dev->dev_private;
3121         const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3122         enum pipe pipe = intel_crtc->pipe;
3123
3124         if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
3125                    sizeof(new_ddb->plane[pipe])))
3126                 return true;
3127
3128         if (memcmp(&new_ddb->cursor[pipe], &cur_ddb->cursor[pipe],
3129                     sizeof(new_ddb->cursor[pipe])))
3130                 return true;
3131
3132         return false;
3133 }
3134
3135 static void skl_compute_wm_global_parameters(struct drm_device *dev,
3136                                              struct intel_wm_config *config)
3137 {
3138         struct drm_crtc *crtc;
3139         struct drm_plane *plane;
3140
3141         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3142                 config->num_pipes_active += to_intel_crtc(crtc)->active;
3143
3144         /* FIXME: I don't think we need those two global parameters on SKL */
3145         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3146                 struct intel_plane *intel_plane = to_intel_plane(plane);
3147
3148                 config->sprites_enabled |= intel_plane->wm.enabled;
3149                 config->sprites_scaled |= intel_plane->wm.scaled;
3150         }
3151 }
3152
3153 static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
3154                                            struct skl_pipe_wm_parameters *p)
3155 {
3156         struct drm_device *dev = crtc->dev;
3157         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3158         enum pipe pipe = intel_crtc->pipe;
3159         struct drm_plane *plane;
3160         struct drm_framebuffer *fb;
3161         int i = 1; /* Index for sprite planes start */
3162
3163         p->active = intel_crtc->active;
3164         if (p->active) {
3165                 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
3166                 p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
3167
3168                 fb = crtc->primary->state->fb;
3169                 /* For planar: Bpp is for uv plane, y_Bpp is for y plane */
3170                 if (fb) {
3171                         p->plane[0].enabled = true;
3172                         p->plane[0].bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
3173                                 drm_format_plane_cpp(fb->pixel_format, 1) : fb->bits_per_pixel / 8;
3174                         p->plane[0].y_bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
3175                                 drm_format_plane_cpp(fb->pixel_format, 0) : 0;
3176                         p->plane[0].tiling = fb->modifier[0];
3177                 } else {
3178                         p->plane[0].enabled = false;
3179                         p->plane[0].bytes_per_pixel = 0;
3180                         p->plane[0].y_bytes_per_pixel = 0;
3181                         p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
3182                 }
3183                 p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
3184                 p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
3185                 p->plane[0].rotation = crtc->primary->state->rotation;
3186
3187                 fb = crtc->cursor->state->fb;
3188                 p->cursor.y_bytes_per_pixel = 0;
3189                 if (fb) {
3190                         p->cursor.enabled = true;
3191                         p->cursor.bytes_per_pixel = fb->bits_per_pixel / 8;
3192                         p->cursor.horiz_pixels = crtc->cursor->state->crtc_w;
3193                         p->cursor.vert_pixels = crtc->cursor->state->crtc_h;
3194                 } else {
3195                         p->cursor.enabled = false;
3196                         p->cursor.bytes_per_pixel = 0;
3197                         p->cursor.horiz_pixels = 64;
3198                         p->cursor.vert_pixels = 64;
3199                 }
3200         }
3201
3202         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3203                 struct intel_plane *intel_plane = to_intel_plane(plane);
3204
3205                 if (intel_plane->pipe == pipe &&
3206                         plane->type == DRM_PLANE_TYPE_OVERLAY)
3207                         p->plane[i++] = intel_plane->wm;
3208         }
3209 }
3210
3211 static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3212                                  struct skl_pipe_wm_parameters *p,
3213                                  struct intel_plane_wm_parameters *p_params,
3214                                  uint16_t ddb_allocation,
3215                                  int level,
3216                                  uint16_t *out_blocks, /* out */
3217                                  uint8_t *out_lines /* out */)
3218 {
3219         uint32_t latency = dev_priv->wm.skl_latency[level];
3220         uint32_t method1, method2;
3221         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3222         uint32_t res_blocks, res_lines;
3223         uint32_t selected_result;
3224         uint8_t bytes_per_pixel;
3225
3226         if (latency == 0 || !p->active || !p_params->enabled)
3227                 return false;
3228
3229         bytes_per_pixel = p_params->y_bytes_per_pixel ?
3230                 p_params->y_bytes_per_pixel :
3231                 p_params->bytes_per_pixel;
3232         method1 = skl_wm_method1(p->pixel_rate,
3233                                  bytes_per_pixel,
3234                                  latency);
3235         method2 = skl_wm_method2(p->pixel_rate,
3236                                  p->pipe_htotal,
3237                                  p_params->horiz_pixels,
3238                                  bytes_per_pixel,
3239                                  p_params->tiling,
3240                                  latency);
3241
3242         plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel;
3243         plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3244
3245         if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
3246             p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
3247                 uint32_t min_scanlines = 4;
3248                 uint32_t y_tile_minimum;
3249                 if (intel_rotation_90_or_270(p_params->rotation)) {
3250                         switch (p_params->bytes_per_pixel) {
3251                         case 1:
3252                                 min_scanlines = 16;
3253                                 break;
3254                         case 2:
3255                                 min_scanlines = 8;
3256                                 break;
3257                         case 8:
3258                                 WARN(1, "Unsupported pixel depth for rotation");
3259                         }
3260                 }
3261                 y_tile_minimum = plane_blocks_per_line * min_scanlines;
3262                 selected_result = max(method2, y_tile_minimum);
3263         } else {
3264                 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3265                         selected_result = min(method1, method2);
3266                 else
3267                         selected_result = method1;
3268         }
3269
3270         res_blocks = selected_result + 1;
3271         res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3272
3273         if (level >= 1 && level <= 7) {
3274                 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
3275                     p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
3276                         res_lines += 4;
3277                 else
3278                         res_blocks++;
3279         }
3280
3281         if (res_blocks >= ddb_allocation || res_lines > 31)
3282                 return false;
3283
3284         *out_blocks = res_blocks;
3285         *out_lines = res_lines;
3286
3287         return true;
3288 }
3289
3290 static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3291                                  struct skl_ddb_allocation *ddb,
3292                                  struct skl_pipe_wm_parameters *p,
3293                                  enum pipe pipe,
3294                                  int level,
3295                                  int num_planes,
3296                                  struct skl_wm_level *result)
3297 {
3298         uint16_t ddb_blocks;
3299         int i;
3300
3301         for (i = 0; i < num_planes; i++) {
3302                 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3303
3304                 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3305                                                 p, &p->plane[i],
3306                                                 ddb_blocks,
3307                                                 level,
3308                                                 &result->plane_res_b[i],
3309                                                 &result->plane_res_l[i]);
3310         }
3311
3312         ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]);
3313         result->cursor_en = skl_compute_plane_wm(dev_priv, p, &p->cursor,
3314                                                  ddb_blocks, level,
3315                                                  &result->cursor_res_b,
3316                                                  &result->cursor_res_l);
3317 }
3318
3319 static uint32_t
3320 skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)
3321 {
3322         if (!to_intel_crtc(crtc)->active)
3323                 return 0;
3324
3325         if (WARN_ON(p->pixel_rate == 0))
3326                 return 0;
3327
3328         return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);
3329 }
3330
3331 static void skl_compute_transition_wm(struct drm_crtc *crtc,
3332                                       struct skl_pipe_wm_parameters *params,
3333                                       struct skl_wm_level *trans_wm /* out */)
3334 {
3335         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3336         int i;
3337
3338         if (!params->active)
3339                 return;
3340
3341         /* Until we know more, just disable transition WMs */
3342         for (i = 0; i < intel_num_planes(intel_crtc); i++)
3343                 trans_wm->plane_en[i] = false;
3344         trans_wm->cursor_en = false;
3345 }
3346
3347 static void skl_compute_pipe_wm(struct drm_crtc *crtc,
3348                                 struct skl_ddb_allocation *ddb,
3349                                 struct skl_pipe_wm_parameters *params,
3350                                 struct skl_pipe_wm *pipe_wm)
3351 {
3352         struct drm_device *dev = crtc->dev;
3353         const struct drm_i915_private *dev_priv = dev->dev_private;
3354         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3355         int level, max_level = ilk_wm_max_level(dev);
3356
3357         for (level = 0; level <= max_level; level++) {
3358                 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,
3359                                      level, intel_num_planes(intel_crtc),
3360                                      &pipe_wm->wm[level]);
3361         }
3362         pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);
3363
3364         skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm);
3365 }
3366
3367 static void skl_compute_wm_results(struct drm_device *dev,
3368                                    struct skl_pipe_wm_parameters *p,
3369                                    struct skl_pipe_wm *p_wm,
3370                                    struct skl_wm_values *r,
3371                                    struct intel_crtc *intel_crtc)
3372 {
3373         int level, max_level = ilk_wm_max_level(dev);
3374         enum pipe pipe = intel_crtc->pipe;
3375         uint32_t temp;
3376         int i;
3377
3378         for (level = 0; level <= max_level; level++) {
3379                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3380                         temp = 0;
3381
3382                         temp |= p_wm->wm[level].plane_res_l[i] <<
3383                                         PLANE_WM_LINES_SHIFT;
3384                         temp |= p_wm->wm[level].plane_res_b[i];
3385                         if (p_wm->wm[level].plane_en[i])
3386                                 temp |= PLANE_WM_EN;
3387
3388                         r->plane[pipe][i][level] = temp;
3389                 }
3390
3391                 temp = 0;
3392
3393                 temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT;
3394                 temp |= p_wm->wm[level].cursor_res_b;
3395
3396                 if (p_wm->wm[level].cursor_en)
3397                         temp |= PLANE_WM_EN;
3398
3399                 r->cursor[pipe][level] = temp;
3400
3401         }
3402
3403         /* transition WMs */
3404         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3405                 temp = 0;
3406                 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3407                 temp |= p_wm->trans_wm.plane_res_b[i];
3408                 if (p_wm->trans_wm.plane_en[i])
3409                         temp |= PLANE_WM_EN;
3410
3411                 r->plane_trans[pipe][i] = temp;
3412         }
3413
3414         temp = 0;
3415         temp |= p_wm->trans_wm.cursor_res_l << PLANE_WM_LINES_SHIFT;
3416         temp |= p_wm->trans_wm.cursor_res_b;
3417         if (p_wm->trans_wm.cursor_en)
3418                 temp |= PLANE_WM_EN;
3419
3420         r->cursor_trans[pipe] = temp;
3421
3422         r->wm_linetime[pipe] = p_wm->linetime;
3423 }
3424
3425 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
3426                                 const struct skl_ddb_entry *entry)
3427 {
3428         if (entry->end)
3429                 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3430         else
3431                 I915_WRITE(reg, 0);
3432 }
3433
3434 static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3435                                 const struct skl_wm_values *new)
3436 {
3437         struct drm_device *dev = dev_priv->dev;
3438         struct intel_crtc *crtc;
3439
3440         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3441                 int i, level, max_level = ilk_wm_max_level(dev);
3442                 enum pipe pipe = crtc->pipe;
3443
3444                 if (!new->dirty[pipe])
3445                         continue;
3446
3447                 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
3448
3449                 for (level = 0; level <= max_level; level++) {
3450                         for (i = 0; i < intel_num_planes(crtc); i++)
3451                                 I915_WRITE(PLANE_WM(pipe, i, level),
3452                                            new->plane[pipe][i][level]);
3453                         I915_WRITE(CUR_WM(pipe, level),
3454                                    new->cursor[pipe][level]);
3455                 }
3456                 for (i = 0; i < intel_num_planes(crtc); i++)
3457                         I915_WRITE(PLANE_WM_TRANS(pipe, i),
3458                                    new->plane_trans[pipe][i]);
3459                 I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]);
3460
3461                 for (i = 0; i < intel_num_planes(crtc); i++) {
3462                         skl_ddb_entry_write(dev_priv,
3463                                             PLANE_BUF_CFG(pipe, i),
3464                                             &new->ddb.plane[pipe][i]);
3465                         skl_ddb_entry_write(dev_priv,
3466                                             PLANE_NV12_BUF_CFG(pipe, i),
3467                                             &new->ddb.y_plane[pipe][i]);
3468                 }
3469
3470                 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3471                                     &new->ddb.cursor[pipe]);
3472         }
3473 }
3474
3475 /*
3476  * When setting up a new DDB allocation arrangement, we need to correctly
3477  * sequence the times at which the new allocations for the pipes are taken into
3478  * account or we'll have pipes fetching from space previously allocated to
3479  * another pipe.
3480  *
3481  * Roughly the sequence looks like:
3482  *  1. re-allocate the pipe(s) with the allocation being reduced and not
3483  *     overlapping with a previous light-up pipe (another way to put it is:
3484  *     pipes with their new allocation strickly included into their old ones).
3485  *  2. re-allocate the other pipes that get their allocation reduced
3486  *  3. allocate the pipes having their allocation increased
3487  *
3488  * Steps 1. and 2. are here to take care of the following case:
3489  * - Initially DDB looks like this:
3490  *     |   B    |   C    |
3491  * - enable pipe A.
3492  * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3493  *   allocation
3494  *     |  A  |  B  |  C  |
3495  *
3496  * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3497  */
3498
3499 static void
3500 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
3501 {
3502         int plane;
3503
3504         DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3505
3506         for_each_plane(dev_priv, pipe, plane) {
3507                 I915_WRITE(PLANE_SURF(pipe, plane),
3508                            I915_READ(PLANE_SURF(pipe, plane)));
3509         }
3510         I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3511 }
3512
3513 static bool
3514 skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3515                             const struct skl_ddb_allocation *new,
3516                             enum pipe pipe)
3517 {
3518         uint16_t old_size, new_size;
3519
3520         old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3521         new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3522
3523         return old_size != new_size &&
3524                new->pipe[pipe].start >= old->pipe[pipe].start &&
3525                new->pipe[pipe].end <= old->pipe[pipe].end;
3526 }
3527
3528 static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3529                                 struct skl_wm_values *new_values)
3530 {
3531         struct drm_device *dev = dev_priv->dev;
3532         struct skl_ddb_allocation *cur_ddb, *new_ddb;
3533         bool reallocated[I915_MAX_PIPES] = {};
3534         struct intel_crtc *crtc;
3535         enum pipe pipe;
3536
3537         new_ddb = &new_values->ddb;
3538         cur_ddb = &dev_priv->wm.skl_hw.ddb;
3539
3540         /*
3541          * First pass: flush the pipes with the new allocation contained into
3542          * the old space.
3543          *
3544          * We'll wait for the vblank on those pipes to ensure we can safely
3545          * re-allocate the freed space without this pipe fetching from it.
3546          */
3547         for_each_intel_crtc(dev, crtc) {
3548                 if (!crtc->active)
3549                         continue;
3550
3551                 pipe = crtc->pipe;
3552
3553                 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3554                         continue;
3555
3556                 skl_wm_flush_pipe(dev_priv, pipe, 1);
3557                 intel_wait_for_vblank(dev, pipe);
3558
3559                 reallocated[pipe] = true;
3560         }
3561
3562
3563         /*
3564          * Second pass: flush the pipes that are having their allocation
3565          * reduced, but overlapping with a previous allocation.
3566          *
3567          * Here as well we need to wait for the vblank to make sure the freed
3568          * space is not used anymore.
3569          */
3570         for_each_intel_crtc(dev, crtc) {
3571                 if (!crtc->active)
3572                         continue;
3573
3574                 pipe = crtc->pipe;
3575
3576                 if (reallocated[pipe])
3577                         continue;
3578
3579                 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3580                     skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
3581                         skl_wm_flush_pipe(dev_priv, pipe, 2);
3582                         intel_wait_for_vblank(dev, pipe);
3583                         reallocated[pipe] = true;
3584                 }
3585         }
3586
3587         /*
3588          * Third pass: flush the pipes that got more space allocated.
3589          *
3590          * We don't need to actively wait for the update here, next vblank
3591          * will just get more DDB space with the correct WM values.
3592          */
3593         for_each_intel_crtc(dev, crtc) {
3594                 if (!crtc->active)
3595                         continue;
3596
3597                 pipe = crtc->pipe;
3598
3599                 /*
3600                  * At this point, only the pipes more space than before are
3601                  * left to re-allocate.
3602                  */
3603                 if (reallocated[pipe])
3604                         continue;
3605
3606                 skl_wm_flush_pipe(dev_priv, pipe, 3);
3607         }
3608 }
3609
3610 static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3611                                struct skl_pipe_wm_parameters *params,
3612                                struct intel_wm_config *config,
3613                                struct skl_ddb_allocation *ddb, /* out */
3614                                struct skl_pipe_wm *pipe_wm /* out */)
3615 {
3616         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3617
3618         skl_compute_wm_pipe_parameters(crtc, params);
3619         skl_allocate_pipe_ddb(crtc, config, params, ddb);
3620         skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);
3621
3622         if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
3623                 return false;
3624
3625         intel_crtc->wm.skl_active = *pipe_wm;
3626
3627         return true;
3628 }
3629
3630 static void skl_update_other_pipe_wm(struct drm_device *dev,
3631                                      struct drm_crtc *crtc,
3632                                      struct intel_wm_config *config,
3633                                      struct skl_wm_values *r)
3634 {
3635         struct intel_crtc *intel_crtc;
3636         struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3637
3638         /*
3639          * If the WM update hasn't changed the allocation for this_crtc (the
3640          * crtc we are currently computing the new WM values for), other
3641          * enabled crtcs will keep the same allocation and we don't need to
3642          * recompute anything for them.
3643          */
3644         if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3645                 return;
3646
3647         /*
3648          * Otherwise, because of this_crtc being freshly enabled/disabled, the
3649          * other active pipes need new DDB allocation and WM values.
3650          */
3651         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3652                                 base.head) {
3653                 struct skl_pipe_wm_parameters params = {};
3654                 struct skl_pipe_wm pipe_wm = {};
3655                 bool wm_changed;
3656
3657                 if (this_crtc->pipe == intel_crtc->pipe)
3658                         continue;
3659
3660                 if (!intel_crtc->active)
3661                         continue;
3662
3663                 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3664                                                 &params, config,
3665                                                 &r->ddb, &pipe_wm);
3666
3667                 /*
3668                  * If we end up re-computing the other pipe WM values, it's
3669                  * because it was really needed, so we expect the WM values to
3670                  * be different.
3671                  */
3672                 WARN_ON(!wm_changed);
3673
3674                 skl_compute_wm_results(dev, &params, &pipe_wm, r, intel_crtc);
3675                 r->dirty[intel_crtc->pipe] = true;
3676         }
3677 }
3678
3679 static void skl_update_wm(struct drm_crtc *crtc)
3680 {
3681         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3682         struct drm_device *dev = crtc->dev;
3683         struct drm_i915_private *dev_priv = dev->dev_private;
3684         struct skl_pipe_wm_parameters params = {};
3685         struct skl_wm_values *results = &dev_priv->wm.skl_results;
3686         struct skl_pipe_wm pipe_wm = {};
3687         struct intel_wm_config config = {};
3688
3689         memset(results, 0, sizeof(*results));
3690
3691         skl_compute_wm_global_parameters(dev, &config);
3692
3693         if (!skl_update_pipe_wm(crtc, &params, &config,
3694                                 &results->ddb, &pipe_wm))
3695                 return;
3696
3697         skl_compute_wm_results(dev, &params, &pipe_wm, results, intel_crtc);
3698         results->dirty[intel_crtc->pipe] = true;
3699
3700         skl_update_other_pipe_wm(dev, crtc, &config, results);
3701         skl_write_wm_values(dev_priv, results);
3702         skl_flush_wm_values(dev_priv, results);
3703
3704         /* store the new configuration */
3705         dev_priv->wm.skl_hw = *results;
3706 }
3707
3708 static void
3709 skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
3710                      uint32_t sprite_width, uint32_t sprite_height,
3711                      int pixel_size, bool enabled, bool scaled)
3712 {
3713         struct intel_plane *intel_plane = to_intel_plane(plane);
3714         struct drm_framebuffer *fb = plane->state->fb;
3715
3716         intel_plane->wm.enabled = enabled;
3717         intel_plane->wm.scaled = scaled;
3718         intel_plane->wm.horiz_pixels = sprite_width;
3719         intel_plane->wm.vert_pixels = sprite_height;
3720         intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
3721
3722         /* For planar: Bpp is for UV plane, y_Bpp is for Y plane */
3723         intel_plane->wm.bytes_per_pixel =
3724                 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3725                 drm_format_plane_cpp(plane->state->fb->pixel_format, 1) : pixel_size;
3726         intel_plane->wm.y_bytes_per_pixel =
3727                 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3728                 drm_format_plane_cpp(plane->state->fb->pixel_format, 0) : 0;
3729
3730         /*
3731          * Framebuffer can be NULL on plane disable, but it does not
3732          * matter for watermarks if we assume no tiling in that case.
3733          */
3734         if (fb)
3735                 intel_plane->wm.tiling = fb->modifier[0];
3736         intel_plane->wm.rotation = plane->state->rotation;
3737
3738         skl_update_wm(crtc);
3739 }
3740
3741 static void ilk_update_wm(struct drm_crtc *crtc)
3742 {
3743         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3744         struct drm_device *dev = crtc->dev;
3745         struct drm_i915_private *dev_priv = dev->dev_private;
3746         struct ilk_wm_maximums max;
3747         struct ilk_pipe_wm_parameters params = {};
3748         struct ilk_wm_values results = {};
3749         enum intel_ddb_partitioning partitioning;
3750         struct intel_pipe_wm pipe_wm = {};
3751         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
3752         struct intel_wm_config config = {};
3753
3754         ilk_compute_wm_parameters(crtc, &params);
3755
3756         intel_compute_pipe_wm(crtc, &params, &pipe_wm);
3757
3758         if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
3759                 return;
3760
3761         intel_crtc->wm.active = pipe_wm;
3762
3763         ilk_compute_wm_config(dev, &config);
3764
3765         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3766         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
3767
3768         /* 5/6 split only in single pipe config on IVB+ */
3769         if (INTEL_INFO(dev)->gen >= 7 &&
3770             config.num_pipes_active == 1 && config.sprites_enabled) {
3771                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3772                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
3773
3774                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
3775         } else {
3776                 best_lp_wm = &lp_wm_1_2;
3777         }
3778
3779         partitioning = (best_lp_wm == &lp_wm_1_2) ?
3780                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
3781
3782         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
3783
3784         ilk_write_wm_values(dev_priv, &results);
3785 }
3786
3787 static void
3788 ilk_update_sprite_wm(struct drm_plane *plane,
3789                      struct drm_crtc *crtc,
3790                      uint32_t sprite_width, uint32_t sprite_height,
3791                      int pixel_size, bool enabled, bool scaled)
3792 {
3793         struct drm_device *dev = plane->dev;
3794         struct intel_plane *intel_plane = to_intel_plane(plane);
3795
3796         intel_plane->wm.enabled = enabled;
3797         intel_plane->wm.scaled = scaled;
3798         intel_plane->wm.horiz_pixels = sprite_width;
3799         intel_plane->wm.vert_pixels = sprite_width;
3800         intel_plane->wm.bytes_per_pixel = pixel_size;
3801
3802         /*
3803          * IVB workaround: must disable low power watermarks for at least
3804          * one frame before enabling scaling.  LP watermarks can be re-enabled
3805          * when scaling is disabled.
3806          *
3807          * WaCxSRDisabledForSpriteScaling:ivb
3808          */
3809         if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
3810                 intel_wait_for_vblank(dev, intel_plane->pipe);
3811
3812         ilk_update_wm(crtc);
3813 }
3814
3815 static void skl_pipe_wm_active_state(uint32_t val,
3816                                      struct skl_pipe_wm *active,
3817                                      bool is_transwm,
3818                                      bool is_cursor,
3819                                      int i,
3820                                      int level)
3821 {
3822         bool is_enabled = (val & PLANE_WM_EN) != 0;
3823
3824         if (!is_transwm) {
3825                 if (!is_cursor) {
3826                         active->wm[level].plane_en[i] = is_enabled;
3827                         active->wm[level].plane_res_b[i] =
3828                                         val & PLANE_WM_BLOCKS_MASK;
3829                         active->wm[level].plane_res_l[i] =
3830                                         (val >> PLANE_WM_LINES_SHIFT) &
3831                                                 PLANE_WM_LINES_MASK;
3832                 } else {
3833                         active->wm[level].cursor_en = is_enabled;
3834                         active->wm[level].cursor_res_b =
3835                                         val & PLANE_WM_BLOCKS_MASK;
3836                         active->wm[level].cursor_res_l =
3837                                         (val >> PLANE_WM_LINES_SHIFT) &
3838                                                 PLANE_WM_LINES_MASK;
3839                 }
3840         } else {
3841                 if (!is_cursor) {
3842                         active->trans_wm.plane_en[i] = is_enabled;
3843                         active->trans_wm.plane_res_b[i] =
3844                                         val & PLANE_WM_BLOCKS_MASK;
3845                         active->trans_wm.plane_res_l[i] =
3846                                         (val >> PLANE_WM_LINES_SHIFT) &
3847                                                 PLANE_WM_LINES_MASK;
3848                 } else {
3849                         active->trans_wm.cursor_en = is_enabled;
3850                         active->trans_wm.cursor_res_b =
3851                                         val & PLANE_WM_BLOCKS_MASK;
3852                         active->trans_wm.cursor_res_l =
3853                                         (val >> PLANE_WM_LINES_SHIFT) &
3854                                                 PLANE_WM_LINES_MASK;
3855                 }
3856         }
3857 }
3858
3859 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3860 {
3861         struct drm_device *dev = crtc->dev;
3862         struct drm_i915_private *dev_priv = dev->dev_private;
3863         struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3864         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3865         struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;
3866         enum pipe pipe = intel_crtc->pipe;
3867         int level, i, max_level;
3868         uint32_t temp;
3869
3870         max_level = ilk_wm_max_level(dev);
3871
3872         hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3873
3874         for (level = 0; level <= max_level; level++) {
3875                 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3876                         hw->plane[pipe][i][level] =
3877                                         I915_READ(PLANE_WM(pipe, i, level));
3878                 hw->cursor[pipe][level] = I915_READ(CUR_WM(pipe, level));
3879         }
3880
3881         for (i = 0; i < intel_num_planes(intel_crtc); i++)
3882                 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3883         hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe));
3884
3885         if (!intel_crtc->active)
3886                 return;
3887
3888         hw->dirty[pipe] = true;
3889
3890         active->linetime = hw->wm_linetime[pipe];
3891
3892         for (level = 0; level <= max_level; level++) {
3893                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3894                         temp = hw->plane[pipe][i][level];
3895                         skl_pipe_wm_active_state(temp, active, false,
3896                                                 false, i, level);
3897                 }
3898                 temp = hw->cursor[pipe][level];
3899                 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3900         }
3901
3902         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3903                 temp = hw->plane_trans[pipe][i];
3904                 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3905         }
3906
3907         temp = hw->cursor_trans[pipe];
3908         skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3909 }
3910
3911 void skl_wm_get_hw_state(struct drm_device *dev)
3912 {
3913         struct drm_i915_private *dev_priv = dev->dev_private;
3914         struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3915         struct drm_crtc *crtc;
3916
3917         skl_ddb_get_hw_state(dev_priv, ddb);
3918         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3919                 skl_pipe_wm_get_hw_state(crtc);
3920 }
3921
3922 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3923 {
3924         struct drm_device *dev = crtc->dev;
3925         struct drm_i915_private *dev_priv = dev->dev_private;
3926         struct ilk_wm_values *hw = &dev_priv->wm.hw;
3927         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3928         struct intel_pipe_wm *active = &intel_crtc->wm.active;
3929         enum pipe pipe = intel_crtc->pipe;
3930         static const unsigned int wm0_pipe_reg[] = {
3931                 [PIPE_A] = WM0_PIPEA_ILK,
3932                 [PIPE_B] = WM0_PIPEB_ILK,
3933                 [PIPE_C] = WM0_PIPEC_IVB,
3934         };
3935
3936         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3937         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3938                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3939
3940         active->pipe_enabled = intel_crtc->active;
3941
3942         if (active->pipe_enabled) {
3943                 u32 tmp = hw->wm_pipe[pipe];
3944
3945                 /*
3946                  * For active pipes LP0 watermark is marked as
3947                  * enabled, and LP1+ watermaks as disabled since
3948                  * we can't really reverse compute them in case
3949                  * multiple pipes are active.
3950                  */
3951                 active->wm[0].enable = true;
3952                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3953                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3954                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3955                 active->linetime = hw->wm_linetime[pipe];
3956         } else {
3957                 int level, max_level = ilk_wm_max_level(dev);
3958
3959                 /*
3960                  * For inactive pipes, all watermark levels
3961                  * should be marked as enabled but zeroed,
3962                  * which is what we'd compute them to.
3963                  */
3964                 for (level = 0; level <= max_level; level++)
3965                         active->wm[level].enable = true;
3966         }
3967 }
3968
3969 #define _FW_WM(value, plane) \
3970         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3971 #define _FW_WM_VLV(value, plane) \
3972         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3973
3974 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3975                                struct vlv_wm_values *wm)
3976 {
3977         enum pipe pipe;
3978         uint32_t tmp;
3979
3980         for_each_pipe(dev_priv, pipe) {
3981                 tmp = I915_READ(VLV_DDL(pipe));
3982
3983                 wm->ddl[pipe].primary =
3984                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3985                 wm->ddl[pipe].cursor =
3986                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3987                 wm->ddl[pipe].sprite[0] =
3988                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3989                 wm->ddl[pipe].sprite[1] =
3990                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3991         }
3992
3993         tmp = I915_READ(DSPFW1);
3994         wm->sr.plane = _FW_WM(tmp, SR);
3995         wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3996         wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3997         wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3998
3999         tmp = I915_READ(DSPFW2);
4000         wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4001         wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4002         wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4003
4004         tmp = I915_READ(DSPFW3);
4005         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4006
4007         if (IS_CHERRYVIEW(dev_priv)) {
4008                 tmp = I915_READ(DSPFW7_CHV);
4009                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4010                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4011
4012                 tmp = I915_READ(DSPFW8_CHV);
4013                 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4014                 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4015
4016                 tmp = I915_READ(DSPFW9_CHV);
4017                 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4018                 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4019
4020                 tmp = I915_READ(DSPHOWM);
4021                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4022                 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4023                 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4024                 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4025                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4026                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4027                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4028                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4029                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4030                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4031         } else {
4032                 tmp = I915_READ(DSPFW7);
4033                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4034                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4035
4036                 tmp = I915_READ(DSPHOWM);
4037                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4038                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4039                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4040                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4041                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4042                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4043                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4044         }
4045 }
4046
4047 #undef _FW_WM
4048 #undef _FW_WM_VLV
4049
4050 void vlv_wm_get_hw_state(struct drm_device *dev)
4051 {
4052         struct drm_i915_private *dev_priv = to_i915(dev);
4053         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4054         struct intel_plane *plane;
4055         enum pipe pipe;
4056         u32 val;
4057
4058         vlv_read_wm_values(dev_priv, wm);
4059
4060         for_each_intel_plane(dev, plane) {
4061                 switch (plane->base.type) {
4062                         int sprite;
4063                 case DRM_PLANE_TYPE_CURSOR:
4064                         plane->wm.fifo_size = 63;
4065                         break;
4066                 case DRM_PLANE_TYPE_PRIMARY:
4067                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4068                         break;
4069                 case DRM_PLANE_TYPE_OVERLAY:
4070                         sprite = plane->plane;
4071                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4072                         break;
4073                 }
4074         }
4075
4076         wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4077         wm->level = VLV_WM_LEVEL_PM2;
4078
4079         if (IS_CHERRYVIEW(dev_priv)) {
4080                 mutex_lock(&dev_priv->rps.hw_lock);
4081
4082                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4083                 if (val & DSP_MAXFIFO_PM5_ENABLE)
4084                         wm->level = VLV_WM_LEVEL_PM5;
4085
4086                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4087                 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4088                         wm->level = VLV_WM_LEVEL_DDR_DVFS;
4089
4090                 mutex_unlock(&dev_priv->rps.hw_lock);
4091         }
4092
4093         for_each_pipe(dev_priv, pipe)
4094                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4095                               pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4096                               wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4097
4098         DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4099                       wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4100 }
4101
4102 void ilk_wm_get_hw_state(struct drm_device *dev)
4103 {
4104         struct drm_i915_private *dev_priv = dev->dev_private;
4105         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4106         struct drm_crtc *crtc;
4107
4108         for_each_crtc(dev, crtc)
4109                 ilk_pipe_wm_get_hw_state(crtc);
4110
4111         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4112         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4113         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4114
4115         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4116         if (INTEL_INFO(dev)->gen >= 7) {
4117                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4118                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4119         }
4120
4121         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4122                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4123                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4124         else if (IS_IVYBRIDGE(dev))
4125                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4126                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4127
4128         hw->enable_fbc_wm =
4129                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4130 }
4131
4132 /**
4133  * intel_update_watermarks - update FIFO watermark values based on current modes
4134  *
4135  * Calculate watermark values for the various WM regs based on current mode
4136  * and plane configuration.
4137  *
4138  * There are several cases to deal with here:
4139  *   - normal (i.e. non-self-refresh)
4140  *   - self-refresh (SR) mode
4141  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4142  *   - lines are small relative to FIFO size (buffer can hold more than 2
4143  *     lines), so need to account for TLB latency
4144  *
4145  *   The normal calculation is:
4146  *     watermark = dotclock * bytes per pixel * latency
4147  *   where latency is platform & configuration dependent (we assume pessimal
4148  *   values here).
4149  *
4150  *   The SR calculation is:
4151  *     watermark = (trunc(latency/line time)+1) * surface width *
4152  *       bytes per pixel
4153  *   where
4154  *     line time = htotal / dotclock
4155  *     surface width = hdisplay for normal plane and 64 for cursor
4156  *   and latency is assumed to be high, as above.
4157  *
4158  * The final value programmed to the register should always be rounded up,
4159  * and include an extra 2 entries to account for clock crossings.
4160  *
4161  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4162  * to set the non-SR watermarks to 8.
4163  */
4164 void intel_update_watermarks(struct drm_crtc *crtc)
4165 {
4166         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4167
4168         if (dev_priv->display.update_wm)
4169                 dev_priv->display.update_wm(crtc);
4170 }
4171
4172 void intel_update_sprite_watermarks(struct drm_plane *plane,
4173                                     struct drm_crtc *crtc,
4174                                     uint32_t sprite_width,
4175                                     uint32_t sprite_height,
4176                                     int pixel_size,
4177                                     bool enabled, bool scaled)
4178 {
4179         struct drm_i915_private *dev_priv = plane->dev->dev_private;
4180
4181         if (dev_priv->display.update_sprite_wm)
4182                 dev_priv->display.update_sprite_wm(plane, crtc,
4183                                                    sprite_width, sprite_height,
4184                                                    pixel_size, enabled, scaled);
4185 }
4186
4187 /**
4188  * Lock protecting IPS related data structures
4189  */
4190 DEFINE_SPINLOCK(mchdev_lock);
4191
4192 /* Global for IPS driver to get at the current i915 device. Protected by
4193  * mchdev_lock. */
4194 static struct drm_i915_private *i915_mch_dev;
4195
4196 bool ironlake_set_drps(struct drm_device *dev, u8 val)
4197 {
4198         struct drm_i915_private *dev_priv = dev->dev_private;
4199         u16 rgvswctl;
4200
4201         assert_spin_locked(&mchdev_lock);
4202
4203         rgvswctl = I915_READ16(MEMSWCTL);
4204         if (rgvswctl & MEMCTL_CMD_STS) {
4205                 DRM_DEBUG("gpu busy, RCS change rejected\n");
4206                 return false; /* still busy with another command */
4207         }
4208
4209         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4210                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4211         I915_WRITE16(MEMSWCTL, rgvswctl);
4212         POSTING_READ16(MEMSWCTL);
4213
4214         rgvswctl |= MEMCTL_CMD_STS;
4215         I915_WRITE16(MEMSWCTL, rgvswctl);
4216
4217         return true;
4218 }
4219
4220 static void ironlake_enable_drps(struct drm_device *dev)
4221 {
4222         struct drm_i915_private *dev_priv = dev->dev_private;
4223         u32 rgvmodectl = I915_READ(MEMMODECTL);
4224         u8 fmax, fmin, fstart, vstart;
4225
4226         spin_lock_irq(&mchdev_lock);
4227
4228         /* Enable temp reporting */
4229         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4230         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4231
4232         /* 100ms RC evaluation intervals */
4233         I915_WRITE(RCUPEI, 100000);
4234         I915_WRITE(RCDNEI, 100000);
4235
4236         /* Set max/min thresholds to 90ms and 80ms respectively */
4237         I915_WRITE(RCBMAXAVG, 90000);
4238         I915_WRITE(RCBMINAVG, 80000);
4239
4240         I915_WRITE(MEMIHYST, 1);
4241
4242         /* Set up min, max, and cur for interrupt handling */
4243         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4244         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4245         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4246                 MEMMODE_FSTART_SHIFT;
4247
4248         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
4249                 PXVFREQ_PX_SHIFT;
4250
4251         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4252         dev_priv->ips.fstart = fstart;
4253
4254         dev_priv->ips.max_delay = fstart;
4255         dev_priv->ips.min_delay = fmin;
4256         dev_priv->ips.cur_delay = fstart;
4257
4258         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4259                          fmax, fmin, fstart);
4260
4261         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4262
4263         /*
4264          * Interrupts will be enabled in ironlake_irq_postinstall
4265          */
4266
4267         I915_WRITE(VIDSTART, vstart);
4268         POSTING_READ(VIDSTART);
4269
4270         rgvmodectl |= MEMMODE_SWMODE_EN;
4271         I915_WRITE(MEMMODECTL, rgvmodectl);
4272
4273         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4274                 DRM_ERROR("stuck trying to change perf mode\n");
4275         mdelay(1);
4276
4277         ironlake_set_drps(dev, fstart);
4278
4279         dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
4280                 I915_READ(0x112e0);
4281         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4282         dev_priv->ips.last_count2 = I915_READ(0x112f4);
4283         dev_priv->ips.last_time2 = ktime_get_raw_ns();
4284
4285         spin_unlock_irq(&mchdev_lock);
4286 }
4287
4288 static void ironlake_disable_drps(struct drm_device *dev)
4289 {
4290         struct drm_i915_private *dev_priv = dev->dev_private;
4291         u16 rgvswctl;
4292
4293         spin_lock_irq(&mchdev_lock);
4294
4295         rgvswctl = I915_READ16(MEMSWCTL);
4296
4297         /* Ack interrupts, disable EFC interrupt */
4298         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4299         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4300         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4301         I915_WRITE(DEIIR, DE_PCU_EVENT);
4302         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4303
4304         /* Go back to the starting frequency */
4305         ironlake_set_drps(dev, dev_priv->ips.fstart);
4306         mdelay(1);
4307         rgvswctl |= MEMCTL_CMD_STS;
4308         I915_WRITE(MEMSWCTL, rgvswctl);
4309         mdelay(1);
4310
4311         spin_unlock_irq(&mchdev_lock);
4312 }
4313
4314 /* There's a funny hw issue where the hw returns all 0 when reading from
4315  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4316  * ourselves, instead of doing a rmw cycle (which might result in us clearing
4317  * all limits and the gpu stuck at whatever frequency it is at atm).
4318  */
4319 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4320 {
4321         u32 limits;
4322
4323         /* Only set the down limit when we've reached the lowest level to avoid
4324          * getting more interrupts, otherwise leave this clear. This prevents a
4325          * race in the hw when coming out of rc6: There's a tiny window where
4326          * the hw runs at the minimal clock before selecting the desired
4327          * frequency, if the down threshold expires in that window we will not
4328          * receive a down interrupt. */
4329         if (IS_GEN9(dev_priv->dev)) {
4330                 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4331                 if (val <= dev_priv->rps.min_freq_softlimit)
4332                         limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4333         } else {
4334                 limits = dev_priv->rps.max_freq_softlimit << 24;
4335                 if (val <= dev_priv->rps.min_freq_softlimit)
4336                         limits |= dev_priv->rps.min_freq_softlimit << 16;
4337         }
4338
4339         return limits;
4340 }
4341
4342 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4343 {
4344         int new_power;
4345         u32 threshold_up = 0, threshold_down = 0; /* in % */
4346         u32 ei_up = 0, ei_down = 0;
4347
4348         new_power = dev_priv->rps.power;
4349         switch (dev_priv->rps.power) {
4350         case LOW_POWER:
4351                 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
4352                         new_power = BETWEEN;
4353                 break;
4354
4355         case BETWEEN:
4356                 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
4357                         new_power = LOW_POWER;
4358                 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
4359                         new_power = HIGH_POWER;
4360                 break;
4361
4362         case HIGH_POWER:
4363                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
4364                         new_power = BETWEEN;
4365                 break;
4366         }
4367         /* Max/min bins are special */
4368         if (val <= dev_priv->rps.min_freq_softlimit)
4369                 new_power = LOW_POWER;
4370         if (val >= dev_priv->rps.max_freq_softlimit)
4371                 new_power = HIGH_POWER;
4372         if (new_power == dev_priv->rps.power)
4373                 return;
4374
4375         /* Note the units here are not exactly 1us, but 1280ns. */
4376         switch (new_power) {
4377         case LOW_POWER:
4378                 /* Upclock if more than 95% busy over 16ms */
4379                 ei_up = 16000;
4380                 threshold_up = 95;
4381
4382                 /* Downclock if less than 85% busy over 32ms */
4383                 ei_down = 32000;
4384                 threshold_down = 85;
4385                 break;
4386
4387         case BETWEEN:
4388                 /* Upclock if more than 90% busy over 13ms */
4389                 ei_up = 13000;
4390                 threshold_up = 90;
4391
4392                 /* Downclock if less than 75% busy over 32ms */
4393                 ei_down = 32000;
4394                 threshold_down = 75;
4395                 break;
4396
4397         case HIGH_POWER:
4398                 /* Upclock if more than 85% busy over 10ms */
4399                 ei_up = 10000;
4400                 threshold_up = 85;
4401
4402                 /* Downclock if less than 60% busy over 32ms */
4403                 ei_down = 32000;
4404                 threshold_down = 60;
4405                 break;
4406         }
4407
4408         I915_WRITE(GEN6_RP_UP_EI,
4409                 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4410         I915_WRITE(GEN6_RP_UP_THRESHOLD,
4411                 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4412
4413         I915_WRITE(GEN6_RP_DOWN_EI,
4414                 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4415         I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4416                 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4417
4418          I915_WRITE(GEN6_RP_CONTROL,
4419                     GEN6_RP_MEDIA_TURBO |
4420                     GEN6_RP_MEDIA_HW_NORMAL_MODE |
4421                     GEN6_RP_MEDIA_IS_GFX |
4422                     GEN6_RP_ENABLE |
4423                     GEN6_RP_UP_BUSY_AVG |
4424                     GEN6_RP_DOWN_IDLE_AVG);
4425
4426         dev_priv->rps.power = new_power;
4427         dev_priv->rps.up_threshold = threshold_up;
4428         dev_priv->rps.down_threshold = threshold_down;
4429         dev_priv->rps.last_adj = 0;
4430 }
4431
4432 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4433 {
4434         u32 mask = 0;
4435
4436         if (val > dev_priv->rps.min_freq_softlimit)
4437                 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4438         if (val < dev_priv->rps.max_freq_softlimit)
4439                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4440
4441         mask &= dev_priv->pm_rps_events;
4442
4443         return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4444 }
4445
4446 /* gen6_set_rps is called to update the frequency request, but should also be
4447  * called when the range (min_delay and max_delay) is modified so that we can
4448  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4449 static void gen6_set_rps(struct drm_device *dev, u8 val)
4450 {
4451         struct drm_i915_private *dev_priv = dev->dev_private;
4452
4453         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4454         WARN_ON(val > dev_priv->rps.max_freq);
4455         WARN_ON(val < dev_priv->rps.min_freq);
4456
4457         /* min/max delay may still have been modified so be sure to
4458          * write the limits value.
4459          */
4460         if (val != dev_priv->rps.cur_freq) {
4461                 gen6_set_rps_thresholds(dev_priv, val);
4462
4463                 if (IS_GEN9(dev))
4464                         I915_WRITE(GEN6_RPNSWREQ,
4465                                    GEN9_FREQUENCY(val));
4466                 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4467                         I915_WRITE(GEN6_RPNSWREQ,
4468                                    HSW_FREQUENCY(val));
4469                 else
4470                         I915_WRITE(GEN6_RPNSWREQ,
4471                                    GEN6_FREQUENCY(val) |
4472                                    GEN6_OFFSET(0) |
4473                                    GEN6_AGGRESSIVE_TURBO);
4474         }
4475
4476         /* Make sure we continue to get interrupts
4477          * until we hit the minimum or maximum frequencies.
4478          */
4479         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4480         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4481
4482         POSTING_READ(GEN6_RPNSWREQ);
4483
4484         dev_priv->rps.cur_freq = val;
4485         trace_intel_gpu_freq_change(val * 50);
4486 }
4487
4488 static void valleyview_set_rps(struct drm_device *dev, u8 val)
4489 {
4490         struct drm_i915_private *dev_priv = dev->dev_private;
4491
4492         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4493         WARN_ON(val > dev_priv->rps.max_freq);
4494         WARN_ON(val < dev_priv->rps.min_freq);
4495
4496         if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4497                       "Odd GPU freq value\n"))
4498                 val &= ~1;
4499
4500         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4501
4502         if (val != dev_priv->rps.cur_freq) {
4503                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4504                 if (!IS_CHERRYVIEW(dev_priv))
4505                         gen6_set_rps_thresholds(dev_priv, val);
4506         }
4507
4508         dev_priv->rps.cur_freq = val;
4509         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4510 }
4511
4512 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4513  *
4514  * * If Gfx is Idle, then
4515  * 1. Forcewake Media well.
4516  * 2. Request idle freq.
4517  * 3. Release Forcewake of Media well.
4518 */
4519 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4520 {
4521         u32 val = dev_priv->rps.idle_freq;
4522
4523         if (dev_priv->rps.cur_freq <= val)
4524                 return;
4525
4526         /* Wake up the media well, as that takes a lot less
4527          * power than the Render well. */
4528         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4529         valleyview_set_rps(dev_priv->dev, val);
4530         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
4531 }
4532
4533 void gen6_rps_busy(struct drm_i915_private *dev_priv)
4534 {
4535         mutex_lock(&dev_priv->rps.hw_lock);
4536         if (dev_priv->rps.enabled) {
4537                 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4538                         gen6_rps_reset_ei(dev_priv);
4539                 I915_WRITE(GEN6_PMINTRMSK,
4540                            gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4541         }
4542         mutex_unlock(&dev_priv->rps.hw_lock);
4543 }
4544
4545 void gen6_rps_idle(struct drm_i915_private *dev_priv)
4546 {
4547         struct drm_device *dev = dev_priv->dev;
4548
4549         mutex_lock(&dev_priv->rps.hw_lock);
4550         if (dev_priv->rps.enabled) {
4551                 if (IS_VALLEYVIEW(dev))
4552                         vlv_set_rps_idle(dev_priv);
4553                 else
4554                         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4555                 dev_priv->rps.last_adj = 0;
4556                 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4557         }
4558         mutex_unlock(&dev_priv->rps.hw_lock);
4559
4560         spin_lock(&dev_priv->rps.client_lock);
4561         while (!list_empty(&dev_priv->rps.clients))
4562                 list_del_init(dev_priv->rps.clients.next);
4563         spin_unlock(&dev_priv->rps.client_lock);
4564 }
4565
4566 void gen6_rps_boost(struct drm_i915_private *dev_priv,
4567                     struct intel_rps_client *rps,
4568                     unsigned long submitted)
4569 {
4570         /* This is intentionally racy! We peek at the state here, then
4571          * validate inside the RPS worker.
4572          */
4573         if (!(dev_priv->mm.busy &&
4574               dev_priv->rps.enabled &&
4575               dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4576                 return;
4577
4578         /* Force a RPS boost (and don't count it against the client) if
4579          * the GPU is severely congested.
4580          */
4581         if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
4582                 rps = NULL;
4583
4584         spin_lock(&dev_priv->rps.client_lock);
4585         if (rps == NULL || list_empty(&rps->link)) {
4586                 spin_lock_irq(&dev_priv->irq_lock);
4587                 if (dev_priv->rps.interrupts_enabled) {
4588                         dev_priv->rps.client_boost = true;
4589                         queue_work(dev_priv->wq, &dev_priv->rps.work);
4590                 }
4591                 spin_unlock_irq(&dev_priv->irq_lock);
4592
4593                 if (rps != NULL) {
4594                         list_add(&rps->link, &dev_priv->rps.clients);
4595                         rps->boosts++;
4596                 } else
4597                         dev_priv->rps.boosts++;
4598         }
4599         spin_unlock(&dev_priv->rps.client_lock);
4600 }
4601
4602 void intel_set_rps(struct drm_device *dev, u8 val)
4603 {
4604         if (IS_VALLEYVIEW(dev))
4605                 valleyview_set_rps(dev, val);
4606         else
4607                 gen6_set_rps(dev, val);
4608 }
4609
4610 static void gen9_disable_rps(struct drm_device *dev)
4611 {
4612         struct drm_i915_private *dev_priv = dev->dev_private;
4613
4614         I915_WRITE(GEN6_RC_CONTROL, 0);
4615         I915_WRITE(GEN9_PG_ENABLE, 0);
4616 }
4617
4618 static void gen6_disable_rps(struct drm_device *dev)
4619 {
4620         struct drm_i915_private *dev_priv = dev->dev_private;
4621
4622         I915_WRITE(GEN6_RC_CONTROL, 0);
4623         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
4624 }
4625
4626 static void cherryview_disable_rps(struct drm_device *dev)
4627 {
4628         struct drm_i915_private *dev_priv = dev->dev_private;
4629
4630         I915_WRITE(GEN6_RC_CONTROL, 0);
4631 }
4632
4633 static void valleyview_disable_rps(struct drm_device *dev)
4634 {
4635         struct drm_i915_private *dev_priv = dev->dev_private;
4636
4637         /* we're doing forcewake before Disabling RC6,
4638          * This what the BIOS expects when going into suspend */
4639         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4640
4641         I915_WRITE(GEN6_RC_CONTROL, 0);
4642
4643         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4644 }
4645
4646 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4647 {
4648         if (IS_VALLEYVIEW(dev)) {
4649                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4650                         mode = GEN6_RC_CTL_RC6_ENABLE;
4651                 else
4652                         mode = 0;
4653         }
4654         if (HAS_RC6p(dev))
4655                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4656                               (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4657                               (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4658                               (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4659
4660         else
4661                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4662                               (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
4663 }
4664
4665 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
4666 {
4667         /* No RC6 before Ironlake and code is gone for ilk. */
4668         if (INTEL_INFO(dev)->gen < 6)
4669                 return 0;
4670
4671         /* Respect the kernel parameter if it is set */
4672         if (enable_rc6 >= 0) {
4673                 int mask;
4674
4675                 if (HAS_RC6p(dev))
4676                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4677                                INTEL_RC6pp_ENABLE;
4678                 else
4679                         mask = INTEL_RC6_ENABLE;
4680
4681                 if ((enable_rc6 & mask) != enable_rc6)
4682                         DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4683                                       enable_rc6 & mask, enable_rc6, mask);
4684
4685                 return enable_rc6 & mask;
4686         }
4687
4688         if (IS_IVYBRIDGE(dev))
4689                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
4690
4691         return INTEL_RC6_ENABLE;
4692 }
4693
4694 int intel_enable_rc6(const struct drm_device *dev)
4695 {
4696         return i915.enable_rc6;
4697 }
4698
4699 static void gen6_init_rps_frequencies(struct drm_device *dev)
4700 {
4701         struct drm_i915_private *dev_priv = dev->dev_private;
4702         uint32_t rp_state_cap;
4703         u32 ddcc_status = 0;
4704         int ret;
4705
4706         /* All of these values are in units of 50MHz */
4707         dev_priv->rps.cur_freq          = 0;
4708         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
4709         if (IS_BROXTON(dev)) {
4710                 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4711                 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4712                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
4713                 dev_priv->rps.min_freq = (rp_state_cap >>  0) & 0xff;
4714         } else {
4715                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4716                 dev_priv->rps.rp0_freq = (rp_state_cap >>  0) & 0xff;
4717                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
4718                 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4719         }
4720
4721         /* hw_max = RP0 until we check for overclocking */
4722         dev_priv->rps.max_freq          = dev_priv->rps.rp0_freq;
4723
4724         dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4725         if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) {
4726                 ret = sandybridge_pcode_read(dev_priv,
4727                                         HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4728                                         &ddcc_status);
4729                 if (0 == ret)
4730                         dev_priv->rps.efficient_freq =
4731                                 clamp_t(u8,
4732                                         ((ddcc_status >> 8) & 0xff),
4733                                         dev_priv->rps.min_freq,
4734                                         dev_priv->rps.max_freq);
4735         }
4736
4737         if (IS_SKYLAKE(dev)) {
4738                 /* Store the frequency values in 16.66 MHZ units, which is
4739                    the natural hardware unit for SKL */
4740                 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4741                 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4742                 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4743                 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4744                 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4745         }
4746
4747         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4748
4749         /* Preserve min/max settings in case of re-init */
4750         if (dev_priv->rps.max_freq_softlimit == 0)
4751                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4752
4753         if (dev_priv->rps.min_freq_softlimit == 0) {
4754                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4755                         dev_priv->rps.min_freq_softlimit =
4756                                 max_t(int, dev_priv->rps.efficient_freq,
4757                                       intel_freq_opcode(dev_priv, 450));
4758                 else
4759                         dev_priv->rps.min_freq_softlimit =
4760                                 dev_priv->rps.min_freq;
4761         }
4762 }
4763
4764 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
4765 static void gen9_enable_rps(struct drm_device *dev)
4766 {
4767         struct drm_i915_private *dev_priv = dev->dev_private;
4768
4769         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4770
4771         gen6_init_rps_frequencies(dev);
4772
4773         /* Program defaults and thresholds for RPS*/
4774         I915_WRITE(GEN6_RC_VIDEO_FREQ,
4775                 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4776
4777         /* 1 second timeout*/
4778         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4779                 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4780
4781         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
4782
4783         /* Leaning on the below call to gen6_set_rps to program/setup the
4784          * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4785          * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4786         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4787         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
4788
4789         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4790 }
4791
4792 static void gen9_enable_rc6(struct drm_device *dev)
4793 {
4794         struct drm_i915_private *dev_priv = dev->dev_private;
4795         struct intel_engine_cs *ring;
4796         uint32_t rc6_mask = 0;
4797         int unused;
4798
4799         /* 1a: Software RC state - RC0 */
4800         I915_WRITE(GEN6_RC_STATE, 0);
4801
4802         /* 1b: Get forcewake during program sequence. Although the driver
4803          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4804         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4805
4806         /* 2a: Disable RC states. */
4807         I915_WRITE(GEN6_RC_CONTROL, 0);
4808
4809         /* 2b: Program RC6 thresholds.*/
4810         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4811         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4812         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4813         for_each_ring(ring, dev_priv, unused)
4814                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4815         I915_WRITE(GEN6_RC_SLEEP, 0);
4816         I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4817
4818         /* 2c: Program Coarse Power Gating Policies. */
4819         I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4820         I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4821
4822         /* 3a: Enable RC6 */
4823         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4824                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4825         DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4826                         "on" : "off");
4827         I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4828                                    GEN6_RC_CTL_EI_MODE(1) |
4829                                    rc6_mask);
4830
4831         /*
4832          * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4833          * WaDisableRenderPowerGating:skl,bxt - Render PG need to be disabled with RC6.
4834          */
4835         I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4836                         GEN9_MEDIA_PG_ENABLE : 0);
4837
4838
4839         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4840
4841 }
4842
4843 static void gen8_enable_rps(struct drm_device *dev)
4844 {
4845         struct drm_i915_private *dev_priv = dev->dev_private;
4846         struct intel_engine_cs *ring;
4847         uint32_t rc6_mask = 0;
4848         int unused;
4849
4850         /* 1a: Software RC state - RC0 */
4851         I915_WRITE(GEN6_RC_STATE, 0);
4852
4853         /* 1c & 1d: Get forcewake during program sequence. Although the driver
4854          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4855         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4856
4857         /* 2a: Disable RC states. */
4858         I915_WRITE(GEN6_RC_CONTROL, 0);
4859
4860         /* Initialize rps frequencies */
4861         gen6_init_rps_frequencies(dev);
4862
4863         /* 2b: Program RC6 thresholds.*/
4864         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4865         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4866         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4867         for_each_ring(ring, dev_priv, unused)
4868                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4869         I915_WRITE(GEN6_RC_SLEEP, 0);
4870         if (IS_BROADWELL(dev))
4871                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4872         else
4873                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4874
4875         /* 3: Enable RC6 */
4876         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4877                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4878         intel_print_rc6_info(dev, rc6_mask);
4879         if (IS_BROADWELL(dev))
4880                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4881                                 GEN7_RC_CTL_TO_MODE |
4882                                 rc6_mask);
4883         else
4884                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4885                                 GEN6_RC_CTL_EI_MODE(1) |
4886                                 rc6_mask);
4887
4888         /* 4 Program defaults and thresholds for RPS*/
4889         I915_WRITE(GEN6_RPNSWREQ,
4890                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4891         I915_WRITE(GEN6_RC_VIDEO_FREQ,
4892                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4893         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4894         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4895
4896         /* Docs recommend 900MHz, and 300 MHz respectively */
4897         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4898                    dev_priv->rps.max_freq_softlimit << 24 |
4899                    dev_priv->rps.min_freq_softlimit << 16);
4900
4901         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4902         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4903         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4904         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4905
4906         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4907
4908         /* 5: Enable RPS */
4909         I915_WRITE(GEN6_RP_CONTROL,
4910                    GEN6_RP_MEDIA_TURBO |
4911                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4912                    GEN6_RP_MEDIA_IS_GFX |
4913                    GEN6_RP_ENABLE |
4914                    GEN6_RP_UP_BUSY_AVG |
4915                    GEN6_RP_DOWN_IDLE_AVG);
4916
4917         /* 6: Ring frequency + overclocking (our driver does this later */
4918
4919         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4920         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4921
4922         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4923 }
4924
4925 static void gen6_enable_rps(struct drm_device *dev)
4926 {
4927         struct drm_i915_private *dev_priv = dev->dev_private;
4928         struct intel_engine_cs *ring;
4929         u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
4930         u32 gtfifodbg;
4931         int rc6_mode;
4932         int i, ret;
4933
4934         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4935
4936         /* Here begins a magic sequence of register writes to enable
4937          * auto-downclocking.
4938          *
4939          * Perhaps there might be some value in exposing these to
4940          * userspace...
4941          */
4942         I915_WRITE(GEN6_RC_STATE, 0);
4943
4944         /* Clear the DBG now so we don't confuse earlier errors */
4945         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4946                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4947                 I915_WRITE(GTFIFODBG, gtfifodbg);
4948         }
4949
4950         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4951
4952         /* Initialize rps frequencies */
4953         gen6_init_rps_frequencies(dev);
4954
4955         /* disable the counters and set deterministic thresholds */
4956         I915_WRITE(GEN6_RC_CONTROL, 0);
4957
4958         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4959         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4960         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4961         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4962         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4963
4964         for_each_ring(ring, dev_priv, i)
4965                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4966
4967         I915_WRITE(GEN6_RC_SLEEP, 0);
4968         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
4969         if (IS_IVYBRIDGE(dev))
4970                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4971         else
4972                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
4973         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
4974         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4975
4976         /* Check if we are enabling RC6 */
4977         rc6_mode = intel_enable_rc6(dev_priv->dev);
4978         if (rc6_mode & INTEL_RC6_ENABLE)
4979                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4980
4981         /* We don't use those on Haswell */
4982         if (!IS_HASWELL(dev)) {
4983                 if (rc6_mode & INTEL_RC6p_ENABLE)
4984                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
4985
4986                 if (rc6_mode & INTEL_RC6pp_ENABLE)
4987                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4988         }
4989
4990         intel_print_rc6_info(dev, rc6_mask);
4991
4992         I915_WRITE(GEN6_RC_CONTROL,
4993                    rc6_mask |
4994                    GEN6_RC_CTL_EI_MODE(1) |
4995                    GEN6_RC_CTL_HW_ENABLE);
4996
4997         /* Power down if completely idle for over 50ms */
4998         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
4999         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5000
5001         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
5002         if (ret)
5003                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
5004
5005         ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
5006         if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
5007                 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
5008                                  (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
5009                                  (pcu_mbox & 0xff) * 50);
5010                 dev_priv->rps.max_freq = pcu_mbox & 0xff;
5011         }
5012
5013         dev_priv->rps.power = HIGH_POWER; /* force a reset */
5014         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
5015
5016         rc6vids = 0;
5017         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5018         if (IS_GEN6(dev) && ret) {
5019                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5020         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5021                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5022                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5023                 rc6vids &= 0xffff00;
5024                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5025                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5026                 if (ret)
5027                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5028         }
5029
5030         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5031 }
5032
5033 static void __gen6_update_ring_freq(struct drm_device *dev)
5034 {
5035         struct drm_i915_private *dev_priv = dev->dev_private;
5036         int min_freq = 15;
5037         unsigned int gpu_freq;
5038         unsigned int max_ia_freq, min_ring_freq;
5039         unsigned int max_gpu_freq, min_gpu_freq;
5040         int scaling_factor = 180;
5041         struct cpufreq_policy *policy;
5042
5043         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5044
5045         policy = cpufreq_cpu_get(0);
5046         if (policy) {
5047                 max_ia_freq = policy->cpuinfo.max_freq;
5048                 cpufreq_cpu_put(policy);
5049         } else {
5050                 /*
5051                  * Default to measured freq if none found, PCU will ensure we
5052                  * don't go over
5053                  */
5054                 max_ia_freq = tsc_khz;
5055         }
5056
5057         /* Convert from kHz to MHz */
5058         max_ia_freq /= 1000;
5059
5060         min_ring_freq = I915_READ(DCLK) & 0xf;
5061         /* convert DDR frequency from units of 266.6MHz to bandwidth */
5062         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5063
5064         if (IS_SKYLAKE(dev)) {
5065                 /* Convert GT frequency to 50 HZ units */
5066                 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5067                 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5068         } else {
5069                 min_gpu_freq = dev_priv->rps.min_freq;
5070                 max_gpu_freq = dev_priv->rps.max_freq;
5071         }
5072
5073         /*
5074          * For each potential GPU frequency, load a ring frequency we'd like
5075          * to use for memory access.  We do this by specifying the IA frequency
5076          * the PCU should use as a reference to determine the ring frequency.
5077          */
5078         for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5079                 int diff = max_gpu_freq - gpu_freq;
5080                 unsigned int ia_freq = 0, ring_freq = 0;
5081
5082                 if (IS_SKYLAKE(dev)) {
5083                         /*
5084                          * ring_freq = 2 * GT. ring_freq is in 100MHz units
5085                          * No floor required for ring frequency on SKL.
5086                          */
5087                         ring_freq = gpu_freq;
5088                 } else if (INTEL_INFO(dev)->gen >= 8) {
5089                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
5090                         ring_freq = max(min_ring_freq, gpu_freq);
5091                 } else if (IS_HASWELL(dev)) {
5092                         ring_freq = mult_frac(gpu_freq, 5, 4);
5093                         ring_freq = max(min_ring_freq, ring_freq);
5094                         /* leave ia_freq as the default, chosen by cpufreq */
5095                 } else {
5096                         /* On older processors, there is no separate ring
5097                          * clock domain, so in order to boost the bandwidth
5098                          * of the ring, we need to upclock the CPU (ia_freq).
5099                          *
5100                          * For GPU frequencies less than 750MHz,
5101                          * just use the lowest ring freq.
5102                          */
5103                         if (gpu_freq < min_freq)
5104                                 ia_freq = 800;
5105                         else
5106                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5107                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5108                 }
5109
5110                 sandybridge_pcode_write(dev_priv,
5111                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5112                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5113                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5114                                         gpu_freq);
5115         }
5116 }
5117
5118 void gen6_update_ring_freq(struct drm_device *dev)
5119 {
5120         struct drm_i915_private *dev_priv = dev->dev_private;
5121
5122         if (!HAS_CORE_RING_FREQ(dev))
5123                 return;
5124
5125         mutex_lock(&dev_priv->rps.hw_lock);
5126         __gen6_update_ring_freq(dev);
5127         mutex_unlock(&dev_priv->rps.hw_lock);
5128 }
5129
5130 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5131 {
5132         struct drm_device *dev = dev_priv->dev;
5133         u32 val, rp0;
5134
5135         if (dev->pdev->revision >= 0x20) {
5136                 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5137
5138                 switch (INTEL_INFO(dev)->eu_total) {
5139                 case 8:
5140                                 /* (2 * 4) config */
5141                                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5142                                 break;
5143                 case 12:
5144                                 /* (2 * 6) config */
5145                                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5146                                 break;
5147                 case 16:
5148                                 /* (2 * 8) config */
5149                 default:
5150                                 /* Setting (2 * 8) Min RP0 for any other combination */
5151                                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5152                                 break;
5153                 }
5154                 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5155         } else {
5156                 /* For pre-production hardware */
5157                 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
5158                 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
5159                        PUNIT_GPU_STATUS_MAX_FREQ_MASK;
5160         }
5161         return rp0;
5162 }
5163
5164 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5165 {
5166         u32 val, rpe;
5167
5168         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5169         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5170
5171         return rpe;
5172 }
5173
5174 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5175 {
5176         struct drm_device *dev = dev_priv->dev;
5177         u32 val, rp1;
5178
5179         if (dev->pdev->revision >= 0x20) {
5180                 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5181                 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5182         } else {
5183                 /* For pre-production hardware */
5184                 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5185                 rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
5186                        PUNIT_GPU_STATUS_MAX_FREQ_MASK);
5187         }
5188         return rp1;
5189 }
5190
5191 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5192 {
5193         u32 val, rp1;
5194
5195         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5196
5197         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5198
5199         return rp1;
5200 }
5201
5202 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5203 {
5204         u32 val, rp0;
5205
5206         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5207
5208         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5209         /* Clamp to max */
5210         rp0 = min_t(u32, rp0, 0xea);
5211
5212         return rp0;
5213 }
5214
5215 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5216 {
5217         u32 val, rpe;
5218
5219         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5220         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5221         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5222         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5223
5224         return rpe;
5225 }
5226
5227 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5228 {
5229         return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5230 }
5231
5232 /* Check that the pctx buffer wasn't move under us. */
5233 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5234 {
5235         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5236
5237         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5238                              dev_priv->vlv_pctx->stolen->start);
5239 }
5240
5241
5242 /* Check that the pcbr address is not empty. */
5243 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5244 {
5245         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5246
5247         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5248 }
5249
5250 static void cherryview_setup_pctx(struct drm_device *dev)
5251 {
5252         struct drm_i915_private *dev_priv = dev->dev_private;
5253         unsigned long pctx_paddr, paddr;
5254         struct i915_gtt *gtt = &dev_priv->gtt;
5255         u32 pcbr;
5256         int pctx_size = 32*1024;
5257
5258         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5259
5260         pcbr = I915_READ(VLV_PCBR);
5261         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5262                 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5263                 paddr = (dev_priv->mm.stolen_base +
5264                          (gtt->stolen_size - pctx_size));
5265
5266                 pctx_paddr = (paddr & (~4095));
5267                 I915_WRITE(VLV_PCBR, pctx_paddr);
5268         }
5269
5270         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5271 }
5272
5273 static void valleyview_setup_pctx(struct drm_device *dev)
5274 {
5275         struct drm_i915_private *dev_priv = dev->dev_private;
5276         struct drm_i915_gem_object *pctx;
5277         unsigned long pctx_paddr;
5278         u32 pcbr;
5279         int pctx_size = 24*1024;
5280
5281         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5282
5283         pcbr = I915_READ(VLV_PCBR);
5284         if (pcbr) {
5285                 /* BIOS set it up already, grab the pre-alloc'd space */
5286                 int pcbr_offset;
5287
5288                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5289                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5290                                                                       pcbr_offset,
5291                                                                       I915_GTT_OFFSET_NONE,
5292                                                                       pctx_size);
5293                 goto out;
5294         }
5295
5296         DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5297
5298         /*
5299          * From the Gunit register HAS:
5300          * The Gfx driver is expected to program this register and ensure
5301          * proper allocation within Gfx stolen memory.  For example, this
5302          * register should be programmed such than the PCBR range does not
5303          * overlap with other ranges, such as the frame buffer, protected
5304          * memory, or any other relevant ranges.
5305          */
5306         pctx = i915_gem_object_create_stolen(dev, pctx_size);
5307         if (!pctx) {
5308                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5309                 return;
5310         }
5311
5312         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5313         I915_WRITE(VLV_PCBR, pctx_paddr);
5314
5315 out:
5316         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5317         dev_priv->vlv_pctx = pctx;
5318 }
5319
5320 static void valleyview_cleanup_pctx(struct drm_device *dev)
5321 {
5322         struct drm_i915_private *dev_priv = dev->dev_private;
5323
5324         if (WARN_ON(!dev_priv->vlv_pctx))
5325                 return;
5326
5327         drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
5328         dev_priv->vlv_pctx = NULL;
5329 }
5330
5331 static void valleyview_init_gt_powersave(struct drm_device *dev)
5332 {
5333         struct drm_i915_private *dev_priv = dev->dev_private;
5334         u32 val;
5335
5336         valleyview_setup_pctx(dev);
5337
5338         mutex_lock(&dev_priv->rps.hw_lock);
5339
5340         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5341         switch ((val >> 6) & 3) {
5342         case 0:
5343         case 1:
5344                 dev_priv->mem_freq = 800;
5345                 break;
5346         case 2:
5347                 dev_priv->mem_freq = 1066;
5348                 break;
5349         case 3:
5350                 dev_priv->mem_freq = 1333;
5351                 break;
5352         }
5353         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5354
5355         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5356         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5357         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5358                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5359                          dev_priv->rps.max_freq);
5360
5361         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5362         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5363                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5364                          dev_priv->rps.efficient_freq);
5365
5366         dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5367         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5368                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5369                          dev_priv->rps.rp1_freq);
5370
5371         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5372         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5373                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5374                          dev_priv->rps.min_freq);
5375
5376         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5377
5378         /* Preserve min/max settings in case of re-init */
5379         if (dev_priv->rps.max_freq_softlimit == 0)
5380                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5381
5382         if (dev_priv->rps.min_freq_softlimit == 0)
5383                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5384
5385         mutex_unlock(&dev_priv->rps.hw_lock);
5386 }
5387
5388 static void cherryview_init_gt_powersave(struct drm_device *dev)
5389 {
5390         struct drm_i915_private *dev_priv = dev->dev_private;
5391         u32 val;
5392
5393         cherryview_setup_pctx(dev);
5394
5395         mutex_lock(&dev_priv->rps.hw_lock);
5396
5397         mutex_lock(&dev_priv->sb_lock);
5398         val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5399         mutex_unlock(&dev_priv->sb_lock);
5400
5401         switch ((val >> 2) & 0x7) {
5402         case 0:
5403         case 1:
5404                 dev_priv->rps.cz_freq = 200;
5405                 dev_priv->mem_freq = 1600;
5406                 break;
5407         case 2:
5408                 dev_priv->rps.cz_freq = 267;
5409                 dev_priv->mem_freq = 1600;
5410                 break;
5411         case 3:
5412                 dev_priv->rps.cz_freq = 333;
5413                 dev_priv->mem_freq = 2000;
5414                 break;
5415         case 4:
5416                 dev_priv->rps.cz_freq = 320;
5417                 dev_priv->mem_freq = 1600;
5418                 break;
5419         case 5:
5420                 dev_priv->rps.cz_freq = 400;
5421                 dev_priv->mem_freq = 1600;
5422                 break;
5423         }
5424         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5425
5426         dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5427         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5428         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5429                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5430                          dev_priv->rps.max_freq);
5431
5432         dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5433         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5434                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5435                          dev_priv->rps.efficient_freq);
5436
5437         dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5438         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5439                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5440                          dev_priv->rps.rp1_freq);
5441
5442         /* PUnit validated range is only [RPe, RP0] */
5443         dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5444         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5445                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5446                          dev_priv->rps.min_freq);
5447
5448         WARN_ONCE((dev_priv->rps.max_freq |
5449                    dev_priv->rps.efficient_freq |
5450                    dev_priv->rps.rp1_freq |
5451                    dev_priv->rps.min_freq) & 1,
5452                   "Odd GPU freq values\n");
5453
5454         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5455
5456         /* Preserve min/max settings in case of re-init */
5457         if (dev_priv->rps.max_freq_softlimit == 0)
5458                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5459
5460         if (dev_priv->rps.min_freq_softlimit == 0)
5461                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5462
5463         mutex_unlock(&dev_priv->rps.hw_lock);
5464 }
5465
5466 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5467 {
5468         valleyview_cleanup_pctx(dev);
5469 }
5470
5471 static void cherryview_enable_rps(struct drm_device *dev)
5472 {
5473         struct drm_i915_private *dev_priv = dev->dev_private;
5474         struct intel_engine_cs *ring;
5475         u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5476         int i;
5477
5478         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5479
5480         gtfifodbg = I915_READ(GTFIFODBG);
5481         if (gtfifodbg) {
5482                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5483                                  gtfifodbg);
5484                 I915_WRITE(GTFIFODBG, gtfifodbg);
5485         }
5486
5487         cherryview_check_pctx(dev_priv);
5488
5489         /* 1a & 1b: Get forcewake during program sequence. Although the driver
5490          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5491         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5492
5493         /*  Disable RC states. */
5494         I915_WRITE(GEN6_RC_CONTROL, 0);
5495
5496         /* 2a: Program RC6 thresholds.*/
5497         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5498         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5499         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5500
5501         for_each_ring(ring, dev_priv, i)
5502                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5503         I915_WRITE(GEN6_RC_SLEEP, 0);
5504
5505         /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5506         I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
5507
5508         /* allows RC6 residency counter to work */
5509         I915_WRITE(VLV_COUNTER_CONTROL,
5510                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5511                                       VLV_MEDIA_RC6_COUNT_EN |
5512                                       VLV_RENDER_RC6_COUNT_EN));
5513
5514         /* For now we assume BIOS is allocating and populating the PCBR  */
5515         pcbr = I915_READ(VLV_PCBR);
5516
5517         /* 3: Enable RC6 */
5518         if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5519                                                 (pcbr >> VLV_PCBR_ADDR_SHIFT))
5520                 rc6_mode = GEN7_RC_CTL_TO_MODE;
5521
5522         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5523
5524         /* 4 Program defaults and thresholds for RPS*/
5525         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5526         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5527         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5528         I915_WRITE(GEN6_RP_UP_EI, 66000);
5529         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5530
5531         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5532
5533         /* 5: Enable RPS */
5534         I915_WRITE(GEN6_RP_CONTROL,
5535                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5536                    GEN6_RP_MEDIA_IS_GFX |
5537                    GEN6_RP_ENABLE |
5538                    GEN6_RP_UP_BUSY_AVG |
5539                    GEN6_RP_DOWN_IDLE_AVG);
5540
5541         /* Setting Fixed Bias */
5542         val = VLV_OVERRIDE_EN |
5543                   VLV_SOC_TDP_EN |
5544                   CHV_BIAS_CPU_50_SOC_50;
5545         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5546
5547         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5548
5549         /* RPS code assumes GPLL is used */
5550         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5551
5552         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
5553         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5554
5555         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5556         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5557                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5558                          dev_priv->rps.cur_freq);
5559
5560         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5561                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5562                          dev_priv->rps.efficient_freq);
5563
5564         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5565
5566         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5567 }
5568
5569 static void valleyview_enable_rps(struct drm_device *dev)
5570 {
5571         struct drm_i915_private *dev_priv = dev->dev_private;
5572         struct intel_engine_cs *ring;
5573         u32 gtfifodbg, val, rc6_mode = 0;
5574         int i;
5575
5576         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5577
5578         valleyview_check_pctx(dev_priv);
5579
5580         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
5581                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5582                                  gtfifodbg);
5583                 I915_WRITE(GTFIFODBG, gtfifodbg);
5584         }
5585
5586         /* If VLV, Forcewake all wells, else re-direct to regular path */
5587         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5588
5589         /*  Disable RC states. */
5590         I915_WRITE(GEN6_RC_CONTROL, 0);
5591
5592         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5593         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5594         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5595         I915_WRITE(GEN6_RP_UP_EI, 66000);
5596         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5597
5598         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5599
5600         I915_WRITE(GEN6_RP_CONTROL,
5601                    GEN6_RP_MEDIA_TURBO |
5602                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5603                    GEN6_RP_MEDIA_IS_GFX |
5604                    GEN6_RP_ENABLE |
5605                    GEN6_RP_UP_BUSY_AVG |
5606                    GEN6_RP_DOWN_IDLE_CONT);
5607
5608         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5609         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5610         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5611
5612         for_each_ring(ring, dev_priv, i)
5613                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5614
5615         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
5616
5617         /* allows RC6 residency counter to work */
5618         I915_WRITE(VLV_COUNTER_CONTROL,
5619                    _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5620                                       VLV_RENDER_RC0_COUNT_EN |
5621                                       VLV_MEDIA_RC6_COUNT_EN |
5622                                       VLV_RENDER_RC6_COUNT_EN));
5623
5624         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
5625                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
5626
5627         intel_print_rc6_info(dev, rc6_mode);
5628
5629         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5630
5631         /* Setting Fixed Bias */
5632         val = VLV_OVERRIDE_EN |
5633                   VLV_SOC_TDP_EN |
5634                   VLV_BIAS_CPU_125_SOC_875;
5635         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5636
5637         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5638
5639         /* RPS code assumes GPLL is used */
5640         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5641
5642         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
5643         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5644
5645         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5646         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5647                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5648                          dev_priv->rps.cur_freq);
5649
5650         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5651                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5652                          dev_priv->rps.efficient_freq);
5653
5654         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5655
5656         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5657 }
5658
5659 static unsigned long intel_pxfreq(u32 vidfreq)
5660 {
5661         unsigned long freq;
5662         int div = (vidfreq & 0x3f0000) >> 16;
5663         int post = (vidfreq & 0x3000) >> 12;
5664         int pre = (vidfreq & 0x7);
5665
5666         if (!pre)
5667                 return 0;
5668
5669         freq = ((div * 133333) / ((1<<post) * pre));
5670
5671         return freq;
5672 }
5673
5674 static const struct cparams {
5675         u16 i;
5676         u16 t;
5677         u16 m;
5678         u16 c;
5679 } cparams[] = {
5680         { 1, 1333, 301, 28664 },
5681         { 1, 1066, 294, 24460 },
5682         { 1, 800, 294, 25192 },
5683         { 0, 1333, 276, 27605 },
5684         { 0, 1066, 276, 27605 },
5685         { 0, 800, 231, 23784 },
5686 };
5687
5688 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
5689 {
5690         u64 total_count, diff, ret;
5691         u32 count1, count2, count3, m = 0, c = 0;
5692         unsigned long now = jiffies_to_msecs(jiffies), diff1;
5693         int i;
5694
5695         assert_spin_locked(&mchdev_lock);
5696
5697         diff1 = now - dev_priv->ips.last_time1;
5698
5699         /* Prevent division-by-zero if we are asking too fast.
5700          * Also, we don't get interesting results if we are polling
5701          * faster than once in 10ms, so just return the saved value
5702          * in such cases.
5703          */
5704         if (diff1 <= 10)
5705                 return dev_priv->ips.chipset_power;
5706
5707         count1 = I915_READ(DMIEC);
5708         count2 = I915_READ(DDREC);
5709         count3 = I915_READ(CSIEC);
5710
5711         total_count = count1 + count2 + count3;
5712
5713         /* FIXME: handle per-counter overflow */
5714         if (total_count < dev_priv->ips.last_count1) {
5715                 diff = ~0UL - dev_priv->ips.last_count1;
5716                 diff += total_count;
5717         } else {
5718                 diff = total_count - dev_priv->ips.last_count1;
5719         }
5720
5721         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
5722                 if (cparams[i].i == dev_priv->ips.c_m &&
5723                     cparams[i].t == dev_priv->ips.r_t) {
5724                         m = cparams[i].m;
5725                         c = cparams[i].c;
5726                         break;
5727                 }
5728         }
5729
5730         diff = div_u64(diff, diff1);
5731         ret = ((m * diff) + c);
5732         ret = div_u64(ret, 10);
5733
5734         dev_priv->ips.last_count1 = total_count;
5735         dev_priv->ips.last_time1 = now;
5736
5737         dev_priv->ips.chipset_power = ret;
5738
5739         return ret;
5740 }
5741
5742 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5743 {
5744         struct drm_device *dev = dev_priv->dev;
5745         unsigned long val;
5746
5747         if (INTEL_INFO(dev)->gen != 5)
5748                 return 0;
5749
5750         spin_lock_irq(&mchdev_lock);
5751
5752         val = __i915_chipset_val(dev_priv);
5753
5754         spin_unlock_irq(&mchdev_lock);
5755
5756         return val;
5757 }
5758
5759 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5760 {
5761         unsigned long m, x, b;
5762         u32 tsfs;
5763
5764         tsfs = I915_READ(TSFS);
5765
5766         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5767         x = I915_READ8(TR1);
5768
5769         b = tsfs & TSFS_INTR_MASK;
5770
5771         return ((m * x) / 127) - b;
5772 }
5773
5774 static int _pxvid_to_vd(u8 pxvid)
5775 {
5776         if (pxvid == 0)
5777                 return 0;
5778
5779         if (pxvid >= 8 && pxvid < 31)
5780                 pxvid = 31;
5781
5782         return (pxvid + 2) * 125;
5783 }
5784
5785 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
5786 {
5787         struct drm_device *dev = dev_priv->dev;
5788         const int vd = _pxvid_to_vd(pxvid);
5789         const int vm = vd - 1125;
5790
5791         if (INTEL_INFO(dev)->is_mobile)
5792                 return vm > 0 ? vm : 0;
5793
5794         return vd;
5795 }
5796
5797 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
5798 {
5799         u64 now, diff, diffms;
5800         u32 count;
5801
5802         assert_spin_locked(&mchdev_lock);
5803
5804         now = ktime_get_raw_ns();
5805         diffms = now - dev_priv->ips.last_time2;
5806         do_div(diffms, NSEC_PER_MSEC);
5807
5808         /* Don't divide by 0 */
5809         if (!diffms)
5810                 return;
5811
5812         count = I915_READ(GFXEC);
5813
5814         if (count < dev_priv->ips.last_count2) {
5815                 diff = ~0UL - dev_priv->ips.last_count2;
5816                 diff += count;
5817         } else {
5818                 diff = count - dev_priv->ips.last_count2;
5819         }
5820
5821         dev_priv->ips.last_count2 = count;
5822         dev_priv->ips.last_time2 = now;
5823
5824         /* More magic constants... */
5825         diff = diff * 1181;
5826         diff = div_u64(diff, diffms * 10);
5827         dev_priv->ips.gfx_power = diff;
5828 }
5829
5830 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5831 {
5832         struct drm_device *dev = dev_priv->dev;
5833
5834         if (INTEL_INFO(dev)->gen != 5)
5835                 return;
5836
5837         spin_lock_irq(&mchdev_lock);
5838
5839         __i915_update_gfx_val(dev_priv);
5840
5841         spin_unlock_irq(&mchdev_lock);
5842 }
5843
5844 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
5845 {
5846         unsigned long t, corr, state1, corr2, state2;
5847         u32 pxvid, ext_v;
5848
5849         assert_spin_locked(&mchdev_lock);
5850
5851         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
5852         pxvid = (pxvid >> 24) & 0x7f;
5853         ext_v = pvid_to_extvid(dev_priv, pxvid);
5854
5855         state1 = ext_v;
5856
5857         t = i915_mch_val(dev_priv);
5858
5859         /* Revel in the empirically derived constants */
5860
5861         /* Correction factor in 1/100000 units */
5862         if (t > 80)
5863                 corr = ((t * 2349) + 135940);
5864         else if (t >= 50)
5865                 corr = ((t * 964) + 29317);
5866         else /* < 50 */
5867                 corr = ((t * 301) + 1004);
5868
5869         corr = corr * ((150142 * state1) / 10000 - 78642);
5870         corr /= 100000;
5871         corr2 = (corr * dev_priv->ips.corr);
5872
5873         state2 = (corr2 * state1) / 10000;
5874         state2 /= 100; /* convert to mW */
5875
5876         __i915_update_gfx_val(dev_priv);
5877
5878         return dev_priv->ips.gfx_power + state2;
5879 }
5880
5881 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5882 {
5883         struct drm_device *dev = dev_priv->dev;
5884         unsigned long val;
5885
5886         if (INTEL_INFO(dev)->gen != 5)
5887                 return 0;
5888
5889         spin_lock_irq(&mchdev_lock);
5890
5891         val = __i915_gfx_val(dev_priv);
5892
5893         spin_unlock_irq(&mchdev_lock);
5894
5895         return val;
5896 }
5897
5898 /**
5899  * i915_read_mch_val - return value for IPS use
5900  *
5901  * Calculate and return a value for the IPS driver to use when deciding whether
5902  * we have thermal and power headroom to increase CPU or GPU power budget.
5903  */
5904 unsigned long i915_read_mch_val(void)
5905 {
5906         struct drm_i915_private *dev_priv;
5907         unsigned long chipset_val, graphics_val, ret = 0;
5908
5909         spin_lock_irq(&mchdev_lock);
5910         if (!i915_mch_dev)
5911                 goto out_unlock;
5912         dev_priv = i915_mch_dev;
5913
5914         chipset_val = __i915_chipset_val(dev_priv);
5915         graphics_val = __i915_gfx_val(dev_priv);
5916
5917         ret = chipset_val + graphics_val;
5918
5919 out_unlock:
5920         spin_unlock_irq(&mchdev_lock);
5921
5922         return ret;
5923 }
5924 EXPORT_SYMBOL_GPL(i915_read_mch_val);
5925
5926 /**
5927  * i915_gpu_raise - raise GPU frequency limit
5928  *
5929  * Raise the limit; IPS indicates we have thermal headroom.
5930  */
5931 bool i915_gpu_raise(void)
5932 {
5933         struct drm_i915_private *dev_priv;
5934         bool ret = true;
5935
5936         spin_lock_irq(&mchdev_lock);
5937         if (!i915_mch_dev) {
5938                 ret = false;
5939                 goto out_unlock;
5940         }
5941         dev_priv = i915_mch_dev;
5942
5943         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5944                 dev_priv->ips.max_delay--;
5945
5946 out_unlock:
5947         spin_unlock_irq(&mchdev_lock);
5948
5949         return ret;
5950 }
5951 EXPORT_SYMBOL_GPL(i915_gpu_raise);
5952
5953 /**
5954  * i915_gpu_lower - lower GPU frequency limit
5955  *
5956  * IPS indicates we're close to a thermal limit, so throttle back the GPU
5957  * frequency maximum.
5958  */
5959 bool i915_gpu_lower(void)
5960 {
5961         struct drm_i915_private *dev_priv;
5962         bool ret = true;
5963
5964         spin_lock_irq(&mchdev_lock);
5965         if (!i915_mch_dev) {
5966                 ret = false;
5967                 goto out_unlock;
5968         }
5969         dev_priv = i915_mch_dev;
5970
5971         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5972                 dev_priv->ips.max_delay++;
5973
5974 out_unlock:
5975         spin_unlock_irq(&mchdev_lock);
5976
5977         return ret;
5978 }
5979 EXPORT_SYMBOL_GPL(i915_gpu_lower);
5980
5981 /**
5982  * i915_gpu_busy - indicate GPU business to IPS
5983  *
5984  * Tell the IPS driver whether or not the GPU is busy.
5985  */
5986 bool i915_gpu_busy(void)
5987 {
5988         struct drm_i915_private *dev_priv;
5989         struct intel_engine_cs *ring;
5990         bool ret = false;
5991         int i;
5992
5993         spin_lock_irq(&mchdev_lock);
5994         if (!i915_mch_dev)
5995                 goto out_unlock;
5996         dev_priv = i915_mch_dev;
5997
5998         for_each_ring(ring, dev_priv, i)
5999                 ret |= !list_empty(&ring->request_list);
6000
6001 out_unlock:
6002         spin_unlock_irq(&mchdev_lock);
6003
6004         return ret;
6005 }
6006 EXPORT_SYMBOL_GPL(i915_gpu_busy);
6007
6008 /**
6009  * i915_gpu_turbo_disable - disable graphics turbo
6010  *
6011  * Disable graphics turbo by resetting the max frequency and setting the
6012  * current frequency to the default.
6013  */
6014 bool i915_gpu_turbo_disable(void)
6015 {
6016         struct drm_i915_private *dev_priv;
6017         bool ret = true;
6018
6019         spin_lock_irq(&mchdev_lock);
6020         if (!i915_mch_dev) {
6021                 ret = false;
6022                 goto out_unlock;
6023         }
6024         dev_priv = i915_mch_dev;
6025
6026         dev_priv->ips.max_delay = dev_priv->ips.fstart;
6027
6028         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
6029                 ret = false;
6030
6031 out_unlock:
6032         spin_unlock_irq(&mchdev_lock);
6033
6034         return ret;
6035 }
6036 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6037
6038 /**
6039  * Tells the intel_ips driver that the i915 driver is now loaded, if
6040  * IPS got loaded first.
6041  *
6042  * This awkward dance is so that neither module has to depend on the
6043  * other in order for IPS to do the appropriate communication of
6044  * GPU turbo limits to i915.
6045  */
6046 static void
6047 ips_ping_for_i915_load(void)
6048 {
6049         void (*link)(void);
6050
6051         link = symbol_get(ips_link_to_i915_driver);
6052         if (link) {
6053                 link();
6054                 symbol_put(ips_link_to_i915_driver);
6055         }
6056 }
6057
6058 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6059 {
6060         /* We only register the i915 ips part with intel-ips once everything is
6061          * set up, to avoid intel-ips sneaking in and reading bogus values. */
6062         spin_lock_irq(&mchdev_lock);
6063         i915_mch_dev = dev_priv;
6064         spin_unlock_irq(&mchdev_lock);
6065
6066         ips_ping_for_i915_load();
6067 }
6068
6069 void intel_gpu_ips_teardown(void)
6070 {
6071         spin_lock_irq(&mchdev_lock);
6072         i915_mch_dev = NULL;
6073         spin_unlock_irq(&mchdev_lock);
6074 }
6075
6076 static void intel_init_emon(struct drm_device *dev)
6077 {
6078         struct drm_i915_private *dev_priv = dev->dev_private;
6079         u32 lcfuse;
6080         u8 pxw[16];
6081         int i;
6082
6083         /* Disable to program */
6084         I915_WRITE(ECR, 0);
6085         POSTING_READ(ECR);
6086
6087         /* Program energy weights for various events */
6088         I915_WRITE(SDEW, 0x15040d00);
6089         I915_WRITE(CSIEW0, 0x007f0000);
6090         I915_WRITE(CSIEW1, 0x1e220004);
6091         I915_WRITE(CSIEW2, 0x04000004);
6092
6093         for (i = 0; i < 5; i++)
6094                 I915_WRITE(PEW + (i * 4), 0);
6095         for (i = 0; i < 3; i++)
6096                 I915_WRITE(DEW + (i * 4), 0);
6097
6098         /* Program P-state weights to account for frequency power adjustment */
6099         for (i = 0; i < 16; i++) {
6100                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
6101                 unsigned long freq = intel_pxfreq(pxvidfreq);
6102                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6103                         PXVFREQ_PX_SHIFT;
6104                 unsigned long val;
6105
6106                 val = vid * vid;
6107                 val *= (freq / 1000);
6108                 val *= 255;
6109                 val /= (127*127*900);
6110                 if (val > 0xff)
6111                         DRM_ERROR("bad pxval: %ld\n", val);
6112                 pxw[i] = val;
6113         }
6114         /* Render standby states get 0 weight */
6115         pxw[14] = 0;
6116         pxw[15] = 0;
6117
6118         for (i = 0; i < 4; i++) {
6119                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6120                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6121                 I915_WRITE(PXW + (i * 4), val);
6122         }
6123
6124         /* Adjust magic regs to magic values (more experimental results) */
6125         I915_WRITE(OGW0, 0);
6126         I915_WRITE(OGW1, 0);
6127         I915_WRITE(EG0, 0x00007f00);
6128         I915_WRITE(EG1, 0x0000000e);
6129         I915_WRITE(EG2, 0x000e0000);
6130         I915_WRITE(EG3, 0x68000300);
6131         I915_WRITE(EG4, 0x42000000);
6132         I915_WRITE(EG5, 0x00140031);
6133         I915_WRITE(EG6, 0);
6134         I915_WRITE(EG7, 0);
6135
6136         for (i = 0; i < 8; i++)
6137                 I915_WRITE(PXWL + (i * 4), 0);
6138
6139         /* Enable PMON + select events */
6140         I915_WRITE(ECR, 0x80000019);
6141
6142         lcfuse = I915_READ(LCFUSE02);
6143
6144         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6145 }
6146
6147 void intel_init_gt_powersave(struct drm_device *dev)
6148 {
6149         i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
6150
6151         if (IS_CHERRYVIEW(dev))
6152                 cherryview_init_gt_powersave(dev);
6153         else if (IS_VALLEYVIEW(dev))
6154                 valleyview_init_gt_powersave(dev);
6155 }
6156
6157 void intel_cleanup_gt_powersave(struct drm_device *dev)
6158 {
6159         if (IS_CHERRYVIEW(dev))
6160                 return;
6161         else if (IS_VALLEYVIEW(dev))
6162                 valleyview_cleanup_gt_powersave(dev);
6163 }
6164
6165 static void gen6_suspend_rps(struct drm_device *dev)
6166 {
6167         struct drm_i915_private *dev_priv = dev->dev_private;
6168
6169         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6170
6171         gen6_disable_rps_interrupts(dev);
6172 }
6173
6174 /**
6175  * intel_suspend_gt_powersave - suspend PM work and helper threads
6176  * @dev: drm device
6177  *
6178  * We don't want to disable RC6 or other features here, we just want
6179  * to make sure any work we've queued has finished and won't bother
6180  * us while we're suspended.
6181  */
6182 void intel_suspend_gt_powersave(struct drm_device *dev)
6183 {
6184         struct drm_i915_private *dev_priv = dev->dev_private;
6185
6186         if (INTEL_INFO(dev)->gen < 6)
6187                 return;
6188
6189         gen6_suspend_rps(dev);
6190
6191         /* Force GPU to min freq during suspend */
6192         gen6_rps_idle(dev_priv);
6193 }
6194
6195 void intel_disable_gt_powersave(struct drm_device *dev)
6196 {
6197         struct drm_i915_private *dev_priv = dev->dev_private;
6198
6199         if (IS_IRONLAKE_M(dev)) {
6200                 ironlake_disable_drps(dev);
6201         } else if (INTEL_INFO(dev)->gen >= 6) {
6202                 intel_suspend_gt_powersave(dev);
6203
6204                 mutex_lock(&dev_priv->rps.hw_lock);
6205                 if (INTEL_INFO(dev)->gen >= 9)
6206                         gen9_disable_rps(dev);
6207                 else if (IS_CHERRYVIEW(dev))
6208                         cherryview_disable_rps(dev);
6209                 else if (IS_VALLEYVIEW(dev))
6210                         valleyview_disable_rps(dev);
6211                 else
6212                         gen6_disable_rps(dev);
6213
6214                 dev_priv->rps.enabled = false;
6215                 mutex_unlock(&dev_priv->rps.hw_lock);
6216         }
6217 }
6218
6219 static void intel_gen6_powersave_work(struct work_struct *work)
6220 {
6221         struct drm_i915_private *dev_priv =
6222                 container_of(work, struct drm_i915_private,
6223                              rps.delayed_resume_work.work);
6224         struct drm_device *dev = dev_priv->dev;
6225
6226         mutex_lock(&dev_priv->rps.hw_lock);
6227
6228         gen6_reset_rps_interrupts(dev);
6229
6230         if (IS_CHERRYVIEW(dev)) {
6231                 cherryview_enable_rps(dev);
6232         } else if (IS_VALLEYVIEW(dev)) {
6233                 valleyview_enable_rps(dev);
6234         } else if (INTEL_INFO(dev)->gen >= 9) {
6235                 gen9_enable_rc6(dev);
6236                 gen9_enable_rps(dev);
6237                 if (IS_SKYLAKE(dev))
6238                         __gen6_update_ring_freq(dev);
6239         } else if (IS_BROADWELL(dev)) {
6240                 gen8_enable_rps(dev);
6241                 __gen6_update_ring_freq(dev);
6242         } else {
6243                 gen6_enable_rps(dev);
6244                 __gen6_update_ring_freq(dev);
6245         }
6246
6247         WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6248         WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6249
6250         WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6251         WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6252
6253         dev_priv->rps.enabled = true;
6254
6255         gen6_enable_rps_interrupts(dev);
6256
6257         mutex_unlock(&dev_priv->rps.hw_lock);
6258
6259         intel_runtime_pm_put(dev_priv);
6260 }
6261
6262 void intel_enable_gt_powersave(struct drm_device *dev)
6263 {
6264         struct drm_i915_private *dev_priv = dev->dev_private;
6265
6266         /* Powersaving is controlled by the host when inside a VM */
6267         if (intel_vgpu_active(dev))
6268                 return;
6269
6270         if (IS_IRONLAKE_M(dev)) {
6271                 mutex_lock(&dev->struct_mutex);
6272                 ironlake_enable_drps(dev);
6273                 intel_init_emon(dev);
6274                 mutex_unlock(&dev->struct_mutex);
6275         } else if (INTEL_INFO(dev)->gen >= 6) {
6276                 /*
6277                  * PCU communication is slow and this doesn't need to be
6278                  * done at any specific time, so do this out of our fast path
6279                  * to make resume and init faster.
6280                  *
6281                  * We depend on the HW RC6 power context save/restore
6282                  * mechanism when entering D3 through runtime PM suspend. So
6283                  * disable RPM until RPS/RC6 is properly setup. We can only
6284                  * get here via the driver load/system resume/runtime resume
6285                  * paths, so the _noresume version is enough (and in case of
6286                  * runtime resume it's necessary).
6287                  */
6288                 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6289                                            round_jiffies_up_relative(HZ)))
6290                         intel_runtime_pm_get_noresume(dev_priv);
6291         }
6292 }
6293
6294 void intel_reset_gt_powersave(struct drm_device *dev)
6295 {
6296         struct drm_i915_private *dev_priv = dev->dev_private;
6297
6298         if (INTEL_INFO(dev)->gen < 6)
6299                 return;
6300
6301         gen6_suspend_rps(dev);
6302         dev_priv->rps.enabled = false;
6303 }
6304
6305 static void ibx_init_clock_gating(struct drm_device *dev)
6306 {
6307         struct drm_i915_private *dev_priv = dev->dev_private;
6308
6309         /*
6310          * On Ibex Peak and Cougar Point, we need to disable clock
6311          * gating for the panel power sequencer or it will fail to
6312          * start up when no ports are active.
6313          */
6314         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6315 }
6316
6317 static void g4x_disable_trickle_feed(struct drm_device *dev)
6318 {
6319         struct drm_i915_private *dev_priv = dev->dev_private;
6320         enum pipe pipe;
6321
6322         for_each_pipe(dev_priv, pipe) {
6323                 I915_WRITE(DSPCNTR(pipe),
6324                            I915_READ(DSPCNTR(pipe)) |
6325                            DISPPLANE_TRICKLE_FEED_DISABLE);
6326
6327                 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6328                 POSTING_READ(DSPSURF(pipe));
6329         }
6330 }
6331
6332 static void ilk_init_lp_watermarks(struct drm_device *dev)
6333 {
6334         struct drm_i915_private *dev_priv = dev->dev_private;
6335
6336         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6337         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6338         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6339
6340         /*
6341          * Don't touch WM1S_LP_EN here.
6342          * Doing so could cause underruns.
6343          */
6344 }
6345
6346 static void ironlake_init_clock_gating(struct drm_device *dev)
6347 {
6348         struct drm_i915_private *dev_priv = dev->dev_private;
6349         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6350
6351         /*
6352          * Required for FBC
6353          * WaFbcDisableDpfcClockGating:ilk
6354          */
6355         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6356                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6357                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6358
6359         I915_WRITE(PCH_3DCGDIS0,
6360                    MARIUNIT_CLOCK_GATE_DISABLE |
6361                    SVSMUNIT_CLOCK_GATE_DISABLE);
6362         I915_WRITE(PCH_3DCGDIS1,
6363                    VFMUNIT_CLOCK_GATE_DISABLE);
6364
6365         /*
6366          * According to the spec the following bits should be set in
6367          * order to enable memory self-refresh
6368          * The bit 22/21 of 0x42004
6369          * The bit 5 of 0x42020
6370          * The bit 15 of 0x45000
6371          */
6372         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6373                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
6374                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6375         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6376         I915_WRITE(DISP_ARB_CTL,
6377                    (I915_READ(DISP_ARB_CTL) |
6378                     DISP_FBC_WM_DIS));
6379
6380         ilk_init_lp_watermarks(dev);
6381
6382         /*
6383          * Based on the document from hardware guys the following bits
6384          * should be set unconditionally in order to enable FBC.
6385          * The bit 22 of 0x42000
6386          * The bit 22 of 0x42004
6387          * The bit 7,8,9 of 0x42020.
6388          */
6389         if (IS_IRONLAKE_M(dev)) {
6390                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6391                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6392                            I915_READ(ILK_DISPLAY_CHICKEN1) |
6393                            ILK_FBCQ_DIS);
6394                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6395                            I915_READ(ILK_DISPLAY_CHICKEN2) |
6396                            ILK_DPARB_GATE);
6397         }
6398
6399         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6400
6401         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6402                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6403                    ILK_ELPIN_409_SELECT);
6404         I915_WRITE(_3D_CHICKEN2,
6405                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6406                    _3D_CHICKEN2_WM_READ_PIPELINED);
6407
6408         /* WaDisableRenderCachePipelinedFlush:ilk */
6409         I915_WRITE(CACHE_MODE_0,
6410                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6411
6412         /* WaDisable_RenderCache_OperationalFlush:ilk */
6413         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6414
6415         g4x_disable_trickle_feed(dev);
6416
6417         ibx_init_clock_gating(dev);
6418 }
6419
6420 static void cpt_init_clock_gating(struct drm_device *dev)
6421 {
6422         struct drm_i915_private *dev_priv = dev->dev_private;
6423         int pipe;
6424         uint32_t val;
6425
6426         /*
6427          * On Ibex Peak and Cougar Point, we need to disable clock
6428          * gating for the panel power sequencer or it will fail to
6429          * start up when no ports are active.
6430          */
6431         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6432                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6433                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
6434         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6435                    DPLS_EDP_PPS_FIX_DIS);
6436         /* The below fixes the weird display corruption, a few pixels shifted
6437          * downward, on (only) LVDS of some HP laptops with IVY.
6438          */
6439         for_each_pipe(dev_priv, pipe) {
6440                 val = I915_READ(TRANS_CHICKEN2(pipe));
6441                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6442                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6443                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6444                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6445                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6446                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6447                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6448                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6449         }
6450         /* WADP0ClockGatingDisable */
6451         for_each_pipe(dev_priv, pipe) {
6452                 I915_WRITE(TRANS_CHICKEN1(pipe),
6453                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6454         }
6455 }
6456
6457 static void gen6_check_mch_setup(struct drm_device *dev)
6458 {
6459         struct drm_i915_private *dev_priv = dev->dev_private;
6460         uint32_t tmp;
6461
6462         tmp = I915_READ(MCH_SSKPD);
6463         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6464                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6465                               tmp);
6466 }
6467
6468 static void gen6_init_clock_gating(struct drm_device *dev)
6469 {
6470         struct drm_i915_private *dev_priv = dev->dev_private;
6471         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6472
6473         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6474
6475         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6476                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6477                    ILK_ELPIN_409_SELECT);
6478
6479         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6480         I915_WRITE(_3D_CHICKEN,
6481                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6482
6483         /* WaDisable_RenderCache_OperationalFlush:snb */
6484         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6485
6486         /*
6487          * BSpec recoomends 8x4 when MSAA is used,
6488          * however in practice 16x4 seems fastest.
6489          *
6490          * Note that PS/WM thread counts depend on the WIZ hashing
6491          * disable bit, which we don't touch here, but it's good
6492          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6493          */
6494         I915_WRITE(GEN6_GT_MODE,
6495                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6496
6497         ilk_init_lp_watermarks(dev);
6498
6499         I915_WRITE(CACHE_MODE_0,
6500                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6501
6502         I915_WRITE(GEN6_UCGCTL1,
6503                    I915_READ(GEN6_UCGCTL1) |
6504                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6505                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6506
6507         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6508          * gating disable must be set.  Failure to set it results in
6509          * flickering pixels due to Z write ordering failures after
6510          * some amount of runtime in the Mesa "fire" demo, and Unigine
6511          * Sanctuary and Tropics, and apparently anything else with
6512          * alpha test or pixel discard.
6513          *
6514          * According to the spec, bit 11 (RCCUNIT) must also be set,
6515          * but we didn't debug actual testcases to find it out.
6516          *
6517          * WaDisableRCCUnitClockGating:snb
6518          * WaDisableRCPBUnitClockGating:snb
6519          */
6520         I915_WRITE(GEN6_UCGCTL2,
6521                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6522                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6523
6524         /* WaStripsFansDisableFastClipPerformanceFix:snb */
6525         I915_WRITE(_3D_CHICKEN3,
6526                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6527
6528         /*
6529          * Bspec says:
6530          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6531          * 3DSTATE_SF number of SF output attributes is more than 16."
6532          */
6533         I915_WRITE(_3D_CHICKEN3,
6534                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6535
6536         /*
6537          * According to the spec the following bits should be
6538          * set in order to enable memory self-refresh and fbc:
6539          * The bit21 and bit22 of 0x42000
6540          * The bit21 and bit22 of 0x42004
6541          * The bit5 and bit7 of 0x42020
6542          * The bit14 of 0x70180
6543          * The bit14 of 0x71180
6544          *
6545          * WaFbcAsynchFlipDisableFbcQueue:snb
6546          */
6547         I915_WRITE(ILK_DISPLAY_CHICKEN1,
6548                    I915_READ(ILK_DISPLAY_CHICKEN1) |
6549                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6550         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6551                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6552                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6553         I915_WRITE(ILK_DSPCLK_GATE_D,
6554                    I915_READ(ILK_DSPCLK_GATE_D) |
6555                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
6556                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6557
6558         g4x_disable_trickle_feed(dev);
6559
6560         cpt_init_clock_gating(dev);
6561
6562         gen6_check_mch_setup(dev);
6563 }
6564
6565 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6566 {
6567         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6568
6569         /*
6570          * WaVSThreadDispatchOverride:ivb,vlv
6571          *
6572          * This actually overrides the dispatch
6573          * mode for all thread types.
6574          */
6575         reg &= ~GEN7_FF_SCHED_MASK;
6576         reg |= GEN7_FF_TS_SCHED_HW;
6577         reg |= GEN7_FF_VS_SCHED_HW;
6578         reg |= GEN7_FF_DS_SCHED_HW;
6579
6580         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6581 }
6582
6583 static void lpt_init_clock_gating(struct drm_device *dev)
6584 {
6585         struct drm_i915_private *dev_priv = dev->dev_private;
6586
6587         /*
6588          * TODO: this bit should only be enabled when really needed, then
6589          * disabled when not needed anymore in order to save power.
6590          */
6591         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
6592                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6593                            I915_READ(SOUTH_DSPCLK_GATE_D) |
6594                            PCH_LP_PARTITION_LEVEL_DISABLE);
6595
6596         /* WADPOClockGatingDisable:hsw */
6597         I915_WRITE(_TRANSA_CHICKEN1,
6598                    I915_READ(_TRANSA_CHICKEN1) |
6599                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6600 }
6601
6602 static void lpt_suspend_hw(struct drm_device *dev)
6603 {
6604         struct drm_i915_private *dev_priv = dev->dev_private;
6605
6606         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6607                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6608
6609                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6610                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6611         }
6612 }
6613
6614 static void broadwell_init_clock_gating(struct drm_device *dev)
6615 {
6616         struct drm_i915_private *dev_priv = dev->dev_private;
6617         enum pipe pipe;
6618         uint32_t misccpctl;
6619
6620         ilk_init_lp_watermarks(dev);
6621
6622         /* WaSwitchSolVfFArbitrationPriority:bdw */
6623         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6624
6625         /* WaPsrDPAMaskVBlankInSRD:bdw */
6626         I915_WRITE(CHICKEN_PAR1_1,
6627                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6628
6629         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
6630         for_each_pipe(dev_priv, pipe) {
6631                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
6632                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
6633                            BDW_DPRS_MASK_VBLANK_SRD);
6634         }
6635
6636         /* WaVSRefCountFullforceMissDisable:bdw */
6637         /* WaDSRefCountFullforceMissDisable:bdw */
6638         I915_WRITE(GEN7_FF_THREAD_MODE,
6639                    I915_READ(GEN7_FF_THREAD_MODE) &
6640                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6641
6642         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6643                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6644
6645         /* WaDisableSDEUnitClockGating:bdw */
6646         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6647                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6648
6649         /*
6650          * WaProgramL3SqcReg1Default:bdw
6651          * WaTempDisableDOPClkGating:bdw
6652          */
6653         misccpctl = I915_READ(GEN7_MISCCPCTL);
6654         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6655         I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6656         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6657
6658         /*
6659          * WaGttCachingOffByDefault:bdw
6660          * GTT cache may not work with big pages, so if those
6661          * are ever enabled GTT cache may need to be disabled.
6662          */
6663         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6664
6665         lpt_init_clock_gating(dev);
6666 }
6667
6668 static void haswell_init_clock_gating(struct drm_device *dev)
6669 {
6670         struct drm_i915_private *dev_priv = dev->dev_private;
6671
6672         ilk_init_lp_watermarks(dev);
6673
6674         /* L3 caching of data atomics doesn't work -- disable it. */
6675         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6676         I915_WRITE(HSW_ROW_CHICKEN3,
6677                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6678
6679         /* This is required by WaCatErrorRejectionIssue:hsw */
6680         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6681                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6682                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6683
6684         /* WaVSRefCountFullforceMissDisable:hsw */
6685         I915_WRITE(GEN7_FF_THREAD_MODE,
6686                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
6687
6688         /* WaDisable_RenderCache_OperationalFlush:hsw */
6689         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6690
6691         /* enable HiZ Raw Stall Optimization */
6692         I915_WRITE(CACHE_MODE_0_GEN7,
6693                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6694
6695         /* WaDisable4x2SubspanOptimization:hsw */
6696         I915_WRITE(CACHE_MODE_1,
6697                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6698
6699         /*
6700          * BSpec recommends 8x4 when MSAA is used,
6701          * however in practice 16x4 seems fastest.
6702          *
6703          * Note that PS/WM thread counts depend on the WIZ hashing
6704          * disable bit, which we don't touch here, but it's good
6705          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6706          */
6707         I915_WRITE(GEN7_GT_MODE,
6708                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6709
6710         /* WaSampleCChickenBitEnable:hsw */
6711         I915_WRITE(HALF_SLICE_CHICKEN3,
6712                    _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6713
6714         /* WaSwitchSolVfFArbitrationPriority:hsw */
6715         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6716
6717         /* WaRsPkgCStateDisplayPMReq:hsw */
6718         I915_WRITE(CHICKEN_PAR1_1,
6719                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
6720
6721         lpt_init_clock_gating(dev);
6722 }
6723
6724 static void ivybridge_init_clock_gating(struct drm_device *dev)
6725 {
6726         struct drm_i915_private *dev_priv = dev->dev_private;
6727         uint32_t snpcr;
6728
6729         ilk_init_lp_watermarks(dev);
6730
6731         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6732
6733         /* WaDisableEarlyCull:ivb */
6734         I915_WRITE(_3D_CHICKEN3,
6735                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6736
6737         /* WaDisableBackToBackFlipFix:ivb */
6738         I915_WRITE(IVB_CHICKEN3,
6739                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6740                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
6741
6742         /* WaDisablePSDDualDispatchEnable:ivb */
6743         if (IS_IVB_GT1(dev))
6744                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6745                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6746
6747         /* WaDisable_RenderCache_OperationalFlush:ivb */
6748         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6749
6750         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6751         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6752                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6753
6754         /* WaApplyL3ControlAndL3ChickenMode:ivb */
6755         I915_WRITE(GEN7_L3CNTLREG1,
6756                         GEN7_WA_FOR_GEN7_L3_CONTROL);
6757         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
6758                    GEN7_WA_L3_CHICKEN_MODE);
6759         if (IS_IVB_GT1(dev))
6760                 I915_WRITE(GEN7_ROW_CHICKEN2,
6761                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6762         else {
6763                 /* must write both registers */
6764                 I915_WRITE(GEN7_ROW_CHICKEN2,
6765                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6766                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6767                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6768         }
6769
6770         /* WaForceL3Serialization:ivb */
6771         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6772                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6773
6774         /*
6775          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6776          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
6777          */
6778         I915_WRITE(GEN6_UCGCTL2,
6779                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6780
6781         /* This is required by WaCatErrorRejectionIssue:ivb */
6782         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6783                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6784                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6785
6786         g4x_disable_trickle_feed(dev);
6787
6788         gen7_setup_fixed_func_scheduler(dev_priv);
6789
6790         if (0) { /* causes HiZ corruption on ivb:gt1 */
6791                 /* enable HiZ Raw Stall Optimization */
6792                 I915_WRITE(CACHE_MODE_0_GEN7,
6793                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6794         }
6795
6796         /* WaDisable4x2SubspanOptimization:ivb */
6797         I915_WRITE(CACHE_MODE_1,
6798                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6799
6800         /*
6801          * BSpec recommends 8x4 when MSAA is used,
6802          * however in practice 16x4 seems fastest.
6803          *
6804          * Note that PS/WM thread counts depend on the WIZ hashing
6805          * disable bit, which we don't touch here, but it's good
6806          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6807          */
6808         I915_WRITE(GEN7_GT_MODE,
6809                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6810
6811         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6812         snpcr &= ~GEN6_MBC_SNPCR_MASK;
6813         snpcr |= GEN6_MBC_SNPCR_MED;
6814         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
6815
6816         if (!HAS_PCH_NOP(dev))
6817                 cpt_init_clock_gating(dev);
6818
6819         gen6_check_mch_setup(dev);
6820 }
6821
6822 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6823 {
6824         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6825
6826         /*
6827          * Disable trickle feed and enable pnd deadline calculation
6828          */
6829         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6830         I915_WRITE(CBR1_VLV, 0);
6831 }
6832
6833 static void valleyview_init_clock_gating(struct drm_device *dev)
6834 {
6835         struct drm_i915_private *dev_priv = dev->dev_private;
6836
6837         vlv_init_display_clock_gating(dev_priv);
6838
6839         /* WaDisableEarlyCull:vlv */
6840         I915_WRITE(_3D_CHICKEN3,
6841                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6842
6843         /* WaDisableBackToBackFlipFix:vlv */
6844         I915_WRITE(IVB_CHICKEN3,
6845                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6846                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
6847
6848         /* WaPsdDispatchEnable:vlv */
6849         /* WaDisablePSDDualDispatchEnable:vlv */
6850         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6851                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6852                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6853
6854         /* WaDisable_RenderCache_OperationalFlush:vlv */
6855         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6856
6857         /* WaForceL3Serialization:vlv */
6858         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6859                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6860
6861         /* WaDisableDopClockGating:vlv */
6862         I915_WRITE(GEN7_ROW_CHICKEN2,
6863                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6864
6865         /* This is required by WaCatErrorRejectionIssue:vlv */
6866         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6867                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6868                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6869
6870         gen7_setup_fixed_func_scheduler(dev_priv);
6871
6872         /*
6873          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6874          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6875          */
6876         I915_WRITE(GEN6_UCGCTL2,
6877                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6878
6879         /* WaDisableL3Bank2xClockGate:vlv
6880          * Disabling L3 clock gating- MMIO 940c[25] = 1
6881          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6882         I915_WRITE(GEN7_UCGCTL4,
6883                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
6884
6885         /*
6886          * BSpec says this must be set, even though
6887          * WaDisable4x2SubspanOptimization isn't listed for VLV.
6888          */
6889         I915_WRITE(CACHE_MODE_1,
6890                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6891
6892         /*
6893          * BSpec recommends 8x4 when MSAA is used,
6894          * however in practice 16x4 seems fastest.
6895          *
6896          * Note that PS/WM thread counts depend on the WIZ hashing
6897          * disable bit, which we don't touch here, but it's good
6898          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6899          */
6900         I915_WRITE(GEN7_GT_MODE,
6901                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6902
6903         /*
6904          * WaIncreaseL3CreditsForVLVB0:vlv
6905          * This is the hardware default actually.
6906          */
6907         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6908
6909         /*
6910          * WaDisableVLVClockGating_VBIIssue:vlv
6911          * Disable clock gating on th GCFG unit to prevent a delay
6912          * in the reporting of vblank events.
6913          */
6914         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6915 }
6916
6917 static void cherryview_init_clock_gating(struct drm_device *dev)
6918 {
6919         struct drm_i915_private *dev_priv = dev->dev_private;
6920
6921         vlv_init_display_clock_gating(dev_priv);
6922
6923         /* WaVSRefCountFullforceMissDisable:chv */
6924         /* WaDSRefCountFullforceMissDisable:chv */
6925         I915_WRITE(GEN7_FF_THREAD_MODE,
6926                    I915_READ(GEN7_FF_THREAD_MODE) &
6927                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6928
6929         /* WaDisableSemaphoreAndSyncFlipWait:chv */
6930         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6931                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6932
6933         /* WaDisableCSUnitClockGating:chv */
6934         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6935                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6936
6937         /* WaDisableSDEUnitClockGating:chv */
6938         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6939                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6940
6941         /*
6942          * GTT cache may not work with big pages, so if those
6943          * are ever enabled GTT cache may need to be disabled.
6944          */
6945         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6946 }
6947
6948 static void g4x_init_clock_gating(struct drm_device *dev)
6949 {
6950         struct drm_i915_private *dev_priv = dev->dev_private;
6951         uint32_t dspclk_gate;
6952
6953         I915_WRITE(RENCLK_GATE_D1, 0);
6954         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6955                    GS_UNIT_CLOCK_GATE_DISABLE |
6956                    CL_UNIT_CLOCK_GATE_DISABLE);
6957         I915_WRITE(RAMCLK_GATE_D, 0);
6958         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6959                 OVRUNIT_CLOCK_GATE_DISABLE |
6960                 OVCUNIT_CLOCK_GATE_DISABLE;
6961         if (IS_GM45(dev))
6962                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6963         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
6964
6965         /* WaDisableRenderCachePipelinedFlush */
6966         I915_WRITE(CACHE_MODE_0,
6967                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6968
6969         /* WaDisable_RenderCache_OperationalFlush:g4x */
6970         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6971
6972         g4x_disable_trickle_feed(dev);
6973 }
6974
6975 static void crestline_init_clock_gating(struct drm_device *dev)
6976 {
6977         struct drm_i915_private *dev_priv = dev->dev_private;
6978
6979         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6980         I915_WRITE(RENCLK_GATE_D2, 0);
6981         I915_WRITE(DSPCLK_GATE_D, 0);
6982         I915_WRITE(RAMCLK_GATE_D, 0);
6983         I915_WRITE16(DEUC, 0);
6984         I915_WRITE(MI_ARB_STATE,
6985                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6986
6987         /* WaDisable_RenderCache_OperationalFlush:gen4 */
6988         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6989 }
6990
6991 static void broadwater_init_clock_gating(struct drm_device *dev)
6992 {
6993         struct drm_i915_private *dev_priv = dev->dev_private;
6994
6995         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6996                    I965_RCC_CLOCK_GATE_DISABLE |
6997                    I965_RCPB_CLOCK_GATE_DISABLE |
6998                    I965_ISC_CLOCK_GATE_DISABLE |
6999                    I965_FBC_CLOCK_GATE_DISABLE);
7000         I915_WRITE(RENCLK_GATE_D2, 0);
7001         I915_WRITE(MI_ARB_STATE,
7002                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7003
7004         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7005         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7006 }
7007
7008 static void gen3_init_clock_gating(struct drm_device *dev)
7009 {
7010         struct drm_i915_private *dev_priv = dev->dev_private;
7011         u32 dstate = I915_READ(D_STATE);
7012
7013         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7014                 DSTATE_DOT_CLOCK_GATING;
7015         I915_WRITE(D_STATE, dstate);
7016
7017         if (IS_PINEVIEW(dev))
7018                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7019
7020         /* IIR "flip pending" means done if this bit is set */
7021         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7022
7023         /* interrupts should cause a wake up from C3 */
7024         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7025
7026         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7027         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7028
7029         I915_WRITE(MI_ARB_STATE,
7030                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7031 }
7032
7033 static void i85x_init_clock_gating(struct drm_device *dev)
7034 {
7035         struct drm_i915_private *dev_priv = dev->dev_private;
7036
7037         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7038
7039         /* interrupts should cause a wake up from C3 */
7040         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7041                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7042
7043         I915_WRITE(MEM_MODE,
7044                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7045 }
7046
7047 static void i830_init_clock_gating(struct drm_device *dev)
7048 {
7049         struct drm_i915_private *dev_priv = dev->dev_private;
7050
7051         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7052
7053         I915_WRITE(MEM_MODE,
7054                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7055                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7056 }
7057
7058 void intel_init_clock_gating(struct drm_device *dev)
7059 {
7060         struct drm_i915_private *dev_priv = dev->dev_private;
7061
7062         if (dev_priv->display.init_clock_gating)
7063                 dev_priv->display.init_clock_gating(dev);
7064 }
7065
7066 void intel_suspend_hw(struct drm_device *dev)
7067 {
7068         if (HAS_PCH_LPT(dev))
7069                 lpt_suspend_hw(dev);
7070 }
7071
7072 /* Set up chip specific power management-related functions */
7073 void intel_init_pm(struct drm_device *dev)
7074 {
7075         struct drm_i915_private *dev_priv = dev->dev_private;
7076
7077         intel_fbc_init(dev_priv);
7078
7079         /* For cxsr */
7080         if (IS_PINEVIEW(dev))
7081                 i915_pineview_get_mem_freq(dev);
7082         else if (IS_GEN5(dev))
7083                 i915_ironlake_get_mem_freq(dev);
7084
7085         /* For FIFO watermark updates */
7086         if (INTEL_INFO(dev)->gen >= 9) {
7087                 skl_setup_wm_latency(dev);
7088
7089                 if (IS_BROXTON(dev))
7090                         dev_priv->display.init_clock_gating =
7091                                 bxt_init_clock_gating;
7092                 else if (IS_SKYLAKE(dev))
7093                         dev_priv->display.init_clock_gating =
7094                                 skl_init_clock_gating;
7095                 dev_priv->display.update_wm = skl_update_wm;
7096                 dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
7097         } else if (HAS_PCH_SPLIT(dev)) {
7098                 ilk_setup_wm_latency(dev);
7099
7100                 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7101                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7102                     (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7103                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7104                         dev_priv->display.update_wm = ilk_update_wm;
7105                         dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
7106                 } else {
7107                         DRM_DEBUG_KMS("Failed to read display plane latency. "
7108                                       "Disable CxSR\n");
7109                 }
7110
7111                 if (IS_GEN5(dev))
7112                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7113                 else if (IS_GEN6(dev))
7114                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7115                 else if (IS_IVYBRIDGE(dev))
7116                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7117                 else if (IS_HASWELL(dev))
7118                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7119                 else if (INTEL_INFO(dev)->gen == 8)
7120                         dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7121         } else if (IS_CHERRYVIEW(dev)) {
7122                 vlv_setup_wm_latency(dev);
7123
7124                 dev_priv->display.update_wm = vlv_update_wm;
7125                 dev_priv->display.init_clock_gating =
7126                         cherryview_init_clock_gating;
7127         } else if (IS_VALLEYVIEW(dev)) {
7128                 vlv_setup_wm_latency(dev);
7129
7130                 dev_priv->display.update_wm = vlv_update_wm;
7131                 dev_priv->display.init_clock_gating =
7132                         valleyview_init_clock_gating;
7133         } else if (IS_PINEVIEW(dev)) {
7134                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7135                                             dev_priv->is_ddr3,
7136                                             dev_priv->fsb_freq,
7137                                             dev_priv->mem_freq)) {
7138                         DRM_INFO("failed to find known CxSR latency "
7139                                  "(found ddr%s fsb freq %d, mem freq %d), "
7140                                  "disabling CxSR\n",
7141                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
7142                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7143                         /* Disable CxSR and never update its watermark again */
7144                         intel_set_memory_cxsr(dev_priv, false);
7145                         dev_priv->display.update_wm = NULL;
7146                 } else
7147                         dev_priv->display.update_wm = pineview_update_wm;
7148                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7149         } else if (IS_G4X(dev)) {
7150                 dev_priv->display.update_wm = g4x_update_wm;
7151                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7152         } else if (IS_GEN4(dev)) {
7153                 dev_priv->display.update_wm = i965_update_wm;
7154                 if (IS_CRESTLINE(dev))
7155                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7156                 else if (IS_BROADWATER(dev))
7157                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7158         } else if (IS_GEN3(dev)) {
7159                 dev_priv->display.update_wm = i9xx_update_wm;
7160                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7161                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7162         } else if (IS_GEN2(dev)) {
7163                 if (INTEL_INFO(dev)->num_pipes == 1) {
7164                         dev_priv->display.update_wm = i845_update_wm;
7165                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7166                 } else {
7167                         dev_priv->display.update_wm = i9xx_update_wm;
7168                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7169                 }
7170
7171                 if (IS_I85X(dev) || IS_I865G(dev))
7172                         dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7173                 else
7174                         dev_priv->display.init_clock_gating = i830_init_clock_gating;
7175         } else {
7176                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7177         }
7178 }
7179
7180 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7181 {
7182         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7183
7184         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7185                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7186                 return -EAGAIN;
7187         }
7188
7189         I915_WRITE(GEN6_PCODE_DATA, *val);
7190         I915_WRITE(GEN6_PCODE_DATA1, 0);
7191         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7192
7193         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7194                      500)) {
7195                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7196                 return -ETIMEDOUT;
7197         }
7198
7199         *val = I915_READ(GEN6_PCODE_DATA);
7200         I915_WRITE(GEN6_PCODE_DATA, 0);
7201
7202         return 0;
7203 }
7204
7205 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
7206 {
7207         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7208
7209         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7210                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7211                 return -EAGAIN;
7212         }
7213
7214         I915_WRITE(GEN6_PCODE_DATA, val);
7215         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7216
7217         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7218                      500)) {
7219                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7220                 return -ETIMEDOUT;
7221         }
7222
7223         I915_WRITE(GEN6_PCODE_DATA, 0);
7224
7225         return 0;
7226 }
7227
7228 static int vlv_gpu_freq_div(unsigned int czclk_freq)
7229 {
7230         switch (czclk_freq) {
7231         case 200:
7232                 return 10;
7233         case 267:
7234                 return 12;
7235         case 320:
7236         case 333:
7237                 return 16;
7238         case 400:
7239                 return 20;
7240         default:
7241                 return -1;
7242         }
7243 }
7244
7245 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7246 {
7247         int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
7248
7249         div = vlv_gpu_freq_div(czclk_freq);
7250         if (div < 0)
7251                 return div;
7252
7253         return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
7254 }
7255
7256 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7257 {
7258         int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
7259
7260         mul = vlv_gpu_freq_div(czclk_freq);
7261         if (mul < 0)
7262                 return mul;
7263
7264         return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
7265 }
7266
7267 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7268 {
7269         int div, czclk_freq = dev_priv->rps.cz_freq;
7270
7271         div = vlv_gpu_freq_div(czclk_freq) / 2;
7272         if (div < 0)
7273                 return div;
7274
7275         return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
7276 }
7277
7278 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7279 {
7280         int mul, czclk_freq = dev_priv->rps.cz_freq;
7281
7282         mul = vlv_gpu_freq_div(czclk_freq) / 2;
7283         if (mul < 0)
7284                 return mul;
7285
7286         /* CHV needs even values */
7287         return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
7288 }
7289
7290 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7291 {
7292         if (IS_GEN9(dev_priv->dev))
7293                 return (val * GT_FREQUENCY_MULTIPLIER) / GEN9_FREQ_SCALER;
7294         else if (IS_CHERRYVIEW(dev_priv->dev))
7295                 return chv_gpu_freq(dev_priv, val);
7296         else if (IS_VALLEYVIEW(dev_priv->dev))
7297                 return byt_gpu_freq(dev_priv, val);
7298         else
7299                 return val * GT_FREQUENCY_MULTIPLIER;
7300 }
7301
7302 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7303 {
7304         if (IS_GEN9(dev_priv->dev))
7305                 return (val * GEN9_FREQ_SCALER) / GT_FREQUENCY_MULTIPLIER;
7306         else if (IS_CHERRYVIEW(dev_priv->dev))
7307                 return chv_freq_opcode(dev_priv, val);
7308         else if (IS_VALLEYVIEW(dev_priv->dev))
7309                 return byt_freq_opcode(dev_priv, val);
7310         else
7311                 return val / GT_FREQUENCY_MULTIPLIER;
7312 }
7313
7314 struct request_boost {
7315         struct work_struct work;
7316         struct drm_i915_gem_request *req;
7317 };
7318
7319 static void __intel_rps_boost_work(struct work_struct *work)
7320 {
7321         struct request_boost *boost = container_of(work, struct request_boost, work);
7322         struct drm_i915_gem_request *req = boost->req;
7323
7324         if (!i915_gem_request_completed(req, true))
7325                 gen6_rps_boost(to_i915(req->ring->dev), NULL,
7326                                req->emitted_jiffies);
7327
7328         i915_gem_request_unreference__unlocked(req);
7329         kfree(boost);
7330 }
7331
7332 void intel_queue_rps_boost_for_request(struct drm_device *dev,
7333                                        struct drm_i915_gem_request *req)
7334 {
7335         struct request_boost *boost;
7336
7337         if (req == NULL || INTEL_INFO(dev)->gen < 6)
7338                 return;
7339
7340         if (i915_gem_request_completed(req, true))
7341                 return;
7342
7343         boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7344         if (boost == NULL)
7345                 return;
7346
7347         i915_gem_request_reference(req);
7348         boost->req = req;
7349
7350         INIT_WORK(&boost->work, __intel_rps_boost_work);
7351         queue_work(to_i915(dev)->wq, &boost->work);
7352 }
7353
7354 void intel_pm_setup(struct drm_device *dev)
7355 {
7356         struct drm_i915_private *dev_priv = dev->dev_private;
7357
7358         mutex_init(&dev_priv->rps.hw_lock);
7359         spin_lock_init(&dev_priv->rps.client_lock);
7360
7361         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7362                           intel_gen6_powersave_work);
7363         INIT_LIST_HEAD(&dev_priv->rps.clients);
7364         INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7365         INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
7366
7367         dev_priv->pm.suspended = false;
7368 }