2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
51 #define INTEL_RC6_ENABLE (1<<0)
52 #define INTEL_RC6p_ENABLE (1<<1)
53 #define INTEL_RC6pp_ENABLE (1<<2)
55 static void bxt_init_clock_gating(struct drm_device *dev)
57 struct drm_i915_private *dev_priv = dev->dev_private;
59 /* WaDisableSDEUnitClockGating:bxt */
60 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
61 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
65 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
67 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
68 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
71 static void i915_pineview_get_mem_freq(struct drm_device *dev)
73 struct drm_i915_private *dev_priv = dev->dev_private;
76 tmp = I915_READ(CLKCFG);
78 switch (tmp & CLKCFG_FSB_MASK) {
80 dev_priv->fsb_freq = 533; /* 133*4 */
83 dev_priv->fsb_freq = 800; /* 200*4 */
86 dev_priv->fsb_freq = 667; /* 167*4 */
89 dev_priv->fsb_freq = 400; /* 100*4 */
93 switch (tmp & CLKCFG_MEM_MASK) {
95 dev_priv->mem_freq = 533;
98 dev_priv->mem_freq = 667;
101 dev_priv->mem_freq = 800;
105 /* detect pineview DDR3 setting */
106 tmp = I915_READ(CSHRDDR3CTL);
107 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
110 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
112 struct drm_i915_private *dev_priv = dev->dev_private;
115 ddrpll = I915_READ16(DDRMPLL1);
116 csipll = I915_READ16(CSIPLL0);
118 switch (ddrpll & 0xff) {
120 dev_priv->mem_freq = 800;
123 dev_priv->mem_freq = 1066;
126 dev_priv->mem_freq = 1333;
129 dev_priv->mem_freq = 1600;
132 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
134 dev_priv->mem_freq = 0;
138 dev_priv->ips.r_t = dev_priv->mem_freq;
140 switch (csipll & 0x3ff) {
142 dev_priv->fsb_freq = 3200;
145 dev_priv->fsb_freq = 3733;
148 dev_priv->fsb_freq = 4266;
151 dev_priv->fsb_freq = 4800;
154 dev_priv->fsb_freq = 5333;
157 dev_priv->fsb_freq = 5866;
160 dev_priv->fsb_freq = 6400;
163 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
165 dev_priv->fsb_freq = 0;
169 if (dev_priv->fsb_freq == 3200) {
170 dev_priv->ips.c_m = 0;
171 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
172 dev_priv->ips.c_m = 1;
174 dev_priv->ips.c_m = 2;
178 static const struct cxsr_latency cxsr_latency_table[] = {
179 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
180 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
181 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
182 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
183 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
185 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
186 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
187 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
188 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
189 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
191 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
192 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
193 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
194 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
195 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
197 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
198 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
199 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
200 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
201 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
203 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
204 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
205 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
206 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
207 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
209 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
210 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
211 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
212 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
213 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
216 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
221 const struct cxsr_latency *latency;
224 if (fsb == 0 || mem == 0)
227 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
228 latency = &cxsr_latency_table[i];
229 if (is_desktop == latency->is_desktop &&
230 is_ddr3 == latency->is_ddr3 &&
231 fsb == latency->fsb_freq && mem == latency->mem_freq)
235 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
240 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
244 mutex_lock(&dev_priv->rps.hw_lock);
246 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
248 val &= ~FORCE_DDR_HIGH_FREQ;
250 val |= FORCE_DDR_HIGH_FREQ;
251 val &= ~FORCE_DDR_LOW_FREQ;
252 val |= FORCE_DDR_FREQ_REQ_ACK;
253 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
255 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
256 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
257 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
259 mutex_unlock(&dev_priv->rps.hw_lock);
262 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
266 mutex_lock(&dev_priv->rps.hw_lock);
268 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
270 val |= DSP_MAXFIFO_PM5_ENABLE;
272 val &= ~DSP_MAXFIFO_PM5_ENABLE;
273 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
275 mutex_unlock(&dev_priv->rps.hw_lock);
278 #define FW_WM(value, plane) \
279 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
281 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
283 struct drm_device *dev = dev_priv->dev;
286 if (IS_VALLEYVIEW(dev)) {
287 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
288 POSTING_READ(FW_BLC_SELF_VLV);
289 dev_priv->wm.vlv.cxsr = enable;
290 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
291 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
292 POSTING_READ(FW_BLC_SELF);
293 } else if (IS_PINEVIEW(dev)) {
294 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
295 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
296 I915_WRITE(DSPFW3, val);
297 POSTING_READ(DSPFW3);
298 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
299 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
300 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
301 I915_WRITE(FW_BLC_SELF, val);
302 POSTING_READ(FW_BLC_SELF);
303 } else if (IS_I915GM(dev)) {
304 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
305 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
306 I915_WRITE(INSTPM, val);
307 POSTING_READ(INSTPM);
312 DRM_DEBUG_KMS("memory self-refresh is %s\n",
313 enable ? "enabled" : "disabled");
318 * Latency for FIFO fetches is dependent on several factors:
319 * - memory configuration (speed, channels)
321 * - current MCH state
322 * It can be fairly high in some situations, so here we assume a fairly
323 * pessimal value. It's a tradeoff between extra memory fetches (if we
324 * set this value too high, the FIFO will fetch frequently to stay full)
325 * and power consumption (set it too low to save power and we might see
326 * FIFO underruns and display "flicker").
328 * A value of 5us seems to be a good balance; safe for very low end
329 * platforms but not overly aggressive on lower latency configs.
331 static const int pessimal_latency_ns = 5000;
333 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
334 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
336 static int vlv_get_fifo_size(struct drm_device *dev,
337 enum pipe pipe, int plane)
339 struct drm_i915_private *dev_priv = dev->dev_private;
340 int sprite0_start, sprite1_start, size;
343 uint32_t dsparb, dsparb2, dsparb3;
345 dsparb = I915_READ(DSPARB);
346 dsparb2 = I915_READ(DSPARB2);
347 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
348 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
351 dsparb = I915_READ(DSPARB);
352 dsparb2 = I915_READ(DSPARB2);
353 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
354 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
357 dsparb2 = I915_READ(DSPARB2);
358 dsparb3 = I915_READ(DSPARB3);
359 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
360 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
368 size = sprite0_start;
371 size = sprite1_start - sprite0_start;
374 size = 512 - 1 - sprite1_start;
380 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
381 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
382 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
388 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
390 struct drm_i915_private *dev_priv = dev->dev_private;
391 uint32_t dsparb = I915_READ(DSPARB);
394 size = dsparb & 0x7f;
396 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
398 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
399 plane ? "B" : "A", size);
404 static int i830_get_fifo_size(struct drm_device *dev, int plane)
406 struct drm_i915_private *dev_priv = dev->dev_private;
407 uint32_t dsparb = I915_READ(DSPARB);
410 size = dsparb & 0x1ff;
412 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
413 size >>= 1; /* Convert to cachelines */
415 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
416 plane ? "B" : "A", size);
421 static int i845_get_fifo_size(struct drm_device *dev, int plane)
423 struct drm_i915_private *dev_priv = dev->dev_private;
424 uint32_t dsparb = I915_READ(DSPARB);
427 size = dsparb & 0x7f;
428 size >>= 2; /* Convert to cachelines */
430 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
437 /* Pineview has different values for various configs */
438 static const struct intel_watermark_params pineview_display_wm = {
439 .fifo_size = PINEVIEW_DISPLAY_FIFO,
440 .max_wm = PINEVIEW_MAX_WM,
441 .default_wm = PINEVIEW_DFT_WM,
442 .guard_size = PINEVIEW_GUARD_WM,
443 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
445 static const struct intel_watermark_params pineview_display_hplloff_wm = {
446 .fifo_size = PINEVIEW_DISPLAY_FIFO,
447 .max_wm = PINEVIEW_MAX_WM,
448 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
449 .guard_size = PINEVIEW_GUARD_WM,
450 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
452 static const struct intel_watermark_params pineview_cursor_wm = {
453 .fifo_size = PINEVIEW_CURSOR_FIFO,
454 .max_wm = PINEVIEW_CURSOR_MAX_WM,
455 .default_wm = PINEVIEW_CURSOR_DFT_WM,
456 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
457 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
459 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
460 .fifo_size = PINEVIEW_CURSOR_FIFO,
461 .max_wm = PINEVIEW_CURSOR_MAX_WM,
462 .default_wm = PINEVIEW_CURSOR_DFT_WM,
463 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
464 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
466 static const struct intel_watermark_params g4x_wm_info = {
467 .fifo_size = G4X_FIFO_SIZE,
468 .max_wm = G4X_MAX_WM,
469 .default_wm = G4X_MAX_WM,
471 .cacheline_size = G4X_FIFO_LINE_SIZE,
473 static const struct intel_watermark_params g4x_cursor_wm_info = {
474 .fifo_size = I965_CURSOR_FIFO,
475 .max_wm = I965_CURSOR_MAX_WM,
476 .default_wm = I965_CURSOR_DFT_WM,
478 .cacheline_size = G4X_FIFO_LINE_SIZE,
480 static const struct intel_watermark_params valleyview_wm_info = {
481 .fifo_size = VALLEYVIEW_FIFO_SIZE,
482 .max_wm = VALLEYVIEW_MAX_WM,
483 .default_wm = VALLEYVIEW_MAX_WM,
485 .cacheline_size = G4X_FIFO_LINE_SIZE,
487 static const struct intel_watermark_params valleyview_cursor_wm_info = {
488 .fifo_size = I965_CURSOR_FIFO,
489 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
490 .default_wm = I965_CURSOR_DFT_WM,
492 .cacheline_size = G4X_FIFO_LINE_SIZE,
494 static const struct intel_watermark_params i965_cursor_wm_info = {
495 .fifo_size = I965_CURSOR_FIFO,
496 .max_wm = I965_CURSOR_MAX_WM,
497 .default_wm = I965_CURSOR_DFT_WM,
499 .cacheline_size = I915_FIFO_LINE_SIZE,
501 static const struct intel_watermark_params i945_wm_info = {
502 .fifo_size = I945_FIFO_SIZE,
503 .max_wm = I915_MAX_WM,
506 .cacheline_size = I915_FIFO_LINE_SIZE,
508 static const struct intel_watermark_params i915_wm_info = {
509 .fifo_size = I915_FIFO_SIZE,
510 .max_wm = I915_MAX_WM,
513 .cacheline_size = I915_FIFO_LINE_SIZE,
515 static const struct intel_watermark_params i830_a_wm_info = {
516 .fifo_size = I855GM_FIFO_SIZE,
517 .max_wm = I915_MAX_WM,
520 .cacheline_size = I830_FIFO_LINE_SIZE,
522 static const struct intel_watermark_params i830_bc_wm_info = {
523 .fifo_size = I855GM_FIFO_SIZE,
524 .max_wm = I915_MAX_WM/2,
527 .cacheline_size = I830_FIFO_LINE_SIZE,
529 static const struct intel_watermark_params i845_wm_info = {
530 .fifo_size = I830_FIFO_SIZE,
531 .max_wm = I915_MAX_WM,
534 .cacheline_size = I830_FIFO_LINE_SIZE,
538 * intel_calculate_wm - calculate watermark level
539 * @clock_in_khz: pixel clock
540 * @wm: chip FIFO params
541 * @pixel_size: display pixel size
542 * @latency_ns: memory latency for the platform
544 * Calculate the watermark level (the level at which the display plane will
545 * start fetching from memory again). Each chip has a different display
546 * FIFO size and allocation, so the caller needs to figure that out and pass
547 * in the correct intel_watermark_params structure.
549 * As the pixel clock runs, the FIFO will be drained at a rate that depends
550 * on the pixel size. When it reaches the watermark level, it'll start
551 * fetching FIFO line sized based chunks from memory until the FIFO fills
552 * past the watermark point. If the FIFO drains completely, a FIFO underrun
553 * will occur, and a display engine hang could result.
555 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
556 const struct intel_watermark_params *wm,
559 unsigned long latency_ns)
561 long entries_required, wm_size;
564 * Note: we need to make sure we don't overflow for various clock &
566 * clocks go from a few thousand to several hundred thousand.
567 * latency is usually a few thousand
569 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
571 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
573 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
575 wm_size = fifo_size - (entries_required + wm->guard_size);
577 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
579 /* Don't promote wm_size to unsigned... */
580 if (wm_size > (long)wm->max_wm)
581 wm_size = wm->max_wm;
583 wm_size = wm->default_wm;
586 * Bspec seems to indicate that the value shouldn't be lower than
587 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
588 * Lets go for 8 which is the burst size since certain platforms
589 * already use a hardcoded 8 (which is what the spec says should be
598 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
600 struct drm_crtc *crtc, *enabled = NULL;
602 for_each_crtc(dev, crtc) {
603 if (intel_crtc_active(crtc)) {
613 static void pineview_update_wm(struct drm_crtc *unused_crtc)
615 struct drm_device *dev = unused_crtc->dev;
616 struct drm_i915_private *dev_priv = dev->dev_private;
617 struct drm_crtc *crtc;
618 const struct cxsr_latency *latency;
622 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
623 dev_priv->fsb_freq, dev_priv->mem_freq);
625 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
626 intel_set_memory_cxsr(dev_priv, false);
630 crtc = single_enabled_crtc(dev);
632 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
633 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
634 int clock = adjusted_mode->crtc_clock;
637 wm = intel_calculate_wm(clock, &pineview_display_wm,
638 pineview_display_wm.fifo_size,
639 pixel_size, latency->display_sr);
640 reg = I915_READ(DSPFW1);
641 reg &= ~DSPFW_SR_MASK;
642 reg |= FW_WM(wm, SR);
643 I915_WRITE(DSPFW1, reg);
644 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
647 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
648 pineview_display_wm.fifo_size,
649 pixel_size, latency->cursor_sr);
650 reg = I915_READ(DSPFW3);
651 reg &= ~DSPFW_CURSOR_SR_MASK;
652 reg |= FW_WM(wm, CURSOR_SR);
653 I915_WRITE(DSPFW3, reg);
655 /* Display HPLL off SR */
656 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
657 pineview_display_hplloff_wm.fifo_size,
658 pixel_size, latency->display_hpll_disable);
659 reg = I915_READ(DSPFW3);
660 reg &= ~DSPFW_HPLL_SR_MASK;
661 reg |= FW_WM(wm, HPLL_SR);
662 I915_WRITE(DSPFW3, reg);
664 /* cursor HPLL off SR */
665 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
666 pineview_display_hplloff_wm.fifo_size,
667 pixel_size, latency->cursor_hpll_disable);
668 reg = I915_READ(DSPFW3);
669 reg &= ~DSPFW_HPLL_CURSOR_MASK;
670 reg |= FW_WM(wm, HPLL_CURSOR);
671 I915_WRITE(DSPFW3, reg);
672 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
674 intel_set_memory_cxsr(dev_priv, true);
676 intel_set_memory_cxsr(dev_priv, false);
680 static bool g4x_compute_wm0(struct drm_device *dev,
682 const struct intel_watermark_params *display,
683 int display_latency_ns,
684 const struct intel_watermark_params *cursor,
685 int cursor_latency_ns,
689 struct drm_crtc *crtc;
690 const struct drm_display_mode *adjusted_mode;
691 int htotal, hdisplay, clock, pixel_size;
692 int line_time_us, line_count;
693 int entries, tlb_miss;
695 crtc = intel_get_crtc_for_plane(dev, plane);
696 if (!intel_crtc_active(crtc)) {
697 *cursor_wm = cursor->guard_size;
698 *plane_wm = display->guard_size;
702 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
703 clock = adjusted_mode->crtc_clock;
704 htotal = adjusted_mode->crtc_htotal;
705 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
706 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
708 /* Use the small buffer method to calculate plane watermark */
709 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
710 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
713 entries = DIV_ROUND_UP(entries, display->cacheline_size);
714 *plane_wm = entries + display->guard_size;
715 if (*plane_wm > (int)display->max_wm)
716 *plane_wm = display->max_wm;
718 /* Use the large buffer method to calculate cursor watermark */
719 line_time_us = max(htotal * 1000 / clock, 1);
720 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
721 entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
722 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
725 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
726 *cursor_wm = entries + cursor->guard_size;
727 if (*cursor_wm > (int)cursor->max_wm)
728 *cursor_wm = (int)cursor->max_wm;
734 * Check the wm result.
736 * If any calculated watermark values is larger than the maximum value that
737 * can be programmed into the associated watermark register, that watermark
740 static bool g4x_check_srwm(struct drm_device *dev,
741 int display_wm, int cursor_wm,
742 const struct intel_watermark_params *display,
743 const struct intel_watermark_params *cursor)
745 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
746 display_wm, cursor_wm);
748 if (display_wm > display->max_wm) {
749 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
750 display_wm, display->max_wm);
754 if (cursor_wm > cursor->max_wm) {
755 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
756 cursor_wm, cursor->max_wm);
760 if (!(display_wm || cursor_wm)) {
761 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
768 static bool g4x_compute_srwm(struct drm_device *dev,
771 const struct intel_watermark_params *display,
772 const struct intel_watermark_params *cursor,
773 int *display_wm, int *cursor_wm)
775 struct drm_crtc *crtc;
776 const struct drm_display_mode *adjusted_mode;
777 int hdisplay, htotal, pixel_size, clock;
778 unsigned long line_time_us;
779 int line_count, line_size;
784 *display_wm = *cursor_wm = 0;
788 crtc = intel_get_crtc_for_plane(dev, plane);
789 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
790 clock = adjusted_mode->crtc_clock;
791 htotal = adjusted_mode->crtc_htotal;
792 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
793 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
795 line_time_us = max(htotal * 1000 / clock, 1);
796 line_count = (latency_ns / line_time_us + 1000) / 1000;
797 line_size = hdisplay * pixel_size;
799 /* Use the minimum of the small and large buffer method for primary */
800 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
801 large = line_count * line_size;
803 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
804 *display_wm = entries + display->guard_size;
806 /* calculate the self-refresh watermark for display cursor */
807 entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
808 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
809 *cursor_wm = entries + cursor->guard_size;
811 return g4x_check_srwm(dev,
812 *display_wm, *cursor_wm,
816 #define FW_WM_VLV(value, plane) \
817 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
819 static void vlv_write_wm_values(struct intel_crtc *crtc,
820 const struct vlv_wm_values *wm)
822 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
823 enum pipe pipe = crtc->pipe;
825 I915_WRITE(VLV_DDL(pipe),
826 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
827 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
828 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
829 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
832 FW_WM(wm->sr.plane, SR) |
833 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
834 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
835 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
837 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
838 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
839 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
841 FW_WM(wm->sr.cursor, CURSOR_SR));
843 if (IS_CHERRYVIEW(dev_priv)) {
844 I915_WRITE(DSPFW7_CHV,
845 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
846 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
847 I915_WRITE(DSPFW8_CHV,
848 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
849 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
850 I915_WRITE(DSPFW9_CHV,
851 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
852 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
854 FW_WM(wm->sr.plane >> 9, SR_HI) |
855 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
856 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
857 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
858 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
859 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
860 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
861 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
862 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
863 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
866 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
867 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
869 FW_WM(wm->sr.plane >> 9, SR_HI) |
870 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
871 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
872 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
873 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
874 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
875 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
878 /* zero (unused) WM1 watermarks */
879 I915_WRITE(DSPFW4, 0);
880 I915_WRITE(DSPFW5, 0);
881 I915_WRITE(DSPFW6, 0);
882 I915_WRITE(DSPHOWM1, 0);
884 POSTING_READ(DSPFW1);
892 VLV_WM_LEVEL_DDR_DVFS,
895 /* latency must be in 0.1us units. */
896 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
897 unsigned int pipe_htotal,
898 unsigned int horiz_pixels,
899 unsigned int bytes_per_pixel,
900 unsigned int latency)
904 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
905 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
906 ret = DIV_ROUND_UP(ret, 64);
911 static void vlv_setup_wm_latency(struct drm_device *dev)
913 struct drm_i915_private *dev_priv = dev->dev_private;
915 /* all latencies in usec */
916 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
918 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
920 if (IS_CHERRYVIEW(dev_priv)) {
921 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
922 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
924 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
928 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
929 struct intel_crtc *crtc,
930 const struct intel_plane_state *state,
933 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
934 int clock, htotal, pixel_size, width, wm;
936 if (dev_priv->wm.pri_latency[level] == 0)
942 pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
943 clock = crtc->config->base.adjusted_mode.crtc_clock;
944 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
945 width = crtc->config->pipe_src_w;
946 if (WARN_ON(htotal == 0))
949 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
951 * FIXME the formula gives values that are
952 * too big for the cursor FIFO, and hence we
953 * would never be able to use cursors. For
954 * now just hardcode the watermark.
958 wm = vlv_wm_method2(clock, htotal, width, pixel_size,
959 dev_priv->wm.pri_latency[level] * 10);
962 return min_t(int, wm, USHRT_MAX);
965 static void vlv_compute_fifo(struct intel_crtc *crtc)
967 struct drm_device *dev = crtc->base.dev;
968 struct vlv_wm_state *wm_state = &crtc->wm_state;
969 struct intel_plane *plane;
970 unsigned int total_rate = 0;
971 const int fifo_size = 512 - 1;
972 int fifo_extra, fifo_left = fifo_size;
974 for_each_intel_plane_on_crtc(dev, crtc, plane) {
975 struct intel_plane_state *state =
976 to_intel_plane_state(plane->base.state);
978 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
981 if (state->visible) {
982 wm_state->num_active_planes++;
983 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
987 for_each_intel_plane_on_crtc(dev, crtc, plane) {
988 struct intel_plane_state *state =
989 to_intel_plane_state(plane->base.state);
992 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
993 plane->wm.fifo_size = 63;
997 if (!state->visible) {
998 plane->wm.fifo_size = 0;
1002 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1003 plane->wm.fifo_size = fifo_size * rate / total_rate;
1004 fifo_left -= plane->wm.fifo_size;
1007 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1009 /* spread the remainder evenly */
1010 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1016 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1019 /* give it all to the first plane if none are active */
1020 if (plane->wm.fifo_size == 0 &&
1021 wm_state->num_active_planes)
1024 plane_extra = min(fifo_extra, fifo_left);
1025 plane->wm.fifo_size += plane_extra;
1026 fifo_left -= plane_extra;
1029 WARN_ON(fifo_left != 0);
1032 static void vlv_invert_wms(struct intel_crtc *crtc)
1034 struct vlv_wm_state *wm_state = &crtc->wm_state;
1037 for (level = 0; level < wm_state->num_levels; level++) {
1038 struct drm_device *dev = crtc->base.dev;
1039 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1040 struct intel_plane *plane;
1042 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1043 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1045 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1046 switch (plane->base.type) {
1048 case DRM_PLANE_TYPE_CURSOR:
1049 wm_state->wm[level].cursor = plane->wm.fifo_size -
1050 wm_state->wm[level].cursor;
1052 case DRM_PLANE_TYPE_PRIMARY:
1053 wm_state->wm[level].primary = plane->wm.fifo_size -
1054 wm_state->wm[level].primary;
1056 case DRM_PLANE_TYPE_OVERLAY:
1057 sprite = plane->plane;
1058 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1059 wm_state->wm[level].sprite[sprite];
1066 static void vlv_compute_wm(struct intel_crtc *crtc)
1068 struct drm_device *dev = crtc->base.dev;
1069 struct vlv_wm_state *wm_state = &crtc->wm_state;
1070 struct intel_plane *plane;
1071 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1074 memset(wm_state, 0, sizeof(*wm_state));
1076 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1077 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
1079 wm_state->num_active_planes = 0;
1081 vlv_compute_fifo(crtc);
1083 if (wm_state->num_active_planes != 1)
1084 wm_state->cxsr = false;
1086 if (wm_state->cxsr) {
1087 for (level = 0; level < wm_state->num_levels; level++) {
1088 wm_state->sr[level].plane = sr_fifo_size;
1089 wm_state->sr[level].cursor = 63;
1093 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1094 struct intel_plane_state *state =
1095 to_intel_plane_state(plane->base.state);
1097 if (!state->visible)
1100 /* normal watermarks */
1101 for (level = 0; level < wm_state->num_levels; level++) {
1102 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1103 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1106 if (WARN_ON(level == 0 && wm > max_wm))
1109 if (wm > plane->wm.fifo_size)
1112 switch (plane->base.type) {
1114 case DRM_PLANE_TYPE_CURSOR:
1115 wm_state->wm[level].cursor = wm;
1117 case DRM_PLANE_TYPE_PRIMARY:
1118 wm_state->wm[level].primary = wm;
1120 case DRM_PLANE_TYPE_OVERLAY:
1121 sprite = plane->plane;
1122 wm_state->wm[level].sprite[sprite] = wm;
1127 wm_state->num_levels = level;
1129 if (!wm_state->cxsr)
1132 /* maxfifo watermarks */
1133 switch (plane->base.type) {
1135 case DRM_PLANE_TYPE_CURSOR:
1136 for (level = 0; level < wm_state->num_levels; level++)
1137 wm_state->sr[level].cursor =
1138 wm_state->wm[level].cursor;
1140 case DRM_PLANE_TYPE_PRIMARY:
1141 for (level = 0; level < wm_state->num_levels; level++)
1142 wm_state->sr[level].plane =
1143 min(wm_state->sr[level].plane,
1144 wm_state->wm[level].primary);
1146 case DRM_PLANE_TYPE_OVERLAY:
1147 sprite = plane->plane;
1148 for (level = 0; level < wm_state->num_levels; level++)
1149 wm_state->sr[level].plane =
1150 min(wm_state->sr[level].plane,
1151 wm_state->wm[level].sprite[sprite]);
1156 /* clear any (partially) filled invalid levels */
1157 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
1158 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1159 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1162 vlv_invert_wms(crtc);
1165 #define VLV_FIFO(plane, value) \
1166 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1168 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1170 struct drm_device *dev = crtc->base.dev;
1171 struct drm_i915_private *dev_priv = to_i915(dev);
1172 struct intel_plane *plane;
1173 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1175 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1176 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1177 WARN_ON(plane->wm.fifo_size != 63);
1181 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1182 sprite0_start = plane->wm.fifo_size;
1183 else if (plane->plane == 0)
1184 sprite1_start = sprite0_start + plane->wm.fifo_size;
1186 fifo_size = sprite1_start + plane->wm.fifo_size;
1189 WARN_ON(fifo_size != 512 - 1);
1191 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1192 pipe_name(crtc->pipe), sprite0_start,
1193 sprite1_start, fifo_size);
1195 switch (crtc->pipe) {
1196 uint32_t dsparb, dsparb2, dsparb3;
1198 dsparb = I915_READ(DSPARB);
1199 dsparb2 = I915_READ(DSPARB2);
1201 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1202 VLV_FIFO(SPRITEB, 0xff));
1203 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1204 VLV_FIFO(SPRITEB, sprite1_start));
1206 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1207 VLV_FIFO(SPRITEB_HI, 0x1));
1208 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1209 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1211 I915_WRITE(DSPARB, dsparb);
1212 I915_WRITE(DSPARB2, dsparb2);
1215 dsparb = I915_READ(DSPARB);
1216 dsparb2 = I915_READ(DSPARB2);
1218 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1219 VLV_FIFO(SPRITED, 0xff));
1220 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1221 VLV_FIFO(SPRITED, sprite1_start));
1223 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1224 VLV_FIFO(SPRITED_HI, 0xff));
1225 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1226 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1228 I915_WRITE(DSPARB, dsparb);
1229 I915_WRITE(DSPARB2, dsparb2);
1232 dsparb3 = I915_READ(DSPARB3);
1233 dsparb2 = I915_READ(DSPARB2);
1235 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1236 VLV_FIFO(SPRITEF, 0xff));
1237 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1238 VLV_FIFO(SPRITEF, sprite1_start));
1240 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1241 VLV_FIFO(SPRITEF_HI, 0xff));
1242 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1243 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1245 I915_WRITE(DSPARB3, dsparb3);
1246 I915_WRITE(DSPARB2, dsparb2);
1255 static void vlv_merge_wm(struct drm_device *dev,
1256 struct vlv_wm_values *wm)
1258 struct intel_crtc *crtc;
1259 int num_active_crtcs = 0;
1261 wm->level = to_i915(dev)->wm.max_level;
1264 for_each_intel_crtc(dev, crtc) {
1265 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1270 if (!wm_state->cxsr)
1274 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1277 if (num_active_crtcs != 1)
1280 if (num_active_crtcs > 1)
1281 wm->level = VLV_WM_LEVEL_PM2;
1283 for_each_intel_crtc(dev, crtc) {
1284 struct vlv_wm_state *wm_state = &crtc->wm_state;
1285 enum pipe pipe = crtc->pipe;
1290 wm->pipe[pipe] = wm_state->wm[wm->level];
1292 wm->sr = wm_state->sr[wm->level];
1294 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1295 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1296 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1297 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1301 static void vlv_update_wm(struct drm_crtc *crtc)
1303 struct drm_device *dev = crtc->dev;
1304 struct drm_i915_private *dev_priv = dev->dev_private;
1305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1306 enum pipe pipe = intel_crtc->pipe;
1307 struct vlv_wm_values wm = {};
1309 vlv_compute_wm(intel_crtc);
1310 vlv_merge_wm(dev, &wm);
1312 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1313 /* FIXME should be part of crtc atomic commit */
1314 vlv_pipe_set_fifo_size(intel_crtc);
1318 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1319 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1320 chv_set_memory_dvfs(dev_priv, false);
1322 if (wm.level < VLV_WM_LEVEL_PM5 &&
1323 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1324 chv_set_memory_pm5(dev_priv, false);
1326 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1327 intel_set_memory_cxsr(dev_priv, false);
1329 /* FIXME should be part of crtc atomic commit */
1330 vlv_pipe_set_fifo_size(intel_crtc);
1332 vlv_write_wm_values(intel_crtc, &wm);
1334 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1335 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1336 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1337 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1338 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1340 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1341 intel_set_memory_cxsr(dev_priv, true);
1343 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1344 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1345 chv_set_memory_pm5(dev_priv, true);
1347 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1348 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1349 chv_set_memory_dvfs(dev_priv, true);
1351 dev_priv->wm.vlv = wm;
1354 #define single_plane_enabled(mask) is_power_of_2(mask)
1356 static void g4x_update_wm(struct drm_crtc *crtc)
1358 struct drm_device *dev = crtc->dev;
1359 static const int sr_latency_ns = 12000;
1360 struct drm_i915_private *dev_priv = dev->dev_private;
1361 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1362 int plane_sr, cursor_sr;
1363 unsigned int enabled = 0;
1366 if (g4x_compute_wm0(dev, PIPE_A,
1367 &g4x_wm_info, pessimal_latency_ns,
1368 &g4x_cursor_wm_info, pessimal_latency_ns,
1369 &planea_wm, &cursora_wm))
1370 enabled |= 1 << PIPE_A;
1372 if (g4x_compute_wm0(dev, PIPE_B,
1373 &g4x_wm_info, pessimal_latency_ns,
1374 &g4x_cursor_wm_info, pessimal_latency_ns,
1375 &planeb_wm, &cursorb_wm))
1376 enabled |= 1 << PIPE_B;
1378 if (single_plane_enabled(enabled) &&
1379 g4x_compute_srwm(dev, ffs(enabled) - 1,
1382 &g4x_cursor_wm_info,
1383 &plane_sr, &cursor_sr)) {
1384 cxsr_enabled = true;
1386 cxsr_enabled = false;
1387 intel_set_memory_cxsr(dev_priv, false);
1388 plane_sr = cursor_sr = 0;
1391 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1392 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1393 planea_wm, cursora_wm,
1394 planeb_wm, cursorb_wm,
1395 plane_sr, cursor_sr);
1398 FW_WM(plane_sr, SR) |
1399 FW_WM(cursorb_wm, CURSORB) |
1400 FW_WM(planeb_wm, PLANEB) |
1401 FW_WM(planea_wm, PLANEA));
1403 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1404 FW_WM(cursora_wm, CURSORA));
1405 /* HPLL off in SR has some issues on G4x... disable it */
1407 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1408 FW_WM(cursor_sr, CURSOR_SR));
1411 intel_set_memory_cxsr(dev_priv, true);
1414 static void i965_update_wm(struct drm_crtc *unused_crtc)
1416 struct drm_device *dev = unused_crtc->dev;
1417 struct drm_i915_private *dev_priv = dev->dev_private;
1418 struct drm_crtc *crtc;
1423 /* Calc sr entries for one plane configs */
1424 crtc = single_enabled_crtc(dev);
1426 /* self-refresh has much higher latency */
1427 static const int sr_latency_ns = 12000;
1428 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1429 int clock = adjusted_mode->crtc_clock;
1430 int htotal = adjusted_mode->crtc_htotal;
1431 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1432 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
1433 unsigned long line_time_us;
1436 line_time_us = max(htotal * 1000 / clock, 1);
1438 /* Use ns/us then divide to preserve precision */
1439 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1440 pixel_size * hdisplay;
1441 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1442 srwm = I965_FIFO_SIZE - entries;
1446 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1449 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1450 pixel_size * crtc->cursor->state->crtc_w;
1451 entries = DIV_ROUND_UP(entries,
1452 i965_cursor_wm_info.cacheline_size);
1453 cursor_sr = i965_cursor_wm_info.fifo_size -
1454 (entries + i965_cursor_wm_info.guard_size);
1456 if (cursor_sr > i965_cursor_wm_info.max_wm)
1457 cursor_sr = i965_cursor_wm_info.max_wm;
1459 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1460 "cursor %d\n", srwm, cursor_sr);
1462 cxsr_enabled = true;
1464 cxsr_enabled = false;
1465 /* Turn off self refresh if both pipes are enabled */
1466 intel_set_memory_cxsr(dev_priv, false);
1469 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1472 /* 965 has limitations... */
1473 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1477 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1478 FW_WM(8, PLANEC_OLD));
1479 /* update cursor SR watermark */
1480 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1483 intel_set_memory_cxsr(dev_priv, true);
1488 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1490 struct drm_device *dev = unused_crtc->dev;
1491 struct drm_i915_private *dev_priv = dev->dev_private;
1492 const struct intel_watermark_params *wm_info;
1497 int planea_wm, planeb_wm;
1498 struct drm_crtc *crtc, *enabled = NULL;
1501 wm_info = &i945_wm_info;
1502 else if (!IS_GEN2(dev))
1503 wm_info = &i915_wm_info;
1505 wm_info = &i830_a_wm_info;
1507 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1508 crtc = intel_get_crtc_for_plane(dev, 0);
1509 if (intel_crtc_active(crtc)) {
1510 const struct drm_display_mode *adjusted_mode;
1511 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1515 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1516 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1517 wm_info, fifo_size, cpp,
1518 pessimal_latency_ns);
1521 planea_wm = fifo_size - wm_info->guard_size;
1522 if (planea_wm > (long)wm_info->max_wm)
1523 planea_wm = wm_info->max_wm;
1527 wm_info = &i830_bc_wm_info;
1529 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1530 crtc = intel_get_crtc_for_plane(dev, 1);
1531 if (intel_crtc_active(crtc)) {
1532 const struct drm_display_mode *adjusted_mode;
1533 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1537 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1538 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1539 wm_info, fifo_size, cpp,
1540 pessimal_latency_ns);
1541 if (enabled == NULL)
1546 planeb_wm = fifo_size - wm_info->guard_size;
1547 if (planeb_wm > (long)wm_info->max_wm)
1548 planeb_wm = wm_info->max_wm;
1551 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1553 if (IS_I915GM(dev) && enabled) {
1554 struct drm_i915_gem_object *obj;
1556 obj = intel_fb_obj(enabled->primary->state->fb);
1558 /* self-refresh seems busted with untiled */
1559 if (obj->tiling_mode == I915_TILING_NONE)
1564 * Overlay gets an aggressive default since video jitter is bad.
1568 /* Play safe and disable self-refresh before adjusting watermarks. */
1569 intel_set_memory_cxsr(dev_priv, false);
1571 /* Calc sr entries for one plane configs */
1572 if (HAS_FW_BLC(dev) && enabled) {
1573 /* self-refresh has much higher latency */
1574 static const int sr_latency_ns = 6000;
1575 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
1576 int clock = adjusted_mode->crtc_clock;
1577 int htotal = adjusted_mode->crtc_htotal;
1578 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1579 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
1580 unsigned long line_time_us;
1583 line_time_us = max(htotal * 1000 / clock, 1);
1585 /* Use ns/us then divide to preserve precision */
1586 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1587 pixel_size * hdisplay;
1588 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1589 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1590 srwm = wm_info->fifo_size - entries;
1594 if (IS_I945G(dev) || IS_I945GM(dev))
1595 I915_WRITE(FW_BLC_SELF,
1596 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1597 else if (IS_I915GM(dev))
1598 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1601 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1602 planea_wm, planeb_wm, cwm, srwm);
1604 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1605 fwater_hi = (cwm & 0x1f);
1607 /* Set request length to 8 cachelines per fetch */
1608 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1609 fwater_hi = fwater_hi | (1 << 8);
1611 I915_WRITE(FW_BLC, fwater_lo);
1612 I915_WRITE(FW_BLC2, fwater_hi);
1615 intel_set_memory_cxsr(dev_priv, true);
1618 static void i845_update_wm(struct drm_crtc *unused_crtc)
1620 struct drm_device *dev = unused_crtc->dev;
1621 struct drm_i915_private *dev_priv = dev->dev_private;
1622 struct drm_crtc *crtc;
1623 const struct drm_display_mode *adjusted_mode;
1627 crtc = single_enabled_crtc(dev);
1631 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1632 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1634 dev_priv->display.get_fifo_size(dev, 0),
1635 4, pessimal_latency_ns);
1636 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1637 fwater_lo |= (3<<8) | planea_wm;
1639 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1641 I915_WRITE(FW_BLC, fwater_lo);
1644 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1646 uint32_t pixel_rate;
1648 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1650 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1651 * adjust the pixel_rate here. */
1653 if (pipe_config->pch_pfit.enabled) {
1654 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1655 uint32_t pfit_size = pipe_config->pch_pfit.size;
1657 pipe_w = pipe_config->pipe_src_w;
1658 pipe_h = pipe_config->pipe_src_h;
1660 pfit_w = (pfit_size >> 16) & 0xFFFF;
1661 pfit_h = pfit_size & 0xFFFF;
1662 if (pipe_w < pfit_w)
1664 if (pipe_h < pfit_h)
1667 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1674 /* latency must be in 0.1us units. */
1675 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1680 if (WARN(latency == 0, "Latency value missing\n"))
1683 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1684 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1689 /* latency must be in 0.1us units. */
1690 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1691 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1696 if (WARN(latency == 0, "Latency value missing\n"))
1699 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1700 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1701 ret = DIV_ROUND_UP(ret, 64) + 2;
1705 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1706 uint8_t bytes_per_pixel)
1708 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1711 struct skl_pipe_wm_parameters {
1713 uint32_t pipe_htotal;
1714 uint32_t pixel_rate; /* in KHz */
1715 struct intel_plane_wm_parameters plane[I915_MAX_PLANES];
1718 struct ilk_wm_maximums {
1725 /* used in computing the new watermarks state */
1726 struct intel_wm_config {
1727 unsigned int num_pipes_active;
1728 bool sprites_enabled;
1729 bool sprites_scaled;
1733 * For both WM_PIPE and WM_LP.
1734 * mem_value must be in 0.1us units.
1736 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1737 const struct intel_plane_state *pstate,
1741 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1742 uint32_t method1, method2;
1744 if (!cstate->base.active || !pstate->visible)
1747 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
1752 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1753 cstate->base.adjusted_mode.crtc_htotal,
1754 drm_rect_width(&pstate->dst),
1758 return min(method1, method2);
1762 * For both WM_PIPE and WM_LP.
1763 * mem_value must be in 0.1us units.
1765 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1766 const struct intel_plane_state *pstate,
1769 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1770 uint32_t method1, method2;
1772 if (!cstate->base.active || !pstate->visible)
1775 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
1776 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1777 cstate->base.adjusted_mode.crtc_htotal,
1778 drm_rect_width(&pstate->dst),
1781 return min(method1, method2);
1785 * For both WM_PIPE and WM_LP.
1786 * mem_value must be in 0.1us units.
1788 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1789 const struct intel_plane_state *pstate,
1792 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1794 if (!cstate->base.active || !pstate->visible)
1797 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1798 cstate->base.adjusted_mode.crtc_htotal,
1799 drm_rect_width(&pstate->dst),
1804 /* Only for WM_LP. */
1805 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1806 const struct intel_plane_state *pstate,
1809 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1811 if (!cstate->base.active || !pstate->visible)
1814 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), bpp);
1817 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1819 if (INTEL_INFO(dev)->gen >= 8)
1821 else if (INTEL_INFO(dev)->gen >= 7)
1827 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1828 int level, bool is_sprite)
1830 if (INTEL_INFO(dev)->gen >= 8)
1831 /* BDW primary/sprite plane watermarks */
1832 return level == 0 ? 255 : 2047;
1833 else if (INTEL_INFO(dev)->gen >= 7)
1834 /* IVB/HSW primary/sprite plane watermarks */
1835 return level == 0 ? 127 : 1023;
1836 else if (!is_sprite)
1837 /* ILK/SNB primary plane watermarks */
1838 return level == 0 ? 127 : 511;
1840 /* ILK/SNB sprite plane watermarks */
1841 return level == 0 ? 63 : 255;
1844 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1847 if (INTEL_INFO(dev)->gen >= 7)
1848 return level == 0 ? 63 : 255;
1850 return level == 0 ? 31 : 63;
1853 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1855 if (INTEL_INFO(dev)->gen >= 8)
1861 /* Calculate the maximum primary/sprite plane watermark */
1862 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1864 const struct intel_wm_config *config,
1865 enum intel_ddb_partitioning ddb_partitioning,
1868 unsigned int fifo_size = ilk_display_fifo_size(dev);
1870 /* if sprites aren't enabled, sprites get nothing */
1871 if (is_sprite && !config->sprites_enabled)
1874 /* HSW allows LP1+ watermarks even with multiple pipes */
1875 if (level == 0 || config->num_pipes_active > 1) {
1876 fifo_size /= INTEL_INFO(dev)->num_pipes;
1879 * For some reason the non self refresh
1880 * FIFO size is only half of the self
1881 * refresh FIFO size on ILK/SNB.
1883 if (INTEL_INFO(dev)->gen <= 6)
1887 if (config->sprites_enabled) {
1888 /* level 0 is always calculated with 1:1 split */
1889 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1898 /* clamp to max that the registers can hold */
1899 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1902 /* Calculate the maximum cursor plane watermark */
1903 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1905 const struct intel_wm_config *config)
1907 /* HSW LP1+ watermarks w/ multiple pipes */
1908 if (level > 0 && config->num_pipes_active > 1)
1911 /* otherwise just report max that registers can hold */
1912 return ilk_cursor_wm_reg_max(dev, level);
1915 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1917 const struct intel_wm_config *config,
1918 enum intel_ddb_partitioning ddb_partitioning,
1919 struct ilk_wm_maximums *max)
1921 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1922 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1923 max->cur = ilk_cursor_wm_max(dev, level, config);
1924 max->fbc = ilk_fbc_wm_reg_max(dev);
1927 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1929 struct ilk_wm_maximums *max)
1931 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1932 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1933 max->cur = ilk_cursor_wm_reg_max(dev, level);
1934 max->fbc = ilk_fbc_wm_reg_max(dev);
1937 static bool ilk_validate_wm_level(int level,
1938 const struct ilk_wm_maximums *max,
1939 struct intel_wm_level *result)
1943 /* already determined to be invalid? */
1944 if (!result->enable)
1947 result->enable = result->pri_val <= max->pri &&
1948 result->spr_val <= max->spr &&
1949 result->cur_val <= max->cur;
1951 ret = result->enable;
1954 * HACK until we can pre-compute everything,
1955 * and thus fail gracefully if LP0 watermarks
1958 if (level == 0 && !result->enable) {
1959 if (result->pri_val > max->pri)
1960 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1961 level, result->pri_val, max->pri);
1962 if (result->spr_val > max->spr)
1963 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1964 level, result->spr_val, max->spr);
1965 if (result->cur_val > max->cur)
1966 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1967 level, result->cur_val, max->cur);
1969 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1970 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1971 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1972 result->enable = true;
1978 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
1979 const struct intel_crtc *intel_crtc,
1981 struct intel_crtc_state *cstate,
1982 struct intel_wm_level *result)
1984 struct intel_plane *intel_plane;
1985 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1986 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1987 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1989 /* WM1+ latency values stored in 0.5us units */
1996 for_each_intel_plane_on_crtc(dev_priv->dev, intel_crtc, intel_plane) {
1997 struct intel_plane_state *pstate =
1998 to_intel_plane_state(intel_plane->base.state);
2000 switch (intel_plane->base.type) {
2001 case DRM_PLANE_TYPE_PRIMARY:
2002 result->pri_val = ilk_compute_pri_wm(cstate, pstate,
2005 result->fbc_val = ilk_compute_fbc_wm(cstate, pstate,
2008 case DRM_PLANE_TYPE_OVERLAY:
2009 result->spr_val = ilk_compute_spr_wm(cstate, pstate,
2012 case DRM_PLANE_TYPE_CURSOR:
2013 result->cur_val = ilk_compute_cur_wm(cstate, pstate,
2019 result->enable = true;
2023 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2025 struct drm_i915_private *dev_priv = dev->dev_private;
2026 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2027 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
2028 u32 linetime, ips_linetime;
2030 if (!intel_crtc->active)
2033 /* The WM are computed with base on how long it takes to fill a single
2034 * row at the given clock rate, multiplied by 8.
2036 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2037 adjusted_mode->crtc_clock);
2038 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2039 dev_priv->cdclk_freq);
2041 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2042 PIPE_WM_LINETIME_TIME(linetime);
2045 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2047 struct drm_i915_private *dev_priv = dev->dev_private;
2052 int level, max_level = ilk_wm_max_level(dev);
2054 /* read the first set of memory latencies[0:3] */
2055 val = 0; /* data0 to be programmed to 0 for first set */
2056 mutex_lock(&dev_priv->rps.hw_lock);
2057 ret = sandybridge_pcode_read(dev_priv,
2058 GEN9_PCODE_READ_MEM_LATENCY,
2060 mutex_unlock(&dev_priv->rps.hw_lock);
2063 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2067 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2068 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2069 GEN9_MEM_LATENCY_LEVEL_MASK;
2070 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2071 GEN9_MEM_LATENCY_LEVEL_MASK;
2072 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2073 GEN9_MEM_LATENCY_LEVEL_MASK;
2075 /* read the second set of memory latencies[4:7] */
2076 val = 1; /* data0 to be programmed to 1 for second set */
2077 mutex_lock(&dev_priv->rps.hw_lock);
2078 ret = sandybridge_pcode_read(dev_priv,
2079 GEN9_PCODE_READ_MEM_LATENCY,
2081 mutex_unlock(&dev_priv->rps.hw_lock);
2083 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2087 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2088 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2089 GEN9_MEM_LATENCY_LEVEL_MASK;
2090 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2091 GEN9_MEM_LATENCY_LEVEL_MASK;
2092 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2093 GEN9_MEM_LATENCY_LEVEL_MASK;
2096 * WaWmMemoryReadLatency:skl
2098 * punit doesn't take into account the read latency so we need
2099 * to add 2us to the various latency levels we retrieve from
2101 * - W0 is a bit special in that it's the only level that
2102 * can't be disabled if we want to have display working, so
2103 * we always add 2us there.
2104 * - For levels >=1, punit returns 0us latency when they are
2105 * disabled, so we respect that and don't add 2us then
2107 * Additionally, if a level n (n > 1) has a 0us latency, all
2108 * levels m (m >= n) need to be disabled. We make sure to
2109 * sanitize the values out of the punit to satisfy this
2113 for (level = 1; level <= max_level; level++)
2117 for (i = level + 1; i <= max_level; i++)
2122 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2123 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2125 wm[0] = (sskpd >> 56) & 0xFF;
2127 wm[0] = sskpd & 0xF;
2128 wm[1] = (sskpd >> 4) & 0xFF;
2129 wm[2] = (sskpd >> 12) & 0xFF;
2130 wm[3] = (sskpd >> 20) & 0x1FF;
2131 wm[4] = (sskpd >> 32) & 0x1FF;
2132 } else if (INTEL_INFO(dev)->gen >= 6) {
2133 uint32_t sskpd = I915_READ(MCH_SSKPD);
2135 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2136 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2137 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2138 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2139 } else if (INTEL_INFO(dev)->gen >= 5) {
2140 uint32_t mltr = I915_READ(MLTR_ILK);
2142 /* ILK primary LP0 latency is 700 ns */
2144 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2145 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2149 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2151 /* ILK sprite LP0 latency is 1300 ns */
2152 if (INTEL_INFO(dev)->gen == 5)
2156 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2158 /* ILK cursor LP0 latency is 1300 ns */
2159 if (INTEL_INFO(dev)->gen == 5)
2162 /* WaDoubleCursorLP3Latency:ivb */
2163 if (IS_IVYBRIDGE(dev))
2167 int ilk_wm_max_level(const struct drm_device *dev)
2169 /* how many WM levels are we expecting */
2170 if (INTEL_INFO(dev)->gen >= 9)
2172 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2174 else if (INTEL_INFO(dev)->gen >= 6)
2180 static void intel_print_wm_latency(struct drm_device *dev,
2182 const uint16_t wm[8])
2184 int level, max_level = ilk_wm_max_level(dev);
2186 for (level = 0; level <= max_level; level++) {
2187 unsigned int latency = wm[level];
2190 DRM_ERROR("%s WM%d latency not provided\n",
2196 * - latencies are in us on gen9.
2197 * - before then, WM1+ latency values are in 0.5us units
2204 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2205 name, level, wm[level],
2206 latency / 10, latency % 10);
2210 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2211 uint16_t wm[5], uint16_t min)
2213 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2218 wm[0] = max(wm[0], min);
2219 for (level = 1; level <= max_level; level++)
2220 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2225 static void snb_wm_latency_quirk(struct drm_device *dev)
2227 struct drm_i915_private *dev_priv = dev->dev_private;
2231 * The BIOS provided WM memory latency values are often
2232 * inadequate for high resolution displays. Adjust them.
2234 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2235 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2236 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2241 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2242 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2243 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2244 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2247 static void ilk_setup_wm_latency(struct drm_device *dev)
2249 struct drm_i915_private *dev_priv = dev->dev_private;
2251 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2253 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2254 sizeof(dev_priv->wm.pri_latency));
2255 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2256 sizeof(dev_priv->wm.pri_latency));
2258 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2259 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2261 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2262 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2263 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2266 snb_wm_latency_quirk(dev);
2269 static void skl_setup_wm_latency(struct drm_device *dev)
2271 struct drm_i915_private *dev_priv = dev->dev_private;
2273 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2274 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2277 static void ilk_compute_wm_config(struct drm_device *dev,
2278 struct intel_wm_config *config)
2280 struct intel_crtc *intel_crtc;
2282 /* Compute the currently _active_ config */
2283 for_each_intel_crtc(dev, intel_crtc) {
2284 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
2286 if (!wm->pipe_enabled)
2289 config->sprites_enabled |= wm->sprites_enabled;
2290 config->sprites_scaled |= wm->sprites_scaled;
2291 config->num_pipes_active++;
2295 /* Compute new watermarks for the pipe */
2296 static bool intel_compute_pipe_wm(struct intel_crtc_state *cstate,
2297 struct intel_pipe_wm *pipe_wm)
2299 struct drm_crtc *crtc = cstate->base.crtc;
2300 struct drm_device *dev = crtc->dev;
2301 const struct drm_i915_private *dev_priv = dev->dev_private;
2302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2303 struct intel_plane *intel_plane;
2304 struct intel_plane_state *sprstate = NULL;
2305 int level, max_level = ilk_wm_max_level(dev);
2306 /* LP0 watermark maximums depend on this pipe alone */
2307 struct intel_wm_config config = {
2308 .num_pipes_active = 1,
2310 struct ilk_wm_maximums max;
2312 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2313 if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY) {
2314 sprstate = to_intel_plane_state(intel_plane->base.state);
2319 config.sprites_enabled = sprstate->visible;
2320 config.sprites_scaled = sprstate->visible &&
2321 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2322 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2324 pipe_wm->pipe_enabled = cstate->base.active;
2325 pipe_wm->sprites_enabled = sprstate->visible;
2326 pipe_wm->sprites_scaled = config.sprites_scaled;
2328 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2329 if (INTEL_INFO(dev)->gen <= 6 && sprstate->visible)
2332 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2333 if (config.sprites_scaled)
2336 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate, &pipe_wm->wm[0]);
2338 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2339 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2341 /* LP0 watermarks always use 1/2 DDB partitioning */
2342 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2344 /* At least LP0 must be valid */
2345 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2348 ilk_compute_wm_reg_maximums(dev, 1, &max);
2350 for (level = 1; level <= max_level; level++) {
2351 struct intel_wm_level wm = {};
2353 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate, &wm);
2356 * Disable any watermark level that exceeds the
2357 * register maximums since such watermarks are
2360 if (!ilk_validate_wm_level(level, &max, &wm))
2363 pipe_wm->wm[level] = wm;
2370 * Merge the watermarks from all active pipes for a specific level.
2372 static void ilk_merge_wm_level(struct drm_device *dev,
2374 struct intel_wm_level *ret_wm)
2376 const struct intel_crtc *intel_crtc;
2378 ret_wm->enable = true;
2380 for_each_intel_crtc(dev, intel_crtc) {
2381 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2382 const struct intel_wm_level *wm = &active->wm[level];
2384 if (!active->pipe_enabled)
2388 * The watermark values may have been used in the past,
2389 * so we must maintain them in the registers for some
2390 * time even if the level is now disabled.
2393 ret_wm->enable = false;
2395 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2396 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2397 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2398 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2403 * Merge all low power watermarks for all active pipes.
2405 static void ilk_wm_merge(struct drm_device *dev,
2406 const struct intel_wm_config *config,
2407 const struct ilk_wm_maximums *max,
2408 struct intel_pipe_wm *merged)
2410 struct drm_i915_private *dev_priv = dev->dev_private;
2411 int level, max_level = ilk_wm_max_level(dev);
2412 int last_enabled_level = max_level;
2414 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2415 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2416 config->num_pipes_active > 1)
2419 /* ILK: FBC WM must be disabled always */
2420 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2422 /* merge each WM1+ level */
2423 for (level = 1; level <= max_level; level++) {
2424 struct intel_wm_level *wm = &merged->wm[level];
2426 ilk_merge_wm_level(dev, level, wm);
2428 if (level > last_enabled_level)
2430 else if (!ilk_validate_wm_level(level, max, wm))
2431 /* make sure all following levels get disabled */
2432 last_enabled_level = level - 1;
2435 * The spec says it is preferred to disable
2436 * FBC WMs instead of disabling a WM level.
2438 if (wm->fbc_val > max->fbc) {
2440 merged->fbc_wm_enabled = false;
2445 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2447 * FIXME this is racy. FBC might get enabled later.
2448 * What we should check here is whether FBC can be
2449 * enabled sometime later.
2451 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2452 intel_fbc_enabled(dev_priv)) {
2453 for (level = 2; level <= max_level; level++) {
2454 struct intel_wm_level *wm = &merged->wm[level];
2461 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2463 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2464 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2467 /* The value we need to program into the WM_LPx latency field */
2468 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2470 struct drm_i915_private *dev_priv = dev->dev_private;
2472 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2475 return dev_priv->wm.pri_latency[level];
2478 static void ilk_compute_wm_results(struct drm_device *dev,
2479 const struct intel_pipe_wm *merged,
2480 enum intel_ddb_partitioning partitioning,
2481 struct ilk_wm_values *results)
2483 struct intel_crtc *intel_crtc;
2486 results->enable_fbc_wm = merged->fbc_wm_enabled;
2487 results->partitioning = partitioning;
2489 /* LP1+ register values */
2490 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2491 const struct intel_wm_level *r;
2493 level = ilk_wm_lp_to_level(wm_lp, merged);
2495 r = &merged->wm[level];
2498 * Maintain the watermark values even if the level is
2499 * disabled. Doing otherwise could cause underruns.
2501 results->wm_lp[wm_lp - 1] =
2502 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2503 (r->pri_val << WM1_LP_SR_SHIFT) |
2507 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2509 if (INTEL_INFO(dev)->gen >= 8)
2510 results->wm_lp[wm_lp - 1] |=
2511 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2513 results->wm_lp[wm_lp - 1] |=
2514 r->fbc_val << WM1_LP_FBC_SHIFT;
2517 * Always set WM1S_LP_EN when spr_val != 0, even if the
2518 * level is disabled. Doing otherwise could cause underruns.
2520 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2521 WARN_ON(wm_lp != 1);
2522 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2524 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2527 /* LP0 register values */
2528 for_each_intel_crtc(dev, intel_crtc) {
2529 enum pipe pipe = intel_crtc->pipe;
2530 const struct intel_wm_level *r =
2531 &intel_crtc->wm.active.wm[0];
2533 if (WARN_ON(!r->enable))
2536 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2538 results->wm_pipe[pipe] =
2539 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2540 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2545 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2546 * case both are at the same level. Prefer r1 in case they're the same. */
2547 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2548 struct intel_pipe_wm *r1,
2549 struct intel_pipe_wm *r2)
2551 int level, max_level = ilk_wm_max_level(dev);
2552 int level1 = 0, level2 = 0;
2554 for (level = 1; level <= max_level; level++) {
2555 if (r1->wm[level].enable)
2557 if (r2->wm[level].enable)
2561 if (level1 == level2) {
2562 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2566 } else if (level1 > level2) {
2573 /* dirty bits used to track which watermarks need changes */
2574 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2575 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2576 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2577 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2578 #define WM_DIRTY_FBC (1 << 24)
2579 #define WM_DIRTY_DDB (1 << 25)
2581 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2582 const struct ilk_wm_values *old,
2583 const struct ilk_wm_values *new)
2585 unsigned int dirty = 0;
2589 for_each_pipe(dev_priv, pipe) {
2590 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2591 dirty |= WM_DIRTY_LINETIME(pipe);
2592 /* Must disable LP1+ watermarks too */
2593 dirty |= WM_DIRTY_LP_ALL;
2596 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2597 dirty |= WM_DIRTY_PIPE(pipe);
2598 /* Must disable LP1+ watermarks too */
2599 dirty |= WM_DIRTY_LP_ALL;
2603 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2604 dirty |= WM_DIRTY_FBC;
2605 /* Must disable LP1+ watermarks too */
2606 dirty |= WM_DIRTY_LP_ALL;
2609 if (old->partitioning != new->partitioning) {
2610 dirty |= WM_DIRTY_DDB;
2611 /* Must disable LP1+ watermarks too */
2612 dirty |= WM_DIRTY_LP_ALL;
2615 /* LP1+ watermarks already deemed dirty, no need to continue */
2616 if (dirty & WM_DIRTY_LP_ALL)
2619 /* Find the lowest numbered LP1+ watermark in need of an update... */
2620 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2621 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2622 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2626 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2627 for (; wm_lp <= 3; wm_lp++)
2628 dirty |= WM_DIRTY_LP(wm_lp);
2633 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2636 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2637 bool changed = false;
2639 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2640 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2641 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2644 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2645 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2646 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2649 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2650 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2651 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2656 * Don't touch WM1S_LP_EN here.
2657 * Doing so could cause underruns.
2664 * The spec says we shouldn't write when we don't need, because every write
2665 * causes WMs to be re-evaluated, expending some power.
2667 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2668 struct ilk_wm_values *results)
2670 struct drm_device *dev = dev_priv->dev;
2671 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2675 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2679 _ilk_disable_lp_wm(dev_priv, dirty);
2681 if (dirty & WM_DIRTY_PIPE(PIPE_A))
2682 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2683 if (dirty & WM_DIRTY_PIPE(PIPE_B))
2684 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2685 if (dirty & WM_DIRTY_PIPE(PIPE_C))
2686 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2688 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2689 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2690 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2691 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2692 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2693 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2695 if (dirty & WM_DIRTY_DDB) {
2696 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2697 val = I915_READ(WM_MISC);
2698 if (results->partitioning == INTEL_DDB_PART_1_2)
2699 val &= ~WM_MISC_DATA_PARTITION_5_6;
2701 val |= WM_MISC_DATA_PARTITION_5_6;
2702 I915_WRITE(WM_MISC, val);
2704 val = I915_READ(DISP_ARB_CTL2);
2705 if (results->partitioning == INTEL_DDB_PART_1_2)
2706 val &= ~DISP_DATA_PARTITION_5_6;
2708 val |= DISP_DATA_PARTITION_5_6;
2709 I915_WRITE(DISP_ARB_CTL2, val);
2713 if (dirty & WM_DIRTY_FBC) {
2714 val = I915_READ(DISP_ARB_CTL);
2715 if (results->enable_fbc_wm)
2716 val &= ~DISP_FBC_WM_DIS;
2718 val |= DISP_FBC_WM_DIS;
2719 I915_WRITE(DISP_ARB_CTL, val);
2722 if (dirty & WM_DIRTY_LP(1) &&
2723 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2724 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2726 if (INTEL_INFO(dev)->gen >= 7) {
2727 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2728 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2729 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2730 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2733 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2734 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2735 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2736 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2737 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2738 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2740 dev_priv->wm.hw = *results;
2743 static bool ilk_disable_lp_wm(struct drm_device *dev)
2745 struct drm_i915_private *dev_priv = dev->dev_private;
2747 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2751 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2752 * different active planes.
2755 #define SKL_DDB_SIZE 896 /* in blocks */
2756 #define BXT_DDB_SIZE 512
2759 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2760 struct drm_crtc *for_crtc,
2761 const struct intel_wm_config *config,
2762 const struct skl_pipe_wm_parameters *params,
2763 struct skl_ddb_entry *alloc /* out */)
2765 struct drm_crtc *crtc;
2766 unsigned int pipe_size, ddb_size;
2767 int nth_active_pipe;
2769 if (!params->active) {
2775 if (IS_BROXTON(dev))
2776 ddb_size = BXT_DDB_SIZE;
2778 ddb_size = SKL_DDB_SIZE;
2780 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2782 nth_active_pipe = 0;
2783 for_each_crtc(dev, crtc) {
2784 if (!to_intel_crtc(crtc)->active)
2787 if (crtc == for_crtc)
2793 pipe_size = ddb_size / config->num_pipes_active;
2794 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
2795 alloc->end = alloc->start + pipe_size;
2798 static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2800 if (config->num_pipes_active == 1)
2806 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2808 entry->start = reg & 0x3ff;
2809 entry->end = (reg >> 16) & 0x3ff;
2814 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2815 struct skl_ddb_allocation *ddb /* out */)
2821 memset(ddb, 0, sizeof(*ddb));
2823 for_each_pipe(dev_priv, pipe) {
2824 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe)))
2827 for_each_plane(dev_priv, pipe, plane) {
2828 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2829 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2833 val = I915_READ(CUR_BUF_CFG(pipe));
2834 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2840 skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p, int y)
2843 /* for planar format */
2844 if (p->y_bytes_per_pixel) {
2845 if (y) /* y-plane data rate */
2846 return p->horiz_pixels * p->vert_pixels * p->y_bytes_per_pixel;
2847 else /* uv-plane data rate */
2848 return (p->horiz_pixels/2) * (p->vert_pixels/2) * p->bytes_per_pixel;
2851 /* for packed formats */
2852 return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel;
2856 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2857 * a 8192x4096@32bpp framebuffer:
2858 * 3 * 4096 * 8192 * 4 < 2^32
2861 skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
2862 const struct skl_pipe_wm_parameters *params)
2864 unsigned int total_data_rate = 0;
2867 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2868 const struct intel_plane_wm_parameters *p;
2870 p = ¶ms->plane[plane];
2874 total_data_rate += skl_plane_relative_data_rate(p, 0); /* packed/uv */
2875 if (p->y_bytes_per_pixel) {
2876 total_data_rate += skl_plane_relative_data_rate(p, 1); /* y-plane */
2880 return total_data_rate;
2884 skl_allocate_pipe_ddb(struct drm_crtc *crtc,
2885 const struct intel_wm_config *config,
2886 const struct skl_pipe_wm_parameters *params,
2887 struct skl_ddb_allocation *ddb /* out */)
2889 struct drm_device *dev = crtc->dev;
2890 struct drm_i915_private *dev_priv = dev->dev_private;
2891 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2892 enum pipe pipe = intel_crtc->pipe;
2893 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
2894 uint16_t alloc_size, start, cursor_blocks;
2895 uint16_t minimum[I915_MAX_PLANES];
2896 uint16_t y_minimum[I915_MAX_PLANES];
2897 unsigned int total_data_rate;
2900 skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc);
2901 alloc_size = skl_ddb_entry_size(alloc);
2902 if (alloc_size == 0) {
2903 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2904 memset(&ddb->plane[pipe][PLANE_CURSOR], 0,
2905 sizeof(ddb->plane[pipe][PLANE_CURSOR]));
2909 cursor_blocks = skl_cursor_allocation(config);
2910 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
2911 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
2913 alloc_size -= cursor_blocks;
2914 alloc->end -= cursor_blocks;
2916 /* 1. Allocate the mininum required blocks for each active plane */
2917 for_each_plane(dev_priv, pipe, plane) {
2918 const struct intel_plane_wm_parameters *p;
2920 p = ¶ms->plane[plane];
2925 alloc_size -= minimum[plane];
2926 y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0;
2927 alloc_size -= y_minimum[plane];
2931 * 2. Distribute the remaining space in proportion to the amount of
2932 * data each plane needs to fetch from memory.
2934 * FIXME: we may not allocate every single block here.
2936 total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
2938 start = alloc->start;
2939 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2940 const struct intel_plane_wm_parameters *p;
2941 unsigned int data_rate, y_data_rate;
2942 uint16_t plane_blocks, y_plane_blocks = 0;
2944 p = ¶ms->plane[plane];
2948 data_rate = skl_plane_relative_data_rate(p, 0);
2951 * allocation for (packed formats) or (uv-plane part of planar format):
2952 * promote the expression to 64 bits to avoid overflowing, the
2953 * result is < available as data_rate / total_data_rate < 1
2955 plane_blocks = minimum[plane];
2956 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
2959 ddb->plane[pipe][plane].start = start;
2960 ddb->plane[pipe][plane].end = start + plane_blocks;
2962 start += plane_blocks;
2965 * allocation for y_plane part of planar format:
2967 if (p->y_bytes_per_pixel) {
2968 y_data_rate = skl_plane_relative_data_rate(p, 1);
2969 y_plane_blocks = y_minimum[plane];
2970 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
2973 ddb->y_plane[pipe][plane].start = start;
2974 ddb->y_plane[pipe][plane].end = start + y_plane_blocks;
2976 start += y_plane_blocks;
2983 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2985 /* TODO: Take into account the scalers once we support them */
2986 return config->base.adjusted_mode.crtc_clock;
2990 * The max latency should be 257 (max the punit can code is 255 and we add 2us
2991 * for the read latency) and bytes_per_pixel should always be <= 8, so that
2992 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
2993 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
2995 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
2998 uint32_t wm_intermediate_val, ret;
3003 wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
3004 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3009 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3010 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
3011 uint64_t tiling, uint32_t latency)
3014 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3015 uint32_t wm_intermediate_val;
3020 plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
3022 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3023 tiling == I915_FORMAT_MOD_Yf_TILED) {
3024 plane_bytes_per_line *= 4;
3025 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3026 plane_blocks_per_line /= 4;
3028 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3031 wm_intermediate_val = latency * pixel_rate;
3032 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3033 plane_blocks_per_line;
3038 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3039 const struct intel_crtc *intel_crtc)
3041 struct drm_device *dev = intel_crtc->base.dev;
3042 struct drm_i915_private *dev_priv = dev->dev_private;
3043 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3044 enum pipe pipe = intel_crtc->pipe;
3046 if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
3047 sizeof(new_ddb->plane[pipe])))
3050 if (memcmp(&new_ddb->plane[pipe][PLANE_CURSOR], &cur_ddb->plane[pipe][PLANE_CURSOR],
3051 sizeof(new_ddb->plane[pipe][PLANE_CURSOR])))
3057 static void skl_compute_wm_global_parameters(struct drm_device *dev,
3058 struct intel_wm_config *config)
3060 struct drm_crtc *crtc;
3061 struct drm_plane *plane;
3063 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3064 config->num_pipes_active += to_intel_crtc(crtc)->active;
3066 /* FIXME: I don't think we need those two global parameters on SKL */
3067 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3068 struct intel_plane *intel_plane = to_intel_plane(plane);
3070 config->sprites_enabled |= intel_plane->wm.enabled;
3071 config->sprites_scaled |= intel_plane->wm.scaled;
3075 static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
3076 struct skl_pipe_wm_parameters *p)
3078 struct drm_device *dev = crtc->dev;
3079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3080 enum pipe pipe = intel_crtc->pipe;
3081 struct drm_plane *plane;
3082 struct drm_framebuffer *fb;
3083 int i = 1; /* Index for sprite planes start */
3085 p->active = intel_crtc->active;
3087 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
3088 p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
3090 fb = crtc->primary->state->fb;
3091 /* For planar: Bpp is for uv plane, y_Bpp is for y plane */
3093 p->plane[0].enabled = true;
3094 p->plane[0].bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
3095 drm_format_plane_cpp(fb->pixel_format, 1) :
3096 drm_format_plane_cpp(fb->pixel_format, 0);
3097 p->plane[0].y_bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
3098 drm_format_plane_cpp(fb->pixel_format, 0) : 0;
3099 p->plane[0].tiling = fb->modifier[0];
3101 p->plane[0].enabled = false;
3102 p->plane[0].bytes_per_pixel = 0;
3103 p->plane[0].y_bytes_per_pixel = 0;
3104 p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
3106 p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
3107 p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
3108 p->plane[0].rotation = crtc->primary->state->rotation;
3110 fb = crtc->cursor->state->fb;
3111 p->plane[PLANE_CURSOR].y_bytes_per_pixel = 0;
3113 p->plane[PLANE_CURSOR].enabled = true;
3114 p->plane[PLANE_CURSOR].bytes_per_pixel = fb->bits_per_pixel / 8;
3115 p->plane[PLANE_CURSOR].horiz_pixels = crtc->cursor->state->crtc_w;
3116 p->plane[PLANE_CURSOR].vert_pixels = crtc->cursor->state->crtc_h;
3118 p->plane[PLANE_CURSOR].enabled = false;
3119 p->plane[PLANE_CURSOR].bytes_per_pixel = 0;
3120 p->plane[PLANE_CURSOR].horiz_pixels = 64;
3121 p->plane[PLANE_CURSOR].vert_pixels = 64;
3125 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3126 struct intel_plane *intel_plane = to_intel_plane(plane);
3128 if (intel_plane->pipe == pipe &&
3129 plane->type == DRM_PLANE_TYPE_OVERLAY)
3130 p->plane[i++] = intel_plane->wm;
3134 static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3135 struct skl_pipe_wm_parameters *p,
3136 struct intel_plane_wm_parameters *p_params,
3137 uint16_t ddb_allocation,
3139 uint16_t *out_blocks, /* out */
3140 uint8_t *out_lines /* out */)
3142 uint32_t latency = dev_priv->wm.skl_latency[level];
3143 uint32_t method1, method2;
3144 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3145 uint32_t res_blocks, res_lines;
3146 uint32_t selected_result;
3147 uint8_t bytes_per_pixel;
3149 if (latency == 0 || !p->active || !p_params->enabled)
3152 bytes_per_pixel = p_params->y_bytes_per_pixel ?
3153 p_params->y_bytes_per_pixel :
3154 p_params->bytes_per_pixel;
3155 method1 = skl_wm_method1(p->pixel_rate,
3158 method2 = skl_wm_method2(p->pixel_rate,
3160 p_params->horiz_pixels,
3165 plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel;
3166 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3168 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
3169 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
3170 uint32_t min_scanlines = 4;
3171 uint32_t y_tile_minimum;
3172 if (intel_rotation_90_or_270(p_params->rotation)) {
3173 switch (p_params->bytes_per_pixel) {
3181 WARN(1, "Unsupported pixel depth for rotation");
3184 y_tile_minimum = plane_blocks_per_line * min_scanlines;
3185 selected_result = max(method2, y_tile_minimum);
3187 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3188 selected_result = min(method1, method2);
3190 selected_result = method1;
3193 res_blocks = selected_result + 1;
3194 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3196 if (level >= 1 && level <= 7) {
3197 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
3198 p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
3204 if (res_blocks >= ddb_allocation || res_lines > 31)
3207 *out_blocks = res_blocks;
3208 *out_lines = res_lines;
3213 static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3214 struct skl_ddb_allocation *ddb,
3215 struct skl_pipe_wm_parameters *p,
3219 struct skl_wm_level *result)
3221 uint16_t ddb_blocks;
3224 for (i = 0; i < num_planes; i++) {
3225 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3227 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3231 &result->plane_res_b[i],
3232 &result->plane_res_l[i]);
3235 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][PLANE_CURSOR]);
3236 result->plane_en[PLANE_CURSOR] = skl_compute_plane_wm(dev_priv, p,
3237 &p->plane[PLANE_CURSOR],
3239 &result->plane_res_b[PLANE_CURSOR],
3240 &result->plane_res_l[PLANE_CURSOR]);
3244 skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)
3246 if (!to_intel_crtc(crtc)->active)
3249 if (WARN_ON(p->pixel_rate == 0))
3252 return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);
3255 static void skl_compute_transition_wm(struct drm_crtc *crtc,
3256 struct skl_pipe_wm_parameters *params,
3257 struct skl_wm_level *trans_wm /* out */)
3259 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3262 if (!params->active)
3265 /* Until we know more, just disable transition WMs */
3266 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3267 trans_wm->plane_en[i] = false;
3268 trans_wm->plane_en[PLANE_CURSOR] = false;
3271 static void skl_compute_pipe_wm(struct drm_crtc *crtc,
3272 struct skl_ddb_allocation *ddb,
3273 struct skl_pipe_wm_parameters *params,
3274 struct skl_pipe_wm *pipe_wm)
3276 struct drm_device *dev = crtc->dev;
3277 const struct drm_i915_private *dev_priv = dev->dev_private;
3278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3279 int level, max_level = ilk_wm_max_level(dev);
3281 for (level = 0; level <= max_level; level++) {
3282 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,
3283 level, intel_num_planes(intel_crtc),
3284 &pipe_wm->wm[level]);
3286 pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);
3288 skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm);
3291 static void skl_compute_wm_results(struct drm_device *dev,
3292 struct skl_pipe_wm_parameters *p,
3293 struct skl_pipe_wm *p_wm,
3294 struct skl_wm_values *r,
3295 struct intel_crtc *intel_crtc)
3297 int level, max_level = ilk_wm_max_level(dev);
3298 enum pipe pipe = intel_crtc->pipe;
3302 for (level = 0; level <= max_level; level++) {
3303 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3306 temp |= p_wm->wm[level].plane_res_l[i] <<
3307 PLANE_WM_LINES_SHIFT;
3308 temp |= p_wm->wm[level].plane_res_b[i];
3309 if (p_wm->wm[level].plane_en[i])
3310 temp |= PLANE_WM_EN;
3312 r->plane[pipe][i][level] = temp;
3317 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3318 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
3320 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
3321 temp |= PLANE_WM_EN;
3323 r->plane[pipe][PLANE_CURSOR][level] = temp;
3327 /* transition WMs */
3328 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3330 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3331 temp |= p_wm->trans_wm.plane_res_b[i];
3332 if (p_wm->trans_wm.plane_en[i])
3333 temp |= PLANE_WM_EN;
3335 r->plane_trans[pipe][i] = temp;
3339 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3340 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3341 if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
3342 temp |= PLANE_WM_EN;
3344 r->plane_trans[pipe][PLANE_CURSOR] = temp;
3346 r->wm_linetime[pipe] = p_wm->linetime;
3349 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
3350 const struct skl_ddb_entry *entry)
3353 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3358 static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3359 const struct skl_wm_values *new)
3361 struct drm_device *dev = dev_priv->dev;
3362 struct intel_crtc *crtc;
3364 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3365 int i, level, max_level = ilk_wm_max_level(dev);
3366 enum pipe pipe = crtc->pipe;
3368 if (!new->dirty[pipe])
3371 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
3373 for (level = 0; level <= max_level; level++) {
3374 for (i = 0; i < intel_num_planes(crtc); i++)
3375 I915_WRITE(PLANE_WM(pipe, i, level),
3376 new->plane[pipe][i][level]);
3377 I915_WRITE(CUR_WM(pipe, level),
3378 new->plane[pipe][PLANE_CURSOR][level]);
3380 for (i = 0; i < intel_num_planes(crtc); i++)
3381 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3382 new->plane_trans[pipe][i]);
3383 I915_WRITE(CUR_WM_TRANS(pipe),
3384 new->plane_trans[pipe][PLANE_CURSOR]);
3386 for (i = 0; i < intel_num_planes(crtc); i++) {
3387 skl_ddb_entry_write(dev_priv,
3388 PLANE_BUF_CFG(pipe, i),
3389 &new->ddb.plane[pipe][i]);
3390 skl_ddb_entry_write(dev_priv,
3391 PLANE_NV12_BUF_CFG(pipe, i),
3392 &new->ddb.y_plane[pipe][i]);
3395 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3396 &new->ddb.plane[pipe][PLANE_CURSOR]);
3401 * When setting up a new DDB allocation arrangement, we need to correctly
3402 * sequence the times at which the new allocations for the pipes are taken into
3403 * account or we'll have pipes fetching from space previously allocated to
3406 * Roughly the sequence looks like:
3407 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3408 * overlapping with a previous light-up pipe (another way to put it is:
3409 * pipes with their new allocation strickly included into their old ones).
3410 * 2. re-allocate the other pipes that get their allocation reduced
3411 * 3. allocate the pipes having their allocation increased
3413 * Steps 1. and 2. are here to take care of the following case:
3414 * - Initially DDB looks like this:
3417 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3421 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3425 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
3429 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3431 for_each_plane(dev_priv, pipe, plane) {
3432 I915_WRITE(PLANE_SURF(pipe, plane),
3433 I915_READ(PLANE_SURF(pipe, plane)));
3435 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3439 skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3440 const struct skl_ddb_allocation *new,
3443 uint16_t old_size, new_size;
3445 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3446 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3448 return old_size != new_size &&
3449 new->pipe[pipe].start >= old->pipe[pipe].start &&
3450 new->pipe[pipe].end <= old->pipe[pipe].end;
3453 static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3454 struct skl_wm_values *new_values)
3456 struct drm_device *dev = dev_priv->dev;
3457 struct skl_ddb_allocation *cur_ddb, *new_ddb;
3458 bool reallocated[I915_MAX_PIPES] = {};
3459 struct intel_crtc *crtc;
3462 new_ddb = &new_values->ddb;
3463 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3466 * First pass: flush the pipes with the new allocation contained into
3469 * We'll wait for the vblank on those pipes to ensure we can safely
3470 * re-allocate the freed space without this pipe fetching from it.
3472 for_each_intel_crtc(dev, crtc) {
3478 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3481 skl_wm_flush_pipe(dev_priv, pipe, 1);
3482 intel_wait_for_vblank(dev, pipe);
3484 reallocated[pipe] = true;
3489 * Second pass: flush the pipes that are having their allocation
3490 * reduced, but overlapping with a previous allocation.
3492 * Here as well we need to wait for the vblank to make sure the freed
3493 * space is not used anymore.
3495 for_each_intel_crtc(dev, crtc) {
3501 if (reallocated[pipe])
3504 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3505 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
3506 skl_wm_flush_pipe(dev_priv, pipe, 2);
3507 intel_wait_for_vblank(dev, pipe);
3508 reallocated[pipe] = true;
3513 * Third pass: flush the pipes that got more space allocated.
3515 * We don't need to actively wait for the update here, next vblank
3516 * will just get more DDB space with the correct WM values.
3518 for_each_intel_crtc(dev, crtc) {
3525 * At this point, only the pipes more space than before are
3526 * left to re-allocate.
3528 if (reallocated[pipe])
3531 skl_wm_flush_pipe(dev_priv, pipe, 3);
3535 static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3536 struct skl_pipe_wm_parameters *params,
3537 struct intel_wm_config *config,
3538 struct skl_ddb_allocation *ddb, /* out */
3539 struct skl_pipe_wm *pipe_wm /* out */)
3541 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3543 skl_compute_wm_pipe_parameters(crtc, params);
3544 skl_allocate_pipe_ddb(crtc, config, params, ddb);
3545 skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);
3547 if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
3550 intel_crtc->wm.skl_active = *pipe_wm;
3555 static void skl_update_other_pipe_wm(struct drm_device *dev,
3556 struct drm_crtc *crtc,
3557 struct intel_wm_config *config,
3558 struct skl_wm_values *r)
3560 struct intel_crtc *intel_crtc;
3561 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3564 * If the WM update hasn't changed the allocation for this_crtc (the
3565 * crtc we are currently computing the new WM values for), other
3566 * enabled crtcs will keep the same allocation and we don't need to
3567 * recompute anything for them.
3569 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3573 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3574 * other active pipes need new DDB allocation and WM values.
3576 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3578 struct skl_pipe_wm_parameters params = {};
3579 struct skl_pipe_wm pipe_wm = {};
3582 if (this_crtc->pipe == intel_crtc->pipe)
3585 if (!intel_crtc->active)
3588 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3593 * If we end up re-computing the other pipe WM values, it's
3594 * because it was really needed, so we expect the WM values to
3597 WARN_ON(!wm_changed);
3599 skl_compute_wm_results(dev, ¶ms, &pipe_wm, r, intel_crtc);
3600 r->dirty[intel_crtc->pipe] = true;
3604 static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3606 watermarks->wm_linetime[pipe] = 0;
3607 memset(watermarks->plane[pipe], 0,
3608 sizeof(uint32_t) * 8 * I915_MAX_PLANES);
3609 memset(watermarks->plane_trans[pipe],
3610 0, sizeof(uint32_t) * I915_MAX_PLANES);
3611 watermarks->plane_trans[pipe][PLANE_CURSOR] = 0;
3613 /* Clear ddb entries for pipe */
3614 memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
3615 memset(&watermarks->ddb.plane[pipe], 0,
3616 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3617 memset(&watermarks->ddb.y_plane[pipe], 0,
3618 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3619 memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0,
3620 sizeof(struct skl_ddb_entry));
3624 static void skl_update_wm(struct drm_crtc *crtc)
3626 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3627 struct drm_device *dev = crtc->dev;
3628 struct drm_i915_private *dev_priv = dev->dev_private;
3629 struct skl_pipe_wm_parameters params = {};
3630 struct skl_wm_values *results = &dev_priv->wm.skl_results;
3631 struct skl_pipe_wm pipe_wm = {};
3632 struct intel_wm_config config = {};
3635 /* Clear all dirty flags */
3636 memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3638 skl_clear_wm(results, intel_crtc->pipe);
3640 skl_compute_wm_global_parameters(dev, &config);
3642 if (!skl_update_pipe_wm(crtc, ¶ms, &config,
3643 &results->ddb, &pipe_wm))
3646 skl_compute_wm_results(dev, ¶ms, &pipe_wm, results, intel_crtc);
3647 results->dirty[intel_crtc->pipe] = true;
3649 skl_update_other_pipe_wm(dev, crtc, &config, results);
3650 skl_write_wm_values(dev_priv, results);
3651 skl_flush_wm_values(dev_priv, results);
3653 /* store the new configuration */
3654 dev_priv->wm.skl_hw = *results;
3658 skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
3659 uint32_t sprite_width, uint32_t sprite_height,
3660 int pixel_size, bool enabled, bool scaled)
3662 struct intel_plane *intel_plane = to_intel_plane(plane);
3663 struct drm_framebuffer *fb = plane->state->fb;
3665 intel_plane->wm.enabled = enabled;
3666 intel_plane->wm.scaled = scaled;
3667 intel_plane->wm.horiz_pixels = sprite_width;
3668 intel_plane->wm.vert_pixels = sprite_height;
3669 intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
3671 /* For planar: Bpp is for UV plane, y_Bpp is for Y plane */
3672 intel_plane->wm.bytes_per_pixel =
3673 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3674 drm_format_plane_cpp(plane->state->fb->pixel_format, 1) : pixel_size;
3675 intel_plane->wm.y_bytes_per_pixel =
3676 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3677 drm_format_plane_cpp(plane->state->fb->pixel_format, 0) : 0;
3680 * Framebuffer can be NULL on plane disable, but it does not
3681 * matter for watermarks if we assume no tiling in that case.
3684 intel_plane->wm.tiling = fb->modifier[0];
3685 intel_plane->wm.rotation = plane->state->rotation;
3687 skl_update_wm(crtc);
3690 static void ilk_update_wm(struct drm_crtc *crtc)
3692 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3693 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3694 struct drm_device *dev = crtc->dev;
3695 struct drm_i915_private *dev_priv = dev->dev_private;
3696 struct ilk_wm_maximums max;
3697 struct ilk_wm_values results = {};
3698 enum intel_ddb_partitioning partitioning;
3699 struct intel_pipe_wm pipe_wm = {};
3700 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
3701 struct intel_wm_config config = {};
3703 WARN_ON(cstate->base.active != intel_crtc->active);
3705 intel_compute_pipe_wm(cstate, &pipe_wm);
3707 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
3710 intel_crtc->wm.active = pipe_wm;
3712 ilk_compute_wm_config(dev, &config);
3714 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3715 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
3717 /* 5/6 split only in single pipe config on IVB+ */
3718 if (INTEL_INFO(dev)->gen >= 7 &&
3719 config.num_pipes_active == 1 && config.sprites_enabled) {
3720 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3721 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
3723 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
3725 best_lp_wm = &lp_wm_1_2;
3728 partitioning = (best_lp_wm == &lp_wm_1_2) ?
3729 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
3731 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
3733 ilk_write_wm_values(dev_priv, &results);
3737 ilk_update_sprite_wm(struct drm_plane *plane,
3738 struct drm_crtc *crtc,
3739 uint32_t sprite_width, uint32_t sprite_height,
3740 int pixel_size, bool enabled, bool scaled)
3742 struct drm_device *dev = plane->dev;
3743 struct intel_plane *intel_plane = to_intel_plane(plane);
3746 * IVB workaround: must disable low power watermarks for at least
3747 * one frame before enabling scaling. LP watermarks can be re-enabled
3748 * when scaling is disabled.
3750 * WaCxSRDisabledForSpriteScaling:ivb
3752 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
3753 intel_wait_for_vblank(dev, intel_plane->pipe);
3755 ilk_update_wm(crtc);
3758 static void skl_pipe_wm_active_state(uint32_t val,
3759 struct skl_pipe_wm *active,
3765 bool is_enabled = (val & PLANE_WM_EN) != 0;
3769 active->wm[level].plane_en[i] = is_enabled;
3770 active->wm[level].plane_res_b[i] =
3771 val & PLANE_WM_BLOCKS_MASK;
3772 active->wm[level].plane_res_l[i] =
3773 (val >> PLANE_WM_LINES_SHIFT) &
3774 PLANE_WM_LINES_MASK;
3776 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
3777 active->wm[level].plane_res_b[PLANE_CURSOR] =
3778 val & PLANE_WM_BLOCKS_MASK;
3779 active->wm[level].plane_res_l[PLANE_CURSOR] =
3780 (val >> PLANE_WM_LINES_SHIFT) &
3781 PLANE_WM_LINES_MASK;
3785 active->trans_wm.plane_en[i] = is_enabled;
3786 active->trans_wm.plane_res_b[i] =
3787 val & PLANE_WM_BLOCKS_MASK;
3788 active->trans_wm.plane_res_l[i] =
3789 (val >> PLANE_WM_LINES_SHIFT) &
3790 PLANE_WM_LINES_MASK;
3792 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
3793 active->trans_wm.plane_res_b[PLANE_CURSOR] =
3794 val & PLANE_WM_BLOCKS_MASK;
3795 active->trans_wm.plane_res_l[PLANE_CURSOR] =
3796 (val >> PLANE_WM_LINES_SHIFT) &
3797 PLANE_WM_LINES_MASK;
3802 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3804 struct drm_device *dev = crtc->dev;
3805 struct drm_i915_private *dev_priv = dev->dev_private;
3806 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3807 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3808 struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;
3809 enum pipe pipe = intel_crtc->pipe;
3810 int level, i, max_level;
3813 max_level = ilk_wm_max_level(dev);
3815 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3817 for (level = 0; level <= max_level; level++) {
3818 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3819 hw->plane[pipe][i][level] =
3820 I915_READ(PLANE_WM(pipe, i, level));
3821 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3824 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3825 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3826 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3828 if (!intel_crtc->active)
3831 hw->dirty[pipe] = true;
3833 active->linetime = hw->wm_linetime[pipe];
3835 for (level = 0; level <= max_level; level++) {
3836 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3837 temp = hw->plane[pipe][i][level];
3838 skl_pipe_wm_active_state(temp, active, false,
3841 temp = hw->plane[pipe][PLANE_CURSOR][level];
3842 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3845 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3846 temp = hw->plane_trans[pipe][i];
3847 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3850 temp = hw->plane_trans[pipe][PLANE_CURSOR];
3851 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3854 void skl_wm_get_hw_state(struct drm_device *dev)
3856 struct drm_i915_private *dev_priv = dev->dev_private;
3857 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3858 struct drm_crtc *crtc;
3860 skl_ddb_get_hw_state(dev_priv, ddb);
3861 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3862 skl_pipe_wm_get_hw_state(crtc);
3865 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3867 struct drm_device *dev = crtc->dev;
3868 struct drm_i915_private *dev_priv = dev->dev_private;
3869 struct ilk_wm_values *hw = &dev_priv->wm.hw;
3870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3871 struct intel_pipe_wm *active = &intel_crtc->wm.active;
3872 enum pipe pipe = intel_crtc->pipe;
3873 static const unsigned int wm0_pipe_reg[] = {
3874 [PIPE_A] = WM0_PIPEA_ILK,
3875 [PIPE_B] = WM0_PIPEB_ILK,
3876 [PIPE_C] = WM0_PIPEC_IVB,
3879 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3880 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3881 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3883 memset(active, 0, sizeof(*active));
3885 active->pipe_enabled = intel_crtc->active;
3887 if (active->pipe_enabled) {
3888 u32 tmp = hw->wm_pipe[pipe];
3891 * For active pipes LP0 watermark is marked as
3892 * enabled, and LP1+ watermaks as disabled since
3893 * we can't really reverse compute them in case
3894 * multiple pipes are active.
3896 active->wm[0].enable = true;
3897 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3898 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3899 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3900 active->linetime = hw->wm_linetime[pipe];
3902 int level, max_level = ilk_wm_max_level(dev);
3905 * For inactive pipes, all watermark levels
3906 * should be marked as enabled but zeroed,
3907 * which is what we'd compute them to.
3909 for (level = 0; level <= max_level; level++)
3910 active->wm[level].enable = true;
3914 #define _FW_WM(value, plane) \
3915 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3916 #define _FW_WM_VLV(value, plane) \
3917 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3919 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3920 struct vlv_wm_values *wm)
3925 for_each_pipe(dev_priv, pipe) {
3926 tmp = I915_READ(VLV_DDL(pipe));
3928 wm->ddl[pipe].primary =
3929 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3930 wm->ddl[pipe].cursor =
3931 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3932 wm->ddl[pipe].sprite[0] =
3933 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3934 wm->ddl[pipe].sprite[1] =
3935 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3938 tmp = I915_READ(DSPFW1);
3939 wm->sr.plane = _FW_WM(tmp, SR);
3940 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3941 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3942 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3944 tmp = I915_READ(DSPFW2);
3945 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
3946 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
3947 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
3949 tmp = I915_READ(DSPFW3);
3950 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
3952 if (IS_CHERRYVIEW(dev_priv)) {
3953 tmp = I915_READ(DSPFW7_CHV);
3954 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3955 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3957 tmp = I915_READ(DSPFW8_CHV);
3958 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
3959 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
3961 tmp = I915_READ(DSPFW9_CHV);
3962 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
3963 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
3965 tmp = I915_READ(DSPHOWM);
3966 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3967 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
3968 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
3969 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
3970 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3971 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3972 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3973 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3974 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3975 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3977 tmp = I915_READ(DSPFW7);
3978 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3979 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3981 tmp = I915_READ(DSPHOWM);
3982 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3983 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3984 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3985 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3986 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3987 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3988 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3995 void vlv_wm_get_hw_state(struct drm_device *dev)
3997 struct drm_i915_private *dev_priv = to_i915(dev);
3998 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
3999 struct intel_plane *plane;
4003 vlv_read_wm_values(dev_priv, wm);
4005 for_each_intel_plane(dev, plane) {
4006 switch (plane->base.type) {
4008 case DRM_PLANE_TYPE_CURSOR:
4009 plane->wm.fifo_size = 63;
4011 case DRM_PLANE_TYPE_PRIMARY:
4012 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4014 case DRM_PLANE_TYPE_OVERLAY:
4015 sprite = plane->plane;
4016 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4021 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4022 wm->level = VLV_WM_LEVEL_PM2;
4024 if (IS_CHERRYVIEW(dev_priv)) {
4025 mutex_lock(&dev_priv->rps.hw_lock);
4027 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4028 if (val & DSP_MAXFIFO_PM5_ENABLE)
4029 wm->level = VLV_WM_LEVEL_PM5;
4032 * If DDR DVFS is disabled in the BIOS, Punit
4033 * will never ack the request. So if that happens
4034 * assume we don't have to enable/disable DDR DVFS
4035 * dynamically. To test that just set the REQ_ACK
4036 * bit to poke the Punit, but don't change the
4037 * HIGH/LOW bits so that we don't actually change
4038 * the current state.
4040 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4041 val |= FORCE_DDR_FREQ_REQ_ACK;
4042 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4044 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4045 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4046 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4047 "assuming DDR DVFS is disabled\n");
4048 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4050 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4051 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4052 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4055 mutex_unlock(&dev_priv->rps.hw_lock);
4058 for_each_pipe(dev_priv, pipe)
4059 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4060 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4061 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4063 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4064 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4067 void ilk_wm_get_hw_state(struct drm_device *dev)
4069 struct drm_i915_private *dev_priv = dev->dev_private;
4070 struct ilk_wm_values *hw = &dev_priv->wm.hw;
4071 struct drm_crtc *crtc;
4073 for_each_crtc(dev, crtc)
4074 ilk_pipe_wm_get_hw_state(crtc);
4076 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4077 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4078 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4080 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4081 if (INTEL_INFO(dev)->gen >= 7) {
4082 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4083 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4086 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4087 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4088 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4089 else if (IS_IVYBRIDGE(dev))
4090 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4091 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4094 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4098 * intel_update_watermarks - update FIFO watermark values based on current modes
4100 * Calculate watermark values for the various WM regs based on current mode
4101 * and plane configuration.
4103 * There are several cases to deal with here:
4104 * - normal (i.e. non-self-refresh)
4105 * - self-refresh (SR) mode
4106 * - lines are large relative to FIFO size (buffer can hold up to 2)
4107 * - lines are small relative to FIFO size (buffer can hold more than 2
4108 * lines), so need to account for TLB latency
4110 * The normal calculation is:
4111 * watermark = dotclock * bytes per pixel * latency
4112 * where latency is platform & configuration dependent (we assume pessimal
4115 * The SR calculation is:
4116 * watermark = (trunc(latency/line time)+1) * surface width *
4119 * line time = htotal / dotclock
4120 * surface width = hdisplay for normal plane and 64 for cursor
4121 * and latency is assumed to be high, as above.
4123 * The final value programmed to the register should always be rounded up,
4124 * and include an extra 2 entries to account for clock crossings.
4126 * We don't use the sprite, so we can ignore that. And on Crestline we have
4127 * to set the non-SR watermarks to 8.
4129 void intel_update_watermarks(struct drm_crtc *crtc)
4131 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4133 if (dev_priv->display.update_wm)
4134 dev_priv->display.update_wm(crtc);
4137 void intel_update_sprite_watermarks(struct drm_plane *plane,
4138 struct drm_crtc *crtc,
4139 uint32_t sprite_width,
4140 uint32_t sprite_height,
4142 bool enabled, bool scaled)
4144 struct drm_i915_private *dev_priv = plane->dev->dev_private;
4146 if (dev_priv->display.update_sprite_wm)
4147 dev_priv->display.update_sprite_wm(plane, crtc,
4148 sprite_width, sprite_height,
4149 pixel_size, enabled, scaled);
4153 * Lock protecting IPS related data structures
4155 DEFINE_SPINLOCK(mchdev_lock);
4157 /* Global for IPS driver to get at the current i915 device. Protected by
4159 static struct drm_i915_private *i915_mch_dev;
4161 bool ironlake_set_drps(struct drm_device *dev, u8 val)
4163 struct drm_i915_private *dev_priv = dev->dev_private;
4166 assert_spin_locked(&mchdev_lock);
4168 rgvswctl = I915_READ16(MEMSWCTL);
4169 if (rgvswctl & MEMCTL_CMD_STS) {
4170 DRM_DEBUG("gpu busy, RCS change rejected\n");
4171 return false; /* still busy with another command */
4174 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4175 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4176 I915_WRITE16(MEMSWCTL, rgvswctl);
4177 POSTING_READ16(MEMSWCTL);
4179 rgvswctl |= MEMCTL_CMD_STS;
4180 I915_WRITE16(MEMSWCTL, rgvswctl);
4185 static void ironlake_enable_drps(struct drm_device *dev)
4187 struct drm_i915_private *dev_priv = dev->dev_private;
4188 u32 rgvmodectl = I915_READ(MEMMODECTL);
4189 u8 fmax, fmin, fstart, vstart;
4191 spin_lock_irq(&mchdev_lock);
4193 /* Enable temp reporting */
4194 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4195 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4197 /* 100ms RC evaluation intervals */
4198 I915_WRITE(RCUPEI, 100000);
4199 I915_WRITE(RCDNEI, 100000);
4201 /* Set max/min thresholds to 90ms and 80ms respectively */
4202 I915_WRITE(RCBMAXAVG, 90000);
4203 I915_WRITE(RCBMINAVG, 80000);
4205 I915_WRITE(MEMIHYST, 1);
4207 /* Set up min, max, and cur for interrupt handling */
4208 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4209 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4210 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4211 MEMMODE_FSTART_SHIFT;
4213 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4216 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4217 dev_priv->ips.fstart = fstart;
4219 dev_priv->ips.max_delay = fstart;
4220 dev_priv->ips.min_delay = fmin;
4221 dev_priv->ips.cur_delay = fstart;
4223 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4224 fmax, fmin, fstart);
4226 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4229 * Interrupts will be enabled in ironlake_irq_postinstall
4232 I915_WRITE(VIDSTART, vstart);
4233 POSTING_READ(VIDSTART);
4235 rgvmodectl |= MEMMODE_SWMODE_EN;
4236 I915_WRITE(MEMMODECTL, rgvmodectl);
4238 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4239 DRM_ERROR("stuck trying to change perf mode\n");
4242 ironlake_set_drps(dev, fstart);
4244 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4245 I915_READ(DDREC) + I915_READ(CSIEC);
4246 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4247 dev_priv->ips.last_count2 = I915_READ(GFXEC);
4248 dev_priv->ips.last_time2 = ktime_get_raw_ns();
4250 spin_unlock_irq(&mchdev_lock);
4253 static void ironlake_disable_drps(struct drm_device *dev)
4255 struct drm_i915_private *dev_priv = dev->dev_private;
4258 spin_lock_irq(&mchdev_lock);
4260 rgvswctl = I915_READ16(MEMSWCTL);
4262 /* Ack interrupts, disable EFC interrupt */
4263 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4264 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4265 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4266 I915_WRITE(DEIIR, DE_PCU_EVENT);
4267 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4269 /* Go back to the starting frequency */
4270 ironlake_set_drps(dev, dev_priv->ips.fstart);
4272 rgvswctl |= MEMCTL_CMD_STS;
4273 I915_WRITE(MEMSWCTL, rgvswctl);
4276 spin_unlock_irq(&mchdev_lock);
4279 /* There's a funny hw issue where the hw returns all 0 when reading from
4280 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4281 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4282 * all limits and the gpu stuck at whatever frequency it is at atm).
4284 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4288 /* Only set the down limit when we've reached the lowest level to avoid
4289 * getting more interrupts, otherwise leave this clear. This prevents a
4290 * race in the hw when coming out of rc6: There's a tiny window where
4291 * the hw runs at the minimal clock before selecting the desired
4292 * frequency, if the down threshold expires in that window we will not
4293 * receive a down interrupt. */
4294 if (IS_GEN9(dev_priv->dev)) {
4295 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4296 if (val <= dev_priv->rps.min_freq_softlimit)
4297 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4299 limits = dev_priv->rps.max_freq_softlimit << 24;
4300 if (val <= dev_priv->rps.min_freq_softlimit)
4301 limits |= dev_priv->rps.min_freq_softlimit << 16;
4307 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4310 u32 threshold_up = 0, threshold_down = 0; /* in % */
4311 u32 ei_up = 0, ei_down = 0;
4313 new_power = dev_priv->rps.power;
4314 switch (dev_priv->rps.power) {
4316 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
4317 new_power = BETWEEN;
4321 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
4322 new_power = LOW_POWER;
4323 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
4324 new_power = HIGH_POWER;
4328 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
4329 new_power = BETWEEN;
4332 /* Max/min bins are special */
4333 if (val <= dev_priv->rps.min_freq_softlimit)
4334 new_power = LOW_POWER;
4335 if (val >= dev_priv->rps.max_freq_softlimit)
4336 new_power = HIGH_POWER;
4337 if (new_power == dev_priv->rps.power)
4340 /* Note the units here are not exactly 1us, but 1280ns. */
4341 switch (new_power) {
4343 /* Upclock if more than 95% busy over 16ms */
4347 /* Downclock if less than 85% busy over 32ms */
4349 threshold_down = 85;
4353 /* Upclock if more than 90% busy over 13ms */
4357 /* Downclock if less than 75% busy over 32ms */
4359 threshold_down = 75;
4363 /* Upclock if more than 85% busy over 10ms */
4367 /* Downclock if less than 60% busy over 32ms */
4369 threshold_down = 60;
4373 I915_WRITE(GEN6_RP_UP_EI,
4374 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4375 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4376 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4378 I915_WRITE(GEN6_RP_DOWN_EI,
4379 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4380 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4381 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4383 I915_WRITE(GEN6_RP_CONTROL,
4384 GEN6_RP_MEDIA_TURBO |
4385 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4386 GEN6_RP_MEDIA_IS_GFX |
4388 GEN6_RP_UP_BUSY_AVG |
4389 GEN6_RP_DOWN_IDLE_AVG);
4391 dev_priv->rps.power = new_power;
4392 dev_priv->rps.up_threshold = threshold_up;
4393 dev_priv->rps.down_threshold = threshold_down;
4394 dev_priv->rps.last_adj = 0;
4397 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4401 if (val > dev_priv->rps.min_freq_softlimit)
4402 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4403 if (val < dev_priv->rps.max_freq_softlimit)
4404 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4406 mask &= dev_priv->pm_rps_events;
4408 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4411 /* gen6_set_rps is called to update the frequency request, but should also be
4412 * called when the range (min_delay and max_delay) is modified so that we can
4413 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4414 static void gen6_set_rps(struct drm_device *dev, u8 val)
4416 struct drm_i915_private *dev_priv = dev->dev_private;
4418 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4419 if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0))
4422 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4423 WARN_ON(val > dev_priv->rps.max_freq);
4424 WARN_ON(val < dev_priv->rps.min_freq);
4426 /* min/max delay may still have been modified so be sure to
4427 * write the limits value.
4429 if (val != dev_priv->rps.cur_freq) {
4430 gen6_set_rps_thresholds(dev_priv, val);
4433 I915_WRITE(GEN6_RPNSWREQ,
4434 GEN9_FREQUENCY(val));
4435 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4436 I915_WRITE(GEN6_RPNSWREQ,
4437 HSW_FREQUENCY(val));
4439 I915_WRITE(GEN6_RPNSWREQ,
4440 GEN6_FREQUENCY(val) |
4442 GEN6_AGGRESSIVE_TURBO);
4445 /* Make sure we continue to get interrupts
4446 * until we hit the minimum or maximum frequencies.
4448 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4449 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4451 POSTING_READ(GEN6_RPNSWREQ);
4453 dev_priv->rps.cur_freq = val;
4454 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4457 static void valleyview_set_rps(struct drm_device *dev, u8 val)
4459 struct drm_i915_private *dev_priv = dev->dev_private;
4461 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4462 WARN_ON(val > dev_priv->rps.max_freq);
4463 WARN_ON(val < dev_priv->rps.min_freq);
4465 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4466 "Odd GPU freq value\n"))
4469 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4471 if (val != dev_priv->rps.cur_freq) {
4472 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4473 if (!IS_CHERRYVIEW(dev_priv))
4474 gen6_set_rps_thresholds(dev_priv, val);
4477 dev_priv->rps.cur_freq = val;
4478 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4481 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4483 * * If Gfx is Idle, then
4484 * 1. Forcewake Media well.
4485 * 2. Request idle freq.
4486 * 3. Release Forcewake of Media well.
4488 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4490 u32 val = dev_priv->rps.idle_freq;
4492 if (dev_priv->rps.cur_freq <= val)
4495 /* Wake up the media well, as that takes a lot less
4496 * power than the Render well. */
4497 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4498 valleyview_set_rps(dev_priv->dev, val);
4499 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
4502 void gen6_rps_busy(struct drm_i915_private *dev_priv)
4504 mutex_lock(&dev_priv->rps.hw_lock);
4505 if (dev_priv->rps.enabled) {
4506 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4507 gen6_rps_reset_ei(dev_priv);
4508 I915_WRITE(GEN6_PMINTRMSK,
4509 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4511 mutex_unlock(&dev_priv->rps.hw_lock);
4514 void gen6_rps_idle(struct drm_i915_private *dev_priv)
4516 struct drm_device *dev = dev_priv->dev;
4518 mutex_lock(&dev_priv->rps.hw_lock);
4519 if (dev_priv->rps.enabled) {
4520 if (IS_VALLEYVIEW(dev))
4521 vlv_set_rps_idle(dev_priv);
4523 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4524 dev_priv->rps.last_adj = 0;
4525 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4527 mutex_unlock(&dev_priv->rps.hw_lock);
4529 spin_lock(&dev_priv->rps.client_lock);
4530 while (!list_empty(&dev_priv->rps.clients))
4531 list_del_init(dev_priv->rps.clients.next);
4532 spin_unlock(&dev_priv->rps.client_lock);
4535 void gen6_rps_boost(struct drm_i915_private *dev_priv,
4536 struct intel_rps_client *rps,
4537 unsigned long submitted)
4539 /* This is intentionally racy! We peek at the state here, then
4540 * validate inside the RPS worker.
4542 if (!(dev_priv->mm.busy &&
4543 dev_priv->rps.enabled &&
4544 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4547 /* Force a RPS boost (and don't count it against the client) if
4548 * the GPU is severely congested.
4550 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
4553 spin_lock(&dev_priv->rps.client_lock);
4554 if (rps == NULL || list_empty(&rps->link)) {
4555 spin_lock_irq(&dev_priv->irq_lock);
4556 if (dev_priv->rps.interrupts_enabled) {
4557 dev_priv->rps.client_boost = true;
4558 queue_work(dev_priv->wq, &dev_priv->rps.work);
4560 spin_unlock_irq(&dev_priv->irq_lock);
4563 list_add(&rps->link, &dev_priv->rps.clients);
4566 dev_priv->rps.boosts++;
4568 spin_unlock(&dev_priv->rps.client_lock);
4571 void intel_set_rps(struct drm_device *dev, u8 val)
4573 if (IS_VALLEYVIEW(dev))
4574 valleyview_set_rps(dev, val);
4576 gen6_set_rps(dev, val);
4579 static void gen9_disable_rps(struct drm_device *dev)
4581 struct drm_i915_private *dev_priv = dev->dev_private;
4583 I915_WRITE(GEN6_RC_CONTROL, 0);
4584 I915_WRITE(GEN9_PG_ENABLE, 0);
4587 static void gen6_disable_rps(struct drm_device *dev)
4589 struct drm_i915_private *dev_priv = dev->dev_private;
4591 I915_WRITE(GEN6_RC_CONTROL, 0);
4592 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
4595 static void cherryview_disable_rps(struct drm_device *dev)
4597 struct drm_i915_private *dev_priv = dev->dev_private;
4599 I915_WRITE(GEN6_RC_CONTROL, 0);
4602 static void valleyview_disable_rps(struct drm_device *dev)
4604 struct drm_i915_private *dev_priv = dev->dev_private;
4606 /* we're doing forcewake before Disabling RC6,
4607 * This what the BIOS expects when going into suspend */
4608 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4610 I915_WRITE(GEN6_RC_CONTROL, 0);
4612 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4615 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4617 if (IS_VALLEYVIEW(dev)) {
4618 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4619 mode = GEN6_RC_CTL_RC6_ENABLE;
4624 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4625 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4626 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4627 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4630 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4631 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
4634 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
4636 /* No RC6 before Ironlake and code is gone for ilk. */
4637 if (INTEL_INFO(dev)->gen < 6)
4640 /* Respect the kernel parameter if it is set */
4641 if (enable_rc6 >= 0) {
4645 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4648 mask = INTEL_RC6_ENABLE;
4650 if ((enable_rc6 & mask) != enable_rc6)
4651 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4652 enable_rc6 & mask, enable_rc6, mask);
4654 return enable_rc6 & mask;
4657 if (IS_IVYBRIDGE(dev))
4658 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
4660 return INTEL_RC6_ENABLE;
4663 int intel_enable_rc6(const struct drm_device *dev)
4665 return i915.enable_rc6;
4668 static void gen6_init_rps_frequencies(struct drm_device *dev)
4670 struct drm_i915_private *dev_priv = dev->dev_private;
4671 uint32_t rp_state_cap;
4672 u32 ddcc_status = 0;
4675 /* All of these values are in units of 50MHz */
4676 dev_priv->rps.cur_freq = 0;
4677 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
4678 if (IS_BROXTON(dev)) {
4679 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4680 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4681 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4682 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
4684 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4685 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
4686 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4687 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4690 /* hw_max = RP0 until we check for overclocking */
4691 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4693 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4694 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) {
4695 ret = sandybridge_pcode_read(dev_priv,
4696 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4699 dev_priv->rps.efficient_freq =
4701 ((ddcc_status >> 8) & 0xff),
4702 dev_priv->rps.min_freq,
4703 dev_priv->rps.max_freq);
4706 if (IS_SKYLAKE(dev)) {
4707 /* Store the frequency values in 16.66 MHZ units, which is
4708 the natural hardware unit for SKL */
4709 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4710 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4711 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4712 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4713 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4716 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4718 /* Preserve min/max settings in case of re-init */
4719 if (dev_priv->rps.max_freq_softlimit == 0)
4720 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4722 if (dev_priv->rps.min_freq_softlimit == 0) {
4723 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4724 dev_priv->rps.min_freq_softlimit =
4725 max_t(int, dev_priv->rps.efficient_freq,
4726 intel_freq_opcode(dev_priv, 450));
4728 dev_priv->rps.min_freq_softlimit =
4729 dev_priv->rps.min_freq;
4733 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
4734 static void gen9_enable_rps(struct drm_device *dev)
4736 struct drm_i915_private *dev_priv = dev->dev_private;
4738 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4740 gen6_init_rps_frequencies(dev);
4742 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4743 if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) {
4744 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4748 /* Program defaults and thresholds for RPS*/
4749 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4750 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4752 /* 1 second timeout*/
4753 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4754 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4756 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
4758 /* Leaning on the below call to gen6_set_rps to program/setup the
4759 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4760 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4761 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4762 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
4764 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4767 static void gen9_enable_rc6(struct drm_device *dev)
4769 struct drm_i915_private *dev_priv = dev->dev_private;
4770 struct intel_engine_cs *ring;
4771 uint32_t rc6_mask = 0;
4774 /* 1a: Software RC state - RC0 */
4775 I915_WRITE(GEN6_RC_STATE, 0);
4777 /* 1b: Get forcewake during program sequence. Although the driver
4778 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4779 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4781 /* 2a: Disable RC states. */
4782 I915_WRITE(GEN6_RC_CONTROL, 0);
4784 /* 2b: Program RC6 thresholds.*/
4786 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
4787 if (IS_SKYLAKE(dev))
4788 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4790 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4791 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4792 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4793 for_each_ring(ring, dev_priv, unused)
4794 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4796 if (HAS_GUC_UCODE(dev))
4797 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
4799 I915_WRITE(GEN6_RC_SLEEP, 0);
4801 /* 2c: Program Coarse Power Gating Policies. */
4802 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4803 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4805 /* 3a: Enable RC6 */
4806 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4807 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4808 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4810 /* WaRsUseTimeoutMode */
4811 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) ||
4812 (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0)) {
4813 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
4814 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4815 GEN7_RC_CTL_TO_MODE |
4818 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4819 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4820 GEN6_RC_CTL_EI_MODE(1) |
4825 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4826 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
4828 if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
4829 ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_F0)))
4830 I915_WRITE(GEN9_PG_ENABLE, 0);
4832 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4833 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
4835 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4839 static void gen8_enable_rps(struct drm_device *dev)
4841 struct drm_i915_private *dev_priv = dev->dev_private;
4842 struct intel_engine_cs *ring;
4843 uint32_t rc6_mask = 0;
4846 /* 1a: Software RC state - RC0 */
4847 I915_WRITE(GEN6_RC_STATE, 0);
4849 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4850 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4851 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4853 /* 2a: Disable RC states. */
4854 I915_WRITE(GEN6_RC_CONTROL, 0);
4856 /* Initialize rps frequencies */
4857 gen6_init_rps_frequencies(dev);
4859 /* 2b: Program RC6 thresholds.*/
4860 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4861 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4862 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4863 for_each_ring(ring, dev_priv, unused)
4864 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4865 I915_WRITE(GEN6_RC_SLEEP, 0);
4866 if (IS_BROADWELL(dev))
4867 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4869 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4872 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4873 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4874 intel_print_rc6_info(dev, rc6_mask);
4875 if (IS_BROADWELL(dev))
4876 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4877 GEN7_RC_CTL_TO_MODE |
4880 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4881 GEN6_RC_CTL_EI_MODE(1) |
4884 /* 4 Program defaults and thresholds for RPS*/
4885 I915_WRITE(GEN6_RPNSWREQ,
4886 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4887 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4888 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4889 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4890 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4892 /* Docs recommend 900MHz, and 300 MHz respectively */
4893 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4894 dev_priv->rps.max_freq_softlimit << 24 |
4895 dev_priv->rps.min_freq_softlimit << 16);
4897 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4898 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4899 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4900 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4902 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4905 I915_WRITE(GEN6_RP_CONTROL,
4906 GEN6_RP_MEDIA_TURBO |
4907 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4908 GEN6_RP_MEDIA_IS_GFX |
4910 GEN6_RP_UP_BUSY_AVG |
4911 GEN6_RP_DOWN_IDLE_AVG);
4913 /* 6: Ring frequency + overclocking (our driver does this later */
4915 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4916 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4918 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4921 static void gen6_enable_rps(struct drm_device *dev)
4923 struct drm_i915_private *dev_priv = dev->dev_private;
4924 struct intel_engine_cs *ring;
4925 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
4930 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4932 /* Here begins a magic sequence of register writes to enable
4933 * auto-downclocking.
4935 * Perhaps there might be some value in exposing these to
4938 I915_WRITE(GEN6_RC_STATE, 0);
4940 /* Clear the DBG now so we don't confuse earlier errors */
4941 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4942 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4943 I915_WRITE(GTFIFODBG, gtfifodbg);
4946 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4948 /* Initialize rps frequencies */
4949 gen6_init_rps_frequencies(dev);
4951 /* disable the counters and set deterministic thresholds */
4952 I915_WRITE(GEN6_RC_CONTROL, 0);
4954 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4955 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4956 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4957 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4958 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4960 for_each_ring(ring, dev_priv, i)
4961 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4963 I915_WRITE(GEN6_RC_SLEEP, 0);
4964 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
4965 if (IS_IVYBRIDGE(dev))
4966 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4968 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
4969 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
4970 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4972 /* Check if we are enabling RC6 */
4973 rc6_mode = intel_enable_rc6(dev_priv->dev);
4974 if (rc6_mode & INTEL_RC6_ENABLE)
4975 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4977 /* We don't use those on Haswell */
4978 if (!IS_HASWELL(dev)) {
4979 if (rc6_mode & INTEL_RC6p_ENABLE)
4980 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
4982 if (rc6_mode & INTEL_RC6pp_ENABLE)
4983 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4986 intel_print_rc6_info(dev, rc6_mask);
4988 I915_WRITE(GEN6_RC_CONTROL,
4990 GEN6_RC_CTL_EI_MODE(1) |
4991 GEN6_RC_CTL_HW_ENABLE);
4993 /* Power down if completely idle for over 50ms */
4994 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
4995 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4997 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
4999 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
5001 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
5002 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
5003 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
5004 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
5005 (pcu_mbox & 0xff) * 50);
5006 dev_priv->rps.max_freq = pcu_mbox & 0xff;
5009 dev_priv->rps.power = HIGH_POWER; /* force a reset */
5010 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
5013 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5014 if (IS_GEN6(dev) && ret) {
5015 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5016 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5017 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5018 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5019 rc6vids &= 0xffff00;
5020 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5021 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5023 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5026 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5029 static void __gen6_update_ring_freq(struct drm_device *dev)
5031 struct drm_i915_private *dev_priv = dev->dev_private;
5033 unsigned int gpu_freq;
5034 unsigned int max_ia_freq, min_ring_freq;
5035 unsigned int max_gpu_freq, min_gpu_freq;
5036 int scaling_factor = 180;
5037 struct cpufreq_policy *policy;
5039 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5041 policy = cpufreq_cpu_get(0);
5043 max_ia_freq = policy->cpuinfo.max_freq;
5044 cpufreq_cpu_put(policy);
5047 * Default to measured freq if none found, PCU will ensure we
5050 max_ia_freq = tsc_khz;
5053 /* Convert from kHz to MHz */
5054 max_ia_freq /= 1000;
5056 min_ring_freq = I915_READ(DCLK) & 0xf;
5057 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5058 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5060 if (IS_SKYLAKE(dev)) {
5061 /* Convert GT frequency to 50 HZ units */
5062 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5063 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5065 min_gpu_freq = dev_priv->rps.min_freq;
5066 max_gpu_freq = dev_priv->rps.max_freq;
5070 * For each potential GPU frequency, load a ring frequency we'd like
5071 * to use for memory access. We do this by specifying the IA frequency
5072 * the PCU should use as a reference to determine the ring frequency.
5074 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5075 int diff = max_gpu_freq - gpu_freq;
5076 unsigned int ia_freq = 0, ring_freq = 0;
5078 if (IS_SKYLAKE(dev)) {
5080 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5081 * No floor required for ring frequency on SKL.
5083 ring_freq = gpu_freq;
5084 } else if (INTEL_INFO(dev)->gen >= 8) {
5085 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5086 ring_freq = max(min_ring_freq, gpu_freq);
5087 } else if (IS_HASWELL(dev)) {
5088 ring_freq = mult_frac(gpu_freq, 5, 4);
5089 ring_freq = max(min_ring_freq, ring_freq);
5090 /* leave ia_freq as the default, chosen by cpufreq */
5092 /* On older processors, there is no separate ring
5093 * clock domain, so in order to boost the bandwidth
5094 * of the ring, we need to upclock the CPU (ia_freq).
5096 * For GPU frequencies less than 750MHz,
5097 * just use the lowest ring freq.
5099 if (gpu_freq < min_freq)
5102 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5103 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5106 sandybridge_pcode_write(dev_priv,
5107 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5108 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5109 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5114 void gen6_update_ring_freq(struct drm_device *dev)
5116 struct drm_i915_private *dev_priv = dev->dev_private;
5118 if (!HAS_CORE_RING_FREQ(dev))
5121 mutex_lock(&dev_priv->rps.hw_lock);
5122 __gen6_update_ring_freq(dev);
5123 mutex_unlock(&dev_priv->rps.hw_lock);
5126 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5128 struct drm_device *dev = dev_priv->dev;
5131 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5133 switch (INTEL_INFO(dev)->eu_total) {
5135 /* (2 * 4) config */
5136 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5139 /* (2 * 6) config */
5140 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5143 /* (2 * 8) config */
5145 /* Setting (2 * 8) Min RP0 for any other combination */
5146 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5150 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5155 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5159 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5160 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5165 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5169 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5170 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5175 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5179 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5181 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5186 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5190 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5192 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5194 rp0 = min_t(u32, rp0, 0xea);
5199 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5203 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5204 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5205 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5206 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5211 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5213 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5216 /* Check that the pctx buffer wasn't move under us. */
5217 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5219 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5221 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5222 dev_priv->vlv_pctx->stolen->start);
5226 /* Check that the pcbr address is not empty. */
5227 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5229 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5231 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5234 static void cherryview_setup_pctx(struct drm_device *dev)
5236 struct drm_i915_private *dev_priv = dev->dev_private;
5237 unsigned long pctx_paddr, paddr;
5238 struct i915_gtt *gtt = &dev_priv->gtt;
5240 int pctx_size = 32*1024;
5242 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5244 pcbr = I915_READ(VLV_PCBR);
5245 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5246 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5247 paddr = (dev_priv->mm.stolen_base +
5248 (gtt->stolen_size - pctx_size));
5250 pctx_paddr = (paddr & (~4095));
5251 I915_WRITE(VLV_PCBR, pctx_paddr);
5254 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5257 static void valleyview_setup_pctx(struct drm_device *dev)
5259 struct drm_i915_private *dev_priv = dev->dev_private;
5260 struct drm_i915_gem_object *pctx;
5261 unsigned long pctx_paddr;
5263 int pctx_size = 24*1024;
5265 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5267 pcbr = I915_READ(VLV_PCBR);
5269 /* BIOS set it up already, grab the pre-alloc'd space */
5272 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5273 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5275 I915_GTT_OFFSET_NONE,
5280 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5283 * From the Gunit register HAS:
5284 * The Gfx driver is expected to program this register and ensure
5285 * proper allocation within Gfx stolen memory. For example, this
5286 * register should be programmed such than the PCBR range does not
5287 * overlap with other ranges, such as the frame buffer, protected
5288 * memory, or any other relevant ranges.
5290 pctx = i915_gem_object_create_stolen(dev, pctx_size);
5292 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5296 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5297 I915_WRITE(VLV_PCBR, pctx_paddr);
5300 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5301 dev_priv->vlv_pctx = pctx;
5304 static void valleyview_cleanup_pctx(struct drm_device *dev)
5306 struct drm_i915_private *dev_priv = dev->dev_private;
5308 if (WARN_ON(!dev_priv->vlv_pctx))
5311 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
5312 dev_priv->vlv_pctx = NULL;
5315 static void valleyview_init_gt_powersave(struct drm_device *dev)
5317 struct drm_i915_private *dev_priv = dev->dev_private;
5320 valleyview_setup_pctx(dev);
5322 mutex_lock(&dev_priv->rps.hw_lock);
5324 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5325 switch ((val >> 6) & 3) {
5328 dev_priv->mem_freq = 800;
5331 dev_priv->mem_freq = 1066;
5334 dev_priv->mem_freq = 1333;
5337 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5339 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5340 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5341 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5342 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5343 dev_priv->rps.max_freq);
5345 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5346 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5347 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5348 dev_priv->rps.efficient_freq);
5350 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5351 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5352 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5353 dev_priv->rps.rp1_freq);
5355 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5356 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5357 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5358 dev_priv->rps.min_freq);
5360 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5362 /* Preserve min/max settings in case of re-init */
5363 if (dev_priv->rps.max_freq_softlimit == 0)
5364 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5366 if (dev_priv->rps.min_freq_softlimit == 0)
5367 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5369 mutex_unlock(&dev_priv->rps.hw_lock);
5372 static void cherryview_init_gt_powersave(struct drm_device *dev)
5374 struct drm_i915_private *dev_priv = dev->dev_private;
5377 cherryview_setup_pctx(dev);
5379 mutex_lock(&dev_priv->rps.hw_lock);
5381 mutex_lock(&dev_priv->sb_lock);
5382 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5383 mutex_unlock(&dev_priv->sb_lock);
5385 switch ((val >> 2) & 0x7) {
5387 dev_priv->mem_freq = 2000;
5390 dev_priv->mem_freq = 1600;
5393 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5395 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5396 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5397 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5398 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5399 dev_priv->rps.max_freq);
5401 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5402 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5403 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5404 dev_priv->rps.efficient_freq);
5406 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5407 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5408 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5409 dev_priv->rps.rp1_freq);
5411 /* PUnit validated range is only [RPe, RP0] */
5412 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5413 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5414 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5415 dev_priv->rps.min_freq);
5417 WARN_ONCE((dev_priv->rps.max_freq |
5418 dev_priv->rps.efficient_freq |
5419 dev_priv->rps.rp1_freq |
5420 dev_priv->rps.min_freq) & 1,
5421 "Odd GPU freq values\n");
5423 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5425 /* Preserve min/max settings in case of re-init */
5426 if (dev_priv->rps.max_freq_softlimit == 0)
5427 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5429 if (dev_priv->rps.min_freq_softlimit == 0)
5430 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5432 mutex_unlock(&dev_priv->rps.hw_lock);
5435 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5437 valleyview_cleanup_pctx(dev);
5440 static void cherryview_enable_rps(struct drm_device *dev)
5442 struct drm_i915_private *dev_priv = dev->dev_private;
5443 struct intel_engine_cs *ring;
5444 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5447 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5449 gtfifodbg = I915_READ(GTFIFODBG);
5451 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5453 I915_WRITE(GTFIFODBG, gtfifodbg);
5456 cherryview_check_pctx(dev_priv);
5458 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5459 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5460 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5462 /* Disable RC states. */
5463 I915_WRITE(GEN6_RC_CONTROL, 0);
5465 /* 2a: Program RC6 thresholds.*/
5466 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5467 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5468 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5470 for_each_ring(ring, dev_priv, i)
5471 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5472 I915_WRITE(GEN6_RC_SLEEP, 0);
5474 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5475 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
5477 /* allows RC6 residency counter to work */
5478 I915_WRITE(VLV_COUNTER_CONTROL,
5479 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5480 VLV_MEDIA_RC6_COUNT_EN |
5481 VLV_RENDER_RC6_COUNT_EN));
5483 /* For now we assume BIOS is allocating and populating the PCBR */
5484 pcbr = I915_READ(VLV_PCBR);
5487 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5488 (pcbr >> VLV_PCBR_ADDR_SHIFT))
5489 rc6_mode = GEN7_RC_CTL_TO_MODE;
5491 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5493 /* 4 Program defaults and thresholds for RPS*/
5494 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5495 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5496 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5497 I915_WRITE(GEN6_RP_UP_EI, 66000);
5498 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5500 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5503 I915_WRITE(GEN6_RP_CONTROL,
5504 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5505 GEN6_RP_MEDIA_IS_GFX |
5507 GEN6_RP_UP_BUSY_AVG |
5508 GEN6_RP_DOWN_IDLE_AVG);
5510 /* Setting Fixed Bias */
5511 val = VLV_OVERRIDE_EN |
5513 CHV_BIAS_CPU_50_SOC_50;
5514 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5516 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5518 /* RPS code assumes GPLL is used */
5519 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5521 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5522 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5524 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5525 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5526 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5527 dev_priv->rps.cur_freq);
5529 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5530 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5531 dev_priv->rps.efficient_freq);
5533 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5535 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5538 static void valleyview_enable_rps(struct drm_device *dev)
5540 struct drm_i915_private *dev_priv = dev->dev_private;
5541 struct intel_engine_cs *ring;
5542 u32 gtfifodbg, val, rc6_mode = 0;
5545 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5547 valleyview_check_pctx(dev_priv);
5549 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
5550 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5552 I915_WRITE(GTFIFODBG, gtfifodbg);
5555 /* If VLV, Forcewake all wells, else re-direct to regular path */
5556 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5558 /* Disable RC states. */
5559 I915_WRITE(GEN6_RC_CONTROL, 0);
5561 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5562 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5563 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5564 I915_WRITE(GEN6_RP_UP_EI, 66000);
5565 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5567 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5569 I915_WRITE(GEN6_RP_CONTROL,
5570 GEN6_RP_MEDIA_TURBO |
5571 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5572 GEN6_RP_MEDIA_IS_GFX |
5574 GEN6_RP_UP_BUSY_AVG |
5575 GEN6_RP_DOWN_IDLE_CONT);
5577 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5578 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5579 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5581 for_each_ring(ring, dev_priv, i)
5582 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5584 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
5586 /* allows RC6 residency counter to work */
5587 I915_WRITE(VLV_COUNTER_CONTROL,
5588 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5589 VLV_RENDER_RC0_COUNT_EN |
5590 VLV_MEDIA_RC6_COUNT_EN |
5591 VLV_RENDER_RC6_COUNT_EN));
5593 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
5594 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
5596 intel_print_rc6_info(dev, rc6_mode);
5598 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5600 /* Setting Fixed Bias */
5601 val = VLV_OVERRIDE_EN |
5603 VLV_BIAS_CPU_125_SOC_875;
5604 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5606 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5608 /* RPS code assumes GPLL is used */
5609 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5611 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5612 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5614 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5615 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5616 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5617 dev_priv->rps.cur_freq);
5619 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5620 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5621 dev_priv->rps.efficient_freq);
5623 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5625 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5628 static unsigned long intel_pxfreq(u32 vidfreq)
5631 int div = (vidfreq & 0x3f0000) >> 16;
5632 int post = (vidfreq & 0x3000) >> 12;
5633 int pre = (vidfreq & 0x7);
5638 freq = ((div * 133333) / ((1<<post) * pre));
5643 static const struct cparams {
5649 { 1, 1333, 301, 28664 },
5650 { 1, 1066, 294, 24460 },
5651 { 1, 800, 294, 25192 },
5652 { 0, 1333, 276, 27605 },
5653 { 0, 1066, 276, 27605 },
5654 { 0, 800, 231, 23784 },
5657 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
5659 u64 total_count, diff, ret;
5660 u32 count1, count2, count3, m = 0, c = 0;
5661 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5664 assert_spin_locked(&mchdev_lock);
5666 diff1 = now - dev_priv->ips.last_time1;
5668 /* Prevent division-by-zero if we are asking too fast.
5669 * Also, we don't get interesting results if we are polling
5670 * faster than once in 10ms, so just return the saved value
5674 return dev_priv->ips.chipset_power;
5676 count1 = I915_READ(DMIEC);
5677 count2 = I915_READ(DDREC);
5678 count3 = I915_READ(CSIEC);
5680 total_count = count1 + count2 + count3;
5682 /* FIXME: handle per-counter overflow */
5683 if (total_count < dev_priv->ips.last_count1) {
5684 diff = ~0UL - dev_priv->ips.last_count1;
5685 diff += total_count;
5687 diff = total_count - dev_priv->ips.last_count1;
5690 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
5691 if (cparams[i].i == dev_priv->ips.c_m &&
5692 cparams[i].t == dev_priv->ips.r_t) {
5699 diff = div_u64(diff, diff1);
5700 ret = ((m * diff) + c);
5701 ret = div_u64(ret, 10);
5703 dev_priv->ips.last_count1 = total_count;
5704 dev_priv->ips.last_time1 = now;
5706 dev_priv->ips.chipset_power = ret;
5711 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5713 struct drm_device *dev = dev_priv->dev;
5716 if (INTEL_INFO(dev)->gen != 5)
5719 spin_lock_irq(&mchdev_lock);
5721 val = __i915_chipset_val(dev_priv);
5723 spin_unlock_irq(&mchdev_lock);
5728 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5730 unsigned long m, x, b;
5733 tsfs = I915_READ(TSFS);
5735 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5736 x = I915_READ8(TR1);
5738 b = tsfs & TSFS_INTR_MASK;
5740 return ((m * x) / 127) - b;
5743 static int _pxvid_to_vd(u8 pxvid)
5748 if (pxvid >= 8 && pxvid < 31)
5751 return (pxvid + 2) * 125;
5754 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
5756 struct drm_device *dev = dev_priv->dev;
5757 const int vd = _pxvid_to_vd(pxvid);
5758 const int vm = vd - 1125;
5760 if (INTEL_INFO(dev)->is_mobile)
5761 return vm > 0 ? vm : 0;
5766 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
5768 u64 now, diff, diffms;
5771 assert_spin_locked(&mchdev_lock);
5773 now = ktime_get_raw_ns();
5774 diffms = now - dev_priv->ips.last_time2;
5775 do_div(diffms, NSEC_PER_MSEC);
5777 /* Don't divide by 0 */
5781 count = I915_READ(GFXEC);
5783 if (count < dev_priv->ips.last_count2) {
5784 diff = ~0UL - dev_priv->ips.last_count2;
5787 diff = count - dev_priv->ips.last_count2;
5790 dev_priv->ips.last_count2 = count;
5791 dev_priv->ips.last_time2 = now;
5793 /* More magic constants... */
5795 diff = div_u64(diff, diffms * 10);
5796 dev_priv->ips.gfx_power = diff;
5799 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5801 struct drm_device *dev = dev_priv->dev;
5803 if (INTEL_INFO(dev)->gen != 5)
5806 spin_lock_irq(&mchdev_lock);
5808 __i915_update_gfx_val(dev_priv);
5810 spin_unlock_irq(&mchdev_lock);
5813 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
5815 unsigned long t, corr, state1, corr2, state2;
5818 assert_spin_locked(&mchdev_lock);
5820 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
5821 pxvid = (pxvid >> 24) & 0x7f;
5822 ext_v = pvid_to_extvid(dev_priv, pxvid);
5826 t = i915_mch_val(dev_priv);
5828 /* Revel in the empirically derived constants */
5830 /* Correction factor in 1/100000 units */
5832 corr = ((t * 2349) + 135940);
5834 corr = ((t * 964) + 29317);
5836 corr = ((t * 301) + 1004);
5838 corr = corr * ((150142 * state1) / 10000 - 78642);
5840 corr2 = (corr * dev_priv->ips.corr);
5842 state2 = (corr2 * state1) / 10000;
5843 state2 /= 100; /* convert to mW */
5845 __i915_update_gfx_val(dev_priv);
5847 return dev_priv->ips.gfx_power + state2;
5850 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5852 struct drm_device *dev = dev_priv->dev;
5855 if (INTEL_INFO(dev)->gen != 5)
5858 spin_lock_irq(&mchdev_lock);
5860 val = __i915_gfx_val(dev_priv);
5862 spin_unlock_irq(&mchdev_lock);
5868 * i915_read_mch_val - return value for IPS use
5870 * Calculate and return a value for the IPS driver to use when deciding whether
5871 * we have thermal and power headroom to increase CPU or GPU power budget.
5873 unsigned long i915_read_mch_val(void)
5875 struct drm_i915_private *dev_priv;
5876 unsigned long chipset_val, graphics_val, ret = 0;
5878 spin_lock_irq(&mchdev_lock);
5881 dev_priv = i915_mch_dev;
5883 chipset_val = __i915_chipset_val(dev_priv);
5884 graphics_val = __i915_gfx_val(dev_priv);
5886 ret = chipset_val + graphics_val;
5889 spin_unlock_irq(&mchdev_lock);
5893 EXPORT_SYMBOL_GPL(i915_read_mch_val);
5896 * i915_gpu_raise - raise GPU frequency limit
5898 * Raise the limit; IPS indicates we have thermal headroom.
5900 bool i915_gpu_raise(void)
5902 struct drm_i915_private *dev_priv;
5905 spin_lock_irq(&mchdev_lock);
5906 if (!i915_mch_dev) {
5910 dev_priv = i915_mch_dev;
5912 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5913 dev_priv->ips.max_delay--;
5916 spin_unlock_irq(&mchdev_lock);
5920 EXPORT_SYMBOL_GPL(i915_gpu_raise);
5923 * i915_gpu_lower - lower GPU frequency limit
5925 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5926 * frequency maximum.
5928 bool i915_gpu_lower(void)
5930 struct drm_i915_private *dev_priv;
5933 spin_lock_irq(&mchdev_lock);
5934 if (!i915_mch_dev) {
5938 dev_priv = i915_mch_dev;
5940 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5941 dev_priv->ips.max_delay++;
5944 spin_unlock_irq(&mchdev_lock);
5948 EXPORT_SYMBOL_GPL(i915_gpu_lower);
5951 * i915_gpu_busy - indicate GPU business to IPS
5953 * Tell the IPS driver whether or not the GPU is busy.
5955 bool i915_gpu_busy(void)
5957 struct drm_i915_private *dev_priv;
5958 struct intel_engine_cs *ring;
5962 spin_lock_irq(&mchdev_lock);
5965 dev_priv = i915_mch_dev;
5967 for_each_ring(ring, dev_priv, i)
5968 ret |= !list_empty(&ring->request_list);
5971 spin_unlock_irq(&mchdev_lock);
5975 EXPORT_SYMBOL_GPL(i915_gpu_busy);
5978 * i915_gpu_turbo_disable - disable graphics turbo
5980 * Disable graphics turbo by resetting the max frequency and setting the
5981 * current frequency to the default.
5983 bool i915_gpu_turbo_disable(void)
5985 struct drm_i915_private *dev_priv;
5988 spin_lock_irq(&mchdev_lock);
5989 if (!i915_mch_dev) {
5993 dev_priv = i915_mch_dev;
5995 dev_priv->ips.max_delay = dev_priv->ips.fstart;
5997 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
6001 spin_unlock_irq(&mchdev_lock);
6005 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6008 * Tells the intel_ips driver that the i915 driver is now loaded, if
6009 * IPS got loaded first.
6011 * This awkward dance is so that neither module has to depend on the
6012 * other in order for IPS to do the appropriate communication of
6013 * GPU turbo limits to i915.
6016 ips_ping_for_i915_load(void)
6020 link = symbol_get(ips_link_to_i915_driver);
6023 symbol_put(ips_link_to_i915_driver);
6027 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6029 /* We only register the i915 ips part with intel-ips once everything is
6030 * set up, to avoid intel-ips sneaking in and reading bogus values. */
6031 spin_lock_irq(&mchdev_lock);
6032 i915_mch_dev = dev_priv;
6033 spin_unlock_irq(&mchdev_lock);
6035 ips_ping_for_i915_load();
6038 void intel_gpu_ips_teardown(void)
6040 spin_lock_irq(&mchdev_lock);
6041 i915_mch_dev = NULL;
6042 spin_unlock_irq(&mchdev_lock);
6045 static void intel_init_emon(struct drm_device *dev)
6047 struct drm_i915_private *dev_priv = dev->dev_private;
6052 /* Disable to program */
6056 /* Program energy weights for various events */
6057 I915_WRITE(SDEW, 0x15040d00);
6058 I915_WRITE(CSIEW0, 0x007f0000);
6059 I915_WRITE(CSIEW1, 0x1e220004);
6060 I915_WRITE(CSIEW2, 0x04000004);
6062 for (i = 0; i < 5; i++)
6063 I915_WRITE(PEW(i), 0);
6064 for (i = 0; i < 3; i++)
6065 I915_WRITE(DEW(i), 0);
6067 /* Program P-state weights to account for frequency power adjustment */
6068 for (i = 0; i < 16; i++) {
6069 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6070 unsigned long freq = intel_pxfreq(pxvidfreq);
6071 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6076 val *= (freq / 1000);
6078 val /= (127*127*900);
6080 DRM_ERROR("bad pxval: %ld\n", val);
6083 /* Render standby states get 0 weight */
6087 for (i = 0; i < 4; i++) {
6088 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6089 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6090 I915_WRITE(PXW(i), val);
6093 /* Adjust magic regs to magic values (more experimental results) */
6094 I915_WRITE(OGW0, 0);
6095 I915_WRITE(OGW1, 0);
6096 I915_WRITE(EG0, 0x00007f00);
6097 I915_WRITE(EG1, 0x0000000e);
6098 I915_WRITE(EG2, 0x000e0000);
6099 I915_WRITE(EG3, 0x68000300);
6100 I915_WRITE(EG4, 0x42000000);
6101 I915_WRITE(EG5, 0x00140031);
6105 for (i = 0; i < 8; i++)
6106 I915_WRITE(PXWL(i), 0);
6108 /* Enable PMON + select events */
6109 I915_WRITE(ECR, 0x80000019);
6111 lcfuse = I915_READ(LCFUSE02);
6113 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6116 void intel_init_gt_powersave(struct drm_device *dev)
6118 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
6120 if (IS_CHERRYVIEW(dev))
6121 cherryview_init_gt_powersave(dev);
6122 else if (IS_VALLEYVIEW(dev))
6123 valleyview_init_gt_powersave(dev);
6126 void intel_cleanup_gt_powersave(struct drm_device *dev)
6128 if (IS_CHERRYVIEW(dev))
6130 else if (IS_VALLEYVIEW(dev))
6131 valleyview_cleanup_gt_powersave(dev);
6134 static void gen6_suspend_rps(struct drm_device *dev)
6136 struct drm_i915_private *dev_priv = dev->dev_private;
6138 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6140 gen6_disable_rps_interrupts(dev);
6144 * intel_suspend_gt_powersave - suspend PM work and helper threads
6147 * We don't want to disable RC6 or other features here, we just want
6148 * to make sure any work we've queued has finished and won't bother
6149 * us while we're suspended.
6151 void intel_suspend_gt_powersave(struct drm_device *dev)
6153 struct drm_i915_private *dev_priv = dev->dev_private;
6155 if (INTEL_INFO(dev)->gen < 6)
6158 gen6_suspend_rps(dev);
6160 /* Force GPU to min freq during suspend */
6161 gen6_rps_idle(dev_priv);
6164 void intel_disable_gt_powersave(struct drm_device *dev)
6166 struct drm_i915_private *dev_priv = dev->dev_private;
6168 if (IS_IRONLAKE_M(dev)) {
6169 ironlake_disable_drps(dev);
6170 } else if (INTEL_INFO(dev)->gen >= 6) {
6171 intel_suspend_gt_powersave(dev);
6173 mutex_lock(&dev_priv->rps.hw_lock);
6174 if (INTEL_INFO(dev)->gen >= 9)
6175 gen9_disable_rps(dev);
6176 else if (IS_CHERRYVIEW(dev))
6177 cherryview_disable_rps(dev);
6178 else if (IS_VALLEYVIEW(dev))
6179 valleyview_disable_rps(dev);
6181 gen6_disable_rps(dev);
6183 dev_priv->rps.enabled = false;
6184 mutex_unlock(&dev_priv->rps.hw_lock);
6188 static void intel_gen6_powersave_work(struct work_struct *work)
6190 struct drm_i915_private *dev_priv =
6191 container_of(work, struct drm_i915_private,
6192 rps.delayed_resume_work.work);
6193 struct drm_device *dev = dev_priv->dev;
6195 mutex_lock(&dev_priv->rps.hw_lock);
6197 gen6_reset_rps_interrupts(dev);
6199 if (IS_CHERRYVIEW(dev)) {
6200 cherryview_enable_rps(dev);
6201 } else if (IS_VALLEYVIEW(dev)) {
6202 valleyview_enable_rps(dev);
6203 } else if (INTEL_INFO(dev)->gen >= 9) {
6204 gen9_enable_rc6(dev);
6205 gen9_enable_rps(dev);
6206 if (IS_SKYLAKE(dev))
6207 __gen6_update_ring_freq(dev);
6208 } else if (IS_BROADWELL(dev)) {
6209 gen8_enable_rps(dev);
6210 __gen6_update_ring_freq(dev);
6212 gen6_enable_rps(dev);
6213 __gen6_update_ring_freq(dev);
6216 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6217 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6219 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6220 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6222 dev_priv->rps.enabled = true;
6224 gen6_enable_rps_interrupts(dev);
6226 mutex_unlock(&dev_priv->rps.hw_lock);
6228 intel_runtime_pm_put(dev_priv);
6231 void intel_enable_gt_powersave(struct drm_device *dev)
6233 struct drm_i915_private *dev_priv = dev->dev_private;
6235 /* Powersaving is controlled by the host when inside a VM */
6236 if (intel_vgpu_active(dev))
6239 if (IS_IRONLAKE_M(dev)) {
6240 mutex_lock(&dev->struct_mutex);
6241 ironlake_enable_drps(dev);
6242 intel_init_emon(dev);
6243 mutex_unlock(&dev->struct_mutex);
6244 } else if (INTEL_INFO(dev)->gen >= 6) {
6246 * PCU communication is slow and this doesn't need to be
6247 * done at any specific time, so do this out of our fast path
6248 * to make resume and init faster.
6250 * We depend on the HW RC6 power context save/restore
6251 * mechanism when entering D3 through runtime PM suspend. So
6252 * disable RPM until RPS/RC6 is properly setup. We can only
6253 * get here via the driver load/system resume/runtime resume
6254 * paths, so the _noresume version is enough (and in case of
6255 * runtime resume it's necessary).
6257 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6258 round_jiffies_up_relative(HZ)))
6259 intel_runtime_pm_get_noresume(dev_priv);
6263 void intel_reset_gt_powersave(struct drm_device *dev)
6265 struct drm_i915_private *dev_priv = dev->dev_private;
6267 if (INTEL_INFO(dev)->gen < 6)
6270 gen6_suspend_rps(dev);
6271 dev_priv->rps.enabled = false;
6274 static void ibx_init_clock_gating(struct drm_device *dev)
6276 struct drm_i915_private *dev_priv = dev->dev_private;
6279 * On Ibex Peak and Cougar Point, we need to disable clock
6280 * gating for the panel power sequencer or it will fail to
6281 * start up when no ports are active.
6283 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6286 static void g4x_disable_trickle_feed(struct drm_device *dev)
6288 struct drm_i915_private *dev_priv = dev->dev_private;
6291 for_each_pipe(dev_priv, pipe) {
6292 I915_WRITE(DSPCNTR(pipe),
6293 I915_READ(DSPCNTR(pipe)) |
6294 DISPPLANE_TRICKLE_FEED_DISABLE);
6296 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6297 POSTING_READ(DSPSURF(pipe));
6301 static void ilk_init_lp_watermarks(struct drm_device *dev)
6303 struct drm_i915_private *dev_priv = dev->dev_private;
6305 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6306 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6307 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6310 * Don't touch WM1S_LP_EN here.
6311 * Doing so could cause underruns.
6315 static void ironlake_init_clock_gating(struct drm_device *dev)
6317 struct drm_i915_private *dev_priv = dev->dev_private;
6318 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6322 * WaFbcDisableDpfcClockGating:ilk
6324 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6325 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6326 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6328 I915_WRITE(PCH_3DCGDIS0,
6329 MARIUNIT_CLOCK_GATE_DISABLE |
6330 SVSMUNIT_CLOCK_GATE_DISABLE);
6331 I915_WRITE(PCH_3DCGDIS1,
6332 VFMUNIT_CLOCK_GATE_DISABLE);
6335 * According to the spec the following bits should be set in
6336 * order to enable memory self-refresh
6337 * The bit 22/21 of 0x42004
6338 * The bit 5 of 0x42020
6339 * The bit 15 of 0x45000
6341 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6342 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6343 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6344 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6345 I915_WRITE(DISP_ARB_CTL,
6346 (I915_READ(DISP_ARB_CTL) |
6349 ilk_init_lp_watermarks(dev);
6352 * Based on the document from hardware guys the following bits
6353 * should be set unconditionally in order to enable FBC.
6354 * The bit 22 of 0x42000
6355 * The bit 22 of 0x42004
6356 * The bit 7,8,9 of 0x42020.
6358 if (IS_IRONLAKE_M(dev)) {
6359 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6360 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6361 I915_READ(ILK_DISPLAY_CHICKEN1) |
6363 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6364 I915_READ(ILK_DISPLAY_CHICKEN2) |
6368 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6370 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6371 I915_READ(ILK_DISPLAY_CHICKEN2) |
6372 ILK_ELPIN_409_SELECT);
6373 I915_WRITE(_3D_CHICKEN2,
6374 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6375 _3D_CHICKEN2_WM_READ_PIPELINED);
6377 /* WaDisableRenderCachePipelinedFlush:ilk */
6378 I915_WRITE(CACHE_MODE_0,
6379 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6381 /* WaDisable_RenderCache_OperationalFlush:ilk */
6382 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6384 g4x_disable_trickle_feed(dev);
6386 ibx_init_clock_gating(dev);
6389 static void cpt_init_clock_gating(struct drm_device *dev)
6391 struct drm_i915_private *dev_priv = dev->dev_private;
6396 * On Ibex Peak and Cougar Point, we need to disable clock
6397 * gating for the panel power sequencer or it will fail to
6398 * start up when no ports are active.
6400 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6401 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6402 PCH_CPUNIT_CLOCK_GATE_DISABLE);
6403 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6404 DPLS_EDP_PPS_FIX_DIS);
6405 /* The below fixes the weird display corruption, a few pixels shifted
6406 * downward, on (only) LVDS of some HP laptops with IVY.
6408 for_each_pipe(dev_priv, pipe) {
6409 val = I915_READ(TRANS_CHICKEN2(pipe));
6410 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6411 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6412 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6413 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6414 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6415 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6416 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6417 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6419 /* WADP0ClockGatingDisable */
6420 for_each_pipe(dev_priv, pipe) {
6421 I915_WRITE(TRANS_CHICKEN1(pipe),
6422 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6426 static void gen6_check_mch_setup(struct drm_device *dev)
6428 struct drm_i915_private *dev_priv = dev->dev_private;
6431 tmp = I915_READ(MCH_SSKPD);
6432 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6433 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6437 static void gen6_init_clock_gating(struct drm_device *dev)
6439 struct drm_i915_private *dev_priv = dev->dev_private;
6440 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6442 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6444 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6445 I915_READ(ILK_DISPLAY_CHICKEN2) |
6446 ILK_ELPIN_409_SELECT);
6448 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6449 I915_WRITE(_3D_CHICKEN,
6450 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6452 /* WaDisable_RenderCache_OperationalFlush:snb */
6453 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6456 * BSpec recoomends 8x4 when MSAA is used,
6457 * however in practice 16x4 seems fastest.
6459 * Note that PS/WM thread counts depend on the WIZ hashing
6460 * disable bit, which we don't touch here, but it's good
6461 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6463 I915_WRITE(GEN6_GT_MODE,
6464 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6466 ilk_init_lp_watermarks(dev);
6468 I915_WRITE(CACHE_MODE_0,
6469 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6471 I915_WRITE(GEN6_UCGCTL1,
6472 I915_READ(GEN6_UCGCTL1) |
6473 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6474 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6476 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6477 * gating disable must be set. Failure to set it results in
6478 * flickering pixels due to Z write ordering failures after
6479 * some amount of runtime in the Mesa "fire" demo, and Unigine
6480 * Sanctuary and Tropics, and apparently anything else with
6481 * alpha test or pixel discard.
6483 * According to the spec, bit 11 (RCCUNIT) must also be set,
6484 * but we didn't debug actual testcases to find it out.
6486 * WaDisableRCCUnitClockGating:snb
6487 * WaDisableRCPBUnitClockGating:snb
6489 I915_WRITE(GEN6_UCGCTL2,
6490 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6491 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6493 /* WaStripsFansDisableFastClipPerformanceFix:snb */
6494 I915_WRITE(_3D_CHICKEN3,
6495 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6499 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6500 * 3DSTATE_SF number of SF output attributes is more than 16."
6502 I915_WRITE(_3D_CHICKEN3,
6503 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6506 * According to the spec the following bits should be
6507 * set in order to enable memory self-refresh and fbc:
6508 * The bit21 and bit22 of 0x42000
6509 * The bit21 and bit22 of 0x42004
6510 * The bit5 and bit7 of 0x42020
6511 * The bit14 of 0x70180
6512 * The bit14 of 0x71180
6514 * WaFbcAsynchFlipDisableFbcQueue:snb
6516 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6517 I915_READ(ILK_DISPLAY_CHICKEN1) |
6518 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6519 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6520 I915_READ(ILK_DISPLAY_CHICKEN2) |
6521 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6522 I915_WRITE(ILK_DSPCLK_GATE_D,
6523 I915_READ(ILK_DSPCLK_GATE_D) |
6524 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6525 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6527 g4x_disable_trickle_feed(dev);
6529 cpt_init_clock_gating(dev);
6531 gen6_check_mch_setup(dev);
6534 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6536 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6539 * WaVSThreadDispatchOverride:ivb,vlv
6541 * This actually overrides the dispatch
6542 * mode for all thread types.
6544 reg &= ~GEN7_FF_SCHED_MASK;
6545 reg |= GEN7_FF_TS_SCHED_HW;
6546 reg |= GEN7_FF_VS_SCHED_HW;
6547 reg |= GEN7_FF_DS_SCHED_HW;
6549 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6552 static void lpt_init_clock_gating(struct drm_device *dev)
6554 struct drm_i915_private *dev_priv = dev->dev_private;
6557 * TODO: this bit should only be enabled when really needed, then
6558 * disabled when not needed anymore in order to save power.
6560 if (HAS_PCH_LPT_LP(dev))
6561 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6562 I915_READ(SOUTH_DSPCLK_GATE_D) |
6563 PCH_LP_PARTITION_LEVEL_DISABLE);
6565 /* WADPOClockGatingDisable:hsw */
6566 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6567 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
6568 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6571 static void lpt_suspend_hw(struct drm_device *dev)
6573 struct drm_i915_private *dev_priv = dev->dev_private;
6575 if (HAS_PCH_LPT_LP(dev)) {
6576 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6578 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6579 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6583 static void broadwell_init_clock_gating(struct drm_device *dev)
6585 struct drm_i915_private *dev_priv = dev->dev_private;
6589 ilk_init_lp_watermarks(dev);
6591 /* WaSwitchSolVfFArbitrationPriority:bdw */
6592 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6594 /* WaPsrDPAMaskVBlankInSRD:bdw */
6595 I915_WRITE(CHICKEN_PAR1_1,
6596 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6598 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
6599 for_each_pipe(dev_priv, pipe) {
6600 I915_WRITE(CHICKEN_PIPESL_1(pipe),
6601 I915_READ(CHICKEN_PIPESL_1(pipe)) |
6602 BDW_DPRS_MASK_VBLANK_SRD);
6605 /* WaVSRefCountFullforceMissDisable:bdw */
6606 /* WaDSRefCountFullforceMissDisable:bdw */
6607 I915_WRITE(GEN7_FF_THREAD_MODE,
6608 I915_READ(GEN7_FF_THREAD_MODE) &
6609 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6611 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6612 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6614 /* WaDisableSDEUnitClockGating:bdw */
6615 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6616 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6619 * WaProgramL3SqcReg1Default:bdw
6620 * WaTempDisableDOPClkGating:bdw
6622 misccpctl = I915_READ(GEN7_MISCCPCTL);
6623 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6624 I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6626 * Wait at least 100 clocks before re-enabling clock gating. See
6627 * the definition of L3SQCREG1 in BSpec.
6629 POSTING_READ(GEN8_L3SQCREG1);
6631 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6634 * WaGttCachingOffByDefault:bdw
6635 * GTT cache may not work with big pages, so if those
6636 * are ever enabled GTT cache may need to be disabled.
6638 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6640 lpt_init_clock_gating(dev);
6643 static void haswell_init_clock_gating(struct drm_device *dev)
6645 struct drm_i915_private *dev_priv = dev->dev_private;
6647 ilk_init_lp_watermarks(dev);
6649 /* L3 caching of data atomics doesn't work -- disable it. */
6650 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6651 I915_WRITE(HSW_ROW_CHICKEN3,
6652 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6654 /* This is required by WaCatErrorRejectionIssue:hsw */
6655 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6656 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6657 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6659 /* WaVSRefCountFullforceMissDisable:hsw */
6660 I915_WRITE(GEN7_FF_THREAD_MODE,
6661 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
6663 /* WaDisable_RenderCache_OperationalFlush:hsw */
6664 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6666 /* enable HiZ Raw Stall Optimization */
6667 I915_WRITE(CACHE_MODE_0_GEN7,
6668 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6670 /* WaDisable4x2SubspanOptimization:hsw */
6671 I915_WRITE(CACHE_MODE_1,
6672 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6675 * BSpec recommends 8x4 when MSAA is used,
6676 * however in practice 16x4 seems fastest.
6678 * Note that PS/WM thread counts depend on the WIZ hashing
6679 * disable bit, which we don't touch here, but it's good
6680 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6682 I915_WRITE(GEN7_GT_MODE,
6683 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6685 /* WaSampleCChickenBitEnable:hsw */
6686 I915_WRITE(HALF_SLICE_CHICKEN3,
6687 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6689 /* WaSwitchSolVfFArbitrationPriority:hsw */
6690 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6692 /* WaRsPkgCStateDisplayPMReq:hsw */
6693 I915_WRITE(CHICKEN_PAR1_1,
6694 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
6696 lpt_init_clock_gating(dev);
6699 static void ivybridge_init_clock_gating(struct drm_device *dev)
6701 struct drm_i915_private *dev_priv = dev->dev_private;
6704 ilk_init_lp_watermarks(dev);
6706 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6708 /* WaDisableEarlyCull:ivb */
6709 I915_WRITE(_3D_CHICKEN3,
6710 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6712 /* WaDisableBackToBackFlipFix:ivb */
6713 I915_WRITE(IVB_CHICKEN3,
6714 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6715 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6717 /* WaDisablePSDDualDispatchEnable:ivb */
6718 if (IS_IVB_GT1(dev))
6719 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6720 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6722 /* WaDisable_RenderCache_OperationalFlush:ivb */
6723 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6725 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6726 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6727 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6729 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6730 I915_WRITE(GEN7_L3CNTLREG1,
6731 GEN7_WA_FOR_GEN7_L3_CONTROL);
6732 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
6733 GEN7_WA_L3_CHICKEN_MODE);
6734 if (IS_IVB_GT1(dev))
6735 I915_WRITE(GEN7_ROW_CHICKEN2,
6736 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6738 /* must write both registers */
6739 I915_WRITE(GEN7_ROW_CHICKEN2,
6740 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6741 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6742 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6745 /* WaForceL3Serialization:ivb */
6746 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6747 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6750 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6751 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
6753 I915_WRITE(GEN6_UCGCTL2,
6754 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6756 /* This is required by WaCatErrorRejectionIssue:ivb */
6757 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6758 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6759 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6761 g4x_disable_trickle_feed(dev);
6763 gen7_setup_fixed_func_scheduler(dev_priv);
6765 if (0) { /* causes HiZ corruption on ivb:gt1 */
6766 /* enable HiZ Raw Stall Optimization */
6767 I915_WRITE(CACHE_MODE_0_GEN7,
6768 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6771 /* WaDisable4x2SubspanOptimization:ivb */
6772 I915_WRITE(CACHE_MODE_1,
6773 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6776 * BSpec recommends 8x4 when MSAA is used,
6777 * however in practice 16x4 seems fastest.
6779 * Note that PS/WM thread counts depend on the WIZ hashing
6780 * disable bit, which we don't touch here, but it's good
6781 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6783 I915_WRITE(GEN7_GT_MODE,
6784 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6786 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6787 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6788 snpcr |= GEN6_MBC_SNPCR_MED;
6789 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
6791 if (!HAS_PCH_NOP(dev))
6792 cpt_init_clock_gating(dev);
6794 gen6_check_mch_setup(dev);
6797 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6799 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6802 * Disable trickle feed and enable pnd deadline calculation
6804 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6805 I915_WRITE(CBR1_VLV, 0);
6808 static void valleyview_init_clock_gating(struct drm_device *dev)
6810 struct drm_i915_private *dev_priv = dev->dev_private;
6812 vlv_init_display_clock_gating(dev_priv);
6814 /* WaDisableEarlyCull:vlv */
6815 I915_WRITE(_3D_CHICKEN3,
6816 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6818 /* WaDisableBackToBackFlipFix:vlv */
6819 I915_WRITE(IVB_CHICKEN3,
6820 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6821 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6823 /* WaPsdDispatchEnable:vlv */
6824 /* WaDisablePSDDualDispatchEnable:vlv */
6825 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6826 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6827 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6829 /* WaDisable_RenderCache_OperationalFlush:vlv */
6830 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6832 /* WaForceL3Serialization:vlv */
6833 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6834 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6836 /* WaDisableDopClockGating:vlv */
6837 I915_WRITE(GEN7_ROW_CHICKEN2,
6838 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6840 /* This is required by WaCatErrorRejectionIssue:vlv */
6841 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6842 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6843 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6845 gen7_setup_fixed_func_scheduler(dev_priv);
6848 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6849 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6851 I915_WRITE(GEN6_UCGCTL2,
6852 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6854 /* WaDisableL3Bank2xClockGate:vlv
6855 * Disabling L3 clock gating- MMIO 940c[25] = 1
6856 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6857 I915_WRITE(GEN7_UCGCTL4,
6858 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
6861 * BSpec says this must be set, even though
6862 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6864 I915_WRITE(CACHE_MODE_1,
6865 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6868 * BSpec recommends 8x4 when MSAA is used,
6869 * however in practice 16x4 seems fastest.
6871 * Note that PS/WM thread counts depend on the WIZ hashing
6872 * disable bit, which we don't touch here, but it's good
6873 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6875 I915_WRITE(GEN7_GT_MODE,
6876 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6879 * WaIncreaseL3CreditsForVLVB0:vlv
6880 * This is the hardware default actually.
6882 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6885 * WaDisableVLVClockGating_VBIIssue:vlv
6886 * Disable clock gating on th GCFG unit to prevent a delay
6887 * in the reporting of vblank events.
6889 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6892 static void cherryview_init_clock_gating(struct drm_device *dev)
6894 struct drm_i915_private *dev_priv = dev->dev_private;
6896 vlv_init_display_clock_gating(dev_priv);
6898 /* WaVSRefCountFullforceMissDisable:chv */
6899 /* WaDSRefCountFullforceMissDisable:chv */
6900 I915_WRITE(GEN7_FF_THREAD_MODE,
6901 I915_READ(GEN7_FF_THREAD_MODE) &
6902 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6904 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6905 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6906 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6908 /* WaDisableCSUnitClockGating:chv */
6909 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6910 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6912 /* WaDisableSDEUnitClockGating:chv */
6913 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6914 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6917 * GTT cache may not work with big pages, so if those
6918 * are ever enabled GTT cache may need to be disabled.
6920 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6923 static void g4x_init_clock_gating(struct drm_device *dev)
6925 struct drm_i915_private *dev_priv = dev->dev_private;
6926 uint32_t dspclk_gate;
6928 I915_WRITE(RENCLK_GATE_D1, 0);
6929 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6930 GS_UNIT_CLOCK_GATE_DISABLE |
6931 CL_UNIT_CLOCK_GATE_DISABLE);
6932 I915_WRITE(RAMCLK_GATE_D, 0);
6933 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6934 OVRUNIT_CLOCK_GATE_DISABLE |
6935 OVCUNIT_CLOCK_GATE_DISABLE;
6937 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6938 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
6940 /* WaDisableRenderCachePipelinedFlush */
6941 I915_WRITE(CACHE_MODE_0,
6942 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6944 /* WaDisable_RenderCache_OperationalFlush:g4x */
6945 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6947 g4x_disable_trickle_feed(dev);
6950 static void crestline_init_clock_gating(struct drm_device *dev)
6952 struct drm_i915_private *dev_priv = dev->dev_private;
6954 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6955 I915_WRITE(RENCLK_GATE_D2, 0);
6956 I915_WRITE(DSPCLK_GATE_D, 0);
6957 I915_WRITE(RAMCLK_GATE_D, 0);
6958 I915_WRITE16(DEUC, 0);
6959 I915_WRITE(MI_ARB_STATE,
6960 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6962 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6963 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6966 static void broadwater_init_clock_gating(struct drm_device *dev)
6968 struct drm_i915_private *dev_priv = dev->dev_private;
6970 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6971 I965_RCC_CLOCK_GATE_DISABLE |
6972 I965_RCPB_CLOCK_GATE_DISABLE |
6973 I965_ISC_CLOCK_GATE_DISABLE |
6974 I965_FBC_CLOCK_GATE_DISABLE);
6975 I915_WRITE(RENCLK_GATE_D2, 0);
6976 I915_WRITE(MI_ARB_STATE,
6977 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6979 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6980 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6983 static void gen3_init_clock_gating(struct drm_device *dev)
6985 struct drm_i915_private *dev_priv = dev->dev_private;
6986 u32 dstate = I915_READ(D_STATE);
6988 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6989 DSTATE_DOT_CLOCK_GATING;
6990 I915_WRITE(D_STATE, dstate);
6992 if (IS_PINEVIEW(dev))
6993 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
6995 /* IIR "flip pending" means done if this bit is set */
6996 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6998 /* interrupts should cause a wake up from C3 */
6999 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7001 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7002 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7004 I915_WRITE(MI_ARB_STATE,
7005 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7008 static void i85x_init_clock_gating(struct drm_device *dev)
7010 struct drm_i915_private *dev_priv = dev->dev_private;
7012 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7014 /* interrupts should cause a wake up from C3 */
7015 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7016 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7018 I915_WRITE(MEM_MODE,
7019 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7022 static void i830_init_clock_gating(struct drm_device *dev)
7024 struct drm_i915_private *dev_priv = dev->dev_private;
7026 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7028 I915_WRITE(MEM_MODE,
7029 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7030 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7033 void intel_init_clock_gating(struct drm_device *dev)
7035 struct drm_i915_private *dev_priv = dev->dev_private;
7037 if (dev_priv->display.init_clock_gating)
7038 dev_priv->display.init_clock_gating(dev);
7041 void intel_suspend_hw(struct drm_device *dev)
7043 if (HAS_PCH_LPT(dev))
7044 lpt_suspend_hw(dev);
7047 /* Set up chip specific power management-related functions */
7048 void intel_init_pm(struct drm_device *dev)
7050 struct drm_i915_private *dev_priv = dev->dev_private;
7052 intel_fbc_init(dev_priv);
7055 if (IS_PINEVIEW(dev))
7056 i915_pineview_get_mem_freq(dev);
7057 else if (IS_GEN5(dev))
7058 i915_ironlake_get_mem_freq(dev);
7060 /* For FIFO watermark updates */
7061 if (INTEL_INFO(dev)->gen >= 9) {
7062 skl_setup_wm_latency(dev);
7064 if (IS_BROXTON(dev))
7065 dev_priv->display.init_clock_gating =
7066 bxt_init_clock_gating;
7067 dev_priv->display.update_wm = skl_update_wm;
7068 dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
7069 } else if (HAS_PCH_SPLIT(dev)) {
7070 ilk_setup_wm_latency(dev);
7072 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7073 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7074 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7075 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7076 dev_priv->display.update_wm = ilk_update_wm;
7077 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
7079 DRM_DEBUG_KMS("Failed to read display plane latency. "
7084 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7085 else if (IS_GEN6(dev))
7086 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7087 else if (IS_IVYBRIDGE(dev))
7088 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7089 else if (IS_HASWELL(dev))
7090 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7091 else if (INTEL_INFO(dev)->gen == 8)
7092 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7093 } else if (IS_CHERRYVIEW(dev)) {
7094 vlv_setup_wm_latency(dev);
7096 dev_priv->display.update_wm = vlv_update_wm;
7097 dev_priv->display.init_clock_gating =
7098 cherryview_init_clock_gating;
7099 } else if (IS_VALLEYVIEW(dev)) {
7100 vlv_setup_wm_latency(dev);
7102 dev_priv->display.update_wm = vlv_update_wm;
7103 dev_priv->display.init_clock_gating =
7104 valleyview_init_clock_gating;
7105 } else if (IS_PINEVIEW(dev)) {
7106 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7109 dev_priv->mem_freq)) {
7110 DRM_INFO("failed to find known CxSR latency "
7111 "(found ddr%s fsb freq %d, mem freq %d), "
7113 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7114 dev_priv->fsb_freq, dev_priv->mem_freq);
7115 /* Disable CxSR and never update its watermark again */
7116 intel_set_memory_cxsr(dev_priv, false);
7117 dev_priv->display.update_wm = NULL;
7119 dev_priv->display.update_wm = pineview_update_wm;
7120 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7121 } else if (IS_G4X(dev)) {
7122 dev_priv->display.update_wm = g4x_update_wm;
7123 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7124 } else if (IS_GEN4(dev)) {
7125 dev_priv->display.update_wm = i965_update_wm;
7126 if (IS_CRESTLINE(dev))
7127 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7128 else if (IS_BROADWATER(dev))
7129 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7130 } else if (IS_GEN3(dev)) {
7131 dev_priv->display.update_wm = i9xx_update_wm;
7132 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7133 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7134 } else if (IS_GEN2(dev)) {
7135 if (INTEL_INFO(dev)->num_pipes == 1) {
7136 dev_priv->display.update_wm = i845_update_wm;
7137 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7139 dev_priv->display.update_wm = i9xx_update_wm;
7140 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7143 if (IS_I85X(dev) || IS_I865G(dev))
7144 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7146 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7148 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7152 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7154 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7156 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7157 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7161 I915_WRITE(GEN6_PCODE_DATA, *val);
7162 I915_WRITE(GEN6_PCODE_DATA1, 0);
7163 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7165 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7167 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7171 *val = I915_READ(GEN6_PCODE_DATA);
7172 I915_WRITE(GEN6_PCODE_DATA, 0);
7177 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
7179 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7181 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7182 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7186 I915_WRITE(GEN6_PCODE_DATA, val);
7187 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7189 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7191 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7195 I915_WRITE(GEN6_PCODE_DATA, 0);
7200 static int vlv_gpu_freq_div(unsigned int czclk_freq)
7202 switch (czclk_freq) {
7217 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7219 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7221 div = vlv_gpu_freq_div(czclk_freq);
7225 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
7228 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7230 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7232 mul = vlv_gpu_freq_div(czclk_freq);
7236 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
7239 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7241 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7243 div = vlv_gpu_freq_div(czclk_freq) / 2;
7247 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
7250 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7252 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7254 mul = vlv_gpu_freq_div(czclk_freq) / 2;
7258 /* CHV needs even values */
7259 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
7262 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7264 if (IS_GEN9(dev_priv->dev))
7265 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7267 else if (IS_CHERRYVIEW(dev_priv->dev))
7268 return chv_gpu_freq(dev_priv, val);
7269 else if (IS_VALLEYVIEW(dev_priv->dev))
7270 return byt_gpu_freq(dev_priv, val);
7272 return val * GT_FREQUENCY_MULTIPLIER;
7275 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7277 if (IS_GEN9(dev_priv->dev))
7278 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7279 GT_FREQUENCY_MULTIPLIER);
7280 else if (IS_CHERRYVIEW(dev_priv->dev))
7281 return chv_freq_opcode(dev_priv, val);
7282 else if (IS_VALLEYVIEW(dev_priv->dev))
7283 return byt_freq_opcode(dev_priv, val);
7285 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
7288 struct request_boost {
7289 struct work_struct work;
7290 struct drm_i915_gem_request *req;
7293 static void __intel_rps_boost_work(struct work_struct *work)
7295 struct request_boost *boost = container_of(work, struct request_boost, work);
7296 struct drm_i915_gem_request *req = boost->req;
7298 if (!i915_gem_request_completed(req, true))
7299 gen6_rps_boost(to_i915(req->ring->dev), NULL,
7300 req->emitted_jiffies);
7302 i915_gem_request_unreference__unlocked(req);
7306 void intel_queue_rps_boost_for_request(struct drm_device *dev,
7307 struct drm_i915_gem_request *req)
7309 struct request_boost *boost;
7311 if (req == NULL || INTEL_INFO(dev)->gen < 6)
7314 if (i915_gem_request_completed(req, true))
7317 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7321 i915_gem_request_reference(req);
7324 INIT_WORK(&boost->work, __intel_rps_boost_work);
7325 queue_work(to_i915(dev)->wq, &boost->work);
7328 void intel_pm_setup(struct drm_device *dev)
7330 struct drm_i915_private *dev_priv = dev->dev_private;
7332 mutex_init(&dev_priv->rps.hw_lock);
7333 spin_lock_init(&dev_priv->rps.client_lock);
7335 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7336 intel_gen6_powersave_work);
7337 INIT_LIST_HEAD(&dev_priv->rps.clients);
7338 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7339 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
7341 dev_priv->pm.suspended = false;