4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Daniel Vetter <daniel@ffwll.ch>
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
29 #include <linux/seq_file.h>
35 #include "intel_drv.h"
37 /* Limits for overlay size. According to intel doc, the real limits are:
38 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
39 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
40 * the mininum of both. */
41 #define IMAGE_MAX_WIDTH 2048
42 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */
43 /* on 830 and 845 these large limits result in the card hanging */
44 #define IMAGE_MAX_WIDTH_LEGACY 1024
45 #define IMAGE_MAX_HEIGHT_LEGACY 1088
47 /* overlay register definitions */
49 #define OCMD_TILED_SURFACE (0x1<<19)
50 #define OCMD_MIRROR_MASK (0x3<<17)
51 #define OCMD_MIRROR_MODE (0x3<<17)
52 #define OCMD_MIRROR_HORIZONTAL (0x1<<17)
53 #define OCMD_MIRROR_VERTICAL (0x2<<17)
54 #define OCMD_MIRROR_BOTH (0x3<<17)
55 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
56 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */
57 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */
58 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */
59 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
60 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */
61 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */
62 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */
63 #define OCMD_YUV_422_PACKED (0x8<<10)
64 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */
65 #define OCMD_YUV_420_PLANAR (0xc<<10)
66 #define OCMD_YUV_422_PLANAR (0xd<<10)
67 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */
68 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9)
69 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7)
70 #define OCMD_BUF_TYPE_MASK (0x1<<5)
71 #define OCMD_BUF_TYPE_FRAME (0x0<<5)
72 #define OCMD_BUF_TYPE_FIELD (0x1<<5)
73 #define OCMD_TEST_MODE (0x1<<4)
74 #define OCMD_BUFFER_SELECT (0x3<<2)
75 #define OCMD_BUFFER0 (0x0<<2)
76 #define OCMD_BUFFER1 (0x1<<2)
77 #define OCMD_FIELD_SELECT (0x1<<2)
78 #define OCMD_FIELD0 (0x0<<1)
79 #define OCMD_FIELD1 (0x1<<1)
80 #define OCMD_ENABLE (0x1<<0)
82 /* OCONFIG register */
83 #define OCONF_PIPE_MASK (0x1<<18)
84 #define OCONF_PIPE_A (0x0<<18)
85 #define OCONF_PIPE_B (0x1<<18)
86 #define OCONF_GAMMA2_ENABLE (0x1<<16)
87 #define OCONF_CSC_MODE_BT601 (0x0<<5)
88 #define OCONF_CSC_MODE_BT709 (0x1<<5)
89 #define OCONF_CSC_BYPASS (0x1<<4)
90 #define OCONF_CC_OUT_8BIT (0x1<<3)
91 #define OCONF_TEST_MODE (0x1<<2)
92 #define OCONF_THREE_LINE_BUFFER (0x1<<0)
93 #define OCONF_TWO_LINE_BUFFER (0x0<<0)
95 /* DCLRKM (dst-key) register */
96 #define DST_KEY_ENABLE (0x1<<31)
97 #define CLK_RGB24_MASK 0x0
98 #define CLK_RGB16_MASK 0x070307
99 #define CLK_RGB15_MASK 0x070707
100 #define CLK_RGB8I_MASK 0xffffff
102 #define RGB16_TO_COLORKEY(c) \
103 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
104 #define RGB15_TO_COLORKEY(c) \
105 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
107 /* overlay flip addr flag */
108 #define OFC_UPDATE 0x1
110 /* polyphase filter coefficients */
111 #define N_HORIZ_Y_TAPS 5
112 #define N_VERT_Y_TAPS 3
113 #define N_HORIZ_UV_TAPS 3
114 #define N_VERT_UV_TAPS 3
118 /* memory bufferd overlay registers */
119 struct overlay_registers {
147 u32 RESERVED1; /* 0x6C */
160 u32 FASTHSCALE; /* 0xA0 */
161 u32 UVSCALEV; /* 0xA4 */
162 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
163 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
164 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
165 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
166 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
167 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
168 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
169 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
170 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
173 /* overlay flip addr flag */
174 #define OFC_UPDATE 0x1
176 #define OVERLAY_NONPHYSICAL(dev) (IS_G33(dev) || IS_I965G(dev))
177 #define OVERLAY_EXISTS(dev) (!IS_G4X(dev) && !IS_IRONLAKE(dev) && !IS_GEN6(dev))
180 static struct overlay_registers *intel_overlay_map_regs_atomic(struct intel_overlay *overlay)
182 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
183 struct overlay_registers *regs;
185 /* no recursive mappings */
186 BUG_ON(overlay->virt_addr);
188 if (OVERLAY_NONPHYSICAL(overlay->dev)) {
189 regs = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
190 overlay->reg_bo->gtt_offset,
194 DRM_ERROR("failed to map overlay regs in GTT\n");
198 regs = overlay->reg_bo->phys_obj->handle->vaddr;
200 return overlay->virt_addr = regs;
203 static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay)
205 if (OVERLAY_NONPHYSICAL(overlay->dev))
206 io_mapping_unmap_atomic(overlay->virt_addr, KM_USER0);
208 overlay->virt_addr = NULL;
213 /* overlay needs to be disable in OCMD reg */
214 static int intel_overlay_on(struct intel_overlay *overlay)
216 struct drm_device *dev = overlay->dev;
218 drm_i915_private_t *dev_priv = dev->dev_private;
220 BUG_ON(overlay->active);
223 overlay->hw_wedged = NEEDS_WAIT_FOR_FLIP;
226 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_ON);
227 OUT_RING(overlay->flip_addr | OFC_UPDATE);
228 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
232 overlay->last_flip_req =
233 i915_add_request(dev, NULL, 0, &dev_priv->render_ring);
234 if (overlay->last_flip_req == 0)
237 ret = i915_do_wait_request(dev,
238 overlay->last_flip_req, 1, &dev_priv->render_ring);
242 overlay->hw_wedged = 0;
243 overlay->last_flip_req = 0;
247 /* overlay needs to be enabled in OCMD reg */
248 static void intel_overlay_continue(struct intel_overlay *overlay,
249 bool load_polyphase_filter)
251 struct drm_device *dev = overlay->dev;
252 drm_i915_private_t *dev_priv = dev->dev_private;
253 u32 flip_addr = overlay->flip_addr;
256 BUG_ON(!overlay->active);
258 if (load_polyphase_filter)
259 flip_addr |= OFC_UPDATE;
261 /* check for underruns */
262 tmp = I915_READ(DOVSTA);
264 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
267 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
271 overlay->last_flip_req =
272 i915_add_request(dev, NULL, 0, &dev_priv->render_ring);
275 static int intel_overlay_wait_flip(struct intel_overlay *overlay)
277 struct drm_device *dev = overlay->dev;
278 drm_i915_private_t *dev_priv = dev->dev_private;
282 if (overlay->last_flip_req != 0) {
283 ret = i915_do_wait_request(dev, overlay->last_flip_req,
284 1, &dev_priv->render_ring);
286 overlay->last_flip_req = 0;
288 tmp = I915_READ(ISR);
290 if (!(tmp & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT))
295 /* synchronous slowpath */
296 overlay->hw_wedged = RELEASE_OLD_VID;
299 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
303 overlay->last_flip_req =
304 i915_add_request(dev, NULL, 0, &dev_priv->render_ring);
305 if (overlay->last_flip_req == 0)
308 ret = i915_do_wait_request(dev, overlay->last_flip_req,
309 1, &dev_priv->render_ring);
313 overlay->hw_wedged = 0;
314 overlay->last_flip_req = 0;
318 /* overlay needs to be disabled in OCMD reg */
319 static int intel_overlay_off(struct intel_overlay *overlay)
321 u32 flip_addr = overlay->flip_addr;
322 struct drm_device *dev = overlay->dev;
323 drm_i915_private_t *dev_priv = dev->dev_private;
326 BUG_ON(!overlay->active);
328 /* According to intel docs the overlay hw may hang (when switching
329 * off) without loading the filter coeffs. It is however unclear whether
330 * this applies to the disabling of the overlay or to the switching off
331 * of the hw. Do it in both cases */
332 flip_addr |= OFC_UPDATE;
334 /* wait for overlay to go idle */
335 overlay->hw_wedged = SWITCH_OFF_STAGE_1;
338 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
340 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
344 overlay->last_flip_req =
345 i915_add_request(dev, NULL, 0, &dev_priv->render_ring);
346 if (overlay->last_flip_req == 0)
349 ret = i915_do_wait_request(dev, overlay->last_flip_req,
350 1, &dev_priv->render_ring);
354 /* turn overlay off */
355 overlay->hw_wedged = SWITCH_OFF_STAGE_2;
358 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
360 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
364 overlay->last_flip_req =
365 i915_add_request(dev, NULL, 0, &dev_priv->render_ring);
366 if (overlay->last_flip_req == 0)
369 ret = i915_do_wait_request(dev, overlay->last_flip_req,
370 1, &dev_priv->render_ring);
374 overlay->hw_wedged = 0;
375 overlay->last_flip_req = 0;
379 static void intel_overlay_off_tail(struct intel_overlay *overlay)
381 struct drm_gem_object *obj;
383 /* never have the overlay hw on without showing a frame */
384 BUG_ON(!overlay->vid_bo);
385 obj = &overlay->vid_bo->base;
387 i915_gem_object_unpin(obj);
388 drm_gem_object_unreference(obj);
389 overlay->vid_bo = NULL;
391 overlay->crtc->overlay = NULL;
392 overlay->crtc = NULL;
396 /* recover from an interruption due to a signal
397 * We have to be careful not to repeat work forever an make forward progess. */
398 int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay,
401 struct drm_device *dev = overlay->dev;
402 struct drm_gem_object *obj;
403 drm_i915_private_t *dev_priv = dev->dev_private;
407 if (overlay->hw_wedged == HW_WEDGED)
410 if (overlay->last_flip_req == 0) {
411 overlay->last_flip_req =
412 i915_add_request(dev, NULL, 0, &dev_priv->render_ring);
413 if (overlay->last_flip_req == 0)
417 ret = i915_do_wait_request(dev, overlay->last_flip_req,
418 interruptible, &dev_priv->render_ring);
422 switch (overlay->hw_wedged) {
423 case RELEASE_OLD_VID:
424 obj = &overlay->old_vid_bo->base;
425 i915_gem_object_unpin(obj);
426 drm_gem_object_unreference(obj);
427 overlay->old_vid_bo = NULL;
429 case SWITCH_OFF_STAGE_1:
430 flip_addr = overlay->flip_addr;
431 flip_addr |= OFC_UPDATE;
433 overlay->hw_wedged = SWITCH_OFF_STAGE_2;
436 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
438 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
442 overlay->last_flip_req = i915_add_request(dev, NULL,
443 0, &dev_priv->render_ring);
444 if (overlay->last_flip_req == 0)
447 ret = i915_do_wait_request(dev, overlay->last_flip_req,
448 interruptible, &dev_priv->render_ring);
452 case SWITCH_OFF_STAGE_2:
453 intel_overlay_off_tail(overlay);
456 BUG_ON(overlay->hw_wedged != NEEDS_WAIT_FOR_FLIP);
459 overlay->hw_wedged = 0;
460 overlay->last_flip_req = 0;
464 /* Wait for pending overlay flip and release old frame.
465 * Needs to be called before the overlay register are changed
466 * via intel_overlay_(un)map_regs_atomic */
467 static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
470 struct drm_gem_object *obj;
472 /* only wait if there is actually an old frame to release to
473 * guarantee forward progress */
474 if (!overlay->old_vid_bo)
477 ret = intel_overlay_wait_flip(overlay);
481 obj = &overlay->old_vid_bo->base;
482 i915_gem_object_unpin(obj);
483 drm_gem_object_unreference(obj);
484 overlay->old_vid_bo = NULL;
489 struct put_image_params {
506 static int packed_depth_bytes(u32 format)
508 switch (format & I915_OVERLAY_DEPTH_MASK) {
509 case I915_OVERLAY_YUV422:
511 case I915_OVERLAY_YUV411:
512 /* return 6; not implemented */
518 static int packed_width_bytes(u32 format, short width)
520 switch (format & I915_OVERLAY_DEPTH_MASK) {
521 case I915_OVERLAY_YUV422:
528 static int uv_hsubsampling(u32 format)
530 switch (format & I915_OVERLAY_DEPTH_MASK) {
531 case I915_OVERLAY_YUV422:
532 case I915_OVERLAY_YUV420:
534 case I915_OVERLAY_YUV411:
535 case I915_OVERLAY_YUV410:
542 static int uv_vsubsampling(u32 format)
544 switch (format & I915_OVERLAY_DEPTH_MASK) {
545 case I915_OVERLAY_YUV420:
546 case I915_OVERLAY_YUV410:
548 case I915_OVERLAY_YUV422:
549 case I915_OVERLAY_YUV411:
556 static u32 calc_swidthsw(struct drm_device *dev, u32 offset, u32 width)
558 u32 mask, shift, ret;
566 ret = ((offset + width + mask) >> shift) - (offset >> shift);
573 static const u16 y_static_hcoeffs[N_HORIZ_Y_TAPS * N_PHASES] = {
574 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
575 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
576 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
577 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
578 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
579 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
580 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
581 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
582 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
583 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
584 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
585 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
586 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
587 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
588 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
589 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
590 0xb000, 0x3000, 0x0800, 0x3000, 0xb000};
591 static const u16 uv_static_hcoeffs[N_HORIZ_UV_TAPS * N_PHASES] = {
592 0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
593 0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
594 0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
595 0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
596 0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
597 0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
598 0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
599 0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
600 0x3000, 0x0800, 0x3000};
602 static void update_polyphase_filter(struct overlay_registers *regs)
604 memcpy(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
605 memcpy(regs->UV_HCOEFS, uv_static_hcoeffs, sizeof(uv_static_hcoeffs));
608 static bool update_scaling_factors(struct intel_overlay *overlay,
609 struct overlay_registers *regs,
610 struct put_image_params *params)
612 /* fixed point with a 12 bit shift */
613 u32 xscale, yscale, xscale_UV, yscale_UV;
615 #define FRACT_MASK 0xfff
616 bool scale_changed = false;
617 int uv_hscale = uv_hsubsampling(params->format);
618 int uv_vscale = uv_vsubsampling(params->format);
620 if (params->dst_w > 1)
621 xscale = ((params->src_scan_w - 1) << FP_SHIFT)
624 xscale = 1 << FP_SHIFT;
626 if (params->dst_h > 1)
627 yscale = ((params->src_scan_h - 1) << FP_SHIFT)
630 yscale = 1 << FP_SHIFT;
632 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
633 xscale_UV = xscale/uv_hscale;
634 yscale_UV = yscale/uv_vscale;
635 /* make the Y scale to UV scale ratio an exact multiply */
636 xscale = xscale_UV * uv_hscale;
637 yscale = yscale_UV * uv_vscale;
643 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
644 scale_changed = true;
645 overlay->old_xscale = xscale;
646 overlay->old_yscale = yscale;
648 regs->YRGBSCALE = ((yscale & FRACT_MASK) << 20)
649 | ((xscale >> FP_SHIFT) << 16)
650 | ((xscale & FRACT_MASK) << 3);
651 regs->UVSCALE = ((yscale_UV & FRACT_MASK) << 20)
652 | ((xscale_UV >> FP_SHIFT) << 16)
653 | ((xscale_UV & FRACT_MASK) << 3);
654 regs->UVSCALEV = ((yscale >> FP_SHIFT) << 16)
655 | ((yscale_UV >> FP_SHIFT) << 0);
658 update_polyphase_filter(regs);
660 return scale_changed;
663 static void update_colorkey(struct intel_overlay *overlay,
664 struct overlay_registers *regs)
666 u32 key = overlay->color_key;
667 switch (overlay->crtc->base.fb->bits_per_pixel) {
670 regs->DCLRKM = CLK_RGB8I_MASK | DST_KEY_ENABLE;
672 if (overlay->crtc->base.fb->depth == 15) {
673 regs->DCLRKV = RGB15_TO_COLORKEY(key);
674 regs->DCLRKM = CLK_RGB15_MASK | DST_KEY_ENABLE;
676 regs->DCLRKV = RGB16_TO_COLORKEY(key);
677 regs->DCLRKM = CLK_RGB16_MASK | DST_KEY_ENABLE;
682 regs->DCLRKM = CLK_RGB24_MASK | DST_KEY_ENABLE;
686 static u32 overlay_cmd_reg(struct put_image_params *params)
688 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
690 if (params->format & I915_OVERLAY_YUV_PLANAR) {
691 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
692 case I915_OVERLAY_YUV422:
693 cmd |= OCMD_YUV_422_PLANAR;
695 case I915_OVERLAY_YUV420:
696 cmd |= OCMD_YUV_420_PLANAR;
698 case I915_OVERLAY_YUV411:
699 case I915_OVERLAY_YUV410:
700 cmd |= OCMD_YUV_410_PLANAR;
703 } else { /* YUV packed */
704 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
705 case I915_OVERLAY_YUV422:
706 cmd |= OCMD_YUV_422_PACKED;
708 case I915_OVERLAY_YUV411:
709 cmd |= OCMD_YUV_411_PACKED;
713 switch (params->format & I915_OVERLAY_SWAP_MASK) {
714 case I915_OVERLAY_NO_SWAP:
716 case I915_OVERLAY_UV_SWAP:
719 case I915_OVERLAY_Y_SWAP:
722 case I915_OVERLAY_Y_AND_UV_SWAP:
723 cmd |= OCMD_Y_AND_UV_SWAP;
731 int intel_overlay_do_put_image(struct intel_overlay *overlay,
732 struct drm_gem_object *new_bo,
733 struct put_image_params *params)
736 struct overlay_registers *regs;
737 bool scale_changed = false;
738 struct drm_i915_gem_object *bo_priv = to_intel_bo(new_bo);
739 struct drm_device *dev = overlay->dev;
741 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
742 BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
745 ret = intel_overlay_release_old_vid(overlay);
749 ret = i915_gem_object_pin(new_bo, PAGE_SIZE);
753 ret = i915_gem_object_set_to_gtt_domain(new_bo, 0);
757 if (!overlay->active) {
758 regs = intel_overlay_map_regs_atomic(overlay);
763 regs->OCONFIG = OCONF_CC_OUT_8BIT;
764 if (IS_I965GM(overlay->dev))
765 regs->OCONFIG |= OCONF_CSC_MODE_BT709;
766 regs->OCONFIG |= overlay->crtc->pipe == 0 ?
767 OCONF_PIPE_A : OCONF_PIPE_B;
768 intel_overlay_unmap_regs_atomic(overlay);
770 ret = intel_overlay_on(overlay);
775 regs = intel_overlay_map_regs_atomic(overlay);
781 regs->DWINPOS = (params->dst_y << 16) | params->dst_x;
782 regs->DWINSZ = (params->dst_h << 16) | params->dst_w;
784 if (params->format & I915_OVERLAY_YUV_PACKED)
785 tmp_width = packed_width_bytes(params->format, params->src_w);
787 tmp_width = params->src_w;
789 regs->SWIDTH = params->src_w;
790 regs->SWIDTHSW = calc_swidthsw(overlay->dev,
791 params->offset_Y, tmp_width);
792 regs->SHEIGHT = params->src_h;
793 regs->OBUF_0Y = bo_priv->gtt_offset + params-> offset_Y;
794 regs->OSTRIDE = params->stride_Y;
796 if (params->format & I915_OVERLAY_YUV_PLANAR) {
797 int uv_hscale = uv_hsubsampling(params->format);
798 int uv_vscale = uv_vsubsampling(params->format);
800 regs->SWIDTH |= (params->src_w/uv_hscale) << 16;
801 tmp_U = calc_swidthsw(overlay->dev, params->offset_U,
802 params->src_w/uv_hscale);
803 tmp_V = calc_swidthsw(overlay->dev, params->offset_V,
804 params->src_w/uv_hscale);
805 regs->SWIDTHSW |= max_t(u32, tmp_U, tmp_V) << 16;
806 regs->SHEIGHT |= (params->src_h/uv_vscale) << 16;
807 regs->OBUF_0U = bo_priv->gtt_offset + params->offset_U;
808 regs->OBUF_0V = bo_priv->gtt_offset + params->offset_V;
809 regs->OSTRIDE |= params->stride_UV << 16;
812 scale_changed = update_scaling_factors(overlay, regs, params);
814 update_colorkey(overlay, regs);
816 regs->OCMD = overlay_cmd_reg(params);
818 intel_overlay_unmap_regs_atomic(overlay);
820 intel_overlay_continue(overlay, scale_changed);
822 overlay->old_vid_bo = overlay->vid_bo;
823 overlay->vid_bo = to_intel_bo(new_bo);
828 i915_gem_object_unpin(new_bo);
832 int intel_overlay_switch_off(struct intel_overlay *overlay)
835 struct overlay_registers *regs;
836 struct drm_device *dev = overlay->dev;
838 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
839 BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
841 if (overlay->hw_wedged) {
842 ret = intel_overlay_recover_from_interrupt(overlay, 1);
847 if (!overlay->active)
850 ret = intel_overlay_release_old_vid(overlay);
854 regs = intel_overlay_map_regs_atomic(overlay);
856 intel_overlay_unmap_regs_atomic(overlay);
858 ret = intel_overlay_off(overlay);
862 intel_overlay_off_tail(overlay);
867 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
868 struct intel_crtc *crtc)
870 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
872 int pipeconf_reg = (crtc->pipe == 0) ? PIPEACONF : PIPEBCONF;
874 if (!crtc->base.enabled || crtc->dpms_mode != DRM_MODE_DPMS_ON)
877 pipeconf = I915_READ(pipeconf_reg);
879 /* can't use the overlay with double wide pipe */
880 if (!IS_I965G(overlay->dev) && pipeconf & PIPEACONF_DOUBLE_WIDE)
886 static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
888 struct drm_device *dev = overlay->dev;
889 drm_i915_private_t *dev_priv = dev->dev_private;
891 u32 pfit_control = I915_READ(PFIT_CONTROL);
893 /* XXX: This is not the same logic as in the xorg driver, but more in
894 * line with the intel documentation for the i965 */
895 if (!IS_I965G(dev) && (pfit_control & VERT_AUTO_SCALE)) {
896 ratio = I915_READ(PFIT_AUTO_RATIOS) >> PFIT_VERT_SCALE_SHIFT;
897 } else { /* on i965 use the PGM reg to read out the autoscaler values */
898 ratio = I915_READ(PFIT_PGM_RATIOS);
900 ratio >>= PFIT_VERT_SCALE_SHIFT_965;
902 ratio >>= PFIT_VERT_SCALE_SHIFT;
905 overlay->pfit_vscale_ratio = ratio;
908 static int check_overlay_dst(struct intel_overlay *overlay,
909 struct drm_intel_overlay_put_image *rec)
911 struct drm_display_mode *mode = &overlay->crtc->base.mode;
913 if ((rec->dst_x < mode->crtc_hdisplay)
914 && (rec->dst_x + rec->dst_width
915 <= mode->crtc_hdisplay)
916 && (rec->dst_y < mode->crtc_vdisplay)
917 && (rec->dst_y + rec->dst_height
918 <= mode->crtc_vdisplay))
924 static int check_overlay_scaling(struct put_image_params *rec)
928 /* downscaling limit is 8.0 */
929 tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16;
932 tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16;
939 static int check_overlay_src(struct drm_device *dev,
940 struct drm_intel_overlay_put_image *rec,
941 struct drm_gem_object *new_bo)
945 int uv_hscale = uv_hsubsampling(rec->flags);
946 int uv_vscale = uv_vsubsampling(rec->flags);
949 /* check src dimensions */
950 if (IS_845G(dev) || IS_I830(dev)) {
951 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY
952 || rec->src_width > IMAGE_MAX_WIDTH_LEGACY)
955 if (rec->src_height > IMAGE_MAX_HEIGHT
956 || rec->src_width > IMAGE_MAX_WIDTH)
959 /* better safe than sorry, use 4 as the maximal subsampling ratio */
960 if (rec->src_height < N_VERT_Y_TAPS*4
961 || rec->src_width < N_HORIZ_Y_TAPS*4)
964 /* check alignment constraints */
965 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
966 case I915_OVERLAY_RGB:
967 /* not implemented */
969 case I915_OVERLAY_YUV_PACKED:
970 depth = packed_depth_bytes(rec->flags);
975 /* ignore UV planes */
979 /* check pixel alignment */
980 if (rec->offset_Y % depth)
983 case I915_OVERLAY_YUV_PLANAR:
984 if (uv_vscale < 0 || uv_hscale < 0)
986 /* no offset restrictions for planar formats */
992 if (rec->src_width % uv_hscale)
995 /* stride checking */
996 if (IS_I830(dev) || IS_845G(dev))
1001 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
1003 if (IS_I965G(dev) && rec->stride_Y < 512)
1006 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
1008 if (rec->stride_Y > tmp*1024 || rec->stride_UV > 2*1024)
1011 /* check buffer dimensions */
1012 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
1013 case I915_OVERLAY_RGB:
1014 case I915_OVERLAY_YUV_PACKED:
1015 /* always 4 Y values per depth pixels */
1016 if (packed_width_bytes(rec->flags, rec->src_width)
1020 tmp = rec->stride_Y*rec->src_height;
1021 if (rec->offset_Y + tmp > new_bo->size)
1024 case I915_OVERLAY_YUV_PLANAR:
1025 if (rec->src_width > rec->stride_Y)
1027 if (rec->src_width/uv_hscale > rec->stride_UV)
1030 tmp = rec->stride_Y*rec->src_height;
1031 if (rec->offset_Y + tmp > new_bo->size)
1033 tmp = rec->stride_UV*rec->src_height;
1035 if (rec->offset_U + tmp > new_bo->size
1036 || rec->offset_V + tmp > new_bo->size)
1044 int intel_overlay_put_image(struct drm_device *dev, void *data,
1045 struct drm_file *file_priv)
1047 struct drm_intel_overlay_put_image *put_image_rec = data;
1048 drm_i915_private_t *dev_priv = dev->dev_private;
1049 struct intel_overlay *overlay;
1050 struct drm_mode_object *drmmode_obj;
1051 struct intel_crtc *crtc;
1052 struct drm_gem_object *new_bo;
1053 struct put_image_params *params;
1057 DRM_ERROR("called with no initialization\n");
1061 overlay = dev_priv->overlay;
1063 DRM_DEBUG("userspace bug: no overlay\n");
1067 if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) {
1068 mutex_lock(&dev->mode_config.mutex);
1069 mutex_lock(&dev->struct_mutex);
1071 ret = intel_overlay_switch_off(overlay);
1073 mutex_unlock(&dev->struct_mutex);
1074 mutex_unlock(&dev->mode_config.mutex);
1079 params = kmalloc(sizeof(struct put_image_params), GFP_KERNEL);
1083 drmmode_obj = drm_mode_object_find(dev, put_image_rec->crtc_id,
1084 DRM_MODE_OBJECT_CRTC);
1089 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
1091 new_bo = drm_gem_object_lookup(dev, file_priv,
1092 put_image_rec->bo_handle);
1098 mutex_lock(&dev->mode_config.mutex);
1099 mutex_lock(&dev->struct_mutex);
1101 if (overlay->hw_wedged) {
1102 ret = intel_overlay_recover_from_interrupt(overlay, 1);
1107 if (overlay->crtc != crtc) {
1108 struct drm_display_mode *mode = &crtc->base.mode;
1109 ret = intel_overlay_switch_off(overlay);
1113 ret = check_overlay_possible_on_crtc(overlay, crtc);
1117 overlay->crtc = crtc;
1118 crtc->overlay = overlay;
1120 if (intel_panel_fitter_pipe(dev) == crtc->pipe
1121 /* and line to wide, i.e. one-line-mode */
1122 && mode->hdisplay > 1024) {
1123 overlay->pfit_active = 1;
1124 update_pfit_vscale_ratio(overlay);
1126 overlay->pfit_active = 0;
1129 ret = check_overlay_dst(overlay, put_image_rec);
1133 if (overlay->pfit_active) {
1134 params->dst_y = ((((u32)put_image_rec->dst_y) << 12) /
1135 overlay->pfit_vscale_ratio);
1136 /* shifting right rounds downwards, so add 1 */
1137 params->dst_h = ((((u32)put_image_rec->dst_height) << 12) /
1138 overlay->pfit_vscale_ratio) + 1;
1140 params->dst_y = put_image_rec->dst_y;
1141 params->dst_h = put_image_rec->dst_height;
1143 params->dst_x = put_image_rec->dst_x;
1144 params->dst_w = put_image_rec->dst_width;
1146 params->src_w = put_image_rec->src_width;
1147 params->src_h = put_image_rec->src_height;
1148 params->src_scan_w = put_image_rec->src_scan_width;
1149 params->src_scan_h = put_image_rec->src_scan_height;
1150 if (params->src_scan_h > params->src_h
1151 || params->src_scan_w > params->src_w) {
1156 ret = check_overlay_src(dev, put_image_rec, new_bo);
1159 params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK;
1160 params->stride_Y = put_image_rec->stride_Y;
1161 params->stride_UV = put_image_rec->stride_UV;
1162 params->offset_Y = put_image_rec->offset_Y;
1163 params->offset_U = put_image_rec->offset_U;
1164 params->offset_V = put_image_rec->offset_V;
1166 /* Check scaling after src size to prevent a divide-by-zero. */
1167 ret = check_overlay_scaling(params);
1171 ret = intel_overlay_do_put_image(overlay, new_bo, params);
1175 mutex_unlock(&dev->struct_mutex);
1176 mutex_unlock(&dev->mode_config.mutex);
1183 mutex_unlock(&dev->struct_mutex);
1184 mutex_unlock(&dev->mode_config.mutex);
1185 drm_gem_object_unreference_unlocked(new_bo);
1192 static void update_reg_attrs(struct intel_overlay *overlay,
1193 struct overlay_registers *regs)
1195 regs->OCLRC0 = (overlay->contrast << 18) | (overlay->brightness & 0xff);
1196 regs->OCLRC1 = overlay->saturation;
1199 static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1203 if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1206 for (i = 0; i < 3; i++) {
1207 if (((gamma1 >> i * 8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
1214 static bool check_gamma5_errata(u32 gamma5)
1218 for (i = 0; i < 3; i++) {
1219 if (((gamma5 >> i*8) & 0xff) == 0x80)
1226 static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1228 if (!check_gamma_bounds(0, attrs->gamma0)
1229 || !check_gamma_bounds(attrs->gamma0, attrs->gamma1)
1230 || !check_gamma_bounds(attrs->gamma1, attrs->gamma2)
1231 || !check_gamma_bounds(attrs->gamma2, attrs->gamma3)
1232 || !check_gamma_bounds(attrs->gamma3, attrs->gamma4)
1233 || !check_gamma_bounds(attrs->gamma4, attrs->gamma5)
1234 || !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
1236 if (!check_gamma5_errata(attrs->gamma5))
1241 int intel_overlay_attrs(struct drm_device *dev, void *data,
1242 struct drm_file *file_priv)
1244 struct drm_intel_overlay_attrs *attrs = data;
1245 drm_i915_private_t *dev_priv = dev->dev_private;
1246 struct intel_overlay *overlay;
1247 struct overlay_registers *regs;
1251 DRM_ERROR("called with no initialization\n");
1255 overlay = dev_priv->overlay;
1257 DRM_DEBUG("userspace bug: no overlay\n");
1261 mutex_lock(&dev->mode_config.mutex);
1262 mutex_lock(&dev->struct_mutex);
1264 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
1265 attrs->color_key = overlay->color_key;
1266 attrs->brightness = overlay->brightness;
1267 attrs->contrast = overlay->contrast;
1268 attrs->saturation = overlay->saturation;
1271 attrs->gamma0 = I915_READ(OGAMC0);
1272 attrs->gamma1 = I915_READ(OGAMC1);
1273 attrs->gamma2 = I915_READ(OGAMC2);
1274 attrs->gamma3 = I915_READ(OGAMC3);
1275 attrs->gamma4 = I915_READ(OGAMC4);
1276 attrs->gamma5 = I915_READ(OGAMC5);
1280 overlay->color_key = attrs->color_key;
1281 if (attrs->brightness >= -128 && attrs->brightness <= 127) {
1282 overlay->brightness = attrs->brightness;
1287 if (attrs->contrast <= 255) {
1288 overlay->contrast = attrs->contrast;
1293 if (attrs->saturation <= 1023) {
1294 overlay->saturation = attrs->saturation;
1300 regs = intel_overlay_map_regs_atomic(overlay);
1306 update_reg_attrs(overlay, regs);
1308 intel_overlay_unmap_regs_atomic(overlay);
1310 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
1311 if (!IS_I9XX(dev)) {
1316 if (overlay->active) {
1321 ret = check_gamma(attrs);
1325 I915_WRITE(OGAMC0, attrs->gamma0);
1326 I915_WRITE(OGAMC1, attrs->gamma1);
1327 I915_WRITE(OGAMC2, attrs->gamma2);
1328 I915_WRITE(OGAMC3, attrs->gamma3);
1329 I915_WRITE(OGAMC4, attrs->gamma4);
1330 I915_WRITE(OGAMC5, attrs->gamma5);
1336 mutex_unlock(&dev->struct_mutex);
1337 mutex_unlock(&dev->mode_config.mutex);
1342 void intel_setup_overlay(struct drm_device *dev)
1344 drm_i915_private_t *dev_priv = dev->dev_private;
1345 struct intel_overlay *overlay;
1346 struct drm_gem_object *reg_bo;
1347 struct overlay_registers *regs;
1350 if (!OVERLAY_EXISTS(dev))
1353 overlay = kzalloc(sizeof(struct intel_overlay), GFP_KERNEL);
1358 reg_bo = i915_gem_alloc_object(dev, PAGE_SIZE);
1361 overlay->reg_bo = to_intel_bo(reg_bo);
1363 if (OVERLAY_NONPHYSICAL(dev)) {
1364 ret = i915_gem_object_pin(reg_bo, PAGE_SIZE);
1366 DRM_ERROR("failed to pin overlay register bo\n");
1369 overlay->flip_addr = overlay->reg_bo->gtt_offset;
1371 ret = i915_gem_attach_phys_object(dev, reg_bo,
1372 I915_GEM_PHYS_OVERLAY_REGS,
1375 DRM_ERROR("failed to attach phys overlay regs\n");
1378 overlay->flip_addr = overlay->reg_bo->phys_obj->handle->busaddr;
1381 /* init all values */
1382 overlay->color_key = 0x0101fe;
1383 overlay->brightness = -19;
1384 overlay->contrast = 75;
1385 overlay->saturation = 146;
1387 regs = intel_overlay_map_regs_atomic(overlay);
1391 memset(regs, 0, sizeof(struct overlay_registers));
1392 update_polyphase_filter(regs);
1394 update_reg_attrs(overlay, regs);
1396 intel_overlay_unmap_regs_atomic(overlay);
1398 dev_priv->overlay = overlay;
1399 DRM_INFO("initialized overlay support\n");
1403 drm_gem_object_unreference(reg_bo);
1409 void intel_cleanup_overlay(struct drm_device *dev)
1411 drm_i915_private_t *dev_priv = dev->dev_private;
1413 if (dev_priv->overlay) {
1414 /* The bo's should be free'd by the generic code already.
1415 * Furthermore modesetting teardown happens beforehand so the
1416 * hardware should be off already */
1417 BUG_ON(dev_priv->overlay->active);
1419 kfree(dev_priv->overlay);
1423 struct intel_overlay_error_state {
1424 struct overlay_registers regs;
1430 struct intel_overlay_error_state *
1431 intel_overlay_capture_error_state(struct drm_device *dev)
1433 drm_i915_private_t *dev_priv = dev->dev_private;
1434 struct intel_overlay *overlay = dev_priv->overlay;
1435 struct intel_overlay_error_state *error;
1436 struct overlay_registers __iomem *regs;
1438 if (!overlay || !overlay->active)
1441 error = kmalloc(sizeof(*error), GFP_ATOMIC);
1445 error->dovsta = I915_READ(DOVSTA);
1446 error->isr = I915_READ(ISR);
1447 if (OVERLAY_NONPHYSICAL(overlay->dev))
1448 error->base = (long) overlay->reg_bo->gtt_offset;
1450 error->base = (long) overlay->reg_bo->phys_obj->handle->vaddr;
1452 regs = intel_overlay_map_regs_atomic(overlay);
1456 memcpy_fromio(&error->regs, regs, sizeof(struct overlay_registers));
1457 intel_overlay_unmap_regs_atomic(overlay);
1467 intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error)
1469 seq_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1470 error->dovsta, error->isr);
1471 seq_printf(m, " Register file at 0x%08lx:\n",
1474 #define P(x) seq_printf(m, " " #x ": 0x%08x\n", error->regs.x)