drivers/gpu/drm/i915/intel_overlay.c

   1 /*
   2  * Copyright © 2009
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Daniel Vetter <daniel@ffwll.ch>
  25  *
  26  * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
  27  */
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "i915_drm.h"
  31 #include "i915_drv.h"
  32 #include "i915_reg.h"
  33 #include "intel_drv.h"
  34
  35 /* Limits for overlay size. According to intel doc, the real limits are:
  36  * Y width: 4095, UV width (planar): 2047, Y height: 2047,
  37  * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
  38  * the mininum of both.  */
  39 #define IMAGE_MAX_WIDTH         2048
  40 #define IMAGE_MAX_HEIGHT        2046 /* 2 * 1023 */
  41 /* on 830 and 845 these large limits result in the card hanging */
  42 #define IMAGE_MAX_WIDTH_LEGACY  1024
  43 #define IMAGE_MAX_HEIGHT_LEGACY 1088
  44
  45 /* overlay register definitions */
  46 /* OCMD register */
  47 #define OCMD_TILED_SURFACE      (0x1<<19)
  48 #define OCMD_MIRROR_MASK        (0x3<<17)
  49 #define OCMD_MIRROR_MODE        (0x3<<17)
  50 #define OCMD_MIRROR_HORIZONTAL  (0x1<<17)
  51 #define OCMD_MIRROR_VERTICAL    (0x2<<17)
  52 #define OCMD_MIRROR_BOTH        (0x3<<17)
  53 #define OCMD_BYTEORDER_MASK     (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
  54 #define OCMD_UV_SWAP            (0x1<<14) /* YVYU */
  55 #define OCMD_Y_SWAP             (0x2<<14) /* UYVY or FOURCC UYVY */
  56 #define OCMD_Y_AND_UV_SWAP      (0x3<<14) /* VYUY */
  57 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
  58 #define OCMD_RGB_888            (0x1<<10) /* not in i965 Intel docs */
  59 #define OCMD_RGB_555            (0x2<<10) /* not in i965 Intel docs */
  60 #define OCMD_RGB_565            (0x3<<10) /* not in i965 Intel docs */
  61 #define OCMD_YUV_422_PACKED     (0x8<<10)
  62 #define OCMD_YUV_411_PACKED     (0x9<<10) /* not in i965 Intel docs */
  63 #define OCMD_YUV_420_PLANAR     (0xc<<10)
  64 #define OCMD_YUV_422_PLANAR     (0xd<<10)
  65 #define OCMD_YUV_410_PLANAR     (0xe<<10) /* also 411 */
  66 #define OCMD_TVSYNCFLIP_PARITY  (0x1<<9)
  67 #define OCMD_TVSYNCFLIP_ENABLE  (0x1<<7)
  68 #define OCMD_BUF_TYPE_MASK      (0x1<<5)
  69 #define OCMD_BUF_TYPE_FRAME     (0x0<<5)
  70 #define OCMD_BUF_TYPE_FIELD     (0x1<<5)
  71 #define OCMD_TEST_MODE          (0x1<<4)
  72 #define OCMD_BUFFER_SELECT      (0x3<<2)
  73 #define OCMD_BUFFER0            (0x0<<2)
  74 #define OCMD_BUFFER1            (0x1<<2)
  75 #define OCMD_FIELD_SELECT       (0x1<<2)
  76 #define OCMD_FIELD0             (0x0<<1)
  77 #define OCMD_FIELD1             (0x1<<1)
  78 #define OCMD_ENABLE             (0x1<<0)
  79
  80 /* OCONFIG register */
  81 #define OCONF_PIPE_MASK         (0x1<<18)
  82 #define OCONF_PIPE_A            (0x0<<18)
  83 #define OCONF_PIPE_B            (0x1<<18)
  84 #define OCONF_GAMMA2_ENABLE     (0x1<<16)
  85 #define OCONF_CSC_MODE_BT601    (0x0<<5)
  86 #define OCONF_CSC_MODE_BT709    (0x1<<5)
  87 #define OCONF_CSC_BYPASS        (0x1<<4)
  88 #define OCONF_CC_OUT_8BIT       (0x1<<3)
  89 #define OCONF_TEST_MODE         (0x1<<2)
  90 #define OCONF_THREE_LINE_BUFFER (0x1<<0)
  91 #define OCONF_TWO_LINE_BUFFER   (0x0<<0)
  92
  93 /* DCLRKM (dst-key) register */
  94 #define DST_KEY_ENABLE          (0x1<<31)
  95 #define CLK_RGB24_MASK          0x0
  96 #define CLK_RGB16_MASK          0x070307
  97 #define CLK_RGB15_MASK          0x070707
  98 #define CLK_RGB8I_MASK          0xffffff
  99
 100 #define RGB16_TO_COLORKEY(c) \
 101         (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
 102 #define RGB15_TO_COLORKEY(c) \
 103         (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
 104
 105 /* overlay flip addr flag */
 106 #define OFC_UPDATE              0x1
 107
 108 /* polyphase filter coefficients */
 109 #define N_HORIZ_Y_TAPS          5
 110 #define N_VERT_Y_TAPS           3
 111 #define N_HORIZ_UV_TAPS         3
 112 #define N_VERT_UV_TAPS          3
 113 #define N_PHASES                17
 114 #define MAX_TAPS                5
 115
 116 /* memory bufferd overlay registers */
 117 struct overlay_registers {
 118         u32 OBUF_0Y;
 119         u32 OBUF_1Y;
 120         u32 OBUF_0U;
 121         u32 OBUF_0V;
 122         u32 OBUF_1U;
 123         u32 OBUF_1V;
 124         u32 OSTRIDE;
 125         u32 YRGB_VPH;
 126         u32 UV_VPH;
 127         u32 HORZ_PH;
 128         u32 INIT_PHS;
 129         u32 DWINPOS;
 130         u32 DWINSZ;
 131         u32 SWIDTH;
 132         u32 SWIDTHSW;
 133         u32 SHEIGHT;
 134         u32 YRGBSCALE;
 135         u32 UVSCALE;
 136         u32 OCLRC0;
 137         u32 OCLRC1;
 138         u32 DCLRKV;
 139         u32 DCLRKM;
 140         u32 SCLRKVH;
 141         u32 SCLRKVL;
 142         u32 SCLRKEN;
 143         u32 OCONFIG;
 144         u32 OCMD;
 145         u32 RESERVED1; /* 0x6C */
 146         u32 OSTART_0Y;
 147         u32 OSTART_1Y;
 148         u32 OSTART_0U;
 149         u32 OSTART_0V;
 150         u32 OSTART_1U;
 151         u32 OSTART_1V;
 152         u32 OTILEOFF_0Y;
 153         u32 OTILEOFF_1Y;
 154         u32 OTILEOFF_0U;
 155         u32 OTILEOFF_0V;
 156         u32 OTILEOFF_1U;
 157         u32 OTILEOFF_1V;
 158         u32 FASTHSCALE; /* 0xA0 */
 159         u32 UVSCALEV; /* 0xA4 */
 160         u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
 161         u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
 162         u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
 163         u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
 164         u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
 165         u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
 166         u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
 167         u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
 168         u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
 169 };
 170
 171 struct intel_overlay {
 172         struct drm_device *dev;
 173         struct intel_crtc *crtc;
 174         struct drm_i915_gem_object *vid_bo;
 175         struct drm_i915_gem_object *old_vid_bo;
 176         int active;
 177         int pfit_active;
 178         u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
 179         u32 color_key;
 180         u32 brightness, contrast, saturation;
 181         u32 old_xscale, old_yscale;
 182         /* register access */
 183         u32 flip_addr;
 184         struct drm_i915_gem_object *reg_bo;
 185         /* flip handling */
 186         uint32_t last_flip_req;
 187         void (*flip_tail)(struct intel_overlay *);
 188 };
 189
 190 static struct overlay_registers __iomem *
 191 intel_overlay_map_regs(struct intel_overlay *overlay)
 192 {
 193         drm_i915_private_t *dev_priv = overlay->dev->dev_private;
 194         struct overlay_registers __iomem *regs;
 195
 196         if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
 197                 regs = (struct overlay_registers __iomem *)overlay->reg_bo->phys_obj->handle->vaddr;
 198         else
 199                 regs = io_mapping_map_wc(dev_priv->mm.gtt_mapping,
 200                                          overlay->reg_bo->gtt_offset);
 201
 202         return regs;
 203 }
 204
 205 static void intel_overlay_unmap_regs(struct intel_overlay *overlay,
 206                                      struct overlay_registers __iomem *regs)
 207 {
 208         if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
 209                 io_mapping_unmap(regs);
 210 }
 211
 212 static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
 213                                          struct drm_i915_gem_request *request,
 214                                          void (*tail)(struct intel_overlay *))
 215 {
 216         struct drm_device *dev = overlay->dev;
 217         drm_i915_private_t *dev_priv = dev->dev_private;
 218         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
 219         int ret;
 220
 221         BUG_ON(overlay->last_flip_req);
 222         ret = i915_add_request(ring, NULL, request);
 223         if (ret) {
 224             kfree(request);
 225             return ret;
 226         }
 227         overlay->last_flip_req = request->seqno;
 228         overlay->flip_tail = tail;
 229         ret = i915_wait_request(ring, overlay->last_flip_req);
 230         if (ret)
 231                 return ret;
 232         i915_gem_retire_requests(dev);
 233
 234         overlay->last_flip_req = 0;
 235         return 0;
 236 }
 237
 238 /* Workaround for i830 bug where pipe a must be enable to change control regs */
 239 static int
 240 i830_activate_pipe_a(struct drm_device *dev)
 241 {
 242         drm_i915_private_t *dev_priv = dev->dev_private;
 243         struct intel_crtc *crtc;
 244         struct drm_crtc_helper_funcs *crtc_funcs;
 245         struct drm_display_mode vesa_640x480 = {
 246                 DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
 247                          752, 800, 0, 480, 489, 492, 525, 0,
 248                          DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)
 249         }, *mode;
 250
 251         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[0]);
 252         if (crtc->dpms_mode == DRM_MODE_DPMS_ON)
 253                 return 0;
 254
 255         /* most i8xx have pipe a forced on, so don't trust dpms mode */
 256         if (I915_READ(_PIPEACONF) & PIPECONF_ENABLE)
 257                 return 0;
 258
 259         crtc_funcs = crtc->base.helper_private;
 260         if (crtc_funcs->dpms == NULL)
 261                 return 0;
 262
 263         DRM_DEBUG_DRIVER("Enabling pipe A in order to enable overlay\n");
 264
 265         mode = drm_mode_duplicate(dev, &vesa_640x480);
 266
 267         if (!drm_crtc_helper_set_mode(&crtc->base, mode,
 268                                        crtc->base.x, crtc->base.y,
 269                                        crtc->base.fb))
 270                 return 0;
 271
 272         crtc_funcs->dpms(&crtc->base, DRM_MODE_DPMS_ON);
 273         return 1;
 274 }
 275
 276 static void
 277 i830_deactivate_pipe_a(struct drm_device *dev)
 278 {
 279         drm_i915_private_t *dev_priv = dev->dev_private;
 280         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[0];
 281         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
 282
 283         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
 284 }
 285
 286 /* overlay needs to be disable in OCMD reg */
 287 static int intel_overlay_on(struct intel_overlay *overlay)
 288 {
 289         struct drm_device *dev = overlay->dev;
 290         struct drm_i915_private *dev_priv = dev->dev_private;
 291         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
 292         struct drm_i915_gem_request *request;
 293         int pipe_a_quirk = 0;
 294         int ret;
 295
 296         BUG_ON(overlay->active);
 297         overlay->active = 1;
 298
 299         if (IS_I830(dev)) {
 300                 pipe_a_quirk = i830_activate_pipe_a(dev);
 301                 if (pipe_a_quirk < 0)
 302                         return pipe_a_quirk;
 303         }
 304
 305         request = kzalloc(sizeof(*request), GFP_KERNEL);
 306         if (request == NULL) {
 307                 ret = -ENOMEM;
 308                 goto out;
 309         }
 310
 311         ret = intel_ring_begin(ring, 4);
 312         if (ret) {
 313                 kfree(request);
 314                 goto out;
 315         }
 316
 317         intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_ON);
 318         intel_ring_emit(ring, overlay->flip_addr | OFC_UPDATE);
 319         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
 320         intel_ring_emit(ring, MI_NOOP);
 321         intel_ring_advance(ring);
 322
 323         ret = intel_overlay_do_wait_request(overlay, request, NULL);
 324 out:
 325         if (pipe_a_quirk)
 326                 i830_deactivate_pipe_a(dev);
 327
 328         return ret;
 329 }
 330
 331 /* overlay needs to be enabled in OCMD reg */
 332 static int intel_overlay_continue(struct intel_overlay *overlay,
 333                                   bool load_polyphase_filter)
 334 {
 335         struct drm_device *dev = overlay->dev;
 336         drm_i915_private_t *dev_priv = dev->dev_private;
 337         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
 338         struct drm_i915_gem_request *request;
 339         u32 flip_addr = overlay->flip_addr;
 340         u32 tmp;
 341         int ret;
 342
 343         BUG_ON(!overlay->active);
 344
 345         request = kzalloc(sizeof(*request), GFP_KERNEL);
 346         if (request == NULL)
 347                 return -ENOMEM;
 348
 349         if (load_polyphase_filter)
 350                 flip_addr |= OFC_UPDATE;
 351
 352         /* check for underruns */
 353         tmp = I915_READ(DOVSTA);
 354         if (tmp & (1 << 17))
 355                 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
 356
 357         ret = intel_ring_begin(ring, 2);
 358         if (ret) {
 359                 kfree(request);
 360                 return ret;
 361         }
 362         intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
 363         intel_ring_emit(ring, flip_addr);
 364         intel_ring_advance(ring);
 365
 366         ret = i915_add_request(ring, NULL, request);
 367         if (ret) {
 368                 kfree(request);
 369                 return ret;
 370         }
 371
 372         overlay->last_flip_req = request->seqno;
 373         return 0;
 374 }
 375
 376 static void intel_overlay_release_old_vid_tail(struct intel_overlay *overlay)
 377 {
 378         struct drm_i915_gem_object *obj = overlay->old_vid_bo;
 379
 380         i915_gem_object_unpin(obj);
 381         drm_gem_object_unreference(&obj->base);
 382
 383         overlay->old_vid_bo = NULL;
 384 }
 385
 386 static void intel_overlay_off_tail(struct intel_overlay *overlay)
 387 {
 388         struct drm_i915_gem_object *obj = overlay->vid_bo;
 389
 390         /* never have the overlay hw on without showing a frame */
 391         BUG_ON(!overlay->vid_bo);
 392
 393         i915_gem_object_unpin(obj);
 394         drm_gem_object_unreference(&obj->base);
 395         overlay->vid_bo = NULL;
 396
 397         overlay->crtc->overlay = NULL;
 398         overlay->crtc = NULL;
 399         overlay->active = 0;
 400 }
 401
 402 /* overlay needs to be disabled in OCMD reg */
 403 static int intel_overlay_off(struct intel_overlay *overlay)
 404 {
 405         struct drm_device *dev = overlay->dev;
 406         struct drm_i915_private *dev_priv = dev->dev_private;
 407         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
 408         u32 flip_addr = overlay->flip_addr;
 409         struct drm_i915_gem_request *request;
 410         int ret;
 411
 412         BUG_ON(!overlay->active);
 413
 414         request = kzalloc(sizeof(*request), GFP_KERNEL);
 415         if (request == NULL)
 416                 return -ENOMEM;
 417
 418         /* According to intel docs the overlay hw may hang (when switching
 419          * off) without loading the filter coeffs. It is however unclear whether
 420          * this applies to the disabling of the overlay or to the switching off
 421          * of the hw. Do it in both cases */
 422         flip_addr |= OFC_UPDATE;
 423
 424         ret = intel_ring_begin(ring, 6);
 425         if (ret) {
 426                 kfree(request);
 427                 return ret;
 428         }
 429         /* wait for overlay to go idle */
 430         intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
 431         intel_ring_emit(ring, flip_addr);
 432         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
 433         /* turn overlay off */
 434         intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
 435         intel_ring_emit(ring, flip_addr);
 436         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
 437         intel_ring_advance(ring);
 438
 439         return intel_overlay_do_wait_request(overlay, request,
 440                                              intel_overlay_off_tail);
 441 }
 442
 443 /* recover from an interruption due to a signal
 444  * We have to be careful not to repeat work forever an make forward progess. */
 445 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay)
 446 {
 447         struct drm_device *dev = overlay->dev;
 448         drm_i915_private_t *dev_priv = dev->dev_private;
 449         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
 450         int ret;
 451
 452         if (overlay->last_flip_req == 0)
 453                 return 0;
 454
 455         ret = i915_wait_request(ring, overlay->last_flip_req);
 456         if (ret)
 457                 return ret;
 458         i915_gem_retire_requests(dev);
 459
 460         if (overlay->flip_tail)
 461                 overlay->flip_tail(overlay);
 462
 463         overlay->last_flip_req = 0;
 464         return 0;
 465 }
 466
 467 /* Wait for pending overlay flip and release old frame.
 468  * Needs to be called before the overlay register are changed
 469  * via intel_overlay_(un)map_regs
 470  */
 471 static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
 472 {
 473         struct drm_device *dev = overlay->dev;
 474         drm_i915_private_t *dev_priv = dev->dev_private;
 475         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
 476         int ret;
 477
 478         /* Only wait if there is actually an old frame to release to
 479          * guarantee forward progress.
 480          */
 481         if (!overlay->old_vid_bo)
 482                 return 0;
 483
 484         if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) {
 485                 struct drm_i915_gem_request *request;
 486
 487                 /* synchronous slowpath */
 488                 request = kzalloc(sizeof(*request), GFP_KERNEL);
 489                 if (request == NULL)
 490                         return -ENOMEM;
 491
 492                 ret = intel_ring_begin(ring, 2);
 493                 if (ret) {
 494                         kfree(request);
 495                         return ret;
 496                 }
 497
 498                 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
 499                 intel_ring_emit(ring, MI_NOOP);
 500                 intel_ring_advance(ring);
 501
 502                 ret = intel_overlay_do_wait_request(overlay, request,
 503                                                     intel_overlay_release_old_vid_tail);
 504                 if (ret)
 505                         return ret;
 506         }
 507
 508         intel_overlay_release_old_vid_tail(overlay);
 509         return 0;
 510 }
 511
 512 struct put_image_params {
 513         int format;
 514         short dst_x;
 515         short dst_y;
 516         short dst_w;
 517         short dst_h;
 518         short src_w;
 519         short src_scan_h;
 520         short src_scan_w;
 521         short src_h;
 522         short stride_Y;
 523         short stride_UV;
 524         int offset_Y;
 525         int offset_U;
 526         int offset_V;
 527 };
 528
 529 static int packed_depth_bytes(u32 format)
 530 {
 531         switch (format & I915_OVERLAY_DEPTH_MASK) {
 532         case I915_OVERLAY_YUV422:
 533                 return 4;
 534         case I915_OVERLAY_YUV411:
 535                 /* return 6; not implemented */
 536         default:
 537                 return -EINVAL;
 538         }
 539 }
 540
 541 static int packed_width_bytes(u32 format, short width)
 542 {
 543         switch (format & I915_OVERLAY_DEPTH_MASK) {
 544         case I915_OVERLAY_YUV422:
 545                 return width << 1;
 546         default:
 547                 return -EINVAL;
 548         }
 549 }
 550
 551 static int uv_hsubsampling(u32 format)
 552 {
 553         switch (format & I915_OVERLAY_DEPTH_MASK) {
 554         case I915_OVERLAY_YUV422:
 555         case I915_OVERLAY_YUV420:
 556                 return 2;
 557         case I915_OVERLAY_YUV411:
 558         case I915_OVERLAY_YUV410:
 559                 return 4;
 560         default:
 561                 return -EINVAL;
 562         }
 563 }
 564
 565 static int uv_vsubsampling(u32 format)
 566 {
 567         switch (format & I915_OVERLAY_DEPTH_MASK) {
 568         case I915_OVERLAY_YUV420:
 569         case I915_OVERLAY_YUV410:
 570                 return 2;
 571         case I915_OVERLAY_YUV422:
 572         case I915_OVERLAY_YUV411:
 573                 return 1;
 574         default:
 575                 return -EINVAL;
 576         }
 577 }
 578
 579 static u32 calc_swidthsw(struct drm_device *dev, u32 offset, u32 width)
 580 {
 581         u32 mask, shift, ret;
 582         if (IS_GEN2(dev)) {
 583                 mask = 0x1f;
 584                 shift = 5;
 585         } else {
 586                 mask = 0x3f;
 587                 shift = 6;
 588         }
 589         ret = ((offset + width + mask) >> shift) - (offset >> shift);
 590         if (!IS_GEN2(dev))
 591                 ret <<= 1;
 592         ret -= 1;
 593         return ret << 2;
 594 }
 595
 596 static const u16 y_static_hcoeffs[N_HORIZ_Y_TAPS * N_PHASES] = {
 597         0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
 598         0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
 599         0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
 600         0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
 601         0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
 602         0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
 603         0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
 604         0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
 605         0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
 606         0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
 607         0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
 608         0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
 609         0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
 610         0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
 611         0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
 612         0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
 613         0xb000, 0x3000, 0x0800, 0x3000, 0xb000
 614 };
 615
 616 static const u16 uv_static_hcoeffs[N_HORIZ_UV_TAPS * N_PHASES] = {
 617         0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
 618         0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
 619         0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
 620         0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
 621         0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
 622         0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
 623         0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
 624         0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
 625         0x3000, 0x0800, 0x3000
 626 };
 627
 628 static void update_polyphase_filter(struct overlay_registers __iomem *regs)
 629 {
 630         memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
 631         memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs,
 632                     sizeof(uv_static_hcoeffs));
 633 }
 634
 635 static bool update_scaling_factors(struct intel_overlay *overlay,
 636                                    struct overlay_registers __iomem *regs,
 637                                    struct put_image_params *params)
 638 {
 639         /* fixed point with a 12 bit shift */
 640         u32 xscale, yscale, xscale_UV, yscale_UV;
 641 #define FP_SHIFT 12
 642 #define FRACT_MASK 0xfff
 643         bool scale_changed = false;
 644         int uv_hscale = uv_hsubsampling(params->format);
 645         int uv_vscale = uv_vsubsampling(params->format);
 646
 647         if (params->dst_w > 1)
 648                 xscale = ((params->src_scan_w - 1) << FP_SHIFT)
 649                         /(params->dst_w);
 650         else
 651                 xscale = 1 << FP_SHIFT;
 652
 653         if (params->dst_h > 1)
 654                 yscale = ((params->src_scan_h - 1) << FP_SHIFT)
 655                         /(params->dst_h);
 656         else
 657                 yscale = 1 << FP_SHIFT;
 658
 659         /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
 660         xscale_UV = xscale/uv_hscale;
 661         yscale_UV = yscale/uv_vscale;
 662         /* make the Y scale to UV scale ratio an exact multiply */
 663         xscale = xscale_UV * uv_hscale;
 664         yscale = yscale_UV * uv_vscale;
 665         /*} else {
 666           xscale_UV = 0;
 667           yscale_UV = 0;
 668           }*/
 669
 670         if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
 671                 scale_changed = true;
 672         overlay->old_xscale = xscale;
 673         overlay->old_yscale = yscale;
 674
 675         iowrite32(((yscale & FRACT_MASK) << 20) |
 676                   ((xscale >> FP_SHIFT)  << 16) |
 677                   ((xscale & FRACT_MASK) << 3),
 678                  &regs->YRGBSCALE);
 679
 680         iowrite32(((yscale_UV & FRACT_MASK) << 20) |
 681                   ((xscale_UV >> FP_SHIFT)  << 16) |
 682                   ((xscale_UV & FRACT_MASK) << 3),
 683                  &regs->UVSCALE);
 684
 685         iowrite32((((yscale    >> FP_SHIFT) << 16) |
 686                    ((yscale_UV >> FP_SHIFT) << 0)),
 687                  &regs->UVSCALEV);
 688
 689         if (scale_changed)
 690                 update_polyphase_filter(regs);
 691
 692         return scale_changed;
 693 }
 694
 695 static void update_colorkey(struct intel_overlay *overlay,
 696                             struct overlay_registers __iomem *regs)
 697 {
 698         u32 key = overlay->color_key;
 699
 700         switch (overlay->crtc->base.fb->bits_per_pixel) {
 701         case 8:
 702                 iowrite32(0, &regs->DCLRKV);
 703                 iowrite32(CLK_RGB8I_MASK | DST_KEY_ENABLE, &regs->DCLRKM);
 704                 break;
 705
 706         case 16:
 707                 if (overlay->crtc->base.fb->depth == 15) {
 708                         iowrite32(RGB15_TO_COLORKEY(key), &regs->DCLRKV);
 709                         iowrite32(CLK_RGB15_MASK | DST_KEY_ENABLE,
 710                                   &regs->DCLRKM);
 711                 } else {
 712                         iowrite32(RGB16_TO_COLORKEY(key), &regs->DCLRKV);
 713                         iowrite32(CLK_RGB16_MASK | DST_KEY_ENABLE,
 714                                   &regs->DCLRKM);
 715                 }
 716                 break;
 717
 718         case 24:
 719         case 32:
 720                 iowrite32(key, &regs->DCLRKV);
 721                 iowrite32(CLK_RGB24_MASK | DST_KEY_ENABLE, &regs->DCLRKM);
 722                 break;
 723         }
 724 }
 725
 726 static u32 overlay_cmd_reg(struct put_image_params *params)
 727 {
 728         u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
 729
 730         if (params->format & I915_OVERLAY_YUV_PLANAR) {
 731                 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
 732                 case I915_OVERLAY_YUV422:
 733                         cmd |= OCMD_YUV_422_PLANAR;
 734                         break;
 735                 case I915_OVERLAY_YUV420:
 736                         cmd |= OCMD_YUV_420_PLANAR;
 737                         break;
 738                 case I915_OVERLAY_YUV411:
 739                 case I915_OVERLAY_YUV410:
 740                         cmd |= OCMD_YUV_410_PLANAR;
 741                         break;
 742                 }
 743         } else { /* YUV packed */
 744                 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
 745                 case I915_OVERLAY_YUV422:
 746                         cmd |= OCMD_YUV_422_PACKED;
 747                         break;
 748                 case I915_OVERLAY_YUV411:
 749                         cmd |= OCMD_YUV_411_PACKED;
 750                         break;
 751                 }
 752
 753                 switch (params->format & I915_OVERLAY_SWAP_MASK) {
 754                 case I915_OVERLAY_NO_SWAP:
 755                         break;
 756                 case I915_OVERLAY_UV_SWAP:
 757                         cmd |= OCMD_UV_SWAP;
 758                         break;
 759                 case I915_OVERLAY_Y_SWAP:
 760                         cmd |= OCMD_Y_SWAP;
 761                         break;
 762                 case I915_OVERLAY_Y_AND_UV_SWAP:
 763                         cmd |= OCMD_Y_AND_UV_SWAP;
 764                         break;
 765                 }
 766         }
 767
 768         return cmd;
 769 }
 770
 771 static int intel_overlay_do_put_image(struct intel_overlay *overlay,
 772                                       struct drm_i915_gem_object *new_bo,
 773                                       struct put_image_params *params)
 774 {
 775         int ret, tmp_width;
 776         struct overlay_registers __iomem *regs;
 777         bool scale_changed = false;
 778         struct drm_device *dev = overlay->dev;
 779         u32 swidth, swidthsw, sheight, ostride;
 780
 781         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
 782         BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
 783         BUG_ON(!overlay);
 784
 785         ret = intel_overlay_release_old_vid(overlay);
 786         if (ret != 0)
 787                 return ret;
 788
 789         ret = i915_gem_object_pin_to_display_plane(new_bo, 0, NULL);
 790         if (ret != 0)
 791                 return ret;
 792
 793         ret = i915_gem_object_put_fence(new_bo);
 794         if (ret)
 795                 goto out_unpin;
 796
 797         if (!overlay->active) {
 798                 u32 oconfig;
 799                 regs = intel_overlay_map_regs(overlay);
 800                 if (!regs) {
 801                         ret = -ENOMEM;
 802                         goto out_unpin;
 803                 }
 804                 oconfig = OCONF_CC_OUT_8BIT;
 805                 if (IS_GEN4(overlay->dev))
 806                         oconfig |= OCONF_CSC_MODE_BT709;
 807                 oconfig |= overlay->crtc->pipe == 0 ?
 808                         OCONF_PIPE_A : OCONF_PIPE_B;
 809                 iowrite32(oconfig, &regs->OCONFIG);
 810                 intel_overlay_unmap_regs(overlay, regs);
 811
 812                 ret = intel_overlay_on(overlay);
 813                 if (ret != 0)
 814                         goto out_unpin;
 815         }
 816
 817         regs = intel_overlay_map_regs(overlay);
 818         if (!regs) {
 819                 ret = -ENOMEM;
 820                 goto out_unpin;
 821         }
 822
 823         iowrite32((params->dst_y << 16) | params->dst_x, &regs->DWINPOS);
 824         iowrite32((params->dst_h << 16) | params->dst_w, &regs->DWINSZ);
 825
 826         if (params->format & I915_OVERLAY_YUV_PACKED)
 827                 tmp_width = packed_width_bytes(params->format, params->src_w);
 828         else
 829                 tmp_width = params->src_w;
 830
 831         swidth = params->src_w;
 832         swidthsw = calc_swidthsw(overlay->dev, params->offset_Y, tmp_width);
 833         sheight = params->src_h;
 834         iowrite32(new_bo->gtt_offset + params->offset_Y, &regs->OBUF_0Y);
 835         ostride = params->stride_Y;
 836
 837         if (params->format & I915_OVERLAY_YUV_PLANAR) {
 838                 int uv_hscale = uv_hsubsampling(params->format);
 839                 int uv_vscale = uv_vsubsampling(params->format);
 840                 u32 tmp_U, tmp_V;
 841                 swidth |= (params->src_w/uv_hscale) << 16;
 842                 tmp_U = calc_swidthsw(overlay->dev, params->offset_U,
 843                                       params->src_w/uv_hscale);
 844                 tmp_V = calc_swidthsw(overlay->dev, params->offset_V,
 845                                       params->src_w/uv_hscale);
 846                 swidthsw |= max_t(u32, tmp_U, tmp_V) << 16;
 847                 sheight |= (params->src_h/uv_vscale) << 16;
 848                 iowrite32(new_bo->gtt_offset + params->offset_U, &regs->OBUF_0U);
 849                 iowrite32(new_bo->gtt_offset + params->offset_V, &regs->OBUF_0V);
 850                 ostride |= params->stride_UV << 16;
 851         }
 852
 853         iowrite32(swidth, &regs->SWIDTH);
 854         iowrite32(swidthsw, &regs->SWIDTHSW);
 855         iowrite32(sheight, &regs->SHEIGHT);
 856         iowrite32(ostride, &regs->OSTRIDE);
 857
 858         scale_changed = update_scaling_factors(overlay, regs, params);
 859
 860         update_colorkey(overlay, regs);
 861
 862         iowrite32(overlay_cmd_reg(params), &regs->OCMD);
 863
 864         intel_overlay_unmap_regs(overlay, regs);
 865
 866         ret = intel_overlay_continue(overlay, scale_changed);
 867         if (ret)
 868                 goto out_unpin;
 869
 870         overlay->old_vid_bo = overlay->vid_bo;
 871         overlay->vid_bo = new_bo;
 872
 873         return 0;
 874
 875 out_unpin:
 876         i915_gem_object_unpin(new_bo);
 877         return ret;
 878 }
 879
 880 int intel_overlay_switch_off(struct intel_overlay *overlay)
 881 {
 882         struct overlay_registers __iomem *regs;
 883         struct drm_device *dev = overlay->dev;
 884         int ret;
 885
 886         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
 887         BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
 888
 889         ret = intel_overlay_recover_from_interrupt(overlay);
 890         if (ret != 0)
 891                 return ret;
 892
 893         if (!overlay->active)
 894                 return 0;
 895
 896         ret = intel_overlay_release_old_vid(overlay);
 897         if (ret != 0)
 898                 return ret;
 899
 900         regs = intel_overlay_map_regs(overlay);
 901         iowrite32(0, &regs->OCMD);
 902         intel_overlay_unmap_regs(overlay, regs);
 903
 904         ret = intel_overlay_off(overlay);
 905         if (ret != 0)
 906                 return ret;
 907
 908         intel_overlay_off_tail(overlay);
 909         return 0;
 910 }
 911
 912 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
 913                                           struct intel_crtc *crtc)
 914 {
 915         drm_i915_private_t *dev_priv = overlay->dev->dev_private;
 916
 917         if (!crtc->active)
 918                 return -EINVAL;
 919
 920         /* can't use the overlay with double wide pipe */
 921         if (INTEL_INFO(overlay->dev)->gen < 4 &&
 922             (I915_READ(PIPECONF(crtc->pipe)) & (PIPECONF_DOUBLE_WIDE | PIPECONF_ENABLE)) != PIPECONF_ENABLE)
 923                 return -EINVAL;
 924
 925         return 0;
 926 }
 927
 928 static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
 929 {
 930         struct drm_device *dev = overlay->dev;
 931         drm_i915_private_t *dev_priv = dev->dev_private;
 932         u32 pfit_control = I915_READ(PFIT_CONTROL);
 933         u32 ratio;
 934
 935         /* XXX: This is not the same logic as in the xorg driver, but more in
 936          * line with the intel documentation for the i965
 937          */
 938         if (INTEL_INFO(dev)->gen >= 4) {
 939                 /* on i965 use the PGM reg to read out the autoscaler values */
 940                 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
 941         } else {
 942                 if (pfit_control & VERT_AUTO_SCALE)
 943                         ratio = I915_READ(PFIT_AUTO_RATIOS);
 944                 else
 945                         ratio = I915_READ(PFIT_PGM_RATIOS);
 946                 ratio >>= PFIT_VERT_SCALE_SHIFT;
 947         }
 948
 949         overlay->pfit_vscale_ratio = ratio;
 950 }
 951
 952 static int check_overlay_dst(struct intel_overlay *overlay,
 953                              struct drm_intel_overlay_put_image *rec)
 954 {
 955         struct drm_display_mode *mode = &overlay->crtc->base.mode;
 956
 957         if (rec->dst_x < mode->hdisplay &&
 958             rec->dst_x + rec->dst_width <= mode->hdisplay &&
 959             rec->dst_y < mode->vdisplay &&
 960             rec->dst_y + rec->dst_height <= mode->vdisplay)
 961                 return 0;
 962         else
 963                 return -EINVAL;
 964 }
 965
 966 static int check_overlay_scaling(struct put_image_params *rec)
 967 {
 968         u32 tmp;
 969
 970         /* downscaling limit is 8.0 */
 971         tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16;
 972         if (tmp > 7)
 973                 return -EINVAL;
 974         tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16;
 975         if (tmp > 7)
 976                 return -EINVAL;
 977
 978         return 0;
 979 }
 980
 981 static int check_overlay_src(struct drm_device *dev,
 982                              struct drm_intel_overlay_put_image *rec,
 983                              struct drm_i915_gem_object *new_bo)
 984 {
 985         int uv_hscale = uv_hsubsampling(rec->flags);
 986         int uv_vscale = uv_vsubsampling(rec->flags);
 987         u32 stride_mask;
 988         int depth;
 989         u32 tmp;
 990
 991         /* check src dimensions */
 992         if (IS_845G(dev) || IS_I830(dev)) {
 993                 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
 994                     rec->src_width  > IMAGE_MAX_WIDTH_LEGACY)
 995                         return -EINVAL;
 996         } else {
 997                 if (rec->src_height > IMAGE_MAX_HEIGHT ||
 998                     rec->src_width  > IMAGE_MAX_WIDTH)
 999                         return -EINVAL;
1000         }
1001
1002         /* better safe than sorry, use 4 as the maximal subsampling ratio */
1003         if (rec->src_height < N_VERT_Y_TAPS*4 ||
1004             rec->src_width  < N_HORIZ_Y_TAPS*4)
1005                 return -EINVAL;
1006
1007         /* check alignment constraints */
1008         switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
1009         case I915_OVERLAY_RGB:
1010                 /* not implemented */
1011                 return -EINVAL;
1012
1013         case I915_OVERLAY_YUV_PACKED:
1014                 if (uv_vscale != 1)
1015                         return -EINVAL;
1016
1017                 depth = packed_depth_bytes(rec->flags);
1018                 if (depth < 0)
1019                         return depth;
1020
1021                 /* ignore UV planes */
1022                 rec->stride_UV = 0;
1023                 rec->offset_U = 0;
1024                 rec->offset_V = 0;
1025                 /* check pixel alignment */
1026                 if (rec->offset_Y % depth)
1027                         return -EINVAL;
1028                 break;
1029
1030         case I915_OVERLAY_YUV_PLANAR:
1031                 if (uv_vscale < 0 || uv_hscale < 0)
1032                         return -EINVAL;
1033                 /* no offset restrictions for planar formats */
1034                 break;
1035
1036         default:
1037                 return -EINVAL;
1038         }
1039
1040         if (rec->src_width % uv_hscale)
1041                 return -EINVAL;
1042
1043         /* stride checking */
1044         if (IS_I830(dev) || IS_845G(dev))
1045                 stride_mask = 255;
1046         else
1047                 stride_mask = 63;
1048
1049         if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
1050                 return -EINVAL;
1051         if (IS_GEN4(dev) && rec->stride_Y < 512)
1052                 return -EINVAL;
1053
1054         tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
1055                 4096 : 8192;
1056         if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
1057                 return -EINVAL;
1058
1059         /* check buffer dimensions */
1060         switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
1061         case I915_OVERLAY_RGB:
1062         case I915_OVERLAY_YUV_PACKED:
1063                 /* always 4 Y values per depth pixels */
1064                 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
1065                         return -EINVAL;
1066
1067                 tmp = rec->stride_Y*rec->src_height;
1068                 if (rec->offset_Y + tmp > new_bo->base.size)
1069                         return -EINVAL;
1070                 break;
1071
1072         case I915_OVERLAY_YUV_PLANAR:
1073                 if (rec->src_width > rec->stride_Y)
1074                         return -EINVAL;
1075                 if (rec->src_width/uv_hscale > rec->stride_UV)
1076                         return -EINVAL;
1077
1078                 tmp = rec->stride_Y * rec->src_height;
1079                 if (rec->offset_Y + tmp > new_bo->base.size)
1080                         return -EINVAL;
1081
1082                 tmp = rec->stride_UV * (rec->src_height / uv_vscale);
1083                 if (rec->offset_U + tmp > new_bo->base.size ||
1084                     rec->offset_V + tmp > new_bo->base.size)
1085                         return -EINVAL;
1086                 break;
1087         }
1088
1089         return 0;
1090 }
1091
1092 /**
1093  * Return the pipe currently connected to the panel fitter,
1094  * or -1 if the panel fitter is not present or not in use
1095  */
1096 static int intel_panel_fitter_pipe(struct drm_device *dev)
1097 {
1098         struct drm_i915_private *dev_priv = dev->dev_private;
1099         u32  pfit_control;
1100
1101         /* i830 doesn't have a panel fitter */
1102         if (IS_I830(dev))
1103                 return -1;
1104
1105         pfit_control = I915_READ(PFIT_CONTROL);
1106
1107         /* See if the panel fitter is in use */
1108         if ((pfit_control & PFIT_ENABLE) == 0)
1109                 return -1;
1110
1111         /* 965 can place panel fitter on either pipe */
1112         if (IS_GEN4(dev))
1113                 return (pfit_control >> 29) & 0x3;
1114
1115         /* older chips can only use pipe 1 */
1116         return 1;
1117 }
1118
1119 int intel_overlay_put_image(struct drm_device *dev, void *data,
1120                             struct drm_file *file_priv)
1121 {
1122         struct drm_intel_overlay_put_image *put_image_rec = data;
1123         drm_i915_private_t *dev_priv = dev->dev_private;
1124         struct intel_overlay *overlay;
1125         struct drm_mode_object *drmmode_obj;
1126         struct intel_crtc *crtc;
1127         struct drm_i915_gem_object *new_bo;
1128         struct put_image_params *params;
1129         int ret;
1130
1131         /* No need to check for DRIVER_MODESET - we don't set it up then. */
1132         overlay = dev_priv->overlay;
1133         if (!overlay) {
1134                 DRM_DEBUG("userspace bug: no overlay\n");
1135                 return -ENODEV;
1136         }
1137
1138         if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) {
1139                 mutex_lock(&dev->mode_config.mutex);
1140                 mutex_lock(&dev->struct_mutex);
1141
1142                 ret = intel_overlay_switch_off(overlay);
1143
1144                 mutex_unlock(&dev->struct_mutex);
1145                 mutex_unlock(&dev->mode_config.mutex);
1146
1147                 return ret;
1148         }
1149
1150         params = kmalloc(sizeof(struct put_image_params), GFP_KERNEL);
1151         if (!params)
1152                 return -ENOMEM;
1153
1154         drmmode_obj = drm_mode_object_find(dev, put_image_rec->crtc_id,
1155                                            DRM_MODE_OBJECT_CRTC);
1156         if (!drmmode_obj) {
1157                 ret = -ENOENT;
1158                 goto out_free;
1159         }
1160         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
1161
1162         new_bo = to_intel_bo(drm_gem_object_lookup(dev, file_priv,
1163                                                    put_image_rec->bo_handle));
1164         if (&new_bo->base == NULL) {
1165                 ret = -ENOENT;
1166                 goto out_free;
1167         }
1168
1169         mutex_lock(&dev->mode_config.mutex);
1170         mutex_lock(&dev->struct_mutex);
1171
1172         if (new_bo->tiling_mode) {
1173                 DRM_ERROR("buffer used for overlay image can not be tiled\n");
1174                 ret = -EINVAL;
1175                 goto out_unlock;
1176         }
1177
1178         ret = intel_overlay_recover_from_interrupt(overlay);
1179         if (ret != 0)
1180                 goto out_unlock;
1181
1182         if (overlay->crtc != crtc) {
1183                 struct drm_display_mode *mode = &crtc->base.mode;
1184                 ret = intel_overlay_switch_off(overlay);
1185                 if (ret != 0)
1186                         goto out_unlock;
1187
1188                 ret = check_overlay_possible_on_crtc(overlay, crtc);
1189                 if (ret != 0)
1190                         goto out_unlock;
1191
1192                 overlay->crtc = crtc;
1193                 crtc->overlay = overlay;
1194
1195                 /* line too wide, i.e. one-line-mode */
1196                 if (mode->hdisplay > 1024 &&
1197                     intel_panel_fitter_pipe(dev) == crtc->pipe) {
1198                         overlay->pfit_active = 1;
1199                         update_pfit_vscale_ratio(overlay);
1200                 } else
1201                         overlay->pfit_active = 0;
1202         }
1203
1204         ret = check_overlay_dst(overlay, put_image_rec);
1205         if (ret != 0)
1206                 goto out_unlock;
1207
1208         if (overlay->pfit_active) {
1209                 params->dst_y = ((((u32)put_image_rec->dst_y) << 12) /
1210                                  overlay->pfit_vscale_ratio);
1211                 /* shifting right rounds downwards, so add 1 */
1212                 params->dst_h = ((((u32)put_image_rec->dst_height) << 12) /
1213                                  overlay->pfit_vscale_ratio) + 1;
1214         } else {
1215                 params->dst_y = put_image_rec->dst_y;
1216                 params->dst_h = put_image_rec->dst_height;
1217         }
1218         params->dst_x = put_image_rec->dst_x;
1219         params->dst_w = put_image_rec->dst_width;
1220
1221         params->src_w = put_image_rec->src_width;
1222         params->src_h = put_image_rec->src_height;
1223         params->src_scan_w = put_image_rec->src_scan_width;
1224         params->src_scan_h = put_image_rec->src_scan_height;
1225         if (params->src_scan_h > params->src_h ||
1226             params->src_scan_w > params->src_w) {
1227                 ret = -EINVAL;
1228                 goto out_unlock;
1229         }
1230
1231         ret = check_overlay_src(dev, put_image_rec, new_bo);
1232         if (ret != 0)
1233                 goto out_unlock;
1234         params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK;
1235         params->stride_Y = put_image_rec->stride_Y;
1236         params->stride_UV = put_image_rec->stride_UV;
1237         params->offset_Y = put_image_rec->offset_Y;
1238         params->offset_U = put_image_rec->offset_U;
1239         params->offset_V = put_image_rec->offset_V;
1240
1241         /* Check scaling after src size to prevent a divide-by-zero. */
1242         ret = check_overlay_scaling(params);
1243         if (ret != 0)
1244                 goto out_unlock;
1245
1246         ret = intel_overlay_do_put_image(overlay, new_bo, params);
1247         if (ret != 0)
1248                 goto out_unlock;
1249
1250         mutex_unlock(&dev->struct_mutex);
1251         mutex_unlock(&dev->mode_config.mutex);
1252
1253         kfree(params);
1254
1255         return 0;
1256
1257 out_unlock:
1258         mutex_unlock(&dev->struct_mutex);
1259         mutex_unlock(&dev->mode_config.mutex);
1260         drm_gem_object_unreference_unlocked(&new_bo->base);
1261 out_free:
1262         kfree(params);
1263
1264         return ret;
1265 }
1266
1267 static void update_reg_attrs(struct intel_overlay *overlay,
1268                              struct overlay_registers __iomem *regs)
1269 {
1270         iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff),
1271                   &regs->OCLRC0);
1272         iowrite32(overlay->saturation, &regs->OCLRC1);
1273 }
1274
1275 static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1276 {
1277         int i;
1278
1279         if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1280                 return false;
1281
1282         for (i = 0; i < 3; i++) {
1283                 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
1284                         return false;
1285         }
1286
1287         return true;
1288 }
1289
1290 static bool check_gamma5_errata(u32 gamma5)
1291 {
1292         int i;
1293
1294         for (i = 0; i < 3; i++) {
1295                 if (((gamma5 >> i*8) & 0xff) == 0x80)
1296                         return false;
1297         }
1298
1299         return true;
1300 }
1301
1302 static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1303 {
1304         if (!check_gamma_bounds(0, attrs->gamma0) ||
1305             !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
1306             !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
1307             !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
1308             !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
1309             !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
1310             !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
1311                 return -EINVAL;
1312
1313         if (!check_gamma5_errata(attrs->gamma5))
1314                 return -EINVAL;
1315
1316         return 0;
1317 }
1318
1319 int intel_overlay_attrs(struct drm_device *dev, void *data,
1320                         struct drm_file *file_priv)
1321 {
1322         struct drm_intel_overlay_attrs *attrs = data;
1323         drm_i915_private_t *dev_priv = dev->dev_private;
1324         struct intel_overlay *overlay;
1325         struct overlay_registers __iomem *regs;
1326         int ret;
1327
1328         /* No need to check for DRIVER_MODESET - we don't set it up then. */
1329         overlay = dev_priv->overlay;
1330         if (!overlay) {
1331                 DRM_DEBUG("userspace bug: no overlay\n");
1332                 return -ENODEV;
1333         }
1334
1335         mutex_lock(&dev->mode_config.mutex);
1336         mutex_lock(&dev->struct_mutex);
1337
1338         ret = -EINVAL;
1339         if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
1340                 attrs->color_key  = overlay->color_key;
1341                 attrs->brightness = overlay->brightness;
1342                 attrs->contrast   = overlay->contrast;
1343                 attrs->saturation = overlay->saturation;
1344
1345                 if (!IS_GEN2(dev)) {
1346                         attrs->gamma0 = I915_READ(OGAMC0);
1347                         attrs->gamma1 = I915_READ(OGAMC1);
1348                         attrs->gamma2 = I915_READ(OGAMC2);
1349                         attrs->gamma3 = I915_READ(OGAMC3);
1350                         attrs->gamma4 = I915_READ(OGAMC4);
1351                         attrs->gamma5 = I915_READ(OGAMC5);
1352                 }
1353         } else {
1354                 if (attrs->brightness < -128 || attrs->brightness > 127)
1355                         goto out_unlock;
1356                 if (attrs->contrast > 255)
1357                         goto out_unlock;
1358                 if (attrs->saturation > 1023)
1359                         goto out_unlock;
1360
1361                 overlay->color_key  = attrs->color_key;
1362                 overlay->brightness = attrs->brightness;
1363                 overlay->contrast   = attrs->contrast;
1364                 overlay->saturation = attrs->saturation;
1365
1366                 regs = intel_overlay_map_regs(overlay);
1367                 if (!regs) {
1368                         ret = -ENOMEM;
1369                         goto out_unlock;
1370                 }
1371
1372                 update_reg_attrs(overlay, regs);
1373
1374                 intel_overlay_unmap_regs(overlay, regs);
1375
1376                 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
1377                         if (IS_GEN2(dev))
1378                                 goto out_unlock;
1379
1380                         if (overlay->active) {
1381                                 ret = -EBUSY;
1382                                 goto out_unlock;
1383                         }
1384
1385                         ret = check_gamma(attrs);
1386                         if (ret)
1387                                 goto out_unlock;
1388
1389                         I915_WRITE(OGAMC0, attrs->gamma0);
1390                         I915_WRITE(OGAMC1, attrs->gamma1);
1391                         I915_WRITE(OGAMC2, attrs->gamma2);
1392                         I915_WRITE(OGAMC3, attrs->gamma3);
1393                         I915_WRITE(OGAMC4, attrs->gamma4);
1394                         I915_WRITE(OGAMC5, attrs->gamma5);
1395                 }
1396         }
1397
1398         ret = 0;
1399 out_unlock:
1400         mutex_unlock(&dev->struct_mutex);
1401         mutex_unlock(&dev->mode_config.mutex);
1402
1403         return ret;
1404 }
1405
1406 void intel_setup_overlay(struct drm_device *dev)
1407 {
1408         drm_i915_private_t *dev_priv = dev->dev_private;
1409         struct intel_overlay *overlay;
1410         struct drm_i915_gem_object *reg_bo;
1411         struct overlay_registers __iomem *regs;
1412         int ret;
1413
1414         if (!HAS_OVERLAY(dev))
1415                 return;
1416
1417         overlay = kzalloc(sizeof(struct intel_overlay), GFP_KERNEL);
1418         if (!overlay)
1419                 return;
1420
1421         mutex_lock(&dev->struct_mutex);
1422         if (WARN_ON(dev_priv->overlay))
1423                 goto out_free;
1424
1425         overlay->dev = dev;
1426
1427         reg_bo = i915_gem_alloc_object(dev, PAGE_SIZE);
1428         if (!reg_bo)
1429                 goto out_free;
1430         overlay->reg_bo = reg_bo;
1431
1432         if (OVERLAY_NEEDS_PHYSICAL(dev)) {
1433                 ret = i915_gem_attach_phys_object(dev, reg_bo,
1434                                                   I915_GEM_PHYS_OVERLAY_REGS,
1435                                                   PAGE_SIZE);
1436                 if (ret) {
1437                         DRM_ERROR("failed to attach phys overlay regs\n");
1438                         goto out_free_bo;
1439                 }
1440                 overlay->flip_addr = reg_bo->phys_obj->handle->busaddr;
1441         } else {
1442                 ret = i915_gem_object_pin(reg_bo, PAGE_SIZE, true);
1443                 if (ret) {
1444                         DRM_ERROR("failed to pin overlay register bo\n");
1445                         goto out_free_bo;
1446                 }
1447                 overlay->flip_addr = reg_bo->gtt_offset;
1448
1449                 ret = i915_gem_object_set_to_gtt_domain(reg_bo, true);
1450                 if (ret) {
1451                         DRM_ERROR("failed to move overlay register bo into the GTT\n");
1452                         goto out_unpin_bo;
1453                 }
1454         }
1455
1456         /* init all values */
1457         overlay->color_key = 0x0101fe;
1458         overlay->brightness = -19;
1459         overlay->contrast = 75;
1460         overlay->saturation = 146;
1461
1462         regs = intel_overlay_map_regs(overlay);
1463         if (!regs)
1464                 goto out_unpin_bo;
1465
1466         memset_io(regs, 0, sizeof(struct overlay_registers));
1467         update_polyphase_filter(regs);
1468         update_reg_attrs(overlay, regs);
1469
1470         intel_overlay_unmap_regs(overlay, regs);
1471
1472         dev_priv->overlay = overlay;
1473         mutex_unlock(&dev->struct_mutex);
1474         DRM_INFO("initialized overlay support\n");
1475         return;
1476
1477 out_unpin_bo:
1478         if (!OVERLAY_NEEDS_PHYSICAL(dev))
1479                 i915_gem_object_unpin(reg_bo);
1480 out_free_bo:
1481         drm_gem_object_unreference(&reg_bo->base);
1482 out_free:
1483         mutex_unlock(&dev->struct_mutex);
1484         kfree(overlay);
1485         return;
1486 }
1487
1488 void intel_cleanup_overlay(struct drm_device *dev)
1489 {
1490         drm_i915_private_t *dev_priv = dev->dev_private;
1491
1492         if (!dev_priv->overlay)
1493                 return;
1494
1495         /* The bo's should be free'd by the generic code already.
1496          * Furthermore modesetting teardown happens beforehand so the
1497          * hardware should be off already */
1498         BUG_ON(dev_priv->overlay->active);
1499
1500         drm_gem_object_unreference_unlocked(&dev_priv->overlay->reg_bo->base);
1501         kfree(dev_priv->overlay);
1502 }
1503
1504 #ifdef CONFIG_DEBUG_FS
1505 #include <linux/seq_file.h>
1506
1507 struct intel_overlay_error_state {
1508         struct overlay_registers regs;
1509         unsigned long base;
1510         u32 dovsta;
1511         u32 isr;
1512 };
1513
1514 static struct overlay_registers __iomem *
1515 intel_overlay_map_regs_atomic(struct intel_overlay *overlay)
1516 {
1517         drm_i915_private_t *dev_priv = overlay->dev->dev_private;
1518         struct overlay_registers __iomem *regs;
1519
1520         if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1521                 /* Cast to make sparse happy, but it's wc memory anyway, so
1522                  * equivalent to the wc io mapping on X86. */
1523                 regs = (struct overlay_registers __iomem *)
1524                         overlay->reg_bo->phys_obj->handle->vaddr;
1525         else
1526                 regs = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
1527                                                 overlay->reg_bo->gtt_offset);
1528
1529         return regs;
1530 }
1531
1532 static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay,
1533                                         struct overlay_registers __iomem *regs)
1534 {
1535         if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1536                 io_mapping_unmap_atomic(regs);
1537 }
1538
1539
1540 struct intel_overlay_error_state *
1541 intel_overlay_capture_error_state(struct drm_device *dev)
1542 {
1543         drm_i915_private_t *dev_priv = dev->dev_private;
1544         struct intel_overlay *overlay = dev_priv->overlay;
1545         struct intel_overlay_error_state *error;
1546         struct overlay_registers __iomem *regs;
1547
1548         if (!overlay || !overlay->active)
1549                 return NULL;
1550
1551         error = kmalloc(sizeof(*error), GFP_ATOMIC);
1552         if (error == NULL)
1553                 return NULL;
1554
1555         error->dovsta = I915_READ(DOVSTA);
1556         error->isr = I915_READ(ISR);
1557         if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1558                 error->base = (__force long)overlay->reg_bo->phys_obj->handle->vaddr;
1559         else
1560                 error->base = overlay->reg_bo->gtt_offset;
1561
1562         regs = intel_overlay_map_regs_atomic(overlay);
1563         if (!regs)
1564                 goto err;
1565
1566         memcpy_fromio(&error->regs, regs, sizeof(struct overlay_registers));
1567         intel_overlay_unmap_regs_atomic(overlay, regs);
1568
1569         return error;
1570
1571 err:
1572         kfree(error);
1573         return NULL;
1574 }
1575
1576 void
1577 intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error)
1578 {
1579         seq_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1580                    error->dovsta, error->isr);
1581         seq_printf(m, "  Register file at 0x%08lx:\n",
1582                    error->base);
1583
1584 #define P(x) seq_printf(m, "    " #x ": 0x%08x\n", error->regs.x)
1585         P(OBUF_0Y);
1586         P(OBUF_1Y);
1587         P(OBUF_0U);
1588         P(OBUF_0V);
1589         P(OBUF_1U);
1590         P(OBUF_1V);
1591         P(OSTRIDE);
1592         P(YRGB_VPH);
1593         P(UV_VPH);
1594         P(HORZ_PH);
1595         P(INIT_PHS);
1596         P(DWINPOS);
1597         P(DWINSZ);
1598         P(SWIDTH);
1599         P(SWIDTHSW);
1600         P(SHEIGHT);
1601         P(YRGBSCALE);
1602         P(UVSCALE);
1603         P(OCLRC0);
1604         P(OCLRC1);
1605         P(DCLRKV);
1606         P(DCLRKM);
1607         P(SCLRKVH);
1608         P(SCLRKVL);
1609         P(SCLRKEN);
1610         P(OCONFIG);
1611         P(OCMD);
1612         P(OSTART_0Y);
1613         P(OSTART_1Y);
1614         P(OSTART_0U);
1615         P(OSTART_0V);
1616         P(OSTART_1U);
1617         P(OSTART_1V);
1618         P(OTILEOFF_0Y);
1619         P(OTILEOFF_1Y);
1620         P(OTILEOFF_0U);
1621         P(OTILEOFF_0V);
1622         P(OTILEOFF_1U);
1623         P(OTILEOFF_1V);
1624         P(FASTHSCALE);
1625         P(UVSCALEV);
1626 #undef P
1627 }
1628 #endif