2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2008,2010 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
26 * Eric Anholt <eric@anholt.net>
27 * Chris Wilson <chris@chris-wilson.co.uk>
29 #include <linux/i2c.h>
30 #include <linux/i2c-algo-bit.h>
31 #include <linux/export.h>
33 #include "intel_drv.h"
34 #include <drm/i915_drm.h>
42 static const struct gmbus_port gmbus_ports[] = {
51 /* Intel GPIO access functions */
53 #define I2C_RISEFALL_TIME 10
55 static inline struct intel_gmbus *
56 to_intel_gmbus(struct i2c_adapter *i2c)
58 return container_of(i2c, struct intel_gmbus, adapter);
62 intel_i2c_reset(struct drm_device *dev)
64 struct drm_i915_private *dev_priv = dev->dev_private;
65 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0);
66 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0);
69 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
73 /* When using bit bashing for I2C, this bit needs to be set to 1 */
74 if (!IS_PINEVIEW(dev_priv->dev))
77 val = I915_READ(DSPCLK_GATE_D);
79 val |= DPCUNIT_CLOCK_GATE_DISABLE;
81 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
82 I915_WRITE(DSPCLK_GATE_D, val);
85 static u32 get_reserved(struct intel_gmbus *bus)
87 struct drm_i915_private *dev_priv = bus->dev_priv;
88 struct drm_device *dev = dev_priv->dev;
91 /* On most chips, these bits must be preserved in software. */
92 if (!IS_I830(dev) && !IS_845G(dev))
93 reserved = I915_READ_NOTRACE(bus->gpio_reg) &
94 (GPIO_DATA_PULLUP_DISABLE |
95 GPIO_CLOCK_PULLUP_DISABLE);
100 static int get_clock(void *data)
102 struct intel_gmbus *bus = data;
103 struct drm_i915_private *dev_priv = bus->dev_priv;
104 u32 reserved = get_reserved(bus);
105 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
106 I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
107 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
110 static int get_data(void *data)
112 struct intel_gmbus *bus = data;
113 struct drm_i915_private *dev_priv = bus->dev_priv;
114 u32 reserved = get_reserved(bus);
115 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
116 I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
117 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
120 static void set_clock(void *data, int state_high)
122 struct intel_gmbus *bus = data;
123 struct drm_i915_private *dev_priv = bus->dev_priv;
124 u32 reserved = get_reserved(bus);
128 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
130 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
133 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits);
134 POSTING_READ(bus->gpio_reg);
137 static void set_data(void *data, int state_high)
139 struct intel_gmbus *bus = data;
140 struct drm_i915_private *dev_priv = bus->dev_priv;
141 u32 reserved = get_reserved(bus);
145 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
147 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
150 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits);
151 POSTING_READ(bus->gpio_reg);
155 intel_gpio_pre_xfer(struct i2c_adapter *adapter)
157 struct intel_gmbus *bus = container_of(adapter,
160 struct drm_i915_private *dev_priv = bus->dev_priv;
162 intel_i2c_reset(dev_priv->dev);
163 intel_i2c_quirk_set(dev_priv, true);
166 udelay(I2C_RISEFALL_TIME);
171 intel_gpio_post_xfer(struct i2c_adapter *adapter)
173 struct intel_gmbus *bus = container_of(adapter,
176 struct drm_i915_private *dev_priv = bus->dev_priv;
180 intel_i2c_quirk_set(dev_priv, false);
184 intel_gpio_setup(struct intel_gmbus *bus, u32 pin)
186 struct drm_i915_private *dev_priv = bus->dev_priv;
187 struct i2c_algo_bit_data *algo;
189 algo = &bus->bit_algo;
191 /* -1 to map pin pair to gmbus index */
192 bus->gpio_reg = dev_priv->gpio_mmio_base + gmbus_ports[pin - 1].reg;
194 bus->adapter.algo_data = algo;
195 algo->setsda = set_data;
196 algo->setscl = set_clock;
197 algo->getsda = get_data;
198 algo->getscl = get_clock;
199 algo->pre_xfer = intel_gpio_pre_xfer;
200 algo->post_xfer = intel_gpio_post_xfer;
201 algo->udelay = I2C_RISEFALL_TIME;
202 algo->timeout = usecs_to_jiffies(2200);
206 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 4)
208 gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
213 int reg_offset = dev_priv->gpio_mmio_base;
217 /* Important: The hw handles only the first bit, so set only one! Since
218 * we also need to check for NAKs besides the hw ready/idle signal, we
219 * need to wake up periodically and check that ourselves. */
220 I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en);
222 for (i = 0; i < msecs_to_jiffies(50) + 1; i++) {
223 prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait,
224 TASK_UNINTERRUPTIBLE);
226 gmbus2 = I915_READ_NOTRACE(GMBUS2 + reg_offset);
227 if (gmbus2 & (GMBUS_SATOER | gmbus2_status))
232 finish_wait(&dev_priv->gmbus_wait_queue, &wait);
234 I915_WRITE(GMBUS4 + reg_offset, 0);
236 if (gmbus2 & GMBUS_SATOER)
238 if (gmbus2 & gmbus2_status)
244 gmbus_wait_idle(struct drm_i915_private *dev_priv)
247 int reg_offset = dev_priv->gpio_mmio_base;
249 #define C ((I915_READ_NOTRACE(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0)
251 if (!HAS_GMBUS_IRQ(dev_priv->dev))
252 return wait_for(C, 10);
254 /* Important: The hw handles only the first bit, so set only one! */
255 I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN);
257 ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 10);
259 I915_WRITE(GMBUS4 + reg_offset, 0);
269 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
272 int reg_offset = dev_priv->gpio_mmio_base;
276 I915_WRITE(GMBUS1 + reg_offset,
279 (len << GMBUS_BYTE_COUNT_SHIFT) |
280 (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
281 GMBUS_SLAVE_READ | GMBUS_SW_RDY);
286 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
291 val = I915_READ(GMBUS3 + reg_offset);
295 } while (--len && ++loop < 4);
302 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
304 int reg_offset = dev_priv->gpio_mmio_base;
310 while (len && loop < 4) {
311 val |= *buf++ << (8 * loop++);
315 I915_WRITE(GMBUS3 + reg_offset, val);
316 I915_WRITE(GMBUS1 + reg_offset,
318 (msg->len << GMBUS_BYTE_COUNT_SHIFT) |
319 (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
320 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
326 val |= *buf++ << (8 * loop);
327 } while (--len && ++loop < 4);
329 I915_WRITE(GMBUS3 + reg_offset, val);
331 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
340 * The gmbus controller can combine a 1 or 2 byte write with a read that
341 * immediately follows it by using an "INDEX" cycle.
344 gmbus_is_index_read(struct i2c_msg *msgs, int i, int num)
346 return (i + 1 < num &&
347 !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 &&
348 (msgs[i + 1].flags & I2C_M_RD));
352 gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
354 int reg_offset = dev_priv->gpio_mmio_base;
355 u32 gmbus1_index = 0;
359 if (msgs[0].len == 2)
360 gmbus5 = GMBUS_2BYTE_INDEX_EN |
361 msgs[0].buf[1] | (msgs[0].buf[0] << 8);
362 if (msgs[0].len == 1)
363 gmbus1_index = GMBUS_CYCLE_INDEX |
364 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
366 /* GMBUS5 holds 16-bit index */
368 I915_WRITE(GMBUS5 + reg_offset, gmbus5);
370 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
372 /* Clear GMBUS5 after each index transfer */
374 I915_WRITE(GMBUS5 + reg_offset, 0);
380 gmbus_xfer(struct i2c_adapter *adapter,
381 struct i2c_msg *msgs,
384 struct intel_gmbus *bus = container_of(adapter,
387 struct drm_i915_private *dev_priv = bus->dev_priv;
391 mutex_lock(&dev_priv->gmbus_mutex);
393 if (bus->force_bit) {
394 ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
398 reg_offset = dev_priv->gpio_mmio_base;
400 I915_WRITE(GMBUS0 + reg_offset, bus->reg0);
402 for (i = 0; i < num; i++) {
403 if (gmbus_is_index_read(msgs, i, num)) {
404 ret = gmbus_xfer_index_read(dev_priv, &msgs[i]);
405 i += 1; /* set i to the index of the read xfer */
406 } else if (msgs[i].flags & I2C_M_RD) {
407 ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
409 ret = gmbus_xfer_write(dev_priv, &msgs[i]);
412 if (ret == -ETIMEDOUT)
417 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_WAIT_PHASE,
425 /* Generate a STOP condition on the bus. Note that gmbus can't generata
426 * a STOP on the very first cycle. To simplify the code we
427 * unconditionally generate the STOP condition with an additional gmbus
429 I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
431 /* Mark the GMBUS interface as disabled after waiting for idle.
432 * We will re-enable it at the start of the next xfer,
433 * till then let it sleep.
435 if (gmbus_wait_idle(dev_priv)) {
436 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
440 I915_WRITE(GMBUS0 + reg_offset, 0);
446 * Wait for bus to IDLE before clearing NAK.
447 * If we clear the NAK while bus is still active, then it will stay
448 * active and the next transaction may fail.
450 * If no ACK is received during the address phase of a transaction, the
451 * adapter must report -ENXIO. It is not clear what to return if no ACK
452 * is received at other times. But we have to be careful to not return
453 * spurious -ENXIO because that will prevent i2c and drm edid functions
454 * from retrying. So return -ENXIO only when gmbus properly quiescents -
455 * timing out seems to happen when there _is_ a ddc chip present, but
456 * it's slow responding and only answers on the 2nd retry.
459 if (gmbus_wait_idle(dev_priv)) {
460 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n",
465 /* Toggle the Software Clear Interrupt bit. This has the effect
466 * of resetting the GMBUS controller and so clearing the
467 * BUS_ERROR raised by the slave's NAK.
469 I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
470 I915_WRITE(GMBUS1 + reg_offset, 0);
471 I915_WRITE(GMBUS0 + reg_offset, 0);
473 DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
474 adapter->name, msgs[i].addr,
475 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
480 DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
481 bus->adapter.name, bus->reg0 & 0xff);
482 I915_WRITE(GMBUS0 + reg_offset, 0);
484 /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
486 ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
489 mutex_unlock(&dev_priv->gmbus_mutex);
493 static u32 gmbus_func(struct i2c_adapter *adapter)
495 return i2c_bit_algo.functionality(adapter) &
496 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
497 /* I2C_FUNC_10BIT_ADDR | */
498 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
499 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
502 static const struct i2c_algorithm gmbus_algorithm = {
503 .master_xfer = gmbus_xfer,
504 .functionality = gmbus_func
508 * intel_gmbus_setup - instantiate all Intel i2c GMBuses
511 int intel_setup_gmbus(struct drm_device *dev)
513 struct drm_i915_private *dev_priv = dev->dev_private;
516 if (HAS_PCH_SPLIT(dev))
517 dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
518 else if (IS_VALLEYVIEW(dev))
519 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
521 dev_priv->gpio_mmio_base = 0;
523 mutex_init(&dev_priv->gmbus_mutex);
524 init_waitqueue_head(&dev_priv->gmbus_wait_queue);
526 for (i = 0; i < GMBUS_NUM_PORTS; i++) {
527 struct intel_gmbus *bus = &dev_priv->gmbus[i];
528 u32 port = i + 1; /* +1 to map gmbus index to pin pair */
530 bus->adapter.owner = THIS_MODULE;
531 bus->adapter.class = I2C_CLASS_DDC;
532 snprintf(bus->adapter.name,
533 sizeof(bus->adapter.name),
535 gmbus_ports[i].name);
537 bus->adapter.dev.parent = &dev->pdev->dev;
538 bus->dev_priv = dev_priv;
540 bus->adapter.algo = &gmbus_algorithm;
542 /* By default use a conservative clock rate */
543 bus->reg0 = port | GMBUS_RATE_100KHZ;
545 /* gmbus seems to be broken on i830 */
549 intel_gpio_setup(bus, port);
551 ret = i2c_add_adapter(&bus->adapter);
556 intel_i2c_reset(dev_priv->dev);
562 struct intel_gmbus *bus = &dev_priv->gmbus[i];
563 i2c_del_adapter(&bus->adapter);
568 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
571 WARN_ON(!intel_gmbus_is_port_valid(port));
572 /* -1 to map pin pair to gmbus index */
573 return (intel_gmbus_is_port_valid(port)) ?
574 &dev_priv->gmbus[port - 1].adapter : NULL;
577 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
579 struct intel_gmbus *bus = to_intel_gmbus(adapter);
581 bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
584 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
586 struct intel_gmbus *bus = to_intel_gmbus(adapter);
588 bus->force_bit += force_bit ? 1 : -1;
589 DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n",
590 force_bit ? "en" : "dis", adapter->name,
594 void intel_teardown_gmbus(struct drm_device *dev)
596 struct drm_i915_private *dev_priv = dev->dev_private;
599 for (i = 0; i < GMBUS_NUM_PORTS; i++) {
600 struct intel_gmbus *bus = &dev_priv->gmbus[i];
601 i2c_del_adapter(&bus->adapter);