2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2008,2010 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
26 * Eric Anholt <eric@anholt.net>
27 * Chris Wilson <chris@chris-wilson.co.uk>
29 #include <linux/i2c.h>
30 #include <linux/i2c-algo-bit.h>
33 #include "intel_drv.h"
37 /* Intel GPIO access functions */
39 #define I2C_RISEFALL_TIME 20
41 static inline struct intel_gmbus *
42 to_intel_gmbus(struct i2c_adapter *i2c)
44 return container_of(i2c, struct intel_gmbus, adapter);
48 struct i2c_adapter adapter;
49 struct i2c_algo_bit_data algo;
50 struct drm_i915_private *dev_priv;
55 intel_i2c_reset(struct drm_device *dev)
57 struct drm_i915_private *dev_priv = dev->dev_private;
58 if (HAS_PCH_SPLIT(dev))
59 I915_WRITE(PCH_GMBUS0, 0);
61 I915_WRITE(GMBUS0, 0);
64 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
68 /* When using bit bashing for I2C, this bit needs to be set to 1 */
69 if (!IS_PINEVIEW(dev_priv->dev))
72 val = I915_READ(DSPCLK_GATE_D);
74 val |= DPCUNIT_CLOCK_GATE_DISABLE;
76 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
77 I915_WRITE(DSPCLK_GATE_D, val);
80 static u32 get_reserved(struct intel_gpio *gpio)
82 struct drm_i915_private *dev_priv = gpio->dev_priv;
83 struct drm_device *dev = dev_priv->dev;
86 /* On most chips, these bits must be preserved in software. */
87 if (!IS_I830(dev) && !IS_845G(dev))
88 reserved = I915_READ(gpio->reg) & (GPIO_DATA_PULLUP_DISABLE |
89 GPIO_CLOCK_PULLUP_DISABLE);
94 static int get_clock(void *data)
96 struct intel_gpio *gpio = data;
97 struct drm_i915_private *dev_priv = gpio->dev_priv;
98 u32 reserved = get_reserved(gpio);
99 I915_WRITE(gpio->reg, reserved | GPIO_CLOCK_DIR_MASK);
100 I915_WRITE(gpio->reg, reserved);
101 return (I915_READ(gpio->reg) & GPIO_CLOCK_VAL_IN) != 0;
104 static int get_data(void *data)
106 struct intel_gpio *gpio = data;
107 struct drm_i915_private *dev_priv = gpio->dev_priv;
108 u32 reserved = get_reserved(gpio);
109 I915_WRITE(gpio->reg, reserved | GPIO_DATA_DIR_MASK);
110 I915_WRITE(gpio->reg, reserved);
111 return (I915_READ(gpio->reg) & GPIO_DATA_VAL_IN) != 0;
114 static void set_clock(void *data, int state_high)
116 struct intel_gpio *gpio = data;
117 struct drm_i915_private *dev_priv = gpio->dev_priv;
118 u32 reserved = get_reserved(gpio);
122 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
124 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
127 I915_WRITE(gpio->reg, reserved | clock_bits);
128 POSTING_READ(gpio->reg);
131 static void set_data(void *data, int state_high)
133 struct intel_gpio *gpio = data;
134 struct drm_i915_private *dev_priv = gpio->dev_priv;
135 u32 reserved = get_reserved(gpio);
139 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
141 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
144 I915_WRITE(gpio->reg, reserved | data_bits);
145 POSTING_READ(gpio->reg);
148 static struct i2c_adapter *
149 intel_gpio_create(struct drm_i915_private *dev_priv, u32 pin)
151 static const int map_pin_to_reg[] = {
161 struct intel_gpio *gpio;
163 if (pin >= ARRAY_SIZE(map_pin_to_reg) || !map_pin_to_reg[pin])
166 gpio = kzalloc(sizeof(struct intel_gpio), GFP_KERNEL);
170 gpio->reg = map_pin_to_reg[pin];
171 if (HAS_PCH_SPLIT(dev_priv->dev))
172 gpio->reg += PCH_GPIOA - GPIOA;
173 gpio->dev_priv = dev_priv;
175 snprintf(gpio->adapter.name, sizeof(gpio->adapter.name),
176 "i915 GPIO%c", "?BACDE?F"[pin]);
177 gpio->adapter.owner = THIS_MODULE;
178 gpio->adapter.algo_data = &gpio->algo;
179 gpio->adapter.dev.parent = &dev_priv->dev->pdev->dev;
180 gpio->algo.setsda = set_data;
181 gpio->algo.setscl = set_clock;
182 gpio->algo.getsda = get_data;
183 gpio->algo.getscl = get_clock;
184 gpio->algo.udelay = I2C_RISEFALL_TIME;
185 gpio->algo.timeout = usecs_to_jiffies(2200);
186 gpio->algo.data = gpio;
188 if (i2c_bit_add_bus(&gpio->adapter))
191 return &gpio->adapter;
199 intel_i2c_quirk_xfer(struct drm_i915_private *dev_priv,
200 struct i2c_adapter *adapter,
201 struct i2c_msg *msgs,
204 struct intel_gpio *gpio = container_of(adapter,
209 intel_i2c_reset(dev_priv->dev);
211 intel_i2c_quirk_set(dev_priv, true);
214 udelay(I2C_RISEFALL_TIME);
216 ret = adapter->algo->master_xfer(adapter, msgs, num);
220 intel_i2c_quirk_set(dev_priv, false);
226 gmbus_xfer(struct i2c_adapter *adapter,
227 struct i2c_msg *msgs,
230 struct intel_gmbus *bus = container_of(adapter,
233 struct drm_i915_private *dev_priv = adapter->algo_data;
237 return intel_i2c_quirk_xfer(dev_priv,
238 bus->force_bit, msgs, num);
240 reg_offset = HAS_PCH_SPLIT(dev_priv->dev) ? PCH_GMBUS0 - GMBUS0 : 0;
242 I915_WRITE(GMBUS0 + reg_offset, bus->reg0);
244 for (i = 0; i < num; i++) {
245 u16 len = msgs[i].len;
246 u8 *buf = msgs[i].buf;
248 if (msgs[i].flags & I2C_M_RD) {
249 I915_WRITE(GMBUS1 + reg_offset,
250 GMBUS_CYCLE_WAIT | (i + 1 == num ? GMBUS_CYCLE_STOP : 0) |
251 (len << GMBUS_BYTE_COUNT_SHIFT) |
252 (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
253 GMBUS_SLAVE_READ | GMBUS_SW_RDY);
254 POSTING_READ(GMBUS2+reg_offset);
258 if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
260 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
263 val = I915_READ(GMBUS3 + reg_offset);
267 } while (--len && ++loop < 4);
274 val |= *buf++ << (8 * loop);
275 } while (--len && ++loop < 4);
277 I915_WRITE(GMBUS3 + reg_offset, val);
278 I915_WRITE(GMBUS1 + reg_offset,
279 (i + 1 == num ? GMBUS_CYCLE_STOP : GMBUS_CYCLE_WAIT) |
280 (msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) |
281 (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
282 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
283 POSTING_READ(GMBUS2+reg_offset);
286 if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
288 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
293 val |= *buf++ << (8 * loop);
294 } while (--len && ++loop < 4);
296 I915_WRITE(GMBUS3 + reg_offset, val);
297 POSTING_READ(GMBUS2+reg_offset);
301 if (i + 1 < num && wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50))
303 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
310 DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n",
311 bus->reg0 & 0xff, bus->adapter.name);
312 /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
313 bus->force_bit = intel_gpio_create(dev_priv, bus->reg0 & 0xff);
317 return intel_i2c_quirk_xfer(dev_priv, bus->force_bit, msgs, num);
320 static u32 gmbus_func(struct i2c_adapter *adapter)
322 struct intel_gmbus *bus = container_of(adapter,
327 bus->force_bit->algo->functionality(bus->force_bit);
329 return (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
330 /* I2C_FUNC_10BIT_ADDR | */
331 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
332 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
335 static const struct i2c_algorithm gmbus_algorithm = {
336 .master_xfer = gmbus_xfer,
337 .functionality = gmbus_func
341 * intel_gmbus_setup - instantiate all Intel i2c GMBuses
344 int intel_setup_gmbus(struct drm_device *dev)
346 static const char *names[GMBUS_NUM_PORTS] = {
356 struct drm_i915_private *dev_priv = dev->dev_private;
359 dev_priv->gmbus = kcalloc(sizeof(struct intel_gmbus), GMBUS_NUM_PORTS,
361 if (dev_priv->gmbus == NULL)
364 for (i = 0; i < GMBUS_NUM_PORTS; i++) {
365 struct intel_gmbus *bus = &dev_priv->gmbus[i];
367 bus->adapter.owner = THIS_MODULE;
368 bus->adapter.class = I2C_CLASS_DDC;
369 snprintf(bus->adapter.name,
370 sizeof(bus->adapter.name),
374 bus->adapter.dev.parent = &dev->pdev->dev;
375 bus->adapter.algo_data = dev_priv;
377 bus->adapter.algo = &gmbus_algorithm;
378 ret = i2c_add_adapter(&bus->adapter);
382 /* By default use a conservative clock rate */
383 bus->reg0 = i | GMBUS_RATE_100KHZ;
385 /* XXX force bit banging until GMBUS is fully debugged */
386 bus->force_bit = intel_gpio_create(dev_priv, i);
389 intel_i2c_reset(dev_priv->dev);
395 struct intel_gmbus *bus = &dev_priv->gmbus[i];
396 i2c_del_adapter(&bus->adapter);
398 kfree(dev_priv->gmbus);
399 dev_priv->gmbus = NULL;
403 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
405 struct intel_gmbus *bus = to_intel_gmbus(adapter);
413 bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | (speed << 8);
416 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
418 struct intel_gmbus *bus = to_intel_gmbus(adapter);
421 if (bus->force_bit == NULL) {
422 struct drm_i915_private *dev_priv = adapter->algo_data;
423 bus->force_bit = intel_gpio_create(dev_priv,
427 if (bus->force_bit) {
428 i2c_del_adapter(bus->force_bit);
429 kfree(bus->force_bit);
430 bus->force_bit = NULL;
435 void intel_teardown_gmbus(struct drm_device *dev)
437 struct drm_i915_private *dev_priv = dev->dev_private;
440 if (dev_priv->gmbus == NULL)
443 for (i = 0; i < GMBUS_NUM_PORTS; i++) {
444 struct intel_gmbus *bus = &dev_priv->gmbus[i];
445 if (bus->force_bit) {
446 i2c_del_adapter(bus->force_bit);
447 kfree(bus->force_bit);
449 i2c_del_adapter(&bus->adapter);
452 kfree(dev_priv->gmbus);
453 dev_priv->gmbus = NULL;