2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <drm/i915_drm.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_fb_helper.h>
36 #include <drm/drm_dp_mst_helper.h>
37 #include <drm/drm_rect.h>
39 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
40 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
43 * _wait_for - magic (register) wait macro
45 * Does the right thing for modeset paths when run under kdgb or similar atomic
46 * contexts. Note that it's important that we check the condition again after
47 * having timed out, since the timeout could be due to preemption or similar and
48 * we've never had a chance to check the condition before the timeout.
50 #define _wait_for(COND, MS, W) ({ \
51 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
54 if (time_after(jiffies, timeout__)) { \
59 if (W && drm_can_sleep()) { \
68 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
69 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
70 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
71 DIV_ROUND_UP((US), 1000), 0)
73 #define KHz(x) (1000 * (x))
74 #define MHz(x) KHz(1000 * (x))
77 * Display related stuff
80 /* store information about an Ixxx DVO */
81 /* The i830->i865 use multiple DVOs with multiple i2cs */
82 /* the i915, i945 have a single sDVO i2c bus - which is different */
84 /* maximum connectors per crtcs in the mode set */
86 /* Maximum cursor sizes */
87 #define GEN2_CURSOR_WIDTH 64
88 #define GEN2_CURSOR_HEIGHT 64
89 #define MAX_CURSOR_WIDTH 256
90 #define MAX_CURSOR_HEIGHT 256
92 #define INTEL_I2C_BUS_DVO 1
93 #define INTEL_I2C_BUS_SDVO 2
95 /* these are outputs from the chip - integrated only
96 external chips are via DVO or SDVO output */
97 enum intel_output_type {
98 INTEL_OUTPUT_UNUSED = 0,
99 INTEL_OUTPUT_ANALOG = 1,
100 INTEL_OUTPUT_DVO = 2,
101 INTEL_OUTPUT_SDVO = 3,
102 INTEL_OUTPUT_LVDS = 4,
103 INTEL_OUTPUT_TVOUT = 5,
104 INTEL_OUTPUT_HDMI = 6,
105 INTEL_OUTPUT_DISPLAYPORT = 7,
106 INTEL_OUTPUT_EDP = 8,
107 INTEL_OUTPUT_DSI = 9,
108 INTEL_OUTPUT_UNKNOWN = 10,
109 INTEL_OUTPUT_DP_MST = 11,
112 #define INTEL_DVO_CHIP_NONE 0
113 #define INTEL_DVO_CHIP_LVDS 1
114 #define INTEL_DVO_CHIP_TMDS 2
115 #define INTEL_DVO_CHIP_TVOUT 4
117 #define INTEL_DSI_VIDEO_MODE 0
118 #define INTEL_DSI_COMMAND_MODE 1
120 struct intel_framebuffer {
121 struct drm_framebuffer base;
122 struct drm_i915_gem_object *obj;
126 struct drm_fb_helper helper;
127 struct intel_framebuffer *fb;
128 struct list_head fbdev_list;
129 struct drm_display_mode *our_mode;
133 struct intel_encoder {
134 struct drm_encoder base;
136 * The new crtc this encoder will be driven from. Only differs from
137 * base->crtc while a modeset is in progress.
139 struct intel_crtc *new_crtc;
141 enum intel_output_type type;
142 unsigned int cloneable;
143 bool connectors_active;
144 void (*hot_plug)(struct intel_encoder *);
145 bool (*compute_config)(struct intel_encoder *,
146 struct intel_crtc_state *);
147 void (*pre_pll_enable)(struct intel_encoder *);
148 void (*pre_enable)(struct intel_encoder *);
149 void (*enable)(struct intel_encoder *);
150 void (*mode_set)(struct intel_encoder *intel_encoder);
151 void (*disable)(struct intel_encoder *);
152 void (*post_disable)(struct intel_encoder *);
153 /* Read out the current hw state of this connector, returning true if
154 * the encoder is active. If the encoder is enabled it also set the pipe
155 * it is connected to in the pipe parameter. */
156 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
157 /* Reconstructs the equivalent mode flags for the current hardware
158 * state. This must be called _after_ display->get_pipe_config has
159 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
160 * be set correctly before calling this function. */
161 void (*get_config)(struct intel_encoder *,
162 struct intel_crtc_state *pipe_config);
164 * Called during system suspend after all pending requests for the
165 * encoder are flushed (for example for DP AUX transactions) and
166 * device interrupts are disabled.
168 void (*suspend)(struct intel_encoder *);
170 enum hpd_pin hpd_pin;
174 struct drm_display_mode *fixed_mode;
175 struct drm_display_mode *downclock_mode;
185 bool combination_mode; /* gen 2/4 only */
187 struct backlight_device *device;
190 void (*backlight_power)(struct intel_connector *, bool enable);
193 struct intel_connector {
194 struct drm_connector base;
196 * The fixed encoder this connector is connected to.
198 struct intel_encoder *encoder;
201 * The new encoder this connector will be driven. Only differs from
202 * encoder while a modeset is in progress.
204 struct intel_encoder *new_encoder;
206 /* Reads out the current hw, returning true if the connector is enabled
207 * and active (i.e. dpms ON state). */
208 bool (*get_hw_state)(struct intel_connector *);
211 * Removes all interfaces through which the connector is accessible
212 * - like sysfs, debugfs entries -, so that no new operations can be
213 * started on the connector. Also makes sure all currently pending
214 * operations finish before returing.
216 void (*unregister)(struct intel_connector *);
218 /* Panel info for eDP and LVDS */
219 struct intel_panel panel;
221 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
223 struct edid *detect_edid;
225 /* since POLL and HPD connectors may use the same HPD line keep the native
226 state of connector->polled in case hotplug storm detection changes it */
229 void *port; /* store this opaque as its illegal to dereference it */
231 struct intel_dp *mst_port;
234 typedef struct dpll {
246 struct intel_plane_state {
247 struct drm_plane_state base;
250 struct drm_rect clip;
254 * used only for sprite planes to determine when to implicitly
255 * enable/disable the primary plane
260 struct intel_initial_plane_config {
261 struct intel_framebuffer *fb;
267 struct intel_crtc_state {
268 struct drm_crtc_state base;
271 * quirks - bitfield with hw state readout quirks
273 * For various reasons the hw state readout code might not be able to
274 * completely faithfully read out the current state. These cases are
275 * tracked with quirk flags so that fastboot and state checker can act
278 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
279 #define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */
280 unsigned long quirks;
282 /* Pipe source size (ie. panel fitter input size)
283 * All planes will be positioned inside this space,
284 * and get clipped at the edges. */
285 int pipe_src_w, pipe_src_h;
287 /* Whether to set up the PCH/FDI. Note that we never allow sharing
288 * between pch encoders and cpu encoders. */
289 bool has_pch_encoder;
291 /* Are we sending infoframes on the attached port */
294 /* CPU Transcoder for the pipe. Currently this can only differ from the
295 * pipe on Haswell (where we have a special eDP transcoder). */
296 enum transcoder cpu_transcoder;
299 * Use reduced/limited/broadcast rbg range, compressing from the full
300 * range fed into the crtcs.
302 bool limited_color_range;
304 /* DP has a bunch of special case unfortunately, so mark the pipe
308 /* Whether we should send NULL infoframes. Required for audio. */
311 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
312 * has_dp_encoder is set. */
316 * Enable dithering, used when the selected pipe bpp doesn't match the
321 /* Controls for the clock computation, to override various stages. */
324 /* SDVO TV has a bunch of special case. To make multifunction encoders
325 * work correctly, we need to track this at runtime.*/
329 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
330 * required. This is set in the 2nd loop of calling encoder's
331 * ->compute_config if the first pick doesn't work out.
335 /* Settings for the intel dpll used on pretty much everything but
339 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
340 enum intel_dpll_id shared_dpll;
343 * - PORT_CLK_SEL for DDI ports on HSW/BDW.
344 * - enum skl_dpll on SKL
346 uint32_t ddi_pll_sel;
348 /* Actual register state of the dpll, for shared dpll cross-checking. */
349 struct intel_dpll_hw_state dpll_hw_state;
352 struct intel_link_m_n dp_m_n;
354 /* m2_n2 for eDP downclock */
355 struct intel_link_m_n dp_m2_n2;
359 * Frequence the dpll for the port should run at. Differs from the
360 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
361 * already multiplied by pixel_multiplier.
365 /* Used by SDVO (and if we ever fix it, HDMI). */
366 unsigned pixel_multiplier;
368 /* Panel fitter controls for gen2-gen4 + VLV */
372 u32 lvds_border_bits;
375 /* Panel fitter placement and size for Ironlake+ */
383 /* FDI configuration, only valid if has_pch_encoder is set. */
385 struct intel_link_m_n fdi_m_n;
391 bool dp_encoder_is_mst;
395 struct intel_pipe_wm {
396 struct intel_wm_level wm[5];
400 bool sprites_enabled;
404 struct intel_mmio_flip {
405 struct drm_i915_gem_request *req;
406 struct work_struct work;
410 struct skl_wm_level wm[8];
411 struct skl_wm_level trans_wm;
416 * Tracking of operations that need to be performed at the beginning/end of an
417 * atomic commit, outside the atomic section where interrupts are disabled.
418 * These are generally operations that grab mutexes or might otherwise sleep
419 * and thus can't be run with interrupts disabled.
421 struct intel_crtc_atomic_commit {
424 unsigned start_vbl_count;
426 /* Sleepable operations to perform before commit */
429 bool pre_disable_primary;
431 unsigned disabled_planes;
433 /* Sleepable operations to perform after commit */
437 bool post_enable_primary;
438 unsigned update_sprite_watermarks;
442 struct drm_crtc base;
445 u8 lut_r[256], lut_g[256], lut_b[256];
447 * Whether the crtc and the connected output pipeline is active. Implies
448 * that crtc->enabled is set, i.e. the current mode configuration has
449 * some outputs connected to this crtc.
452 unsigned long enabled_power_domains;
453 bool primary_enabled; /* is the primary plane (partially) visible? */
455 struct intel_overlay *overlay;
456 struct intel_unpin_work *unpin_work;
458 atomic_t unpin_work_count;
460 /* Display surface base address adjustement for pageflips. Note that on
461 * gen4+ this only adjusts up to a tile, offsets within a tile are
462 * handled in the hw itself (with the TILEOFF register). */
463 unsigned long dspaddr_offset;
465 struct drm_i915_gem_object *cursor_bo;
466 uint32_t cursor_addr;
467 int16_t cursor_width, cursor_height;
468 uint32_t cursor_cntl;
469 uint32_t cursor_size;
470 uint32_t cursor_base;
472 struct intel_initial_plane_config plane_config;
473 struct intel_crtc_state *config;
474 struct intel_crtc_state *new_config;
477 /* reset counter value when the last flip was submitted */
478 unsigned int reset_counter;
480 /* Access to these should be protected by dev_priv->irq_lock. */
481 bool cpu_fifo_underrun_disabled;
482 bool pch_fifo_underrun_disabled;
484 /* per-pipe watermark state */
486 /* watermarks currently being used */
487 struct intel_pipe_wm active;
488 /* SKL wm values currently in use */
489 struct skl_pipe_wm skl_active;
493 struct intel_mmio_flip mmio_flip;
495 struct intel_crtc_atomic_commit atomic;
498 struct intel_plane_wm_parameters {
499 uint32_t horiz_pixels;
500 uint32_t vert_pixels;
501 uint8_t bytes_per_pixel;
507 struct drm_plane base;
510 struct drm_i915_gem_object *obj;
514 /* Since we need to change the watermarks before/after
515 * enabling/disabling the planes, we need to store the parameters here
516 * as the other pieces of the struct may not reflect the values we want
517 * for the watermark calculations. Currently only Haswell uses this.
519 struct intel_plane_wm_parameters wm;
522 * NOTE: Do not place new plane state fields here (e.g., when adding
523 * new plane properties). New runtime state should now be placed in
524 * the intel_plane_state structure and accessed via drm_plane->state.
527 void (*update_plane)(struct drm_plane *plane,
528 struct drm_crtc *crtc,
529 struct drm_framebuffer *fb,
530 struct drm_i915_gem_object *obj,
531 int crtc_x, int crtc_y,
532 unsigned int crtc_w, unsigned int crtc_h,
533 uint32_t x, uint32_t y,
534 uint32_t src_w, uint32_t src_h);
535 void (*disable_plane)(struct drm_plane *plane,
536 struct drm_crtc *crtc);
537 int (*check_plane)(struct drm_plane *plane,
538 struct intel_plane_state *state);
539 void (*commit_plane)(struct drm_plane *plane,
540 struct intel_plane_state *state);
541 int (*update_colorkey)(struct drm_plane *plane,
542 struct drm_intel_sprite_colorkey *key);
543 void (*get_colorkey)(struct drm_plane *plane,
544 struct drm_intel_sprite_colorkey *key);
547 struct intel_watermark_params {
548 unsigned long fifo_size;
549 unsigned long max_wm;
550 unsigned long default_wm;
551 unsigned long guard_size;
552 unsigned long cacheline_size;
555 struct cxsr_latency {
558 unsigned long fsb_freq;
559 unsigned long mem_freq;
560 unsigned long display_sr;
561 unsigned long display_hpll_disable;
562 unsigned long cursor_sr;
563 unsigned long cursor_hpll_disable;
566 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
567 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
568 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
569 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
570 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
571 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
572 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
577 uint32_t color_range;
578 bool color_range_auto;
581 enum hdmi_force_audio force_audio;
582 bool rgb_quant_range_selectable;
583 enum hdmi_picture_aspect aspect_ratio;
584 void (*write_infoframe)(struct drm_encoder *encoder,
585 enum hdmi_infoframe_type type,
586 const void *frame, ssize_t len);
587 void (*set_infoframes)(struct drm_encoder *encoder,
589 struct drm_display_mode *adjusted_mode);
590 bool (*infoframe_enabled)(struct drm_encoder *encoder);
593 struct intel_dp_mst_encoder;
594 #define DP_MAX_DOWNSTREAM_PORTS 0x10
598 uint32_t aux_ch_ctl_reg;
601 enum hdmi_force_audio force_audio;
602 uint32_t color_range;
603 bool color_range_auto;
606 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
607 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
608 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
609 struct drm_dp_aux aux;
610 uint8_t train_set[4];
611 int panel_power_up_delay;
612 int panel_power_down_delay;
613 int panel_power_cycle_delay;
614 int backlight_on_delay;
615 int backlight_off_delay;
616 struct delayed_work panel_vdd_work;
618 unsigned long last_power_cycle;
619 unsigned long last_power_on;
620 unsigned long last_backlight_off;
622 struct notifier_block edp_notifier;
625 * Pipe whose power sequencer is currently locked into
626 * this port. Only relevant on VLV/CHV.
629 struct edp_power_seq pps_delays;
632 bool can_mst; /* this port supports mst */
634 int active_mst_links;
635 /* connector directly attached - won't be use for modeset in mst world */
636 struct intel_connector *attached_connector;
638 /* mst connector list */
639 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
640 struct drm_dp_mst_topology_mgr mst_mgr;
642 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
644 * This function returns the value we have to program the AUX_CTL
645 * register with to kick off an AUX transaction.
647 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
650 uint32_t aux_clock_divider);
653 struct intel_digital_port {
654 struct intel_encoder base;
658 struct intel_hdmi hdmi;
659 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
662 struct intel_dp_mst_encoder {
663 struct intel_encoder base;
665 struct intel_digital_port *primary;
666 void *port; /* store this opaque as its illegal to dereference it */
670 vlv_dport_to_channel(struct intel_digital_port *dport)
672 switch (dport->port) {
684 vlv_pipe_to_channel(enum pipe pipe)
697 static inline struct drm_crtc *
698 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
700 struct drm_i915_private *dev_priv = dev->dev_private;
701 return dev_priv->pipe_to_crtc_mapping[pipe];
704 static inline struct drm_crtc *
705 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
707 struct drm_i915_private *dev_priv = dev->dev_private;
708 return dev_priv->plane_to_crtc_mapping[plane];
711 struct intel_unpin_work {
712 struct work_struct work;
713 struct drm_crtc *crtc;
714 struct drm_framebuffer *old_fb;
715 struct drm_i915_gem_object *pending_flip_obj;
716 struct drm_pending_vblank_event *event;
718 #define INTEL_FLIP_INACTIVE 0
719 #define INTEL_FLIP_PENDING 1
720 #define INTEL_FLIP_COMPLETE 2
723 struct drm_i915_gem_request *flip_queued_req;
724 int flip_queued_vblank;
725 int flip_ready_vblank;
726 bool enable_stall_check;
729 struct intel_set_config {
730 struct drm_encoder **save_connector_encoders;
731 struct drm_crtc **save_encoder_crtcs;
732 bool *save_crtc_enabled;
738 struct intel_load_detect_pipe {
739 struct drm_framebuffer *release_fb;
740 bool load_detect_temp;
744 static inline struct intel_encoder *
745 intel_attached_encoder(struct drm_connector *connector)
747 return to_intel_connector(connector)->encoder;
750 static inline struct intel_digital_port *
751 enc_to_dig_port(struct drm_encoder *encoder)
753 return container_of(encoder, struct intel_digital_port, base.base);
756 static inline struct intel_dp_mst_encoder *
757 enc_to_mst(struct drm_encoder *encoder)
759 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
762 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
764 return &enc_to_dig_port(encoder)->dp;
767 static inline struct intel_digital_port *
768 dp_to_dig_port(struct intel_dp *intel_dp)
770 return container_of(intel_dp, struct intel_digital_port, dp);
773 static inline struct intel_digital_port *
774 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
776 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
780 * Returns the number of planes for this pipe, ie the number of sprites + 1
781 * (primary plane). This doesn't count the cursor plane then.
783 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
785 return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
788 /* intel_fifo_underrun.c */
789 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
790 enum pipe pipe, bool enable);
791 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
792 enum transcoder pch_transcoder,
794 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
796 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
797 enum transcoder pch_transcoder);
798 void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);
801 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
802 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
803 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
804 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
805 void gen6_reset_rps_interrupts(struct drm_device *dev);
806 void gen6_enable_rps_interrupts(struct drm_device *dev);
807 void gen6_disable_rps_interrupts(struct drm_device *dev);
808 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
809 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
810 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
811 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
814 * We only use drm_irq_uninstall() at unload and VT switch, so
815 * this is the only thing we need to check.
817 return dev_priv->pm.irqs_enabled;
820 int intel_get_crtc_scanline(struct intel_crtc *crtc);
821 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv);
824 void intel_crt_init(struct drm_device *dev);
828 void intel_prepare_ddi(struct drm_device *dev);
829 void hsw_fdi_link_train(struct drm_crtc *crtc);
830 void intel_ddi_init(struct drm_device *dev, enum port port);
831 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
832 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
833 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
834 void intel_ddi_pll_init(struct drm_device *dev);
835 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
836 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
837 enum transcoder cpu_transcoder);
838 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
839 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
840 bool intel_ddi_pll_select(struct intel_crtc *crtc,
841 struct intel_crtc_state *crtc_state);
842 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
843 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
844 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
845 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
846 void intel_ddi_get_config(struct intel_encoder *encoder,
847 struct intel_crtc_state *pipe_config);
849 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
850 void intel_ddi_clock_get(struct intel_encoder *encoder,
851 struct intel_crtc_state *pipe_config);
852 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
854 /* intel_frontbuffer.c */
855 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
856 struct intel_engine_cs *ring);
857 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
858 unsigned frontbuffer_bits);
859 void intel_frontbuffer_flip_complete(struct drm_device *dev,
860 unsigned frontbuffer_bits);
861 void intel_frontbuffer_flush(struct drm_device *dev,
862 unsigned frontbuffer_bits);
864 * intel_frontbuffer_flip - synchronous frontbuffer flip
866 * @frontbuffer_bits: frontbuffer plane tracking bits
868 * This function gets called after scheduling a flip on @obj. This is for
869 * synchronous plane updates which will happen on the next vblank and which will
870 * not get delayed by pending gpu rendering.
872 * Can be called without any locks held.
875 void intel_frontbuffer_flip(struct drm_device *dev,
876 unsigned frontbuffer_bits)
878 intel_frontbuffer_flush(dev, frontbuffer_bits);
881 int intel_fb_align_height(struct drm_device *dev, int height,
882 uint32_t pixel_format,
883 uint64_t fb_format_modifier);
884 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
888 void intel_init_audio(struct drm_device *dev);
889 void intel_audio_codec_enable(struct intel_encoder *encoder);
890 void intel_audio_codec_disable(struct intel_encoder *encoder);
891 void i915_audio_component_init(struct drm_i915_private *dev_priv);
892 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
894 /* intel_display.c */
895 extern const struct drm_plane_funcs intel_plane_funcs;
896 bool intel_has_pending_fb_unpin(struct drm_device *dev);
897 int intel_pch_rawclk(struct drm_device *dev);
898 void intel_mark_busy(struct drm_device *dev);
899 void intel_mark_idle(struct drm_device *dev);
900 void intel_crtc_restore_mode(struct drm_crtc *crtc);
901 void intel_crtc_control(struct drm_crtc *crtc, bool enable);
902 void intel_crtc_update_dpms(struct drm_crtc *crtc);
903 void intel_encoder_destroy(struct drm_encoder *encoder);
904 void intel_connector_dpms(struct drm_connector *, int mode);
905 bool intel_connector_get_hw_state(struct intel_connector *connector);
906 void intel_modeset_check_state(struct drm_device *dev);
907 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
908 struct intel_digital_port *port);
909 void intel_connector_attach_encoder(struct intel_connector *connector,
910 struct intel_encoder *encoder);
911 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
912 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
913 struct drm_crtc *crtc);
914 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
915 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
916 struct drm_file *file_priv);
917 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
919 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
921 intel_wait_for_vblank(struct drm_device *dev, int pipe)
923 drm_wait_one_vblank(dev, pipe);
925 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
926 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
927 struct intel_digital_port *dport);
928 bool intel_get_load_detect_pipe(struct drm_connector *connector,
929 struct drm_display_mode *mode,
930 struct intel_load_detect_pipe *old,
931 struct drm_modeset_acquire_ctx *ctx);
932 void intel_release_load_detect_pipe(struct drm_connector *connector,
933 struct intel_load_detect_pipe *old);
934 int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
935 struct drm_framebuffer *fb,
936 struct intel_engine_cs *pipelined);
937 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
938 struct drm_framebuffer *
939 __intel_framebuffer_create(struct drm_device *dev,
940 struct drm_mode_fb_cmd2 *mode_cmd,
941 struct drm_i915_gem_object *obj);
942 void intel_prepare_page_flip(struct drm_device *dev, int plane);
943 void intel_finish_page_flip(struct drm_device *dev, int pipe);
944 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
945 void intel_check_page_flip(struct drm_device *dev, int pipe);
946 int intel_prepare_plane_fb(struct drm_plane *plane,
947 struct drm_framebuffer *fb);
948 void intel_cleanup_plane_fb(struct drm_plane *plane,
949 struct drm_framebuffer *fb);
950 int intel_plane_atomic_get_property(struct drm_plane *plane,
951 const struct drm_plane_state *state,
952 struct drm_property *property,
954 int intel_plane_atomic_set_property(struct drm_plane *plane,
955 struct drm_plane_state *state,
956 struct drm_property *property,
959 /* shared dpll functions */
960 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
961 void assert_shared_dpll(struct drm_i915_private *dev_priv,
962 struct intel_shared_dpll *pll,
964 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
965 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
966 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
967 struct intel_crtc_state *state);
968 void intel_put_shared_dpll(struct intel_crtc *crtc);
970 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
971 const struct dpll *dpll);
972 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
974 /* modesetting asserts */
975 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
977 void assert_pll(struct drm_i915_private *dev_priv,
978 enum pipe pipe, bool state);
979 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
980 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
981 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
982 enum pipe pipe, bool state);
983 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
984 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
985 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
986 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
987 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
988 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
989 unsigned int tiling_mode,
992 void intel_prepare_reset(struct drm_device *dev);
993 void intel_finish_reset(struct drm_device *dev);
994 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
995 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
996 void intel_dp_get_m_n(struct intel_crtc *crtc,
997 struct intel_crtc_state *pipe_config);
998 void intel_dp_set_m_n(struct intel_crtc *crtc);
999 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1001 ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
1003 bool intel_crtc_active(struct drm_crtc *crtc);
1004 void hsw_enable_ips(struct intel_crtc *crtc);
1005 void hsw_disable_ips(struct intel_crtc *crtc);
1006 enum intel_display_power_domain
1007 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1008 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1009 struct intel_crtc_state *pipe_config);
1010 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
1011 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
1014 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
1015 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1016 struct intel_connector *intel_connector);
1017 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1018 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
1019 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1020 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1021 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1022 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1023 bool intel_dp_compute_config(struct intel_encoder *encoder,
1024 struct intel_crtc_state *pipe_config);
1025 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1026 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1028 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1029 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1030 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1031 void intel_edp_panel_on(struct intel_dp *intel_dp);
1032 void intel_edp_panel_off(struct intel_dp *intel_dp);
1033 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1034 void intel_dp_mst_suspend(struct drm_device *dev);
1035 void intel_dp_mst_resume(struct drm_device *dev);
1036 int intel_dp_max_link_bw(struct intel_dp *intel_dp);
1037 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1038 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1039 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1040 void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes);
1041 void intel_plane_destroy(struct drm_plane *plane);
1042 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1043 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1044 void intel_edp_drrs_invalidate(struct drm_device *dev,
1045 unsigned frontbuffer_bits);
1046 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1048 /* intel_dp_mst.c */
1049 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1050 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1052 void intel_dsi_init(struct drm_device *dev);
1056 void intel_dvo_init(struct drm_device *dev);
1059 /* legacy fbdev emulation in intel_fbdev.c */
1060 #ifdef CONFIG_DRM_I915_FBDEV
1061 extern int intel_fbdev_init(struct drm_device *dev);
1062 extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
1063 extern void intel_fbdev_fini(struct drm_device *dev);
1064 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1065 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1066 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1068 static inline int intel_fbdev_init(struct drm_device *dev)
1073 static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
1077 static inline void intel_fbdev_fini(struct drm_device *dev)
1081 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1085 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1091 bool intel_fbc_enabled(struct drm_device *dev);
1092 void intel_fbc_update(struct drm_device *dev);
1093 void intel_fbc_init(struct drm_i915_private *dev_priv);
1094 void intel_fbc_disable(struct drm_device *dev);
1095 void bdw_fbc_sw_flush(struct drm_device *dev, u32 value);
1098 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
1099 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1100 struct intel_connector *intel_connector);
1101 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1102 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1103 struct intel_crtc_state *pipe_config);
1107 void intel_lvds_init(struct drm_device *dev);
1108 bool intel_is_dual_link_lvds(struct drm_device *dev);
1112 int intel_connector_update_modes(struct drm_connector *connector,
1114 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1115 void intel_attach_force_audio_property(struct drm_connector *connector);
1116 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1119 /* intel_overlay.c */
1120 void intel_setup_overlay(struct drm_device *dev);
1121 void intel_cleanup_overlay(struct drm_device *dev);
1122 int intel_overlay_switch_off(struct intel_overlay *overlay);
1123 int intel_overlay_put_image(struct drm_device *dev, void *data,
1124 struct drm_file *file_priv);
1125 int intel_overlay_attrs(struct drm_device *dev, void *data,
1126 struct drm_file *file_priv);
1127 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1131 int intel_panel_init(struct intel_panel *panel,
1132 struct drm_display_mode *fixed_mode,
1133 struct drm_display_mode *downclock_mode);
1134 void intel_panel_fini(struct intel_panel *panel);
1135 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1136 struct drm_display_mode *adjusted_mode);
1137 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1138 struct intel_crtc_state *pipe_config,
1140 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1141 struct intel_crtc_state *pipe_config,
1143 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1144 u32 level, u32 max);
1145 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1146 void intel_panel_enable_backlight(struct intel_connector *connector);
1147 void intel_panel_disable_backlight(struct intel_connector *connector);
1148 void intel_panel_destroy_backlight(struct drm_connector *connector);
1149 void intel_panel_init_backlight_funcs(struct drm_device *dev);
1150 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1151 extern struct drm_display_mode *intel_find_panel_downclock(
1152 struct drm_device *dev,
1153 struct drm_display_mode *fixed_mode,
1154 struct drm_connector *connector);
1155 void intel_backlight_register(struct drm_device *dev);
1156 void intel_backlight_unregister(struct drm_device *dev);
1160 void intel_psr_enable(struct intel_dp *intel_dp);
1161 void intel_psr_disable(struct intel_dp *intel_dp);
1162 void intel_psr_invalidate(struct drm_device *dev,
1163 unsigned frontbuffer_bits);
1164 void intel_psr_flush(struct drm_device *dev,
1165 unsigned frontbuffer_bits);
1166 void intel_psr_init(struct drm_device *dev);
1168 /* intel_runtime_pm.c */
1169 int intel_power_domains_init(struct drm_i915_private *);
1170 void intel_power_domains_fini(struct drm_i915_private *);
1171 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
1172 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1174 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1175 enum intel_display_power_domain domain);
1176 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1177 enum intel_display_power_domain domain);
1178 void intel_display_power_get(struct drm_i915_private *dev_priv,
1179 enum intel_display_power_domain domain);
1180 void intel_display_power_put(struct drm_i915_private *dev_priv,
1181 enum intel_display_power_domain domain);
1182 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
1183 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
1184 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1185 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1186 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1188 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1191 void intel_init_clock_gating(struct drm_device *dev);
1192 void intel_suspend_hw(struct drm_device *dev);
1193 int ilk_wm_max_level(const struct drm_device *dev);
1194 void intel_update_watermarks(struct drm_crtc *crtc);
1195 void intel_update_sprite_watermarks(struct drm_plane *plane,
1196 struct drm_crtc *crtc,
1197 uint32_t sprite_width,
1198 uint32_t sprite_height,
1200 bool enabled, bool scaled);
1201 void intel_init_pm(struct drm_device *dev);
1202 void intel_pm_setup(struct drm_device *dev);
1203 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1204 void intel_gpu_ips_teardown(void);
1205 void intel_init_gt_powersave(struct drm_device *dev);
1206 void intel_cleanup_gt_powersave(struct drm_device *dev);
1207 void intel_enable_gt_powersave(struct drm_device *dev);
1208 void intel_disable_gt_powersave(struct drm_device *dev);
1209 void intel_suspend_gt_powersave(struct drm_device *dev);
1210 void intel_reset_gt_powersave(struct drm_device *dev);
1211 void ironlake_teardown_rc6(struct drm_device *dev);
1212 void gen6_update_ring_freq(struct drm_device *dev);
1213 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1214 void gen6_rps_boost(struct drm_i915_private *dev_priv);
1215 void ilk_wm_get_hw_state(struct drm_device *dev);
1216 void skl_wm_get_hw_state(struct drm_device *dev);
1217 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1218 struct skl_ddb_allocation *ddb /* out */);
1222 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1225 /* intel_sprite.c */
1226 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1227 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1229 int intel_plane_restore(struct drm_plane *plane);
1230 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1231 struct drm_file *file_priv);
1232 int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
1233 struct drm_file *file_priv);
1234 bool intel_pipe_update_start(struct intel_crtc *crtc,
1235 uint32_t *start_vbl_count);
1236 void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count);
1237 void intel_post_enable_primary(struct drm_crtc *crtc);
1238 void intel_pre_disable_primary(struct drm_crtc *crtc);
1241 void intel_tv_init(struct drm_device *dev);
1243 /* intel_atomic.c */
1244 int intel_atomic_check(struct drm_device *dev,
1245 struct drm_atomic_state *state);
1246 int intel_atomic_commit(struct drm_device *dev,
1247 struct drm_atomic_state *state,
1249 int intel_connector_atomic_get_property(struct drm_connector *connector,
1250 const struct drm_connector_state *state,
1251 struct drm_property *property,
1253 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1254 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1255 struct drm_crtc_state *state);
1257 /* intel_atomic_plane.c */
1258 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1259 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1260 void intel_plane_destroy_state(struct drm_plane *plane,
1261 struct drm_plane_state *state);
1262 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1264 #endif /* __INTEL_DRV_H__ */