2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/i2c.h>
29 #include <linux/hdmi.h>
30 #include <drm/i915_drm.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_fb_helper.h>
35 #include <drm/drm_dp_mst_helper.h>
38 * _wait_for - magic (register) wait macro
40 * Does the right thing for modeset paths when run under kdgb or similar atomic
41 * contexts. Note that it's important that we check the condition again after
42 * having timed out, since the timeout could be due to preemption or similar and
43 * we've never had a chance to check the condition before the timeout.
45 #define _wait_for(COND, MS, W) ({ \
46 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
49 if (time_after(jiffies, timeout__)) { \
54 if (W && drm_can_sleep()) { \
63 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
64 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
65 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
66 DIV_ROUND_UP((US), 1000), 0)
68 #define KHz(x) (1000 * (x))
69 #define MHz(x) KHz(1000 * (x))
72 * Display related stuff
75 /* store information about an Ixxx DVO */
76 /* The i830->i865 use multiple DVOs with multiple i2cs */
77 /* the i915, i945 have a single sDVO i2c bus - which is different */
79 /* maximum connectors per crtcs in the mode set */
81 /* Maximum cursor sizes */
82 #define GEN2_CURSOR_WIDTH 64
83 #define GEN2_CURSOR_HEIGHT 64
84 #define MAX_CURSOR_WIDTH 256
85 #define MAX_CURSOR_HEIGHT 256
87 #define INTEL_I2C_BUS_DVO 1
88 #define INTEL_I2C_BUS_SDVO 2
90 /* these are outputs from the chip - integrated only
91 external chips are via DVO or SDVO output */
92 #define INTEL_OUTPUT_UNUSED 0
93 #define INTEL_OUTPUT_ANALOG 1
94 #define INTEL_OUTPUT_DVO 2
95 #define INTEL_OUTPUT_SDVO 3
96 #define INTEL_OUTPUT_LVDS 4
97 #define INTEL_OUTPUT_TVOUT 5
98 #define INTEL_OUTPUT_HDMI 6
99 #define INTEL_OUTPUT_DISPLAYPORT 7
100 #define INTEL_OUTPUT_EDP 8
101 #define INTEL_OUTPUT_DSI 9
102 #define INTEL_OUTPUT_UNKNOWN 10
103 #define INTEL_OUTPUT_DP_MST 11
105 #define INTEL_DVO_CHIP_NONE 0
106 #define INTEL_DVO_CHIP_LVDS 1
107 #define INTEL_DVO_CHIP_TMDS 2
108 #define INTEL_DVO_CHIP_TVOUT 4
110 #define INTEL_DSI_VIDEO_MODE 0
111 #define INTEL_DSI_COMMAND_MODE 1
113 struct intel_framebuffer {
114 struct drm_framebuffer base;
115 struct drm_i915_gem_object *obj;
119 struct drm_fb_helper helper;
120 struct intel_framebuffer *fb;
121 struct list_head fbdev_list;
122 struct drm_display_mode *our_mode;
126 struct intel_encoder {
127 struct drm_encoder base;
129 * The new crtc this encoder will be driven from. Only differs from
130 * base->crtc while a modeset is in progress.
132 struct intel_crtc *new_crtc;
135 unsigned int cloneable;
136 bool connectors_active;
137 void (*hot_plug)(struct intel_encoder *);
138 bool (*compute_config)(struct intel_encoder *,
139 struct intel_crtc_config *);
140 void (*pre_pll_enable)(struct intel_encoder *);
141 void (*pre_enable)(struct intel_encoder *);
142 void (*enable)(struct intel_encoder *);
143 void (*mode_set)(struct intel_encoder *intel_encoder);
144 void (*disable)(struct intel_encoder *);
145 void (*post_disable)(struct intel_encoder *);
146 /* Read out the current hw state of this connector, returning true if
147 * the encoder is active. If the encoder is enabled it also set the pipe
148 * it is connected to in the pipe parameter. */
149 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
150 /* Reconstructs the equivalent mode flags for the current hardware
151 * state. This must be called _after_ display->get_pipe_config has
152 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
153 * be set correctly before calling this function. */
154 void (*get_config)(struct intel_encoder *,
155 struct intel_crtc_config *pipe_config);
157 enum hpd_pin hpd_pin;
161 struct drm_display_mode *fixed_mode;
162 struct drm_display_mode *downclock_mode;
172 bool combination_mode; /* gen 2/4 only */
174 struct backlight_device *device;
178 struct intel_connector {
179 struct drm_connector base;
181 * The fixed encoder this connector is connected to.
183 struct intel_encoder *encoder;
186 * The new encoder this connector will be driven. Only differs from
187 * encoder while a modeset is in progress.
189 struct intel_encoder *new_encoder;
191 /* Reads out the current hw, returning true if the connector is enabled
192 * and active (i.e. dpms ON state). */
193 bool (*get_hw_state)(struct intel_connector *);
196 * Removes all interfaces through which the connector is accessible
197 * - like sysfs, debugfs entries -, so that no new operations can be
198 * started on the connector. Also makes sure all currently pending
199 * operations finish before returing.
201 void (*unregister)(struct intel_connector *);
203 /* Panel info for eDP and LVDS */
204 struct intel_panel panel;
206 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
209 /* since POLL and HPD connectors may use the same HPD line keep the native
210 state of connector->polled in case hotplug storm detection changes it */
213 void *port; /* store this opaque as its illegal to dereference it */
215 struct intel_dp *mst_port;
218 typedef struct dpll {
230 struct intel_plane_config {
236 struct intel_crtc_config {
238 * quirks - bitfield with hw state readout quirks
240 * For various reasons the hw state readout code might not be able to
241 * completely faithfully read out the current state. These cases are
242 * tracked with quirk flags so that fastboot and state checker can act
245 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
246 #define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */
247 unsigned long quirks;
249 /* User requested mode, only valid as a starting point to
250 * compute adjusted_mode, except in the case of (S)DVO where
251 * it's also for the output timings of the (S)DVO chip.
252 * adjusted_mode will then correspond to the S(DVO) chip's
253 * preferred input timings. */
254 struct drm_display_mode requested_mode;
255 /* Actual pipe timings ie. what we program into the pipe timing
256 * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
257 struct drm_display_mode adjusted_mode;
259 /* Pipe source size (ie. panel fitter input size)
260 * All planes will be positioned inside this space,
261 * and get clipped at the edges. */
262 int pipe_src_w, pipe_src_h;
264 /* Whether to set up the PCH/FDI. Note that we never allow sharing
265 * between pch encoders and cpu encoders. */
266 bool has_pch_encoder;
268 /* CPU Transcoder for the pipe. Currently this can only differ from the
269 * pipe on Haswell (where we have a special eDP transcoder). */
270 enum transcoder cpu_transcoder;
273 * Use reduced/limited/broadcast rbg range, compressing from the full
274 * range fed into the crtcs.
276 bool limited_color_range;
278 /* DP has a bunch of special case unfortunately, so mark the pipe
282 /* Whether we should send NULL infoframes. Required for audio. */
285 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
286 * has_dp_encoder is set. */
290 * Enable dithering, used when the selected pipe bpp doesn't match the
295 /* Controls for the clock computation, to override various stages. */
298 /* SDVO TV has a bunch of special case. To make multifunction encoders
299 * work correctly, we need to track this at runtime.*/
303 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
304 * required. This is set in the 2nd loop of calling encoder's
305 * ->compute_config if the first pick doesn't work out.
309 /* Settings for the intel dpll used on pretty much everything but
313 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
314 enum intel_dpll_id shared_dpll;
316 /* PORT_CLK_SEL for DDI ports. */
317 uint32_t ddi_pll_sel;
319 /* Actual register state of the dpll, for shared dpll cross-checking. */
320 struct intel_dpll_hw_state dpll_hw_state;
323 struct intel_link_m_n dp_m_n;
325 /* m2_n2 for eDP downclock */
326 struct intel_link_m_n dp_m2_n2;
329 * Frequence the dpll for the port should run at. Differs from the
330 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
331 * already multiplied by pixel_multiplier.
335 /* Used by SDVO (and if we ever fix it, HDMI). */
336 unsigned pixel_multiplier;
338 /* Panel fitter controls for gen2-gen4 + VLV */
342 u32 lvds_border_bits;
345 /* Panel fitter placement and size for Ironlake+ */
353 /* FDI configuration, only valid if has_pch_encoder is set. */
355 struct intel_link_m_n fdi_m_n;
361 bool dp_encoder_is_mst;
365 struct intel_pipe_wm {
366 struct intel_wm_level wm[5];
370 bool sprites_enabled;
374 struct intel_mmio_flip {
380 struct drm_crtc base;
383 u8 lut_r[256], lut_g[256], lut_b[256];
385 * Whether the crtc and the connected output pipeline is active. Implies
386 * that crtc->enabled is set, i.e. the current mode configuration has
387 * some outputs connected to this crtc.
390 unsigned long enabled_power_domains;
391 bool primary_enabled; /* is the primary plane (partially) visible? */
393 struct intel_overlay *overlay;
394 struct intel_unpin_work *unpin_work;
396 atomic_t unpin_work_count;
398 /* Display surface base address adjustement for pageflips. Note that on
399 * gen4+ this only adjusts up to a tile, offsets within a tile are
400 * handled in the hw itself (with the TILEOFF register). */
401 unsigned long dspaddr_offset;
403 struct drm_i915_gem_object *cursor_bo;
404 uint32_t cursor_addr;
405 int16_t cursor_width, cursor_height;
406 uint32_t cursor_cntl;
407 uint32_t cursor_base;
409 struct intel_plane_config plane_config;
410 struct intel_crtc_config config;
411 struct intel_crtc_config *new_config;
414 /* reset counter value when the last flip was submitted */
415 unsigned int reset_counter;
417 /* Access to these should be protected by dev_priv->irq_lock. */
418 bool cpu_fifo_underrun_disabled;
419 bool pch_fifo_underrun_disabled;
421 /* per-pipe watermark state */
423 /* watermarks currently being used */
424 struct intel_pipe_wm active;
427 wait_queue_head_t vbl_wait;
430 struct intel_mmio_flip mmio_flip;
433 struct intel_plane_wm_parameters {
434 uint32_t horiz_pixels;
435 uint32_t vert_pixels;
436 uint8_t bytes_per_pixel;
442 struct drm_plane base;
445 struct drm_i915_gem_object *obj;
449 unsigned int crtc_w, crtc_h;
450 uint32_t src_x, src_y;
451 uint32_t src_w, src_h;
453 /* Since we need to change the watermarks before/after
454 * enabling/disabling the planes, we need to store the parameters here
455 * as the other pieces of the struct may not reflect the values we want
456 * for the watermark calculations. Currently only Haswell uses this.
458 struct intel_plane_wm_parameters wm;
460 void (*update_plane)(struct drm_plane *plane,
461 struct drm_crtc *crtc,
462 struct drm_framebuffer *fb,
463 struct drm_i915_gem_object *obj,
464 int crtc_x, int crtc_y,
465 unsigned int crtc_w, unsigned int crtc_h,
466 uint32_t x, uint32_t y,
467 uint32_t src_w, uint32_t src_h);
468 void (*disable_plane)(struct drm_plane *plane,
469 struct drm_crtc *crtc);
470 int (*update_colorkey)(struct drm_plane *plane,
471 struct drm_intel_sprite_colorkey *key);
472 void (*get_colorkey)(struct drm_plane *plane,
473 struct drm_intel_sprite_colorkey *key);
476 struct intel_watermark_params {
477 unsigned long fifo_size;
478 unsigned long max_wm;
479 unsigned long default_wm;
480 unsigned long guard_size;
481 unsigned long cacheline_size;
484 struct cxsr_latency {
487 unsigned long fsb_freq;
488 unsigned long mem_freq;
489 unsigned long display_sr;
490 unsigned long display_hpll_disable;
491 unsigned long cursor_sr;
492 unsigned long cursor_hpll_disable;
495 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
496 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
497 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
498 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
499 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
500 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
505 uint32_t color_range;
506 bool color_range_auto;
509 enum hdmi_force_audio force_audio;
510 bool rgb_quant_range_selectable;
511 enum hdmi_picture_aspect aspect_ratio;
512 void (*write_infoframe)(struct drm_encoder *encoder,
513 enum hdmi_infoframe_type type,
514 const void *frame, ssize_t len);
515 void (*set_infoframes)(struct drm_encoder *encoder,
517 struct drm_display_mode *adjusted_mode);
520 struct intel_dp_mst_encoder;
521 #define DP_MAX_DOWNSTREAM_PORTS 0x10
524 * HIGH_RR is the highest eDP panel refresh rate read from EDID
525 * LOW_RR is the lowest eDP panel refresh rate found from EDID
526 * parsing for same resolution.
528 enum edp_drrs_refresh_rate_type {
531 DRRS_MAX_RR, /* RR count */
536 uint32_t aux_ch_ctl_reg;
539 enum hdmi_force_audio force_audio;
540 uint32_t color_range;
541 bool color_range_auto;
544 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
545 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
546 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
547 struct drm_dp_aux aux;
548 uint8_t train_set[4];
549 int panel_power_up_delay;
550 int panel_power_down_delay;
551 int panel_power_cycle_delay;
552 int backlight_on_delay;
553 int backlight_off_delay;
554 struct delayed_work panel_vdd_work;
556 unsigned long last_power_cycle;
557 unsigned long last_power_on;
558 unsigned long last_backlight_off;
560 struct notifier_block edp_notifier;
563 bool can_mst; /* this port supports mst */
565 int active_mst_links;
566 /* connector directly attached - won't be use for modeset in mst world */
567 struct intel_connector *attached_connector;
569 /* mst connector list */
570 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
571 struct drm_dp_mst_topology_mgr mst_mgr;
573 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
575 * This function returns the value we have to program the AUX_CTL
576 * register with to kick off an AUX transaction.
578 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
581 uint32_t aux_clock_divider);
583 enum drrs_support_type type;
584 enum edp_drrs_refresh_rate_type refresh_rate_type;
590 struct intel_digital_port {
591 struct intel_encoder base;
595 struct intel_hdmi hdmi;
596 bool (*hpd_pulse)(struct intel_digital_port *, bool);
599 struct intel_dp_mst_encoder {
600 struct intel_encoder base;
602 struct intel_digital_port *primary;
603 void *port; /* store this opaque as its illegal to dereference it */
607 vlv_dport_to_channel(struct intel_digital_port *dport)
609 switch (dport->port) {
621 vlv_pipe_to_channel(enum pipe pipe)
634 static inline struct drm_crtc *
635 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
637 struct drm_i915_private *dev_priv = dev->dev_private;
638 return dev_priv->pipe_to_crtc_mapping[pipe];
641 static inline struct drm_crtc *
642 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
644 struct drm_i915_private *dev_priv = dev->dev_private;
645 return dev_priv->plane_to_crtc_mapping[plane];
648 struct intel_unpin_work {
649 struct work_struct work;
650 struct drm_crtc *crtc;
651 struct drm_i915_gem_object *old_fb_obj;
652 struct drm_i915_gem_object *pending_flip_obj;
653 struct drm_pending_vblank_event *event;
655 #define INTEL_FLIP_INACTIVE 0
656 #define INTEL_FLIP_PENDING 1
657 #define INTEL_FLIP_COMPLETE 2
660 bool enable_stall_check;
663 struct intel_set_config {
664 struct drm_encoder **save_connector_encoders;
665 struct drm_crtc **save_encoder_crtcs;
666 bool *save_crtc_enabled;
672 struct intel_load_detect_pipe {
673 struct drm_framebuffer *release_fb;
674 bool load_detect_temp;
678 static inline struct intel_encoder *
679 intel_attached_encoder(struct drm_connector *connector)
681 return to_intel_connector(connector)->encoder;
684 static inline struct intel_digital_port *
685 enc_to_dig_port(struct drm_encoder *encoder)
687 return container_of(encoder, struct intel_digital_port, base.base);
690 static inline struct intel_dp_mst_encoder *
691 enc_to_mst(struct drm_encoder *encoder)
693 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
696 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
698 return &enc_to_dig_port(encoder)->dp;
701 static inline struct intel_digital_port *
702 dp_to_dig_port(struct intel_dp *intel_dp)
704 return container_of(intel_dp, struct intel_digital_port, dp);
707 static inline struct intel_digital_port *
708 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
710 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
715 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
716 enum pipe pipe, bool enable);
717 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
718 enum transcoder pch_transcoder,
720 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
721 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
722 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
723 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
724 void gen8_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
725 void gen8_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
726 void intel_runtime_pm_disable_interrupts(struct drm_device *dev);
727 void intel_runtime_pm_restore_interrupts(struct drm_device *dev);
728 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
731 * We only use drm_irq_uninstall() at unload and VT switch, so
732 * this is the only thing we need to check.
734 return !dev_priv->pm._irqs_disabled;
737 int intel_get_crtc_scanline(struct intel_crtc *crtc);
738 void i9xx_check_fifo_underruns(struct drm_device *dev);
739 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv);
742 void intel_crt_init(struct drm_device *dev);
746 void intel_prepare_ddi(struct drm_device *dev);
747 void hsw_fdi_link_train(struct drm_crtc *crtc);
748 void intel_ddi_init(struct drm_device *dev, enum port port);
749 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
750 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
751 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
752 void intel_ddi_pll_init(struct drm_device *dev);
753 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
754 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
755 enum transcoder cpu_transcoder);
756 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
757 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
758 bool intel_ddi_pll_select(struct intel_crtc *crtc);
759 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
760 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
761 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
762 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
763 void intel_ddi_get_config(struct intel_encoder *encoder,
764 struct intel_crtc_config *pipe_config);
766 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
767 void intel_ddi_clock_get(struct intel_encoder *encoder,
768 struct intel_crtc_config *pipe_config);
769 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
771 /* intel_display.c */
772 const char *intel_output_name(int output);
773 bool intel_has_pending_fb_unpin(struct drm_device *dev);
774 int intel_pch_rawclk(struct drm_device *dev);
775 void intel_mark_busy(struct drm_device *dev);
776 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
777 struct intel_engine_cs *ring);
778 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
779 unsigned frontbuffer_bits);
780 void intel_frontbuffer_flip_complete(struct drm_device *dev,
781 unsigned frontbuffer_bits);
782 void intel_frontbuffer_flush(struct drm_device *dev,
783 unsigned frontbuffer_bits);
785 * intel_frontbuffer_flip - prepare frontbuffer flip
787 * @frontbuffer_bits: frontbuffer plane tracking bits
789 * This function gets called after scheduling a flip on @obj. This is for
790 * synchronous plane updates which will happen on the next vblank and which will
791 * not get delayed by pending gpu rendering.
793 * Can be called without any locks held.
796 void intel_frontbuffer_flip(struct drm_device *dev,
797 unsigned frontbuffer_bits)
799 intel_frontbuffer_flush(dev, frontbuffer_bits);
802 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
803 void intel_mark_idle(struct drm_device *dev);
804 void intel_crtc_restore_mode(struct drm_crtc *crtc);
805 void intel_crtc_control(struct drm_crtc *crtc, bool enable);
806 void intel_crtc_update_dpms(struct drm_crtc *crtc);
807 void intel_encoder_destroy(struct drm_encoder *encoder);
808 void intel_connector_dpms(struct drm_connector *, int mode);
809 bool intel_connector_get_hw_state(struct intel_connector *connector);
810 void intel_modeset_check_state(struct drm_device *dev);
811 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
812 struct intel_digital_port *port);
813 void intel_connector_attach_encoder(struct intel_connector *connector,
814 struct intel_encoder *encoder);
815 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
816 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
817 struct drm_crtc *crtc);
818 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
819 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
820 struct drm_file *file_priv);
821 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
823 void intel_wait_for_vblank(struct drm_device *dev, int pipe);
824 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
825 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
826 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
827 struct intel_digital_port *dport);
828 bool intel_get_load_detect_pipe(struct drm_connector *connector,
829 struct drm_display_mode *mode,
830 struct intel_load_detect_pipe *old,
831 struct drm_modeset_acquire_ctx *ctx);
832 void intel_release_load_detect_pipe(struct drm_connector *connector,
833 struct intel_load_detect_pipe *old,
834 struct drm_modeset_acquire_ctx *ctx);
835 int intel_pin_and_fence_fb_obj(struct drm_device *dev,
836 struct drm_i915_gem_object *obj,
837 struct intel_engine_cs *pipelined);
838 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
839 struct drm_framebuffer *
840 __intel_framebuffer_create(struct drm_device *dev,
841 struct drm_mode_fb_cmd2 *mode_cmd,
842 struct drm_i915_gem_object *obj);
843 void intel_prepare_page_flip(struct drm_device *dev, int plane);
844 void intel_finish_page_flip(struct drm_device *dev, int pipe);
845 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
847 /* shared dpll functions */
848 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
849 void assert_shared_dpll(struct drm_i915_private *dev_priv,
850 struct intel_shared_dpll *pll,
852 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
853 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
854 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc);
855 void intel_put_shared_dpll(struct intel_crtc *crtc);
857 /* modesetting asserts */
858 void assert_pll(struct drm_i915_private *dev_priv,
859 enum pipe pipe, bool state);
860 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
861 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
862 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
863 enum pipe pipe, bool state);
864 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
865 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
866 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
867 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
868 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
869 void intel_write_eld(struct drm_encoder *encoder,
870 struct drm_display_mode *mode);
871 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
872 unsigned int tiling_mode,
875 void intel_display_handle_reset(struct drm_device *dev);
876 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
877 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
878 void intel_dp_get_m_n(struct intel_crtc *crtc,
879 struct intel_crtc_config *pipe_config);
880 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
882 ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
884 bool intel_crtc_active(struct drm_crtc *crtc);
885 void hsw_enable_ips(struct intel_crtc *crtc);
886 void hsw_disable_ips(struct intel_crtc *crtc);
887 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
888 enum intel_display_power_domain
889 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
890 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
891 struct intel_crtc_config *pipe_config);
892 int intel_format_to_fourcc(int format);
893 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
897 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
898 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
899 struct intel_connector *intel_connector);
900 void intel_dp_start_link_train(struct intel_dp *intel_dp);
901 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
902 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
903 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
904 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
905 void intel_dp_check_link_status(struct intel_dp *intel_dp);
906 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
907 bool intel_dp_compute_config(struct intel_encoder *encoder,
908 struct intel_crtc_config *pipe_config);
909 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
910 bool intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
912 void intel_edp_backlight_on(struct intel_dp *intel_dp);
913 void intel_edp_backlight_off(struct intel_dp *intel_dp);
914 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
915 void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder);
916 void intel_edp_panel_on(struct intel_dp *intel_dp);
917 void intel_edp_panel_off(struct intel_dp *intel_dp);
918 void intel_edp_psr_enable(struct intel_dp *intel_dp);
919 void intel_edp_psr_disable(struct intel_dp *intel_dp);
920 void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate);
921 void intel_edp_psr_invalidate(struct drm_device *dev,
922 unsigned frontbuffer_bits);
923 void intel_edp_psr_flush(struct drm_device *dev,
924 unsigned frontbuffer_bits);
925 void intel_edp_psr_init(struct drm_device *dev);
927 int intel_dp_handle_hpd_irq(struct intel_digital_port *digport, bool long_hpd);
928 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
929 void intel_dp_mst_suspend(struct drm_device *dev);
930 void intel_dp_mst_resume(struct drm_device *dev);
931 int intel_dp_max_link_bw(struct intel_dp *intel_dp);
932 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
934 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
935 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
937 void intel_dsi_init(struct drm_device *dev);
941 void intel_dvo_init(struct drm_device *dev);
944 /* legacy fbdev emulation in intel_fbdev.c */
945 #ifdef CONFIG_DRM_I915_FBDEV
946 extern int intel_fbdev_init(struct drm_device *dev);
947 extern void intel_fbdev_initial_config(struct drm_device *dev);
948 extern void intel_fbdev_fini(struct drm_device *dev);
949 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
950 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
951 extern void intel_fbdev_restore_mode(struct drm_device *dev);
953 static inline int intel_fbdev_init(struct drm_device *dev)
958 static inline void intel_fbdev_initial_config(struct drm_device *dev)
962 static inline void intel_fbdev_fini(struct drm_device *dev)
966 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state)
970 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
976 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
977 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
978 struct intel_connector *intel_connector);
979 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
980 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
981 struct intel_crtc_config *pipe_config);
985 void intel_lvds_init(struct drm_device *dev);
986 bool intel_is_dual_link_lvds(struct drm_device *dev);
990 int intel_connector_update_modes(struct drm_connector *connector,
992 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
993 void intel_attach_force_audio_property(struct drm_connector *connector);
994 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
997 /* intel_overlay.c */
998 void intel_setup_overlay(struct drm_device *dev);
999 void intel_cleanup_overlay(struct drm_device *dev);
1000 int intel_overlay_switch_off(struct intel_overlay *overlay);
1001 int intel_overlay_put_image(struct drm_device *dev, void *data,
1002 struct drm_file *file_priv);
1003 int intel_overlay_attrs(struct drm_device *dev, void *data,
1004 struct drm_file *file_priv);
1008 int intel_panel_init(struct intel_panel *panel,
1009 struct drm_display_mode *fixed_mode,
1010 struct drm_display_mode *downclock_mode);
1011 void intel_panel_fini(struct intel_panel *panel);
1012 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1013 struct drm_display_mode *adjusted_mode);
1014 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1015 struct intel_crtc_config *pipe_config,
1017 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1018 struct intel_crtc_config *pipe_config,
1020 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1021 u32 level, u32 max);
1022 int intel_panel_setup_backlight(struct drm_connector *connector);
1023 void intel_panel_enable_backlight(struct intel_connector *connector);
1024 void intel_panel_disable_backlight(struct intel_connector *connector);
1025 void intel_panel_destroy_backlight(struct drm_connector *connector);
1026 void intel_panel_init_backlight_funcs(struct drm_device *dev);
1027 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1028 extern struct drm_display_mode *intel_find_panel_downclock(
1029 struct drm_device *dev,
1030 struct drm_display_mode *fixed_mode,
1031 struct drm_connector *connector);
1034 void intel_init_clock_gating(struct drm_device *dev);
1035 void intel_suspend_hw(struct drm_device *dev);
1036 int ilk_wm_max_level(const struct drm_device *dev);
1037 void intel_update_watermarks(struct drm_crtc *crtc);
1038 void intel_update_sprite_watermarks(struct drm_plane *plane,
1039 struct drm_crtc *crtc,
1040 uint32_t sprite_width,
1041 uint32_t sprite_height,
1043 bool enabled, bool scaled);
1044 void intel_init_pm(struct drm_device *dev);
1045 void intel_pm_setup(struct drm_device *dev);
1046 bool intel_fbc_enabled(struct drm_device *dev);
1047 void intel_update_fbc(struct drm_device *dev);
1048 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1049 void intel_gpu_ips_teardown(void);
1050 int intel_power_domains_init(struct drm_i915_private *);
1051 void intel_power_domains_remove(struct drm_i915_private *);
1052 bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
1053 enum intel_display_power_domain domain);
1054 bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv,
1055 enum intel_display_power_domain domain);
1056 void intel_display_power_get(struct drm_i915_private *dev_priv,
1057 enum intel_display_power_domain domain);
1058 void intel_display_power_put(struct drm_i915_private *dev_priv,
1059 enum intel_display_power_domain domain);
1060 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
1061 void intel_init_gt_powersave(struct drm_device *dev);
1062 void intel_cleanup_gt_powersave(struct drm_device *dev);
1063 void intel_enable_gt_powersave(struct drm_device *dev);
1064 void intel_disable_gt_powersave(struct drm_device *dev);
1065 void intel_suspend_gt_powersave(struct drm_device *dev);
1066 void intel_reset_gt_powersave(struct drm_device *dev);
1067 void ironlake_teardown_rc6(struct drm_device *dev);
1068 void gen6_update_ring_freq(struct drm_device *dev);
1069 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1070 void gen6_rps_boost(struct drm_i915_private *dev_priv);
1071 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
1072 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
1073 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1074 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1075 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1076 void intel_init_runtime_pm(struct drm_i915_private *dev_priv);
1077 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv);
1078 void ilk_wm_get_hw_state(struct drm_device *dev);
1082 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1085 /* intel_sprite.c */
1086 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1087 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1089 void intel_plane_restore(struct drm_plane *plane);
1090 void intel_plane_disable(struct drm_plane *plane);
1091 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1092 struct drm_file *file_priv);
1093 int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
1094 struct drm_file *file_priv);
1098 void intel_tv_init(struct drm_device *dev);
1100 #endif /* __INTEL_DRV_H__ */