drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/notifier.h>
  32 #include <linux/reboot.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_edid.h>
  37 #include "intel_drv.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40
  41 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  42
  43 struct dp_link_dpll {
  44         int link_bw;
  45         struct dpll dpll;
  46 };
  47
  48 static const struct dp_link_dpll gen4_dpll[] = {
  49         { DP_LINK_BW_1_62,
  50                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  51         { DP_LINK_BW_2_7,
  52                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  53 };
  54
  55 static const struct dp_link_dpll pch_dpll[] = {
  56         { DP_LINK_BW_1_62,
  57                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  58         { DP_LINK_BW_2_7,
  59                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  60 };
  61
  62 static const struct dp_link_dpll vlv_dpll[] = {
  63         { DP_LINK_BW_1_62,
  64                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  65         { DP_LINK_BW_2_7,
  66                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  67 };
  68
  69 /*
  70  * CHV supports eDP 1.4 that have  more link rates.
  71  * Below only provides the fixed rate but exclude variable rate.
  72  */
  73 static const struct dp_link_dpll chv_dpll[] = {
  74         /*
  75          * CHV requires to program fractional division for m2.
  76          * m2 is stored in fixed point format using formula below
  77          * (m2_int << 22) | m2_fraction
  78          */
  79         { DP_LINK_BW_1_62,      /* m2_int = 32, m2_fraction = 1677722 */
  80                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  81         { DP_LINK_BW_2_7,       /* m2_int = 27, m2_fraction = 0 */
  82                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  83         { DP_LINK_BW_5_4,       /* m2_int = 27, m2_fraction = 0 */
  84                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  85 };
  86
  87 /**
  88  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  89  * @intel_dp: DP struct
  90  *
  91  * If a CPU or PCH DP output is attached to an eDP panel, this function
  92  * will return true, and false otherwise.
  93  */
  94 static bool is_edp(struct intel_dp *intel_dp)
  95 {
  96         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  97
  98         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  99 }
 100
 101 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 102 {
 103         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 104
 105         return intel_dig_port->base.base.dev;
 106 }
 107
 108 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 109 {
 110         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 111 }
 112
 113 static void intel_dp_link_down(struct intel_dp *intel_dp);
 114 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 115 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 116 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
 117 static void vlv_steal_power_sequencer(struct drm_device *dev,
 118                                       enum pipe pipe);
 119
 120 int
 121 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 122 {
 123         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 124         struct drm_device *dev = intel_dp->attached_connector->base.dev;
 125
 126         switch (max_link_bw) {
 127         case DP_LINK_BW_1_62:
 128         case DP_LINK_BW_2_7:
 129                 break;
 130         case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
 131                 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
 132                      INTEL_INFO(dev)->gen >= 8) &&
 133                     intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
 134                         max_link_bw = DP_LINK_BW_5_4;
 135                 else
 136                         max_link_bw = DP_LINK_BW_2_7;
 137                 break;
 138         default:
 139                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 140                      max_link_bw);
 141                 max_link_bw = DP_LINK_BW_1_62;
 142                 break;
 143         }
 144         return max_link_bw;
 145 }
 146
 147 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 148 {
 149         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 150         struct drm_device *dev = intel_dig_port->base.base.dev;
 151         u8 source_max, sink_max;
 152
 153         source_max = 4;
 154         if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
 155             (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
 156                 source_max = 2;
 157
 158         sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 159
 160         return min(source_max, sink_max);
 161 }
 162
 163 /*
 164  * The units on the numbers in the next two are... bizarre.  Examples will
 165  * make it clearer; this one parallels an example in the eDP spec.
 166  *
 167  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 168  *
 169  *     270000 * 1 * 8 / 10 == 216000
 170  *
 171  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 172  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 173  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 174  * 119000.  At 18bpp that's 2142000 kilobits per second.
 175  *
 176  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 177  * get the result in decakilobits instead of kilobits.
 178  */
 179
 180 static int
 181 intel_dp_link_required(int pixel_clock, int bpp)
 182 {
 183         return (pixel_clock * bpp + 9) / 10;
 184 }
 185
 186 static int
 187 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 188 {
 189         return (max_link_clock * max_lanes * 8) / 10;
 190 }
 191
 192 static enum drm_mode_status
 193 intel_dp_mode_valid(struct drm_connector *connector,
 194                     struct drm_display_mode *mode)
 195 {
 196         struct intel_dp *intel_dp = intel_attached_dp(connector);
 197         struct intel_connector *intel_connector = to_intel_connector(connector);
 198         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 199         int target_clock = mode->clock;
 200         int max_rate, mode_rate, max_lanes, max_link_clock;
 201
 202         if (is_edp(intel_dp) && fixed_mode) {
 203                 if (mode->hdisplay > fixed_mode->hdisplay)
 204                         return MODE_PANEL;
 205
 206                 if (mode->vdisplay > fixed_mode->vdisplay)
 207                         return MODE_PANEL;
 208
 209                 target_clock = fixed_mode->clock;
 210         }
 211
 212         max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
 213         max_lanes = intel_dp_max_lane_count(intel_dp);
 214
 215         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 216         mode_rate = intel_dp_link_required(target_clock, 18);
 217
 218         if (mode_rate > max_rate)
 219                 return MODE_CLOCK_HIGH;
 220
 221         if (mode->clock < 10000)
 222                 return MODE_CLOCK_LOW;
 223
 224         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 225                 return MODE_H_ILLEGAL;
 226
 227         return MODE_OK;
 228 }
 229
 230 static uint32_t
 231 pack_aux(const uint8_t *src, int src_bytes)
 232 {
 233         int     i;
 234         uint32_t v = 0;
 235
 236         if (src_bytes > 4)
 237                 src_bytes = 4;
 238         for (i = 0; i < src_bytes; i++)
 239                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 240         return v;
 241 }
 242
 243 static void
 244 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 245 {
 246         int i;
 247         if (dst_bytes > 4)
 248                 dst_bytes = 4;
 249         for (i = 0; i < dst_bytes; i++)
 250                 dst[i] = src >> ((3-i) * 8);
 251 }
 252
 253 /* hrawclock is 1/4 the FSB frequency */
 254 static int
 255 intel_hrawclk(struct drm_device *dev)
 256 {
 257         struct drm_i915_private *dev_priv = dev->dev_private;
 258         uint32_t clkcfg;
 259
 260         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 261         if (IS_VALLEYVIEW(dev))
 262                 return 200;
 263
 264         clkcfg = I915_READ(CLKCFG);
 265         switch (clkcfg & CLKCFG_FSB_MASK) {
 266         case CLKCFG_FSB_400:
 267                 return 100;
 268         case CLKCFG_FSB_533:
 269                 return 133;
 270         case CLKCFG_FSB_667:
 271                 return 166;
 272         case CLKCFG_FSB_800:
 273                 return 200;
 274         case CLKCFG_FSB_1067:
 275                 return 266;
 276         case CLKCFG_FSB_1333:
 277                 return 333;
 278         /* these two are just a guess; one of them might be right */
 279         case CLKCFG_FSB_1600:
 280         case CLKCFG_FSB_1600_ALT:
 281                 return 400;
 282         default:
 283                 return 133;
 284         }
 285 }
 286
 287 static void
 288 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 289                                     struct intel_dp *intel_dp);
 290 static void
 291 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 292                                               struct intel_dp *intel_dp);
 293
 294 static void pps_lock(struct intel_dp *intel_dp)
 295 {
 296         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 297         struct intel_encoder *encoder = &intel_dig_port->base;
 298         struct drm_device *dev = encoder->base.dev;
 299         struct drm_i915_private *dev_priv = dev->dev_private;
 300         enum intel_display_power_domain power_domain;
 301
 302         /*
 303          * See vlv_power_sequencer_reset() why we need
 304          * a power domain reference here.
 305          */
 306         power_domain = intel_display_port_power_domain(encoder);
 307         intel_display_power_get(dev_priv, power_domain);
 308
 309         mutex_lock(&dev_priv->pps_mutex);
 310 }
 311
 312 static void pps_unlock(struct intel_dp *intel_dp)
 313 {
 314         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 315         struct intel_encoder *encoder = &intel_dig_port->base;
 316         struct drm_device *dev = encoder->base.dev;
 317         struct drm_i915_private *dev_priv = dev->dev_private;
 318         enum intel_display_power_domain power_domain;
 319
 320         mutex_unlock(&dev_priv->pps_mutex);
 321
 322         power_domain = intel_display_port_power_domain(encoder);
 323         intel_display_power_put(dev_priv, power_domain);
 324 }
 325
 326 static void
 327 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 328 {
 329         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 330         struct drm_device *dev = intel_dig_port->base.base.dev;
 331         struct drm_i915_private *dev_priv = dev->dev_private;
 332         enum pipe pipe = intel_dp->pps_pipe;
 333         uint32_t DP;
 334
 335         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 336                  "skipping pipe %c power seqeuncer kick due to port %c being active\n",
 337                  pipe_name(pipe), port_name(intel_dig_port->port)))
 338                 return;
 339
 340         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 341                       pipe_name(pipe), port_name(intel_dig_port->port));
 342
 343         /* Preserve the BIOS-computed detected bit. This is
 344          * supposed to be read-only.
 345          */
 346         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 347         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 348         DP |= DP_PORT_WIDTH(1);
 349         DP |= DP_LINK_TRAIN_PAT_1;
 350
 351         if (IS_CHERRYVIEW(dev))
 352                 DP |= DP_PIPE_SELECT_CHV(pipe);
 353         else if (pipe == PIPE_B)
 354                 DP |= DP_PIPEB_SELECT;
 355
 356         /*
 357          * Similar magic as in intel_dp_enable_port().
 358          * We _must_ do this port enable + disable trick
 359          * to make this power seqeuencer lock onto the port.
 360          * Otherwise even VDD force bit won't work.
 361          */
 362         I915_WRITE(intel_dp->output_reg, DP);
 363         POSTING_READ(intel_dp->output_reg);
 364
 365         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 366         POSTING_READ(intel_dp->output_reg);
 367
 368         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 369         POSTING_READ(intel_dp->output_reg);
 370 }
 371
 372 static enum pipe
 373 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 374 {
 375         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 376         struct drm_device *dev = intel_dig_port->base.base.dev;
 377         struct drm_i915_private *dev_priv = dev->dev_private;
 378         struct intel_encoder *encoder;
 379         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 380         enum pipe pipe;
 381
 382         lockdep_assert_held(&dev_priv->pps_mutex);
 383
 384         /* We should never land here with regular DP ports */
 385         WARN_ON(!is_edp(intel_dp));
 386
 387         if (intel_dp->pps_pipe != INVALID_PIPE)
 388                 return intel_dp->pps_pipe;
 389
 390         /*
 391          * We don't have power sequencer currently.
 392          * Pick one that's not used by other ports.
 393          */
 394         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
 395                             base.head) {
 396                 struct intel_dp *tmp;
 397
 398                 if (encoder->type != INTEL_OUTPUT_EDP)
 399                         continue;
 400
 401                 tmp = enc_to_intel_dp(&encoder->base);
 402
 403                 if (tmp->pps_pipe != INVALID_PIPE)
 404                         pipes &= ~(1 << tmp->pps_pipe);
 405         }
 406
 407         /*
 408          * Didn't find one. This should not happen since there
 409          * are two power sequencers and up to two eDP ports.
 410          */
 411         if (WARN_ON(pipes == 0))
 412                 pipe = PIPE_A;
 413         else
 414                 pipe = ffs(pipes) - 1;
 415
 416         vlv_steal_power_sequencer(dev, pipe);
 417         intel_dp->pps_pipe = pipe;
 418
 419         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 420                       pipe_name(intel_dp->pps_pipe),
 421                       port_name(intel_dig_port->port));
 422
 423         /* init power sequencer on this pipe and port */
 424         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 425         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 426
 427         /*
 428          * Even vdd force doesn't work until we've made
 429          * the power sequencer lock in on the port.
 430          */
 431         vlv_power_sequencer_kick(intel_dp);
 432
 433         return intel_dp->pps_pipe;
 434 }
 435
 436 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 437                                enum pipe pipe);
 438
 439 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 440                                enum pipe pipe)
 441 {
 442         return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
 443 }
 444
 445 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 446                                 enum pipe pipe)
 447 {
 448         return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 449 }
 450
 451 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 452                          enum pipe pipe)
 453 {
 454         return true;
 455 }
 456
 457 static enum pipe
 458 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 459                      enum port port,
 460                      vlv_pipe_check pipe_check)
 461 {
 462         enum pipe pipe;
 463
 464         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 465                 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
 466                         PANEL_PORT_SELECT_MASK;
 467
 468                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 469                         continue;
 470
 471                 if (!pipe_check(dev_priv, pipe))
 472                         continue;
 473
 474                 return pipe;
 475         }
 476
 477         return INVALID_PIPE;
 478 }
 479
 480 static void
 481 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 482 {
 483         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 484         struct drm_device *dev = intel_dig_port->base.base.dev;
 485         struct drm_i915_private *dev_priv = dev->dev_private;
 486         enum port port = intel_dig_port->port;
 487
 488         lockdep_assert_held(&dev_priv->pps_mutex);
 489
 490         /* try to find a pipe with this port selected */
 491         /* first pick one where the panel is on */
 492         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 493                                                   vlv_pipe_has_pp_on);
 494         /* didn't find one? pick one where vdd is on */
 495         if (intel_dp->pps_pipe == INVALID_PIPE)
 496                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 497                                                           vlv_pipe_has_vdd_on);
 498         /* didn't find one? pick one with just the correct port */
 499         if (intel_dp->pps_pipe == INVALID_PIPE)
 500                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 501                                                           vlv_pipe_any);
 502
 503         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 504         if (intel_dp->pps_pipe == INVALID_PIPE) {
 505                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 506                               port_name(port));
 507                 return;
 508         }
 509
 510         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 511                       port_name(port), pipe_name(intel_dp->pps_pipe));
 512
 513         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 514         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 515 }
 516
 517 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
 518 {
 519         struct drm_device *dev = dev_priv->dev;
 520         struct intel_encoder *encoder;
 521
 522         if (WARN_ON(!IS_VALLEYVIEW(dev)))
 523                 return;
 524
 525         /*
 526          * We can't grab pps_mutex here due to deadlock with power_domain
 527          * mutex when power_domain functions are called while holding pps_mutex.
 528          * That also means that in order to use pps_pipe the code needs to
 529          * hold both a power domain reference and pps_mutex, and the power domain
 530          * reference get/put must be done while _not_ holding pps_mutex.
 531          * pps_{lock,unlock}() do these steps in the correct order, so one
 532          * should use them always.
 533          */
 534
 535         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
 536                 struct intel_dp *intel_dp;
 537
 538                 if (encoder->type != INTEL_OUTPUT_EDP)
 539                         continue;
 540
 541                 intel_dp = enc_to_intel_dp(&encoder->base);
 542                 intel_dp->pps_pipe = INVALID_PIPE;
 543         }
 544 }
 545
 546 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
 547 {
 548         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 549
 550         if (HAS_PCH_SPLIT(dev))
 551                 return PCH_PP_CONTROL;
 552         else
 553                 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
 554 }
 555
 556 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
 557 {
 558         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 559
 560         if (HAS_PCH_SPLIT(dev))
 561                 return PCH_PP_STATUS;
 562         else
 563                 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
 564 }
 565
 566 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 567    This function only applicable when panel PM state is not to be tracked */
 568 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 569                               void *unused)
 570 {
 571         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 572                                                  edp_notifier);
 573         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 574         struct drm_i915_private *dev_priv = dev->dev_private;
 575         u32 pp_div;
 576         u32 pp_ctrl_reg, pp_div_reg;
 577
 578         if (!is_edp(intel_dp) || code != SYS_RESTART)
 579                 return 0;
 580
 581         pps_lock(intel_dp);
 582
 583         if (IS_VALLEYVIEW(dev)) {
 584                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 585
 586                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
 587                 pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
 588                 pp_div = I915_READ(pp_div_reg);
 589                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 590
 591                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 592                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 593                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 594                 msleep(intel_dp->panel_power_cycle_delay);
 595         }
 596
 597         pps_unlock(intel_dp);
 598
 599         return 0;
 600 }
 601
 602 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 603 {
 604         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 605         struct drm_i915_private *dev_priv = dev->dev_private;
 606
 607         lockdep_assert_held(&dev_priv->pps_mutex);
 608
 609         if (IS_VALLEYVIEW(dev) &&
 610             intel_dp->pps_pipe == INVALID_PIPE)
 611                 return false;
 612
 613         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 614 }
 615
 616 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 617 {
 618         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 619         struct drm_i915_private *dev_priv = dev->dev_private;
 620
 621         lockdep_assert_held(&dev_priv->pps_mutex);
 622
 623         if (IS_VALLEYVIEW(dev) &&
 624             intel_dp->pps_pipe == INVALID_PIPE)
 625                 return false;
 626
 627         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
 628 }
 629
 630 static void
 631 intel_dp_check_edp(struct intel_dp *intel_dp)
 632 {
 633         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 634         struct drm_i915_private *dev_priv = dev->dev_private;
 635
 636         if (!is_edp(intel_dp))
 637                 return;
 638
 639         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 640                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 641                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 642                               I915_READ(_pp_stat_reg(intel_dp)),
 643                               I915_READ(_pp_ctrl_reg(intel_dp)));
 644         }
 645 }
 646
 647 static uint32_t
 648 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 649 {
 650         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 651         struct drm_device *dev = intel_dig_port->base.base.dev;
 652         struct drm_i915_private *dev_priv = dev->dev_private;
 653         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 654         uint32_t status;
 655         bool done;
 656
 657 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 658         if (has_aux_irq)
 659                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 660                                           msecs_to_jiffies_timeout(10));
 661         else
 662                 done = wait_for_atomic(C, 10) == 0;
 663         if (!done)
 664                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 665                           has_aux_irq);
 666 #undef C
 667
 668         return status;
 669 }
 670
 671 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 672 {
 673         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 674         struct drm_device *dev = intel_dig_port->base.base.dev;
 675
 676         /*
 677          * The clock divider is based off the hrawclk, and would like to run at
 678          * 2MHz.  So, take the hrawclk value and divide by 2 and use that
 679          */
 680         return index ? 0 : intel_hrawclk(dev) / 2;
 681 }
 682
 683 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 684 {
 685         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 686         struct drm_device *dev = intel_dig_port->base.base.dev;
 687
 688         if (index)
 689                 return 0;
 690
 691         if (intel_dig_port->port == PORT_A) {
 692                 if (IS_GEN6(dev) || IS_GEN7(dev))
 693                         return 200; /* SNB & IVB eDP input clock at 400Mhz */
 694                 else
 695                         return 225; /* eDP input clock at 450Mhz */
 696         } else {
 697                 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 698         }
 699 }
 700
 701 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 702 {
 703         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 704         struct drm_device *dev = intel_dig_port->base.base.dev;
 705         struct drm_i915_private *dev_priv = dev->dev_private;
 706
 707         if (intel_dig_port->port == PORT_A) {
 708                 if (index)
 709                         return 0;
 710                 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
 711         } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 712                 /* Workaround for non-ULT HSW */
 713                 switch (index) {
 714                 case 0: return 63;
 715                 case 1: return 72;
 716                 default: return 0;
 717                 }
 718         } else  {
 719                 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 720         }
 721 }
 722
 723 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 724 {
 725         return index ? 0 : 100;
 726 }
 727
 728 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 729 {
 730         /*
 731          * SKL doesn't need us to program the AUX clock divider (Hardware will
 732          * derive the clock from CDCLK automatically). We still implement the
 733          * get_aux_clock_divider vfunc to plug-in into the existing code.
 734          */
 735         return index ? 0 : 1;
 736 }
 737
 738 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
 739                                       bool has_aux_irq,
 740                                       int send_bytes,
 741                                       uint32_t aux_clock_divider)
 742 {
 743         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 744         struct drm_device *dev = intel_dig_port->base.base.dev;
 745         uint32_t precharge, timeout;
 746
 747         if (IS_GEN6(dev))
 748                 precharge = 3;
 749         else
 750                 precharge = 5;
 751
 752         if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
 753                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 754         else
 755                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
 756
 757         return DP_AUX_CH_CTL_SEND_BUSY |
 758                DP_AUX_CH_CTL_DONE |
 759                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 760                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 761                timeout |
 762                DP_AUX_CH_CTL_RECEIVE_ERROR |
 763                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 764                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 765                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
 766 }
 767
 768 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
 769                                       bool has_aux_irq,
 770                                       int send_bytes,
 771                                       uint32_t unused)
 772 {
 773         return DP_AUX_CH_CTL_SEND_BUSY |
 774                DP_AUX_CH_CTL_DONE |
 775                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 776                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 777                DP_AUX_CH_CTL_TIME_OUT_1600us |
 778                DP_AUX_CH_CTL_RECEIVE_ERROR |
 779                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 780                DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
 781 }
 782
 783 static int
 784 intel_dp_aux_ch(struct intel_dp *intel_dp,
 785                 const uint8_t *send, int send_bytes,
 786                 uint8_t *recv, int recv_size)
 787 {
 788         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 789         struct drm_device *dev = intel_dig_port->base.base.dev;
 790         struct drm_i915_private *dev_priv = dev->dev_private;
 791         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 792         uint32_t ch_data = ch_ctl + 4;
 793         uint32_t aux_clock_divider;
 794         int i, ret, recv_bytes;
 795         uint32_t status;
 796         int try, clock = 0;
 797         bool has_aux_irq = HAS_AUX_IRQ(dev);
 798         bool vdd;
 799
 800         pps_lock(intel_dp);
 801
 802         /*
 803          * We will be called with VDD already enabled for dpcd/edid/oui reads.
 804          * In such cases we want to leave VDD enabled and it's up to upper layers
 805          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
 806          * ourselves.
 807          */
 808         vdd = edp_panel_vdd_on(intel_dp);
 809
 810         /* dp aux is extremely sensitive to irq latency, hence request the
 811          * lowest possible wakeup latency and so prevent the cpu from going into
 812          * deep sleep states.
 813          */
 814         pm_qos_update_request(&dev_priv->pm_qos, 0);
 815
 816         intel_dp_check_edp(intel_dp);
 817
 818         intel_aux_display_runtime_get(dev_priv);
 819
 820         /* Try to wait for any previous AUX channel activity */
 821         for (try = 0; try < 3; try++) {
 822                 status = I915_READ_NOTRACE(ch_ctl);
 823                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 824                         break;
 825                 msleep(1);
 826         }
 827
 828         if (try == 3) {
 829                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 830                      I915_READ(ch_ctl));
 831                 ret = -EBUSY;
 832                 goto out;
 833         }
 834
 835         /* Only 5 data registers! */
 836         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
 837                 ret = -E2BIG;
 838                 goto out;
 839         }
 840
 841         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
 842                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
 843                                                           has_aux_irq,
 844                                                           send_bytes,
 845                                                           aux_clock_divider);
 846
 847                 /* Must try at least 3 times according to DP spec */
 848                 for (try = 0; try < 5; try++) {
 849                         /* Load the send data into the aux channel data registers */
 850                         for (i = 0; i < send_bytes; i += 4)
 851                                 I915_WRITE(ch_data + i,
 852                                            pack_aux(send + i, send_bytes - i));
 853
 854                         /* Send the command and wait for it to complete */
 855                         I915_WRITE(ch_ctl, send_ctl);
 856
 857                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 858
 859                         /* Clear done status and any errors */
 860                         I915_WRITE(ch_ctl,
 861                                    status |
 862                                    DP_AUX_CH_CTL_DONE |
 863                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 864                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 865
 866                         if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 867                                       DP_AUX_CH_CTL_RECEIVE_ERROR))
 868                                 continue;
 869                         if (status & DP_AUX_CH_CTL_DONE)
 870                                 break;
 871                 }
 872                 if (status & DP_AUX_CH_CTL_DONE)
 873                         break;
 874         }
 875
 876         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 877                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 878                 ret = -EBUSY;
 879                 goto out;
 880         }
 881
 882         /* Check for timeout or receive error.
 883          * Timeouts occur when the sink is not connected
 884          */
 885         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 886                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 887                 ret = -EIO;
 888                 goto out;
 889         }
 890
 891         /* Timeouts occur when the device isn't connected, so they're
 892          * "normal" -- don't fill the kernel log with these */
 893         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 894                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 895                 ret = -ETIMEDOUT;
 896                 goto out;
 897         }
 898
 899         /* Unload any bytes sent back from the other side */
 900         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 901                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 902         if (recv_bytes > recv_size)
 903                 recv_bytes = recv_size;
 904
 905         for (i = 0; i < recv_bytes; i += 4)
 906                 unpack_aux(I915_READ(ch_data + i),
 907                            recv + i, recv_bytes - i);
 908
 909         ret = recv_bytes;
 910 out:
 911         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 912         intel_aux_display_runtime_put(dev_priv);
 913
 914         if (vdd)
 915                 edp_panel_vdd_off(intel_dp, false);
 916
 917         pps_unlock(intel_dp);
 918
 919         return ret;
 920 }
 921
 922 #define BARE_ADDRESS_SIZE       3
 923 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
 924 static ssize_t
 925 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 926 {
 927         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
 928         uint8_t txbuf[20], rxbuf[20];
 929         size_t txsize, rxsize;
 930         int ret;
 931
 932         txbuf[0] = msg->request << 4;
 933         txbuf[1] = msg->address >> 8;
 934         txbuf[2] = msg->address & 0xff;
 935         txbuf[3] = msg->size - 1;
 936
 937         switch (msg->request & ~DP_AUX_I2C_MOT) {
 938         case DP_AUX_NATIVE_WRITE:
 939         case DP_AUX_I2C_WRITE:
 940                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
 941                 rxsize = 1;
 942
 943                 if (WARN_ON(txsize > 20))
 944                         return -E2BIG;
 945
 946                 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
 947
 948                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 949                 if (ret > 0) {
 950                         msg->reply = rxbuf[0] >> 4;
 951
 952                         /* Return payload size. */
 953                         ret = msg->size;
 954                 }
 955                 break;
 956
 957         case DP_AUX_NATIVE_READ:
 958         case DP_AUX_I2C_READ:
 959                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
 960                 rxsize = msg->size + 1;
 961
 962                 if (WARN_ON(rxsize > 20))
 963                         return -E2BIG;
 964
 965                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 966                 if (ret > 0) {
 967                         msg->reply = rxbuf[0] >> 4;
 968                         /*
 969                          * Assume happy day, and copy the data. The caller is
 970                          * expected to check msg->reply before touching it.
 971                          *
 972                          * Return payload size.
 973                          */
 974                         ret--;
 975                         memcpy(msg->buffer, rxbuf + 1, ret);
 976                 }
 977                 break;
 978
 979         default:
 980                 ret = -EINVAL;
 981                 break;
 982         }
 983
 984         return ret;
 985 }
 986
 987 static void
 988 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
 989 {
 990         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 991         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 992         enum port port = intel_dig_port->port;
 993         const char *name = NULL;
 994         int ret;
 995
 996         switch (port) {
 997         case PORT_A:
 998                 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
 999                 name = "DPDDC-A";
1000                 break;
1001         case PORT_B:
1002                 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
1003                 name = "DPDDC-B";
1004                 break;
1005         case PORT_C:
1006                 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
1007                 name = "DPDDC-C";
1008                 break;
1009         case PORT_D:
1010                 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
1011                 name = "DPDDC-D";
1012                 break;
1013         default:
1014                 BUG();
1015         }
1016
1017         /*
1018          * The AUX_CTL register is usually DP_CTL + 0x10.
1019          *
1020          * On Haswell and Broadwell though:
1021          *   - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1022          *   - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1023          *
1024          * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1025          */
1026         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1027                 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
1028
1029         intel_dp->aux.name = name;
1030         intel_dp->aux.dev = dev->dev;
1031         intel_dp->aux.transfer = intel_dp_aux_transfer;
1032
1033         DRM_DEBUG_KMS("registering %s bus for %s\n", name,
1034                       connector->base.kdev->kobj.name);
1035
1036         ret = drm_dp_aux_register(&intel_dp->aux);
1037         if (ret < 0) {
1038                 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1039                           name, ret);
1040                 return;
1041         }
1042
1043         ret = sysfs_create_link(&connector->base.kdev->kobj,
1044                                 &intel_dp->aux.ddc.dev.kobj,
1045                                 intel_dp->aux.ddc.dev.kobj.name);
1046         if (ret < 0) {
1047                 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
1048                 drm_dp_aux_unregister(&intel_dp->aux);
1049         }
1050 }
1051
1052 static void
1053 intel_dp_connector_unregister(struct intel_connector *intel_connector)
1054 {
1055         struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1056
1057         if (!intel_connector->mst_port)
1058                 sysfs_remove_link(&intel_connector->base.kdev->kobj,
1059                                   intel_dp->aux.ddc.dev.kobj.name);
1060         intel_connector_unregister(intel_connector);
1061 }
1062
1063 static void
1064 hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
1065 {
1066         switch (link_bw) {
1067         case DP_LINK_BW_1_62:
1068                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1069                 break;
1070         case DP_LINK_BW_2_7:
1071                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1072                 break;
1073         case DP_LINK_BW_5_4:
1074                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1075                 break;
1076         }
1077 }
1078
1079 static void
1080 intel_dp_set_clock(struct intel_encoder *encoder,
1081                    struct intel_crtc_config *pipe_config, int link_bw)
1082 {
1083         struct drm_device *dev = encoder->base.dev;
1084         const struct dp_link_dpll *divisor = NULL;
1085         int i, count = 0;
1086
1087         if (IS_G4X(dev)) {
1088                 divisor = gen4_dpll;
1089                 count = ARRAY_SIZE(gen4_dpll);
1090         } else if (HAS_PCH_SPLIT(dev)) {
1091                 divisor = pch_dpll;
1092                 count = ARRAY_SIZE(pch_dpll);
1093         } else if (IS_CHERRYVIEW(dev)) {
1094                 divisor = chv_dpll;
1095                 count = ARRAY_SIZE(chv_dpll);
1096         } else if (IS_VALLEYVIEW(dev)) {
1097                 divisor = vlv_dpll;
1098                 count = ARRAY_SIZE(vlv_dpll);
1099         }
1100
1101         if (divisor && count) {
1102                 for (i = 0; i < count; i++) {
1103                         if (link_bw == divisor[i].link_bw) {
1104                                 pipe_config->dpll = divisor[i].dpll;
1105                                 pipe_config->clock_set = true;
1106                                 break;
1107                         }
1108                 }
1109         }
1110 }
1111
1112 bool
1113 intel_dp_compute_config(struct intel_encoder *encoder,
1114                         struct intel_crtc_config *pipe_config)
1115 {
1116         struct drm_device *dev = encoder->base.dev;
1117         struct drm_i915_private *dev_priv = dev->dev_private;
1118         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
1119         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1120         enum port port = dp_to_dig_port(intel_dp)->port;
1121         struct intel_crtc *intel_crtc = encoder->new_crtc;
1122         struct intel_connector *intel_connector = intel_dp->attached_connector;
1123         int lane_count, clock;
1124         int min_lane_count = 1;
1125         int max_lane_count = intel_dp_max_lane_count(intel_dp);
1126         /* Conveniently, the link BW constants become indices with a shift...*/
1127         int min_clock = 0;
1128         int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
1129         int bpp, mode_rate;
1130         static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
1131         int link_avail, link_clock;
1132
1133         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
1134                 pipe_config->has_pch_encoder = true;
1135
1136         pipe_config->has_dp_encoder = true;
1137         pipe_config->has_drrs = false;
1138         pipe_config->has_audio = intel_dp->has_audio;
1139
1140         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1141                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1142                                        adjusted_mode);
1143                 if (!HAS_PCH_SPLIT(dev))
1144                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
1145                                                  intel_connector->panel.fitting_mode);
1146                 else
1147                         intel_pch_panel_fitting(intel_crtc, pipe_config,
1148                                                 intel_connector->panel.fitting_mode);
1149         }
1150
1151         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1152                 return false;
1153
1154         DRM_DEBUG_KMS("DP link computation with max lane count %i "
1155                       "max bw %02x pixel clock %iKHz\n",
1156                       max_lane_count, bws[max_clock],
1157                       adjusted_mode->crtc_clock);
1158
1159         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1160          * bpc in between. */
1161         bpp = pipe_config->pipe_bpp;
1162         if (is_edp(intel_dp)) {
1163                 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1164                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1165                                       dev_priv->vbt.edp_bpp);
1166                         bpp = dev_priv->vbt.edp_bpp;
1167                 }
1168
1169                 /*
1170                  * Use the maximum clock and number of lanes the eDP panel
1171                  * advertizes being capable of. The panels are generally
1172                  * designed to support only a single clock and lane
1173                  * configuration, and typically these values correspond to the
1174                  * native resolution of the panel.
1175                  */
1176                 min_lane_count = max_lane_count;
1177                 min_clock = max_clock;
1178         }
1179
1180         for (; bpp >= 6*3; bpp -= 2*3) {
1181                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1182                                                    bpp);
1183
1184                 for (clock = min_clock; clock <= max_clock; clock++) {
1185                         for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
1186                                 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
1187                                 link_avail = intel_dp_max_data_rate(link_clock,
1188                                                                     lane_count);
1189
1190                                 if (mode_rate <= link_avail) {
1191                                         goto found;
1192                                 }
1193                         }
1194                 }
1195         }
1196
1197         return false;
1198
1199 found:
1200         if (intel_dp->color_range_auto) {
1201                 /*
1202                  * See:
1203                  * CEA-861-E - 5.1 Default Encoding Parameters
1204                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1205                  */
1206                 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
1207                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
1208                 else
1209                         intel_dp->color_range = 0;
1210         }
1211
1212         if (intel_dp->color_range)
1213                 pipe_config->limited_color_range = true;
1214
1215         intel_dp->link_bw = bws[clock];
1216         intel_dp->lane_count = lane_count;
1217         pipe_config->pipe_bpp = bpp;
1218         pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
1219
1220         DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1221                       intel_dp->link_bw, intel_dp->lane_count,
1222                       pipe_config->port_clock, bpp);
1223         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1224                       mode_rate, link_avail);
1225
1226         intel_link_compute_m_n(bpp, lane_count,
1227                                adjusted_mode->crtc_clock,
1228                                pipe_config->port_clock,
1229                                &pipe_config->dp_m_n);
1230
1231         if (intel_connector->panel.downclock_mode != NULL &&
1232                 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
1233                         pipe_config->has_drrs = true;
1234                         intel_link_compute_m_n(bpp, lane_count,
1235                                 intel_connector->panel.downclock_mode->clock,
1236                                 pipe_config->port_clock,
1237                                 &pipe_config->dp_m2_n2);
1238         }
1239
1240         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1241                 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1242         else
1243                 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
1244
1245         return true;
1246 }
1247
1248 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
1249 {
1250         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1251         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1252         struct drm_device *dev = crtc->base.dev;
1253         struct drm_i915_private *dev_priv = dev->dev_private;
1254         u32 dpa_ctl;
1255
1256         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
1257         dpa_ctl = I915_READ(DP_A);
1258         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1259
1260         if (crtc->config.port_clock == 162000) {
1261                 /* For a long time we've carried around a ILK-DevA w/a for the
1262                  * 160MHz clock. If we're really unlucky, it's still required.
1263                  */
1264                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1265                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1266                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
1267         } else {
1268                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1269                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
1270         }
1271
1272         I915_WRITE(DP_A, dpa_ctl);
1273
1274         POSTING_READ(DP_A);
1275         udelay(500);
1276 }
1277
1278 static void intel_dp_prepare(struct intel_encoder *encoder)
1279 {
1280         struct drm_device *dev = encoder->base.dev;
1281         struct drm_i915_private *dev_priv = dev->dev_private;
1282         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1283         enum port port = dp_to_dig_port(intel_dp)->port;
1284         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1285         struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
1286
1287         /*
1288          * There are four kinds of DP registers:
1289          *
1290          *      IBX PCH
1291          *      SNB CPU
1292          *      IVB CPU
1293          *      CPT PCH
1294          *
1295          * IBX PCH and CPU are the same for almost everything,
1296          * except that the CPU DP PLL is configured in this
1297          * register
1298          *
1299          * CPT PCH is quite different, having many bits moved
1300          * to the TRANS_DP_CTL register instead. That
1301          * configuration happens (oddly) in ironlake_pch_enable
1302          */
1303
1304         /* Preserve the BIOS-computed detected bit. This is
1305          * supposed to be read-only.
1306          */
1307         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1308
1309         /* Handle DP bits in common between all three register formats */
1310         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1311         intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
1312
1313         if (crtc->config.has_audio) {
1314                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
1315                                  pipe_name(crtc->pipe));
1316                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1317                 intel_write_eld(encoder);
1318         }
1319
1320         /* Split out the IBX/CPU vs CPT settings */
1321
1322         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1323                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1324                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1325                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1326                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1327                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1328
1329                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1330                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1331
1332                 intel_dp->DP |= crtc->pipe << 29;
1333         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1334                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
1335                         intel_dp->DP |= intel_dp->color_range;
1336
1337                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1338                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1339                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1340                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1341                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1342
1343                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1344                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1345
1346                 if (!IS_CHERRYVIEW(dev)) {
1347                         if (crtc->pipe == 1)
1348                                 intel_dp->DP |= DP_PIPEB_SELECT;
1349                 } else {
1350                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1351                 }
1352         } else {
1353                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1354         }
1355 }
1356
1357 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1358 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1359
1360 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1361 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1362
1363 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1364 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1365
1366 static void wait_panel_status(struct intel_dp *intel_dp,
1367                                        u32 mask,
1368                                        u32 value)
1369 {
1370         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1371         struct drm_i915_private *dev_priv = dev->dev_private;
1372         u32 pp_stat_reg, pp_ctrl_reg;
1373
1374         lockdep_assert_held(&dev_priv->pps_mutex);
1375
1376         pp_stat_reg = _pp_stat_reg(intel_dp);
1377         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1378
1379         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1380                         mask, value,
1381                         I915_READ(pp_stat_reg),
1382                         I915_READ(pp_ctrl_reg));
1383
1384         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1385                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1386                                 I915_READ(pp_stat_reg),
1387                                 I915_READ(pp_ctrl_reg));
1388         }
1389
1390         DRM_DEBUG_KMS("Wait complete\n");
1391 }
1392
1393 static void wait_panel_on(struct intel_dp *intel_dp)
1394 {
1395         DRM_DEBUG_KMS("Wait for panel power on\n");
1396         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1397 }
1398
1399 static void wait_panel_off(struct intel_dp *intel_dp)
1400 {
1401         DRM_DEBUG_KMS("Wait for panel power off time\n");
1402         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1403 }
1404
1405 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1406 {
1407         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1408
1409         /* When we disable the VDD override bit last we have to do the manual
1410          * wait. */
1411         wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1412                                        intel_dp->panel_power_cycle_delay);
1413
1414         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1415 }
1416
1417 static void wait_backlight_on(struct intel_dp *intel_dp)
1418 {
1419         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1420                                        intel_dp->backlight_on_delay);
1421 }
1422
1423 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1424 {
1425         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1426                                        intel_dp->backlight_off_delay);
1427 }
1428
1429 /* Read the current pp_control value, unlocking the register if it
1430  * is locked
1431  */
1432
1433 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1434 {
1435         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1436         struct drm_i915_private *dev_priv = dev->dev_private;
1437         u32 control;
1438
1439         lockdep_assert_held(&dev_priv->pps_mutex);
1440
1441         control = I915_READ(_pp_ctrl_reg(intel_dp));
1442         control &= ~PANEL_UNLOCK_MASK;
1443         control |= PANEL_UNLOCK_REGS;
1444         return control;
1445 }
1446
1447 /*
1448  * Must be paired with edp_panel_vdd_off().
1449  * Must hold pps_mutex around the whole on/off sequence.
1450  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1451  */
1452 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1453 {
1454         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1455         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1456         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1457         struct drm_i915_private *dev_priv = dev->dev_private;
1458         enum intel_display_power_domain power_domain;
1459         u32 pp;
1460         u32 pp_stat_reg, pp_ctrl_reg;
1461         bool need_to_disable = !intel_dp->want_panel_vdd;
1462
1463         lockdep_assert_held(&dev_priv->pps_mutex);
1464
1465         if (!is_edp(intel_dp))
1466                 return false;
1467
1468         intel_dp->want_panel_vdd = true;
1469
1470         if (edp_have_panel_vdd(intel_dp))
1471                 return need_to_disable;
1472
1473         power_domain = intel_display_port_power_domain(intel_encoder);
1474         intel_display_power_get(dev_priv, power_domain);
1475
1476         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1477                       port_name(intel_dig_port->port));
1478
1479         if (!edp_have_panel_power(intel_dp))
1480                 wait_panel_power_cycle(intel_dp);
1481
1482         pp = ironlake_get_pp_control(intel_dp);
1483         pp |= EDP_FORCE_VDD;
1484
1485         pp_stat_reg = _pp_stat_reg(intel_dp);
1486         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1487
1488         I915_WRITE(pp_ctrl_reg, pp);
1489         POSTING_READ(pp_ctrl_reg);
1490         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1491                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1492         /*
1493          * If the panel wasn't on, delay before accessing aux channel
1494          */
1495         if (!edp_have_panel_power(intel_dp)) {
1496                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1497                               port_name(intel_dig_port->port));
1498                 msleep(intel_dp->panel_power_up_delay);
1499         }
1500
1501         return need_to_disable;
1502 }
1503
1504 /*
1505  * Must be paired with intel_edp_panel_vdd_off() or
1506  * intel_edp_panel_off().
1507  * Nested calls to these functions are not allowed since
1508  * we drop the lock. Caller must use some higher level
1509  * locking to prevent nested calls from other threads.
1510  */
1511 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1512 {
1513         bool vdd;
1514
1515         if (!is_edp(intel_dp))
1516                 return;
1517
1518         pps_lock(intel_dp);
1519         vdd = edp_panel_vdd_on(intel_dp);
1520         pps_unlock(intel_dp);
1521
1522         WARN(!vdd, "eDP port %c VDD already requested on\n",
1523              port_name(dp_to_dig_port(intel_dp)->port));
1524 }
1525
1526 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1527 {
1528         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1529         struct drm_i915_private *dev_priv = dev->dev_private;
1530         struct intel_digital_port *intel_dig_port =
1531                 dp_to_dig_port(intel_dp);
1532         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1533         enum intel_display_power_domain power_domain;
1534         u32 pp;
1535         u32 pp_stat_reg, pp_ctrl_reg;
1536
1537         lockdep_assert_held(&dev_priv->pps_mutex);
1538
1539         WARN_ON(intel_dp->want_panel_vdd);
1540
1541         if (!edp_have_panel_vdd(intel_dp))
1542                 return;
1543
1544         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1545                       port_name(intel_dig_port->port));
1546
1547         pp = ironlake_get_pp_control(intel_dp);
1548         pp &= ~EDP_FORCE_VDD;
1549
1550         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1551         pp_stat_reg = _pp_stat_reg(intel_dp);
1552
1553         I915_WRITE(pp_ctrl_reg, pp);
1554         POSTING_READ(pp_ctrl_reg);
1555
1556         /* Make sure sequencer is idle before allowing subsequent activity */
1557         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1558         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1559
1560         if ((pp & POWER_TARGET_ON) == 0)
1561                 intel_dp->last_power_cycle = jiffies;
1562
1563         power_domain = intel_display_port_power_domain(intel_encoder);
1564         intel_display_power_put(dev_priv, power_domain);
1565 }
1566
1567 static void edp_panel_vdd_work(struct work_struct *__work)
1568 {
1569         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1570                                                  struct intel_dp, panel_vdd_work);
1571
1572         pps_lock(intel_dp);
1573         if (!intel_dp->want_panel_vdd)
1574                 edp_panel_vdd_off_sync(intel_dp);
1575         pps_unlock(intel_dp);
1576 }
1577
1578 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1579 {
1580         unsigned long delay;
1581
1582         /*
1583          * Queue the timer to fire a long time from now (relative to the power
1584          * down delay) to keep the panel power up across a sequence of
1585          * operations.
1586          */
1587         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1588         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1589 }
1590
1591 /*
1592  * Must be paired with edp_panel_vdd_on().
1593  * Must hold pps_mutex around the whole on/off sequence.
1594  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1595  */
1596 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1597 {
1598         struct drm_i915_private *dev_priv =
1599                 intel_dp_to_dev(intel_dp)->dev_private;
1600
1601         lockdep_assert_held(&dev_priv->pps_mutex);
1602
1603         if (!is_edp(intel_dp))
1604                 return;
1605
1606         WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
1607              port_name(dp_to_dig_port(intel_dp)->port));
1608
1609         intel_dp->want_panel_vdd = false;
1610
1611         if (sync)
1612                 edp_panel_vdd_off_sync(intel_dp);
1613         else
1614                 edp_panel_vdd_schedule_off(intel_dp);
1615 }
1616
1617 static void edp_panel_on(struct intel_dp *intel_dp)
1618 {
1619         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1620         struct drm_i915_private *dev_priv = dev->dev_private;
1621         u32 pp;
1622         u32 pp_ctrl_reg;
1623
1624         lockdep_assert_held(&dev_priv->pps_mutex);
1625
1626         if (!is_edp(intel_dp))
1627                 return;
1628
1629         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1630                       port_name(dp_to_dig_port(intel_dp)->port));
1631
1632         if (WARN(edp_have_panel_power(intel_dp),
1633                  "eDP port %c panel power already on\n",
1634                  port_name(dp_to_dig_port(intel_dp)->port)))
1635                 return;
1636
1637         wait_panel_power_cycle(intel_dp);
1638
1639         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1640         pp = ironlake_get_pp_control(intel_dp);
1641         if (IS_GEN5(dev)) {
1642                 /* ILK workaround: disable reset around power sequence */
1643                 pp &= ~PANEL_POWER_RESET;
1644                 I915_WRITE(pp_ctrl_reg, pp);
1645                 POSTING_READ(pp_ctrl_reg);
1646         }
1647
1648         pp |= POWER_TARGET_ON;
1649         if (!IS_GEN5(dev))
1650                 pp |= PANEL_POWER_RESET;
1651
1652         I915_WRITE(pp_ctrl_reg, pp);
1653         POSTING_READ(pp_ctrl_reg);
1654
1655         wait_panel_on(intel_dp);
1656         intel_dp->last_power_on = jiffies;
1657
1658         if (IS_GEN5(dev)) {
1659                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1660                 I915_WRITE(pp_ctrl_reg, pp);
1661                 POSTING_READ(pp_ctrl_reg);
1662         }
1663 }
1664
1665 void intel_edp_panel_on(struct intel_dp *intel_dp)
1666 {
1667         if (!is_edp(intel_dp))
1668                 return;
1669
1670         pps_lock(intel_dp);
1671         edp_panel_on(intel_dp);
1672         pps_unlock(intel_dp);
1673 }
1674
1675
1676 static void edp_panel_off(struct intel_dp *intel_dp)
1677 {
1678         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1679         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1680         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1681         struct drm_i915_private *dev_priv = dev->dev_private;
1682         enum intel_display_power_domain power_domain;
1683         u32 pp;
1684         u32 pp_ctrl_reg;
1685
1686         lockdep_assert_held(&dev_priv->pps_mutex);
1687
1688         if (!is_edp(intel_dp))
1689                 return;
1690
1691         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
1692                       port_name(dp_to_dig_port(intel_dp)->port));
1693
1694         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
1695              port_name(dp_to_dig_port(intel_dp)->port));
1696
1697         pp = ironlake_get_pp_control(intel_dp);
1698         /* We need to switch off panel power _and_ force vdd, for otherwise some
1699          * panels get very unhappy and cease to work. */
1700         pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1701                 EDP_BLC_ENABLE);
1702
1703         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1704
1705         intel_dp->want_panel_vdd = false;
1706
1707         I915_WRITE(pp_ctrl_reg, pp);
1708         POSTING_READ(pp_ctrl_reg);
1709
1710         intel_dp->last_power_cycle = jiffies;
1711         wait_panel_off(intel_dp);
1712
1713         /* We got a reference when we enabled the VDD. */
1714         power_domain = intel_display_port_power_domain(intel_encoder);
1715         intel_display_power_put(dev_priv, power_domain);
1716 }
1717
1718 void intel_edp_panel_off(struct intel_dp *intel_dp)
1719 {
1720         if (!is_edp(intel_dp))
1721                 return;
1722
1723         pps_lock(intel_dp);
1724         edp_panel_off(intel_dp);
1725         pps_unlock(intel_dp);
1726 }
1727
1728 /* Enable backlight in the panel power control. */
1729 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
1730 {
1731         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1732         struct drm_device *dev = intel_dig_port->base.base.dev;
1733         struct drm_i915_private *dev_priv = dev->dev_private;
1734         u32 pp;
1735         u32 pp_ctrl_reg;
1736
1737         /*
1738          * If we enable the backlight right away following a panel power
1739          * on, we may see slight flicker as the panel syncs with the eDP
1740          * link.  So delay a bit to make sure the image is solid before
1741          * allowing it to appear.
1742          */
1743         wait_backlight_on(intel_dp);
1744
1745         pps_lock(intel_dp);
1746
1747         pp = ironlake_get_pp_control(intel_dp);
1748         pp |= EDP_BLC_ENABLE;
1749
1750         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1751
1752         I915_WRITE(pp_ctrl_reg, pp);
1753         POSTING_READ(pp_ctrl_reg);
1754
1755         pps_unlock(intel_dp);
1756 }
1757
1758 /* Enable backlight PWM and backlight PP control. */
1759 void intel_edp_backlight_on(struct intel_dp *intel_dp)
1760 {
1761         if (!is_edp(intel_dp))
1762                 return;
1763
1764         DRM_DEBUG_KMS("\n");
1765
1766         intel_panel_enable_backlight(intel_dp->attached_connector);
1767         _intel_edp_backlight_on(intel_dp);
1768 }
1769
1770 /* Disable backlight in the panel power control. */
1771 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
1772 {
1773         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1774         struct drm_i915_private *dev_priv = dev->dev_private;
1775         u32 pp;
1776         u32 pp_ctrl_reg;
1777
1778         if (!is_edp(intel_dp))
1779                 return;
1780
1781         pps_lock(intel_dp);
1782
1783         pp = ironlake_get_pp_control(intel_dp);
1784         pp &= ~EDP_BLC_ENABLE;
1785
1786         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1787
1788         I915_WRITE(pp_ctrl_reg, pp);
1789         POSTING_READ(pp_ctrl_reg);
1790
1791         pps_unlock(intel_dp);
1792
1793         intel_dp->last_backlight_off = jiffies;
1794         edp_wait_backlight_off(intel_dp);
1795 }
1796
1797 /* Disable backlight PP control and backlight PWM. */
1798 void intel_edp_backlight_off(struct intel_dp *intel_dp)
1799 {
1800         if (!is_edp(intel_dp))
1801                 return;
1802
1803         DRM_DEBUG_KMS("\n");
1804
1805         _intel_edp_backlight_off(intel_dp);
1806         intel_panel_disable_backlight(intel_dp->attached_connector);
1807 }
1808
1809 /*
1810  * Hook for controlling the panel power control backlight through the bl_power
1811  * sysfs attribute. Take care to handle multiple calls.
1812  */
1813 static void intel_edp_backlight_power(struct intel_connector *connector,
1814                                       bool enable)
1815 {
1816         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
1817         bool is_enabled;
1818
1819         pps_lock(intel_dp);
1820         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
1821         pps_unlock(intel_dp);
1822
1823         if (is_enabled == enable)
1824                 return;
1825
1826         DRM_DEBUG_KMS("panel power control backlight %s\n",
1827                       enable ? "enable" : "disable");
1828
1829         if (enable)
1830                 _intel_edp_backlight_on(intel_dp);
1831         else
1832                 _intel_edp_backlight_off(intel_dp);
1833 }
1834
1835 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1836 {
1837         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1838         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1839         struct drm_device *dev = crtc->dev;
1840         struct drm_i915_private *dev_priv = dev->dev_private;
1841         u32 dpa_ctl;
1842
1843         assert_pipe_disabled(dev_priv,
1844                              to_intel_crtc(crtc)->pipe);
1845
1846         DRM_DEBUG_KMS("\n");
1847         dpa_ctl = I915_READ(DP_A);
1848         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1849         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1850
1851         /* We don't adjust intel_dp->DP while tearing down the link, to
1852          * facilitate link retraining (e.g. after hotplug). Hence clear all
1853          * enable bits here to ensure that we don't enable too much. */
1854         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1855         intel_dp->DP |= DP_PLL_ENABLE;
1856         I915_WRITE(DP_A, intel_dp->DP);
1857         POSTING_READ(DP_A);
1858         udelay(200);
1859 }
1860
1861 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1862 {
1863         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1864         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1865         struct drm_device *dev = crtc->dev;
1866         struct drm_i915_private *dev_priv = dev->dev_private;
1867         u32 dpa_ctl;
1868
1869         assert_pipe_disabled(dev_priv,
1870                              to_intel_crtc(crtc)->pipe);
1871
1872         dpa_ctl = I915_READ(DP_A);
1873         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1874              "dp pll off, should be on\n");
1875         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1876
1877         /* We can't rely on the value tracked for the DP register in
1878          * intel_dp->DP because link_down must not change that (otherwise link
1879          * re-training will fail. */
1880         dpa_ctl &= ~DP_PLL_ENABLE;
1881         I915_WRITE(DP_A, dpa_ctl);
1882         POSTING_READ(DP_A);
1883         udelay(200);
1884 }
1885
1886 /* If the sink supports it, try to set the power state appropriately */
1887 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1888 {
1889         int ret, i;
1890
1891         /* Should have a valid DPCD by this point */
1892         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1893                 return;
1894
1895         if (mode != DRM_MODE_DPMS_ON) {
1896                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1897                                          DP_SET_POWER_D3);
1898         } else {
1899                 /*
1900                  * When turning on, we need to retry for 1ms to give the sink
1901                  * time to wake up.
1902                  */
1903                 for (i = 0; i < 3; i++) {
1904                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1905                                                  DP_SET_POWER_D0);
1906                         if (ret == 1)
1907                                 break;
1908                         msleep(1);
1909                 }
1910         }
1911
1912         if (ret != 1)
1913                 DRM_DEBUG_KMS("failed to %s sink power state\n",
1914                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
1915 }
1916
1917 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1918                                   enum pipe *pipe)
1919 {
1920         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1921         enum port port = dp_to_dig_port(intel_dp)->port;
1922         struct drm_device *dev = encoder->base.dev;
1923         struct drm_i915_private *dev_priv = dev->dev_private;
1924         enum intel_display_power_domain power_domain;
1925         u32 tmp;
1926
1927         power_domain = intel_display_port_power_domain(encoder);
1928         if (!intel_display_power_is_enabled(dev_priv, power_domain))
1929                 return false;
1930
1931         tmp = I915_READ(intel_dp->output_reg);
1932
1933         if (!(tmp & DP_PORT_EN))
1934                 return false;
1935
1936         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1937                 *pipe = PORT_TO_PIPE_CPT(tmp);
1938         } else if (IS_CHERRYVIEW(dev)) {
1939                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
1940         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1941                 *pipe = PORT_TO_PIPE(tmp);
1942         } else {
1943                 u32 trans_sel;
1944                 u32 trans_dp;
1945                 int i;
1946
1947                 switch (intel_dp->output_reg) {
1948                 case PCH_DP_B:
1949                         trans_sel = TRANS_DP_PORT_SEL_B;
1950                         break;
1951                 case PCH_DP_C:
1952                         trans_sel = TRANS_DP_PORT_SEL_C;
1953                         break;
1954                 case PCH_DP_D:
1955                         trans_sel = TRANS_DP_PORT_SEL_D;
1956                         break;
1957                 default:
1958                         return true;
1959                 }
1960
1961                 for_each_pipe(dev_priv, i) {
1962                         trans_dp = I915_READ(TRANS_DP_CTL(i));
1963                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1964                                 *pipe = i;
1965                                 return true;
1966                         }
1967                 }
1968
1969                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1970                               intel_dp->output_reg);
1971         }
1972
1973         return true;
1974 }
1975
1976 static void intel_dp_get_config(struct intel_encoder *encoder,
1977                                 struct intel_crtc_config *pipe_config)
1978 {
1979         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1980         u32 tmp, flags = 0;
1981         struct drm_device *dev = encoder->base.dev;
1982         struct drm_i915_private *dev_priv = dev->dev_private;
1983         enum port port = dp_to_dig_port(intel_dp)->port;
1984         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1985         int dotclock;
1986
1987         tmp = I915_READ(intel_dp->output_reg);
1988         if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1989                 pipe_config->has_audio = true;
1990
1991         if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1992                 if (tmp & DP_SYNC_HS_HIGH)
1993                         flags |= DRM_MODE_FLAG_PHSYNC;
1994                 else
1995                         flags |= DRM_MODE_FLAG_NHSYNC;
1996
1997                 if (tmp & DP_SYNC_VS_HIGH)
1998                         flags |= DRM_MODE_FLAG_PVSYNC;
1999                 else
2000                         flags |= DRM_MODE_FLAG_NVSYNC;
2001         } else {
2002                 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2003                 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2004                         flags |= DRM_MODE_FLAG_PHSYNC;
2005                 else
2006                         flags |= DRM_MODE_FLAG_NHSYNC;
2007
2008                 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2009                         flags |= DRM_MODE_FLAG_PVSYNC;
2010                 else
2011                         flags |= DRM_MODE_FLAG_NVSYNC;
2012         }
2013
2014         pipe_config->adjusted_mode.flags |= flags;
2015
2016         if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2017             tmp & DP_COLOR_RANGE_16_235)
2018                 pipe_config->limited_color_range = true;
2019
2020         pipe_config->has_dp_encoder = true;
2021
2022         intel_dp_get_m_n(crtc, pipe_config);
2023
2024         if (port == PORT_A) {
2025                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
2026                         pipe_config->port_clock = 162000;
2027                 else
2028                         pipe_config->port_clock = 270000;
2029         }
2030
2031         dotclock = intel_dotclock_calculate(pipe_config->port_clock,
2032                                             &pipe_config->dp_m_n);
2033
2034         if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
2035                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
2036
2037         pipe_config->adjusted_mode.crtc_clock = dotclock;
2038
2039         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
2040             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2041                 /*
2042                  * This is a big fat ugly hack.
2043                  *
2044                  * Some machines in UEFI boot mode provide us a VBT that has 18
2045                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2046                  * unknown we fail to light up. Yet the same BIOS boots up with
2047                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2048                  * max, not what it tells us to use.
2049                  *
2050                  * Note: This will still be broken if the eDP panel is not lit
2051                  * up by the BIOS, and thus we can't get the mode at module
2052                  * load.
2053                  */
2054                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2055                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2056                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2057         }
2058 }
2059
2060 static bool is_edp_psr(struct intel_dp *intel_dp)
2061 {
2062         return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
2063 }
2064
2065 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
2066 {
2067         struct drm_i915_private *dev_priv = dev->dev_private;
2068
2069         if (!HAS_PSR(dev))
2070                 return false;
2071
2072         return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2073 }
2074
2075 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
2076                                     struct edp_vsc_psr *vsc_psr)
2077 {
2078         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2079         struct drm_device *dev = dig_port->base.base.dev;
2080         struct drm_i915_private *dev_priv = dev->dev_private;
2081         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
2082         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
2083         u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
2084         uint32_t *data = (uint32_t *) vsc_psr;
2085         unsigned int i;
2086
2087         /* As per BSPec (Pipe Video Data Island Packet), we need to disable
2088            the video DIP being updated before program video DIP data buffer
2089            registers for DIP being updated. */
2090         I915_WRITE(ctl_reg, 0);
2091         POSTING_READ(ctl_reg);
2092
2093         for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
2094                 if (i < sizeof(struct edp_vsc_psr))
2095                         I915_WRITE(data_reg + i, *data++);
2096                 else
2097                         I915_WRITE(data_reg + i, 0);
2098         }
2099
2100         I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
2101         POSTING_READ(ctl_reg);
2102 }
2103
2104 static void intel_edp_psr_setup_vsc(struct intel_dp *intel_dp)
2105 {
2106         struct edp_vsc_psr psr_vsc;
2107
2108         /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
2109         memset(&psr_vsc, 0, sizeof(psr_vsc));
2110         psr_vsc.sdp_header.HB0 = 0;
2111         psr_vsc.sdp_header.HB1 = 0x7;
2112         psr_vsc.sdp_header.HB2 = 0x2;
2113         psr_vsc.sdp_header.HB3 = 0x8;
2114         intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
2115 }
2116
2117 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
2118 {
2119         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2120         struct drm_device *dev = dig_port->base.base.dev;
2121         struct drm_i915_private *dev_priv = dev->dev_private;
2122         uint32_t aux_clock_divider;
2123         int precharge = 0x3;
2124         bool only_standby = false;
2125         static const uint8_t aux_msg[] = {
2126                 [0] = DP_AUX_NATIVE_WRITE << 4,
2127                 [1] = DP_SET_POWER >> 8,
2128                 [2] = DP_SET_POWER & 0xff,
2129                 [3] = 1 - 1,
2130                 [4] = DP_SET_POWER_D0,
2131         };
2132         int i;
2133
2134         BUILD_BUG_ON(sizeof(aux_msg) > 20);
2135
2136         aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
2137
2138         if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2139                 only_standby = true;
2140
2141         /* Enable PSR in sink */
2142         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
2143                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2144                                    DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2145         else
2146                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2147                                    DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2148
2149         /* Setup AUX registers */
2150         for (i = 0; i < sizeof(aux_msg); i += 4)
2151                 I915_WRITE(EDP_PSR_AUX_DATA1(dev) + i,
2152                            pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
2153
2154         I915_WRITE(EDP_PSR_AUX_CTL(dev),
2155                    DP_AUX_CH_CTL_TIME_OUT_400us |
2156                    (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
2157                    (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
2158                    (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
2159 }
2160
2161 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
2162 {
2163         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2164         struct drm_device *dev = dig_port->base.base.dev;
2165         struct drm_i915_private *dev_priv = dev->dev_private;
2166         uint32_t max_sleep_time = 0x1f;
2167         uint32_t idle_frames = 1;
2168         uint32_t val = 0x0;
2169         const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
2170         bool only_standby = false;
2171
2172         if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2173                 only_standby = true;
2174
2175         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2176                 val |= EDP_PSR_LINK_STANDBY;
2177                 val |= EDP_PSR_TP2_TP3_TIME_0us;
2178                 val |= EDP_PSR_TP1_TIME_0us;
2179                 val |= EDP_PSR_SKIP_AUX_EXIT;
2180                 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2181         } else
2182                 val |= EDP_PSR_LINK_DISABLE;
2183
2184         I915_WRITE(EDP_PSR_CTL(dev), val |
2185                    (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2186                    max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
2187                    idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
2188                    EDP_PSR_ENABLE);
2189 }
2190
2191 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
2192 {
2193         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2194         struct drm_device *dev = dig_port->base.base.dev;
2195         struct drm_i915_private *dev_priv = dev->dev_private;
2196         struct drm_crtc *crtc = dig_port->base.base.crtc;
2197         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2198
2199         lockdep_assert_held(&dev_priv->psr.lock);
2200         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
2201         WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
2202
2203         dev_priv->psr.source_ok = false;
2204
2205         if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
2206                 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
2207                 return false;
2208         }
2209
2210         if (!i915.enable_psr) {
2211                 DRM_DEBUG_KMS("PSR disable by flag\n");
2212                 return false;
2213         }
2214
2215         /* Below limitations aren't valid for Broadwell */
2216         if (IS_BROADWELL(dev))
2217                 goto out;
2218
2219         if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
2220             S3D_ENABLE) {
2221                 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
2222                 return false;
2223         }
2224
2225         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
2226                 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
2227                 return false;
2228         }
2229
2230  out:
2231         dev_priv->psr.source_ok = true;
2232         return true;
2233 }
2234
2235 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2236 {
2237         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2238         struct drm_device *dev = intel_dig_port->base.base.dev;
2239         struct drm_i915_private *dev_priv = dev->dev_private;
2240
2241         WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2242         WARN_ON(dev_priv->psr.active);
2243         lockdep_assert_held(&dev_priv->psr.lock);
2244
2245         /* Enable/Re-enable PSR on the host */
2246         intel_edp_psr_enable_source(intel_dp);
2247
2248         dev_priv->psr.active = true;
2249 }
2250
2251 void intel_edp_psr_enable(struct intel_dp *intel_dp)
2252 {
2253         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2254         struct drm_i915_private *dev_priv = dev->dev_private;
2255
2256         if (!HAS_PSR(dev)) {
2257                 DRM_DEBUG_KMS("PSR not supported on this platform\n");
2258                 return;
2259         }
2260
2261         if (!is_edp_psr(intel_dp)) {
2262                 DRM_DEBUG_KMS("PSR not supported by this panel\n");
2263                 return;
2264         }
2265
2266         mutex_lock(&dev_priv->psr.lock);
2267         if (dev_priv->psr.enabled) {
2268                 DRM_DEBUG_KMS("PSR already in use\n");
2269                 goto unlock;
2270         }
2271
2272         if (!intel_edp_psr_match_conditions(intel_dp))
2273                 goto unlock;
2274
2275         dev_priv->psr.busy_frontbuffer_bits = 0;
2276
2277         intel_edp_psr_setup_vsc(intel_dp);
2278
2279         /* Avoid continuous PSR exit by masking memup and hpd */
2280         I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
2281                    EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2282
2283         /* Enable PSR on the panel */
2284         intel_edp_psr_enable_sink(intel_dp);
2285
2286         dev_priv->psr.enabled = intel_dp;
2287 unlock:
2288         mutex_unlock(&dev_priv->psr.lock);
2289 }
2290
2291 void intel_edp_psr_disable(struct intel_dp *intel_dp)
2292 {
2293         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2294         struct drm_i915_private *dev_priv = dev->dev_private;
2295
2296         mutex_lock(&dev_priv->psr.lock);
2297         if (!dev_priv->psr.enabled) {
2298                 mutex_unlock(&dev_priv->psr.lock);
2299                 return;
2300         }
2301
2302         if (dev_priv->psr.active) {
2303                 I915_WRITE(EDP_PSR_CTL(dev),
2304                            I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2305
2306                 /* Wait till PSR is idle */
2307                 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2308                                EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
2309                         DRM_ERROR("Timed out waiting for PSR Idle State\n");
2310
2311                 dev_priv->psr.active = false;
2312         } else {
2313                 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2314         }
2315
2316         dev_priv->psr.enabled = NULL;
2317         mutex_unlock(&dev_priv->psr.lock);
2318
2319         cancel_delayed_work_sync(&dev_priv->psr.work);
2320 }
2321
2322 static void intel_edp_psr_work(struct work_struct *work)
2323 {
2324         struct drm_i915_private *dev_priv =
2325                 container_of(work, typeof(*dev_priv), psr.work.work);
2326         struct intel_dp *intel_dp = dev_priv->psr.enabled;
2327
2328         /* We have to make sure PSR is ready for re-enable
2329          * otherwise it keeps disabled until next full enable/disable cycle.
2330          * PSR might take some time to get fully disabled
2331          * and be ready for re-enable.
2332          */
2333         if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
2334                       EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
2335                 DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
2336                 return;
2337         }
2338
2339         mutex_lock(&dev_priv->psr.lock);
2340         intel_dp = dev_priv->psr.enabled;
2341
2342         if (!intel_dp)
2343                 goto unlock;
2344
2345         /*
2346          * The delayed work can race with an invalidate hence we need to
2347          * recheck. Since psr_flush first clears this and then reschedules we
2348          * won't ever miss a flush when bailing out here.
2349          */
2350         if (dev_priv->psr.busy_frontbuffer_bits)
2351                 goto unlock;
2352
2353         intel_edp_psr_do_enable(intel_dp);
2354 unlock:
2355         mutex_unlock(&dev_priv->psr.lock);
2356 }
2357
2358 static void intel_edp_psr_do_exit(struct drm_device *dev)
2359 {
2360         struct drm_i915_private *dev_priv = dev->dev_private;
2361
2362         if (dev_priv->psr.active) {
2363                 u32 val = I915_READ(EDP_PSR_CTL(dev));
2364
2365                 WARN_ON(!(val & EDP_PSR_ENABLE));
2366
2367                 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
2368
2369                 dev_priv->psr.active = false;
2370         }
2371
2372 }
2373
2374 void intel_edp_psr_invalidate(struct drm_device *dev,
2375                               unsigned frontbuffer_bits)
2376 {
2377         struct drm_i915_private *dev_priv = dev->dev_private;
2378         struct drm_crtc *crtc;
2379         enum pipe pipe;
2380
2381         mutex_lock(&dev_priv->psr.lock);
2382         if (!dev_priv->psr.enabled) {
2383                 mutex_unlock(&dev_priv->psr.lock);
2384                 return;
2385         }
2386
2387         crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2388         pipe = to_intel_crtc(crtc)->pipe;
2389
2390         intel_edp_psr_do_exit(dev);
2391
2392         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
2393
2394         dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
2395         mutex_unlock(&dev_priv->psr.lock);
2396 }
2397
2398 void intel_edp_psr_flush(struct drm_device *dev,
2399                          unsigned frontbuffer_bits)
2400 {
2401         struct drm_i915_private *dev_priv = dev->dev_private;
2402         struct drm_crtc *crtc;
2403         enum pipe pipe;
2404
2405         mutex_lock(&dev_priv->psr.lock);
2406         if (!dev_priv->psr.enabled) {
2407                 mutex_unlock(&dev_priv->psr.lock);
2408                 return;
2409         }
2410
2411         crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2412         pipe = to_intel_crtc(crtc)->pipe;
2413         dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2414
2415         /*
2416          * On Haswell sprite plane updates don't result in a psr invalidating
2417          * signal in the hardware. Which means we need to manually fake this in
2418          * software for all flushes, not just when we've seen a preceding
2419          * invalidation through frontbuffer rendering.
2420          */
2421         if (IS_HASWELL(dev) &&
2422             (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2423                 intel_edp_psr_do_exit(dev);
2424
2425         if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2426                 schedule_delayed_work(&dev_priv->psr.work,
2427                                       msecs_to_jiffies(100));
2428         mutex_unlock(&dev_priv->psr.lock);
2429 }
2430
2431 void intel_edp_psr_init(struct drm_device *dev)
2432 {
2433         struct drm_i915_private *dev_priv = dev->dev_private;
2434
2435         INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
2436         mutex_init(&dev_priv->psr.lock);
2437 }
2438
2439 static void intel_disable_dp(struct intel_encoder *encoder)
2440 {
2441         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2442         struct drm_device *dev = encoder->base.dev;
2443
2444         /* Make sure the panel is off before trying to change the mode. But also
2445          * ensure that we have vdd while we switch off the panel. */
2446         intel_edp_panel_vdd_on(intel_dp);
2447         intel_edp_backlight_off(intel_dp);
2448         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2449         intel_edp_panel_off(intel_dp);
2450
2451         /* disable the port before the pipe on g4x */
2452         if (INTEL_INFO(dev)->gen < 5)
2453                 intel_dp_link_down(intel_dp);
2454 }
2455
2456 static void ilk_post_disable_dp(struct intel_encoder *encoder)
2457 {
2458         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2459         enum port port = dp_to_dig_port(intel_dp)->port;
2460
2461         intel_dp_link_down(intel_dp);
2462         if (port == PORT_A)
2463                 ironlake_edp_pll_off(intel_dp);
2464 }
2465
2466 static void vlv_post_disable_dp(struct intel_encoder *encoder)
2467 {
2468         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2469
2470         intel_dp_link_down(intel_dp);
2471 }
2472
2473 static void chv_post_disable_dp(struct intel_encoder *encoder)
2474 {
2475         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2476         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2477         struct drm_device *dev = encoder->base.dev;
2478         struct drm_i915_private *dev_priv = dev->dev_private;
2479         struct intel_crtc *intel_crtc =
2480                 to_intel_crtc(encoder->base.crtc);
2481         enum dpio_channel ch = vlv_dport_to_channel(dport);
2482         enum pipe pipe = intel_crtc->pipe;
2483         u32 val;
2484
2485         intel_dp_link_down(intel_dp);
2486
2487         mutex_lock(&dev_priv->dpio_lock);
2488
2489         /* Propagate soft reset to data lane reset */
2490         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2491         val |= CHV_PCS_REQ_SOFTRESET_EN;
2492         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2493
2494         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2495         val |= CHV_PCS_REQ_SOFTRESET_EN;
2496         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2497
2498         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2499         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2500         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2501
2502         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2503         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2504         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2505
2506         mutex_unlock(&dev_priv->dpio_lock);
2507 }
2508
2509 static void
2510 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2511                          uint32_t *DP,
2512                          uint8_t dp_train_pat)
2513 {
2514         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2515         struct drm_device *dev = intel_dig_port->base.base.dev;
2516         struct drm_i915_private *dev_priv = dev->dev_private;
2517         enum port port = intel_dig_port->port;
2518
2519         if (HAS_DDI(dev)) {
2520                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2521
2522                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2523                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2524                 else
2525                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2526
2527                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2528                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2529                 case DP_TRAINING_PATTERN_DISABLE:
2530                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2531
2532                         break;
2533                 case DP_TRAINING_PATTERN_1:
2534                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2535                         break;
2536                 case DP_TRAINING_PATTERN_2:
2537                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2538                         break;
2539                 case DP_TRAINING_PATTERN_3:
2540                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2541                         break;
2542                 }
2543                 I915_WRITE(DP_TP_CTL(port), temp);
2544
2545         } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2546                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2547
2548                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2549                 case DP_TRAINING_PATTERN_DISABLE:
2550                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2551                         break;
2552                 case DP_TRAINING_PATTERN_1:
2553                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2554                         break;
2555                 case DP_TRAINING_PATTERN_2:
2556                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2557                         break;
2558                 case DP_TRAINING_PATTERN_3:
2559                         DRM_ERROR("DP training pattern 3 not supported\n");
2560                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2561                         break;
2562                 }
2563
2564         } else {
2565                 if (IS_CHERRYVIEW(dev))
2566                         *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2567                 else
2568                         *DP &= ~DP_LINK_TRAIN_MASK;
2569
2570                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2571                 case DP_TRAINING_PATTERN_DISABLE:
2572                         *DP |= DP_LINK_TRAIN_OFF;
2573                         break;
2574                 case DP_TRAINING_PATTERN_1:
2575                         *DP |= DP_LINK_TRAIN_PAT_1;
2576                         break;
2577                 case DP_TRAINING_PATTERN_2:
2578                         *DP |= DP_LINK_TRAIN_PAT_2;
2579                         break;
2580                 case DP_TRAINING_PATTERN_3:
2581                         if (IS_CHERRYVIEW(dev)) {
2582                                 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2583                         } else {
2584                                 DRM_ERROR("DP training pattern 3 not supported\n");
2585                                 *DP |= DP_LINK_TRAIN_PAT_2;
2586                         }
2587                         break;
2588                 }
2589         }
2590 }
2591
2592 static void intel_dp_enable_port(struct intel_dp *intel_dp)
2593 {
2594         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2595         struct drm_i915_private *dev_priv = dev->dev_private;
2596
2597         /* enable with pattern 1 (as per spec) */
2598         _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2599                                  DP_TRAINING_PATTERN_1);
2600
2601         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2602         POSTING_READ(intel_dp->output_reg);
2603
2604         /*
2605          * Magic for VLV/CHV. We _must_ first set up the register
2606          * without actually enabling the port, and then do another
2607          * write to enable the port. Otherwise link training will
2608          * fail when the power sequencer is freshly used for this port.
2609          */
2610         intel_dp->DP |= DP_PORT_EN;
2611
2612         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2613         POSTING_READ(intel_dp->output_reg);
2614 }
2615
2616 static void intel_enable_dp(struct intel_encoder *encoder)
2617 {
2618         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2619         struct drm_device *dev = encoder->base.dev;
2620         struct drm_i915_private *dev_priv = dev->dev_private;
2621         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2622
2623         if (WARN_ON(dp_reg & DP_PORT_EN))
2624                 return;
2625
2626         pps_lock(intel_dp);
2627
2628         if (IS_VALLEYVIEW(dev))
2629                 vlv_init_panel_power_sequencer(intel_dp);
2630
2631         intel_dp_enable_port(intel_dp);
2632
2633         edp_panel_vdd_on(intel_dp);
2634         edp_panel_on(intel_dp);
2635         edp_panel_vdd_off(intel_dp, true);
2636
2637         pps_unlock(intel_dp);
2638
2639         if (IS_VALLEYVIEW(dev))
2640                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp));
2641
2642         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2643         intel_dp_start_link_train(intel_dp);
2644         intel_dp_complete_link_train(intel_dp);
2645         intel_dp_stop_link_train(intel_dp);
2646 }
2647
2648 static void g4x_enable_dp(struct intel_encoder *encoder)
2649 {
2650         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2651
2652         intel_enable_dp(encoder);
2653         intel_edp_backlight_on(intel_dp);
2654 }
2655
2656 static void vlv_enable_dp(struct intel_encoder *encoder)
2657 {
2658         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2659
2660         intel_edp_backlight_on(intel_dp);
2661 }
2662
2663 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2664 {
2665         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2666         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2667
2668         intel_dp_prepare(encoder);
2669
2670         /* Only ilk+ has port A */
2671         if (dport->port == PORT_A) {
2672                 ironlake_set_pll_cpu_edp(intel_dp);
2673                 ironlake_edp_pll_on(intel_dp);
2674         }
2675 }
2676
2677 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2678 {
2679         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2680         struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2681         enum pipe pipe = intel_dp->pps_pipe;
2682         int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2683
2684         edp_panel_vdd_off_sync(intel_dp);
2685
2686         /*
2687          * VLV seems to get confused when multiple power seqeuencers
2688          * have the same port selected (even if only one has power/vdd
2689          * enabled). The failure manifests as vlv_wait_port_ready() failing
2690          * CHV on the other hand doesn't seem to mind having the same port
2691          * selected in multiple power seqeuencers, but let's clear the
2692          * port select always when logically disconnecting a power sequencer
2693          * from a port.
2694          */
2695         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2696                       pipe_name(pipe), port_name(intel_dig_port->port));
2697         I915_WRITE(pp_on_reg, 0);
2698         POSTING_READ(pp_on_reg);
2699
2700         intel_dp->pps_pipe = INVALID_PIPE;
2701 }
2702
2703 static void vlv_steal_power_sequencer(struct drm_device *dev,
2704                                       enum pipe pipe)
2705 {
2706         struct drm_i915_private *dev_priv = dev->dev_private;
2707         struct intel_encoder *encoder;
2708
2709         lockdep_assert_held(&dev_priv->pps_mutex);
2710
2711         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2712                 return;
2713
2714         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2715                             base.head) {
2716                 struct intel_dp *intel_dp;
2717                 enum port port;
2718
2719                 if (encoder->type != INTEL_OUTPUT_EDP)
2720                         continue;
2721
2722                 intel_dp = enc_to_intel_dp(&encoder->base);
2723                 port = dp_to_dig_port(intel_dp)->port;
2724
2725                 if (intel_dp->pps_pipe != pipe)
2726                         continue;
2727
2728                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2729                               pipe_name(pipe), port_name(port));
2730
2731                 WARN(encoder->connectors_active,
2732                      "stealing pipe %c power sequencer from active eDP port %c\n",
2733                      pipe_name(pipe), port_name(port));
2734
2735                 /* make sure vdd is off before we steal it */
2736                 vlv_detach_power_sequencer(intel_dp);
2737         }
2738 }
2739
2740 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2741 {
2742         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2743         struct intel_encoder *encoder = &intel_dig_port->base;
2744         struct drm_device *dev = encoder->base.dev;
2745         struct drm_i915_private *dev_priv = dev->dev_private;
2746         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2747
2748         lockdep_assert_held(&dev_priv->pps_mutex);
2749
2750         if (!is_edp(intel_dp))
2751                 return;
2752
2753         if (intel_dp->pps_pipe == crtc->pipe)
2754                 return;
2755
2756         /*
2757          * If another power sequencer was being used on this
2758          * port previously make sure to turn off vdd there while
2759          * we still have control of it.
2760          */
2761         if (intel_dp->pps_pipe != INVALID_PIPE)
2762                 vlv_detach_power_sequencer(intel_dp);
2763
2764         /*
2765          * We may be stealing the power
2766          * sequencer from another port.
2767          */
2768         vlv_steal_power_sequencer(dev, crtc->pipe);
2769
2770         /* now it's all ours */
2771         intel_dp->pps_pipe = crtc->pipe;
2772
2773         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2774                       pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2775
2776         /* init power sequencer on this pipe and port */
2777         intel_dp_init_panel_power_sequencer(dev, intel_dp);
2778         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
2779 }
2780
2781 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2782 {
2783         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2784         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2785         struct drm_device *dev = encoder->base.dev;
2786         struct drm_i915_private *dev_priv = dev->dev_private;
2787         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2788         enum dpio_channel port = vlv_dport_to_channel(dport);
2789         int pipe = intel_crtc->pipe;
2790         u32 val;
2791
2792         mutex_lock(&dev_priv->dpio_lock);
2793
2794         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
2795         val = 0;
2796         if (pipe)
2797                 val |= (1<<21);
2798         else
2799                 val &= ~(1<<21);
2800         val |= 0x001000c4;
2801         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2802         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2803         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
2804
2805         mutex_unlock(&dev_priv->dpio_lock);
2806
2807         intel_enable_dp(encoder);
2808 }
2809
2810 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2811 {
2812         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2813         struct drm_device *dev = encoder->base.dev;
2814         struct drm_i915_private *dev_priv = dev->dev_private;
2815         struct intel_crtc *intel_crtc =
2816                 to_intel_crtc(encoder->base.crtc);
2817         enum dpio_channel port = vlv_dport_to_channel(dport);
2818         int pipe = intel_crtc->pipe;
2819
2820         intel_dp_prepare(encoder);
2821
2822         /* Program Tx lane resets to default */
2823         mutex_lock(&dev_priv->dpio_lock);
2824         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
2825                          DPIO_PCS_TX_LANE2_RESET |
2826                          DPIO_PCS_TX_LANE1_RESET);
2827         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
2828                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2829                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2830                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2831                                  DPIO_PCS_CLK_SOFT_RESET);
2832
2833         /* Fix up inter-pair skew failure */
2834         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2835         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2836         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
2837         mutex_unlock(&dev_priv->dpio_lock);
2838 }
2839
2840 static void chv_pre_enable_dp(struct intel_encoder *encoder)
2841 {
2842         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2843         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2844         struct drm_device *dev = encoder->base.dev;
2845         struct drm_i915_private *dev_priv = dev->dev_private;
2846         struct intel_crtc *intel_crtc =
2847                 to_intel_crtc(encoder->base.crtc);
2848         enum dpio_channel ch = vlv_dport_to_channel(dport);
2849         int pipe = intel_crtc->pipe;
2850         int data, i;
2851         u32 val;
2852
2853         mutex_lock(&dev_priv->dpio_lock);
2854
2855         /* allow hardware to manage TX FIFO reset source */
2856         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2857         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2858         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2859
2860         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2861         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2862         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2863
2864         /* Deassert soft data lane reset*/
2865         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2866         val |= CHV_PCS_REQ_SOFTRESET_EN;
2867         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2868
2869         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2870         val |= CHV_PCS_REQ_SOFTRESET_EN;
2871         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2872
2873         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2874         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2875         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2876
2877         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2878         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2879         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2880
2881         /* Program Tx lane latency optimal setting*/
2882         for (i = 0; i < 4; i++) {
2883                 /* Set the latency optimal bit */
2884                 data = (i == 1) ? 0x0 : 0x6;
2885                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2886                                 data << DPIO_FRC_LATENCY_SHFIT);
2887
2888                 /* Set the upar bit */
2889                 data = (i == 1) ? 0x0 : 0x1;
2890                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2891                                 data << DPIO_UPAR_SHIFT);
2892         }
2893
2894         /* Data lane stagger programming */
2895         /* FIXME: Fix up value only after power analysis */
2896
2897         mutex_unlock(&dev_priv->dpio_lock);
2898
2899         intel_enable_dp(encoder);
2900 }
2901
2902 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2903 {
2904         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2905         struct drm_device *dev = encoder->base.dev;
2906         struct drm_i915_private *dev_priv = dev->dev_private;
2907         struct intel_crtc *intel_crtc =
2908                 to_intel_crtc(encoder->base.crtc);
2909         enum dpio_channel ch = vlv_dport_to_channel(dport);
2910         enum pipe pipe = intel_crtc->pipe;
2911         u32 val;
2912
2913         intel_dp_prepare(encoder);
2914
2915         mutex_lock(&dev_priv->dpio_lock);
2916
2917         /* program left/right clock distribution */
2918         if (pipe != PIPE_B) {
2919                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2920                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2921                 if (ch == DPIO_CH0)
2922                         val |= CHV_BUFLEFTENA1_FORCE;
2923                 if (ch == DPIO_CH1)
2924                         val |= CHV_BUFRIGHTENA1_FORCE;
2925                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2926         } else {
2927                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2928                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2929                 if (ch == DPIO_CH0)
2930                         val |= CHV_BUFLEFTENA2_FORCE;
2931                 if (ch == DPIO_CH1)
2932                         val |= CHV_BUFRIGHTENA2_FORCE;
2933                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2934         }
2935
2936         /* program clock channel usage */
2937         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2938         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2939         if (pipe != PIPE_B)
2940                 val &= ~CHV_PCS_USEDCLKCHANNEL;
2941         else
2942                 val |= CHV_PCS_USEDCLKCHANNEL;
2943         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2944
2945         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2946         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2947         if (pipe != PIPE_B)
2948                 val &= ~CHV_PCS_USEDCLKCHANNEL;
2949         else
2950                 val |= CHV_PCS_USEDCLKCHANNEL;
2951         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2952
2953         /*
2954          * This a a bit weird since generally CL
2955          * matches the pipe, but here we need to
2956          * pick the CL based on the port.
2957          */
2958         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2959         if (pipe != PIPE_B)
2960                 val &= ~CHV_CMN_USEDCLKCHANNEL;
2961         else
2962                 val |= CHV_CMN_USEDCLKCHANNEL;
2963         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2964
2965         mutex_unlock(&dev_priv->dpio_lock);
2966 }
2967
2968 /*
2969  * Native read with retry for link status and receiver capability reads for
2970  * cases where the sink may still be asleep.
2971  *
2972  * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2973  * supposed to retry 3 times per the spec.
2974  */
2975 static ssize_t
2976 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2977                         void *buffer, size_t size)
2978 {
2979         ssize_t ret;
2980         int i;
2981
2982         for (i = 0; i < 3; i++) {
2983                 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2984                 if (ret == size)
2985                         return ret;
2986                 msleep(1);
2987         }
2988
2989         return ret;
2990 }
2991
2992 /*
2993  * Fetch AUX CH registers 0x202 - 0x207 which contain
2994  * link status information
2995  */
2996 static bool
2997 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2998 {
2999         return intel_dp_dpcd_read_wake(&intel_dp->aux,
3000                                        DP_LANE0_1_STATUS,
3001                                        link_status,
3002                                        DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3003 }
3004
3005 /* These are source-specific values. */
3006 static uint8_t
3007 intel_dp_voltage_max(struct intel_dp *intel_dp)
3008 {
3009         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3010         enum port port = dp_to_dig_port(intel_dp)->port;
3011
3012         if (INTEL_INFO(dev)->gen >= 9)
3013                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3014         else if (IS_VALLEYVIEW(dev))
3015                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3016         else if (IS_GEN7(dev) && port == PORT_A)
3017                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3018         else if (HAS_PCH_CPT(dev) && port != PORT_A)
3019                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3020         else
3021                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3022 }
3023
3024 static uint8_t
3025 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3026 {
3027         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3028         enum port port = dp_to_dig_port(intel_dp)->port;
3029
3030         if (INTEL_INFO(dev)->gen >= 9) {
3031                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3032                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3033                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3034                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3035                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3036                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3037                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3038                 default:
3039                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3040                 }
3041         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3042                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3043                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3044                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3045                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3046                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3047                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3048                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3049                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3050                 default:
3051                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3052                 }
3053         } else if (IS_VALLEYVIEW(dev)) {
3054                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3055                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3056                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3057                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3058                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3059                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3060                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3061                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3062                 default:
3063                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3064                 }
3065         } else if (IS_GEN7(dev) && port == PORT_A) {
3066                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3067                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3068                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3069                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3070                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3071                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3072                 default:
3073                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3074                 }
3075         } else {
3076                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3077                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3078                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3079                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3080                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3081                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3082                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3083                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3084                 default:
3085                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3086                 }
3087         }
3088 }
3089
3090 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
3091 {
3092         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3093         struct drm_i915_private *dev_priv = dev->dev_private;
3094         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3095         struct intel_crtc *intel_crtc =
3096                 to_intel_crtc(dport->base.base.crtc);
3097         unsigned long demph_reg_value, preemph_reg_value,
3098                 uniqtranscale_reg_value;
3099         uint8_t train_set = intel_dp->train_set[0];
3100         enum dpio_channel port = vlv_dport_to_channel(dport);
3101         int pipe = intel_crtc->pipe;
3102
3103         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3104         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3105                 preemph_reg_value = 0x0004000;
3106                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3107                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3108                         demph_reg_value = 0x2B405555;
3109                         uniqtranscale_reg_value = 0x552AB83A;
3110                         break;
3111                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3112                         demph_reg_value = 0x2B404040;
3113                         uniqtranscale_reg_value = 0x5548B83A;
3114                         break;
3115                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3116                         demph_reg_value = 0x2B245555;
3117                         uniqtranscale_reg_value = 0x5560B83A;
3118                         break;
3119                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3120                         demph_reg_value = 0x2B405555;
3121                         uniqtranscale_reg_value = 0x5598DA3A;
3122                         break;
3123                 default:
3124                         return 0;
3125                 }
3126                 break;
3127         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3128                 preemph_reg_value = 0x0002000;
3129                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3130                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3131                         demph_reg_value = 0x2B404040;
3132                         uniqtranscale_reg_value = 0x5552B83A;
3133                         break;
3134                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3135                         demph_reg_value = 0x2B404848;
3136                         uniqtranscale_reg_value = 0x5580B83A;
3137                         break;
3138                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3139                         demph_reg_value = 0x2B404040;
3140                         uniqtranscale_reg_value = 0x55ADDA3A;
3141                         break;
3142                 default:
3143                         return 0;
3144                 }
3145                 break;
3146         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3147                 preemph_reg_value = 0x0000000;
3148                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3149                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3150                         demph_reg_value = 0x2B305555;
3151                         uniqtranscale_reg_value = 0x5570B83A;
3152                         break;
3153                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3154                         demph_reg_value = 0x2B2B4040;
3155                         uniqtranscale_reg_value = 0x55ADDA3A;
3156                         break;
3157                 default:
3158                         return 0;
3159                 }
3160                 break;
3161         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3162                 preemph_reg_value = 0x0006000;
3163                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3164                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3165                         demph_reg_value = 0x1B405555;
3166                         uniqtranscale_reg_value = 0x55ADDA3A;
3167                         break;
3168                 default:
3169                         return 0;
3170                 }
3171                 break;
3172         default:
3173                 return 0;
3174         }
3175
3176         mutex_lock(&dev_priv->dpio_lock);
3177         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
3178         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3179         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
3180                          uniqtranscale_reg_value);
3181         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3182         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3183         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3184         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
3185         mutex_unlock(&dev_priv->dpio_lock);
3186
3187         return 0;
3188 }
3189
3190 static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
3191 {
3192         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3193         struct drm_i915_private *dev_priv = dev->dev_private;
3194         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3195         struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
3196         u32 deemph_reg_value, margin_reg_value, val;
3197         uint8_t train_set = intel_dp->train_set[0];
3198         enum dpio_channel ch = vlv_dport_to_channel(dport);
3199         enum pipe pipe = intel_crtc->pipe;
3200         int i;
3201
3202         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3203         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3204                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3205                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3206                         deemph_reg_value = 128;
3207                         margin_reg_value = 52;
3208                         break;
3209                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3210                         deemph_reg_value = 128;
3211                         margin_reg_value = 77;
3212                         break;
3213                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3214                         deemph_reg_value = 128;
3215                         margin_reg_value = 102;
3216                         break;
3217                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3218                         deemph_reg_value = 128;
3219                         margin_reg_value = 154;
3220                         /* FIXME extra to set for 1200 */
3221                         break;
3222                 default:
3223                         return 0;
3224                 }
3225                 break;
3226         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3227                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3228                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3229                         deemph_reg_value = 85;
3230                         margin_reg_value = 78;
3231                         break;
3232                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3233                         deemph_reg_value = 85;
3234                         margin_reg_value = 116;
3235                         break;
3236                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3237                         deemph_reg_value = 85;
3238                         margin_reg_value = 154;
3239                         break;
3240                 default:
3241                         return 0;
3242                 }
3243                 break;
3244         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3245                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3246                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3247                         deemph_reg_value = 64;
3248                         margin_reg_value = 104;
3249                         break;
3250                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3251                         deemph_reg_value = 64;
3252                         margin_reg_value = 154;
3253                         break;
3254                 default:
3255                         return 0;
3256                 }
3257                 break;
3258         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3259                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3260                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3261                         deemph_reg_value = 43;
3262                         margin_reg_value = 154;
3263                         break;
3264                 default:
3265                         return 0;
3266                 }
3267                 break;
3268         default:
3269                 return 0;
3270         }
3271
3272         mutex_lock(&dev_priv->dpio_lock);
3273
3274         /* Clear calc init */
3275         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3276         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3277         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3278         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
3279         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3280
3281         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3282         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3283         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3284         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
3285         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3286
3287         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
3288         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3289         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3290         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
3291
3292         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
3293         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3294         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3295         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
3296
3297         /* Program swing deemph */
3298         for (i = 0; i < 4; i++) {
3299                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3300                 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3301                 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3302                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3303         }
3304
3305         /* Program swing margin */
3306         for (i = 0; i < 4; i++) {
3307                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3308                 val &= ~DPIO_SWING_MARGIN000_MASK;
3309                 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
3310                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3311         }
3312
3313         /* Disable unique transition scale */
3314         for (i = 0; i < 4; i++) {
3315                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3316                 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3317                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3318         }
3319
3320         if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
3321                         == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
3322                 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
3323                         == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
3324
3325                 /*
3326                  * The document said it needs to set bit 27 for ch0 and bit 26
3327                  * for ch1. Might be a typo in the doc.
3328                  * For now, for this unique transition scale selection, set bit
3329                  * 27 for ch0 and ch1.
3330                  */
3331                 for (i = 0; i < 4; i++) {
3332                         val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3333                         val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3334                         vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3335                 }
3336
3337                 for (i = 0; i < 4; i++) {
3338                         val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3339                         val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3340                         val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3341                         vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3342                 }
3343         }
3344
3345         /* Start swing calculation */
3346         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3347         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3348         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3349
3350         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3351         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3352         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3353
3354         /* LRC Bypass */
3355         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3356         val |= DPIO_LRC_BYPASS;
3357         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3358
3359         mutex_unlock(&dev_priv->dpio_lock);
3360
3361         return 0;
3362 }
3363
3364 static void
3365 intel_get_adjust_train(struct intel_dp *intel_dp,
3366                        const uint8_t link_status[DP_LINK_STATUS_SIZE])
3367 {
3368         uint8_t v = 0;
3369         uint8_t p = 0;
3370         int lane;
3371         uint8_t voltage_max;
3372         uint8_t preemph_max;
3373
3374         for (lane = 0; lane < intel_dp->lane_count; lane++) {
3375                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3376                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
3377
3378                 if (this_v > v)
3379                         v = this_v;
3380                 if (this_p > p)
3381                         p = this_p;
3382         }
3383
3384         voltage_max = intel_dp_voltage_max(intel_dp);
3385         if (v >= voltage_max)
3386                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
3387
3388         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3389         if (p >= preemph_max)
3390                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
3391
3392         for (lane = 0; lane < 4; lane++)
3393                 intel_dp->train_set[lane] = v | p;
3394 }
3395
3396 static uint32_t
3397 intel_gen4_signal_levels(uint8_t train_set)
3398 {
3399         uint32_t        signal_levels = 0;
3400
3401         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3402         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3403         default:
3404                 signal_levels |= DP_VOLTAGE_0_4;
3405                 break;
3406         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3407                 signal_levels |= DP_VOLTAGE_0_6;
3408                 break;
3409         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3410                 signal_levels |= DP_VOLTAGE_0_8;
3411                 break;
3412         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3413                 signal_levels |= DP_VOLTAGE_1_2;
3414                 break;
3415         }
3416         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3417         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3418         default:
3419                 signal_levels |= DP_PRE_EMPHASIS_0;
3420                 break;
3421         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3422                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3423                 break;
3424         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3425                 signal_levels |= DP_PRE_EMPHASIS_6;
3426                 break;
3427         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3428                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3429                 break;
3430         }
3431         return signal_levels;
3432 }
3433
3434 /* Gen6's DP voltage swing and pre-emphasis control */
3435 static uint32_t
3436 intel_gen6_edp_signal_levels(uint8_t train_set)
3437 {
3438         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3439                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3440         switch (signal_levels) {
3441         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3442         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3443                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3444         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3445                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3446         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3447         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3448                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3449         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3450         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3451                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3452         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3453         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3454                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3455         default:
3456                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3457                               "0x%x\n", signal_levels);
3458                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3459         }
3460 }
3461
3462 /* Gen7's DP voltage swing and pre-emphasis control */
3463 static uint32_t
3464 intel_gen7_edp_signal_levels(uint8_t train_set)
3465 {
3466         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3467                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3468         switch (signal_levels) {
3469         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3470                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3471         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3472                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3473         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3474                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3475
3476         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3477                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3478         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3479                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3480
3481         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3482                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3483         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3484                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3485
3486         default:
3487                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3488                               "0x%x\n", signal_levels);
3489                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3490         }
3491 }
3492
3493 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3494 static uint32_t
3495 intel_hsw_signal_levels(uint8_t train_set)
3496 {
3497         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3498                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3499         switch (signal_levels) {
3500         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3501                 return DDI_BUF_TRANS_SELECT(0);
3502         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3503                 return DDI_BUF_TRANS_SELECT(1);
3504         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3505                 return DDI_BUF_TRANS_SELECT(2);
3506         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
3507                 return DDI_BUF_TRANS_SELECT(3);
3508
3509         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3510                 return DDI_BUF_TRANS_SELECT(4);
3511         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3512                 return DDI_BUF_TRANS_SELECT(5);
3513         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3514                 return DDI_BUF_TRANS_SELECT(6);
3515
3516         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3517                 return DDI_BUF_TRANS_SELECT(7);
3518         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3519                 return DDI_BUF_TRANS_SELECT(8);
3520         default:
3521                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3522                               "0x%x\n", signal_levels);
3523                 return DDI_BUF_TRANS_SELECT(0);
3524         }
3525 }
3526
3527 /* Properly updates "DP" with the correct signal levels. */
3528 static void
3529 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3530 {
3531         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3532         enum port port = intel_dig_port->port;
3533         struct drm_device *dev = intel_dig_port->base.base.dev;
3534         uint32_t signal_levels, mask;
3535         uint8_t train_set = intel_dp->train_set[0];
3536
3537         if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
3538                 signal_levels = intel_hsw_signal_levels(train_set);
3539                 mask = DDI_BUF_EMP_MASK;
3540         } else if (IS_CHERRYVIEW(dev)) {
3541                 signal_levels = intel_chv_signal_levels(intel_dp);
3542                 mask = 0;
3543         } else if (IS_VALLEYVIEW(dev)) {
3544                 signal_levels = intel_vlv_signal_levels(intel_dp);
3545                 mask = 0;
3546         } else if (IS_GEN7(dev) && port == PORT_A) {
3547                 signal_levels = intel_gen7_edp_signal_levels(train_set);
3548                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3549         } else if (IS_GEN6(dev) && port == PORT_A) {
3550                 signal_levels = intel_gen6_edp_signal_levels(train_set);
3551                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3552         } else {
3553                 signal_levels = intel_gen4_signal_levels(train_set);
3554                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3555         }
3556
3557         DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3558
3559         *DP = (*DP & ~mask) | signal_levels;
3560 }
3561
3562 static bool
3563 intel_dp_set_link_train(struct intel_dp *intel_dp,
3564                         uint32_t *DP,
3565                         uint8_t dp_train_pat)
3566 {
3567         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3568         struct drm_device *dev = intel_dig_port->base.base.dev;
3569         struct drm_i915_private *dev_priv = dev->dev_private;
3570         uint8_t buf[sizeof(intel_dp->train_set) + 1];
3571         int ret, len;
3572
3573         _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3574
3575         I915_WRITE(intel_dp->output_reg, *DP);
3576         POSTING_READ(intel_dp->output_reg);
3577
3578         buf[0] = dp_train_pat;
3579         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
3580             DP_TRAINING_PATTERN_DISABLE) {
3581                 /* don't write DP_TRAINING_LANEx_SET on disable */
3582                 len = 1;
3583         } else {
3584                 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3585                 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3586                 len = intel_dp->lane_count + 1;
3587         }
3588
3589         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3590                                 buf, len);
3591
3592         return ret == len;
3593 }
3594
3595 static bool
3596 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3597                         uint8_t dp_train_pat)
3598 {
3599         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
3600         intel_dp_set_signal_levels(intel_dp, DP);
3601         return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3602 }
3603
3604 static bool
3605 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3606                            const uint8_t link_status[DP_LINK_STATUS_SIZE])
3607 {
3608         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3609         struct drm_device *dev = intel_dig_port->base.base.dev;
3610         struct drm_i915_private *dev_priv = dev->dev_private;
3611         int ret;
3612
3613         intel_get_adjust_train(intel_dp, link_status);
3614         intel_dp_set_signal_levels(intel_dp, DP);
3615
3616         I915_WRITE(intel_dp->output_reg, *DP);
3617         POSTING_READ(intel_dp->output_reg);
3618
3619         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3620                                 intel_dp->train_set, intel_dp->lane_count);
3621
3622         return ret == intel_dp->lane_count;
3623 }
3624
3625 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3626 {
3627         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3628         struct drm_device *dev = intel_dig_port->base.base.dev;
3629         struct drm_i915_private *dev_priv = dev->dev_private;
3630         enum port port = intel_dig_port->port;
3631         uint32_t val;
3632
3633         if (!HAS_DDI(dev))
3634                 return;
3635
3636         val = I915_READ(DP_TP_CTL(port));
3637         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3638         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3639         I915_WRITE(DP_TP_CTL(port), val);
3640
3641         /*
3642          * On PORT_A we can have only eDP in SST mode. There the only reason
3643          * we need to set idle transmission mode is to work around a HW issue
3644          * where we enable the pipe while not in idle link-training mode.
3645          * In this case there is requirement to wait for a minimum number of
3646          * idle patterns to be sent.
3647          */
3648         if (port == PORT_A)
3649                 return;
3650
3651         if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3652                      1))
3653                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3654 }
3655
3656 /* Enable corresponding port and start training pattern 1 */
3657 void
3658 intel_dp_start_link_train(struct intel_dp *intel_dp)
3659 {
3660         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
3661         struct drm_device *dev = encoder->dev;
3662         int i;
3663         uint8_t voltage;
3664         int voltage_tries, loop_tries;
3665         uint32_t DP = intel_dp->DP;
3666         uint8_t link_config[2];
3667
3668         if (HAS_DDI(dev))
3669                 intel_ddi_prepare_link_retrain(encoder);
3670
3671         /* Write the link configuration data */
3672         link_config[0] = intel_dp->link_bw;
3673         link_config[1] = intel_dp->lane_count;
3674         if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3675                 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
3676         drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
3677
3678         link_config[0] = 0;
3679         link_config[1] = DP_SET_ANSI_8B10B;
3680         drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
3681
3682         DP |= DP_PORT_EN;
3683
3684         /* clock recovery */
3685         if (!intel_dp_reset_link_train(intel_dp, &DP,
3686                                        DP_TRAINING_PATTERN_1 |
3687                                        DP_LINK_SCRAMBLING_DISABLE)) {
3688                 DRM_ERROR("failed to enable link training\n");
3689                 return;
3690         }
3691
3692         voltage = 0xff;
3693         voltage_tries = 0;
3694         loop_tries = 0;
3695         for (;;) {
3696                 uint8_t link_status[DP_LINK_STATUS_SIZE];
3697
3698                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
3699                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3700                         DRM_ERROR("failed to get link status\n");
3701                         break;
3702                 }
3703
3704                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3705                         DRM_DEBUG_KMS("clock recovery OK\n");
3706                         break;
3707                 }
3708
3709                 /* Check to see if we've tried the max voltage */
3710                 for (i = 0; i < intel_dp->lane_count; i++)
3711                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
3712                                 break;
3713                 if (i == intel_dp->lane_count) {
3714                         ++loop_tries;
3715                         if (loop_tries == 5) {
3716                                 DRM_ERROR("too many full retries, give up\n");
3717                                 break;
3718                         }
3719                         intel_dp_reset_link_train(intel_dp, &DP,
3720                                                   DP_TRAINING_PATTERN_1 |
3721                                                   DP_LINK_SCRAMBLING_DISABLE);
3722                         voltage_tries = 0;
3723                         continue;
3724                 }
3725
3726                 /* Check to see if we've tried the same voltage 5 times */
3727                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
3728                         ++voltage_tries;
3729                         if (voltage_tries == 5) {
3730                                 DRM_ERROR("too many voltage retries, give up\n");
3731                                 break;
3732                         }
3733                 } else
3734                         voltage_tries = 0;
3735                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
3736
3737                 /* Update training set as requested by target */
3738                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3739                         DRM_ERROR("failed to update link training\n");
3740                         break;
3741                 }
3742         }
3743
3744         intel_dp->DP = DP;
3745 }
3746
3747 void
3748 intel_dp_complete_link_train(struct intel_dp *intel_dp)
3749 {
3750         bool channel_eq = false;
3751         int tries, cr_tries;
3752         uint32_t DP = intel_dp->DP;
3753         uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3754
3755         /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3756         if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3757                 training_pattern = DP_TRAINING_PATTERN_3;
3758
3759         /* channel equalization */
3760         if (!intel_dp_set_link_train(intel_dp, &DP,
3761                                      training_pattern |
3762                                      DP_LINK_SCRAMBLING_DISABLE)) {
3763                 DRM_ERROR("failed to start channel equalization\n");
3764                 return;
3765         }
3766
3767         tries = 0;
3768         cr_tries = 0;
3769         channel_eq = false;
3770         for (;;) {
3771                 uint8_t link_status[DP_LINK_STATUS_SIZE];
3772
3773                 if (cr_tries > 5) {
3774                         DRM_ERROR("failed to train DP, aborting\n");
3775                         break;
3776                 }
3777
3778                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
3779                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3780                         DRM_ERROR("failed to get link status\n");
3781                         break;
3782                 }
3783
3784                 /* Make sure clock is still ok */
3785                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3786                         intel_dp_start_link_train(intel_dp);
3787                         intel_dp_set_link_train(intel_dp, &DP,
3788                                                 training_pattern |
3789                                                 DP_LINK_SCRAMBLING_DISABLE);
3790                         cr_tries++;
3791                         continue;
3792                 }
3793
3794                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3795                         channel_eq = true;
3796                         break;
3797                 }
3798
3799                 /* Try 5 times, then try clock recovery if that fails */
3800                 if (tries > 5) {
3801                         intel_dp_link_down(intel_dp);
3802                         intel_dp_start_link_train(intel_dp);
3803                         intel_dp_set_link_train(intel_dp, &DP,
3804                                                 training_pattern |
3805                                                 DP_LINK_SCRAMBLING_DISABLE);
3806                         tries = 0;
3807                         cr_tries++;
3808                         continue;
3809                 }
3810
3811                 /* Update training set as requested by target */
3812                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3813                         DRM_ERROR("failed to update link training\n");
3814                         break;
3815                 }
3816                 ++tries;
3817         }
3818
3819         intel_dp_set_idle_link_train(intel_dp);
3820
3821         intel_dp->DP = DP;
3822
3823         if (channel_eq)
3824                 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3825
3826 }
3827
3828 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3829 {
3830         intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3831                                 DP_TRAINING_PATTERN_DISABLE);
3832 }
3833
3834 static void
3835 intel_dp_link_down(struct intel_dp *intel_dp)
3836 {
3837         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3838         enum port port = intel_dig_port->port;
3839         struct drm_device *dev = intel_dig_port->base.base.dev;
3840         struct drm_i915_private *dev_priv = dev->dev_private;
3841         struct intel_crtc *intel_crtc =
3842                 to_intel_crtc(intel_dig_port->base.base.crtc);
3843         uint32_t DP = intel_dp->DP;
3844
3845         if (WARN_ON(HAS_DDI(dev)))
3846                 return;
3847
3848         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3849                 return;
3850
3851         DRM_DEBUG_KMS("\n");
3852
3853         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
3854                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3855                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
3856         } else {
3857                 if (IS_CHERRYVIEW(dev))
3858                         DP &= ~DP_LINK_TRAIN_MASK_CHV;
3859                 else
3860                         DP &= ~DP_LINK_TRAIN_MASK;
3861                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
3862         }
3863         POSTING_READ(intel_dp->output_reg);
3864
3865         if (HAS_PCH_IBX(dev) &&
3866             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
3867                 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
3868
3869                 /* Hardware workaround: leaving our transcoder select
3870                  * set to transcoder B while it's off will prevent the
3871                  * corresponding HDMI output on transcoder A.
3872                  *
3873                  * Combine this with another hardware workaround:
3874                  * transcoder select bit can only be cleared while the
3875                  * port is enabled.
3876                  */
3877                 DP &= ~DP_PIPEB_SELECT;
3878                 I915_WRITE(intel_dp->output_reg, DP);
3879
3880                 /* Changes to enable or select take place the vblank
3881                  * after being written.
3882                  */
3883                 if (WARN_ON(crtc == NULL)) {
3884                         /* We should never try to disable a port without a crtc
3885                          * attached. For paranoia keep the code around for a
3886                          * bit. */
3887                         POSTING_READ(intel_dp->output_reg);
3888                         msleep(50);
3889                 } else
3890                         intel_wait_for_vblank(dev, intel_crtc->pipe);
3891         }
3892
3893         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
3894         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3895         POSTING_READ(intel_dp->output_reg);
3896         msleep(intel_dp->panel_power_down_delay);
3897 }
3898
3899 static bool
3900 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3901 {
3902         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3903         struct drm_device *dev = dig_port->base.base.dev;
3904         struct drm_i915_private *dev_priv = dev->dev_private;
3905
3906         if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3907                                     sizeof(intel_dp->dpcd)) < 0)
3908                 return false; /* aux transfer failed */
3909
3910         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3911
3912         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3913                 return false; /* DPCD not present */
3914
3915         /* Check if the panel supports PSR */
3916         memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3917         if (is_edp(intel_dp)) {
3918                 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3919                                         intel_dp->psr_dpcd,
3920                                         sizeof(intel_dp->psr_dpcd));
3921                 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3922                         dev_priv->psr.sink_support = true;
3923                         DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3924                 }
3925         }
3926
3927         /* Training Pattern 3 support */
3928         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3929             intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3930                 intel_dp->use_tps3 = true;
3931                 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
3932         } else
3933                 intel_dp->use_tps3 = false;
3934
3935         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3936               DP_DWN_STRM_PORT_PRESENT))
3937                 return true; /* native DP sink */
3938
3939         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3940                 return true; /* no per-port downstream info */
3941
3942         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3943                                     intel_dp->downstream_ports,
3944                                     DP_MAX_DOWNSTREAM_PORTS) < 0)
3945                 return false; /* downstream port status fetch failed */
3946
3947         return true;
3948 }
3949
3950 static void
3951 intel_dp_probe_oui(struct intel_dp *intel_dp)
3952 {
3953         u8 buf[3];
3954
3955         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3956                 return;
3957
3958         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3959                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3960                               buf[0], buf[1], buf[2]);
3961
3962         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3963                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3964                               buf[0], buf[1], buf[2]);
3965 }
3966
3967 static bool
3968 intel_dp_probe_mst(struct intel_dp *intel_dp)
3969 {
3970         u8 buf[1];
3971
3972         if (!intel_dp->can_mst)
3973                 return false;
3974
3975         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3976                 return false;
3977
3978         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3979                 if (buf[0] & DP_MST_CAP) {
3980                         DRM_DEBUG_KMS("Sink is MST capable\n");
3981                         intel_dp->is_mst = true;
3982                 } else {
3983                         DRM_DEBUG_KMS("Sink is not MST capable\n");
3984                         intel_dp->is_mst = false;
3985                 }
3986         }
3987
3988         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3989         return intel_dp->is_mst;
3990 }
3991
3992 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3993 {
3994         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3995         struct drm_device *dev = intel_dig_port->base.base.dev;
3996         struct intel_crtc *intel_crtc =
3997                 to_intel_crtc(intel_dig_port->base.base.crtc);
3998         u8 buf;
3999         int test_crc_count;
4000         int attempts = 6;
4001
4002         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
4003                 return -EIO;
4004
4005         if (!(buf & DP_TEST_CRC_SUPPORTED))
4006                 return -ENOTTY;
4007
4008         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
4009                 return -EIO;
4010
4011         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
4012                                 buf | DP_TEST_SINK_START) < 0)
4013                 return -EIO;
4014
4015         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
4016                 return -EIO;
4017         test_crc_count = buf & DP_TEST_COUNT_MASK;
4018
4019         do {
4020                 if (drm_dp_dpcd_readb(&intel_dp->aux,
4021                                       DP_TEST_SINK_MISC, &buf) < 0)
4022                         return -EIO;
4023                 intel_wait_for_vblank(dev, intel_crtc->pipe);
4024         } while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count);
4025
4026         if (attempts == 0) {
4027                 DRM_ERROR("Panel is unable to calculate CRC after 6 vblanks\n");
4028                 return -EIO;
4029         }
4030
4031         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
4032                 return -EIO;
4033
4034         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
4035                 return -EIO;
4036         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
4037                                buf & ~DP_TEST_SINK_START) < 0)
4038                 return -EIO;
4039
4040         return 0;
4041 }
4042
4043 static bool
4044 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4045 {
4046         return intel_dp_dpcd_read_wake(&intel_dp->aux,
4047                                        DP_DEVICE_SERVICE_IRQ_VECTOR,
4048                                        sink_irq_vector, 1) == 1;
4049 }
4050
4051 static bool
4052 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4053 {
4054         int ret;
4055
4056         ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
4057                                              DP_SINK_COUNT_ESI,
4058                                              sink_irq_vector, 14);
4059         if (ret != 14)
4060                 return false;
4061
4062         return true;
4063 }
4064
4065 static void
4066 intel_dp_handle_test_request(struct intel_dp *intel_dp)
4067 {
4068         /* NAK by default */
4069         drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
4070 }
4071
4072 static int
4073 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4074 {
4075         bool bret;
4076
4077         if (intel_dp->is_mst) {
4078                 u8 esi[16] = { 0 };
4079                 int ret = 0;
4080                 int retry;
4081                 bool handled;
4082                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4083 go_again:
4084                 if (bret == true) {
4085
4086                         /* check link status - esi[10] = 0x200c */
4087                         if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4088                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4089                                 intel_dp_start_link_train(intel_dp);
4090                                 intel_dp_complete_link_train(intel_dp);
4091                                 intel_dp_stop_link_train(intel_dp);
4092                         }
4093
4094                         DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4095                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4096
4097                         if (handled) {
4098                                 for (retry = 0; retry < 3; retry++) {
4099                                         int wret;
4100                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4101                                                                  DP_SINK_COUNT_ESI+1,
4102                                                                  &esi[1], 3);
4103                                         if (wret == 3) {
4104                                                 break;
4105                                         }
4106                                 }
4107
4108                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4109                                 if (bret == true) {
4110                                         DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4111                                         goto go_again;
4112                                 }
4113                         } else
4114                                 ret = 0;
4115
4116                         return ret;
4117                 } else {
4118                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4119                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4120                         intel_dp->is_mst = false;
4121                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4122                         /* send a hotplug event */
4123                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4124                 }
4125         }
4126         return -EINVAL;
4127 }
4128
4129 /*
4130  * According to DP spec
4131  * 5.1.2:
4132  *  1. Read DPCD
4133  *  2. Configure link according to Receiver Capabilities
4134  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4135  *  4. Check link status on receipt of hot-plug interrupt
4136  */
4137 void
4138 intel_dp_check_link_status(struct intel_dp *intel_dp)
4139 {
4140         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4141         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4142         u8 sink_irq_vector;
4143         u8 link_status[DP_LINK_STATUS_SIZE];
4144
4145         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4146
4147         if (!intel_encoder->connectors_active)
4148                 return;
4149
4150         if (WARN_ON(!intel_encoder->base.crtc))
4151                 return;
4152
4153         if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4154                 return;
4155
4156         /* Try to read receiver status if the link appears to be up */
4157         if (!intel_dp_get_link_status(intel_dp, link_status)) {
4158                 return;
4159         }
4160
4161         /* Now read the DPCD to see if it's actually running */
4162         if (!intel_dp_get_dpcd(intel_dp)) {
4163                 return;
4164         }
4165
4166         /* Try to read the source of the interrupt */
4167         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4168             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4169                 /* Clear interrupt source */
4170                 drm_dp_dpcd_writeb(&intel_dp->aux,
4171                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4172                                    sink_irq_vector);
4173
4174                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4175                         intel_dp_handle_test_request(intel_dp);
4176                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4177                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4178         }
4179
4180         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
4181                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4182                               intel_encoder->base.name);
4183                 intel_dp_start_link_train(intel_dp);
4184                 intel_dp_complete_link_train(intel_dp);
4185                 intel_dp_stop_link_train(intel_dp);
4186         }
4187 }
4188
4189 /* XXX this is probably wrong for multiple downstream ports */
4190 static enum drm_connector_status
4191 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4192 {
4193         uint8_t *dpcd = intel_dp->dpcd;
4194         uint8_t type;
4195
4196         if (!intel_dp_get_dpcd(intel_dp))
4197                 return connector_status_disconnected;
4198
4199         /* if there's no downstream port, we're done */
4200         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
4201                 return connector_status_connected;
4202
4203         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4204         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4205             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4206                 uint8_t reg;
4207
4208                 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4209                                             &reg, 1) < 0)
4210                         return connector_status_unknown;
4211
4212                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4213                                               : connector_status_disconnected;
4214         }
4215
4216         /* If no HPD, poke DDC gently */
4217         if (drm_probe_ddc(&intel_dp->aux.ddc))
4218                 return connector_status_connected;
4219
4220         /* Well we tried, say unknown for unreliable port types */
4221         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4222                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4223                 if (type == DP_DS_PORT_TYPE_VGA ||
4224                     type == DP_DS_PORT_TYPE_NON_EDID)
4225                         return connector_status_unknown;
4226         } else {
4227                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4228                         DP_DWN_STRM_PORT_TYPE_MASK;
4229                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4230                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4231                         return connector_status_unknown;
4232         }
4233
4234         /* Anything else is out of spec, warn and ignore */
4235         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4236         return connector_status_disconnected;
4237 }
4238
4239 static enum drm_connector_status
4240 edp_detect(struct intel_dp *intel_dp)
4241 {
4242         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4243         enum drm_connector_status status;
4244
4245         status = intel_panel_detect(dev);
4246         if (status == connector_status_unknown)
4247                 status = connector_status_connected;
4248
4249         return status;
4250 }
4251
4252 static enum drm_connector_status
4253 ironlake_dp_detect(struct intel_dp *intel_dp)
4254 {
4255         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4256         struct drm_i915_private *dev_priv = dev->dev_private;
4257         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4258
4259         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4260                 return connector_status_disconnected;
4261
4262         return intel_dp_detect_dpcd(intel_dp);
4263 }
4264
4265 static int g4x_digital_port_connected(struct drm_device *dev,
4266                                        struct intel_digital_port *intel_dig_port)
4267 {
4268         struct drm_i915_private *dev_priv = dev->dev_private;
4269         uint32_t bit;
4270
4271         if (IS_VALLEYVIEW(dev)) {
4272                 switch (intel_dig_port->port) {
4273                 case PORT_B:
4274                         bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4275                         break;
4276                 case PORT_C:
4277                         bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4278                         break;
4279                 case PORT_D:
4280                         bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4281                         break;
4282                 default:
4283                         return -EINVAL;
4284                 }
4285         } else {
4286                 switch (intel_dig_port->port) {
4287                 case PORT_B:
4288                         bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4289                         break;
4290                 case PORT_C:
4291                         bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4292                         break;
4293                 case PORT_D:
4294                         bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4295                         break;
4296                 default:
4297                         return -EINVAL;
4298                 }
4299         }
4300
4301         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
4302                 return 0;
4303         return 1;
4304 }
4305
4306 static enum drm_connector_status
4307 g4x_dp_detect(struct intel_dp *intel_dp)
4308 {
4309         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4310         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4311         int ret;
4312
4313         /* Can't disconnect eDP, but you can close the lid... */
4314         if (is_edp(intel_dp)) {
4315                 enum drm_connector_status status;
4316
4317                 status = intel_panel_detect(dev);
4318                 if (status == connector_status_unknown)
4319                         status = connector_status_connected;
4320                 return status;
4321         }
4322
4323         ret = g4x_digital_port_connected(dev, intel_dig_port);
4324         if (ret == -EINVAL)
4325                 return connector_status_unknown;
4326         else if (ret == 0)
4327                 return connector_status_disconnected;
4328
4329         return intel_dp_detect_dpcd(intel_dp);
4330 }
4331
4332 static struct edid *
4333 intel_dp_get_edid(struct intel_dp *intel_dp)
4334 {
4335         struct intel_connector *intel_connector = intel_dp->attached_connector;
4336
4337         /* use cached edid if we have one */
4338         if (intel_connector->edid) {
4339                 /* invalid edid */
4340                 if (IS_ERR(intel_connector->edid))
4341                         return NULL;
4342
4343                 return drm_edid_duplicate(intel_connector->edid);
4344         } else
4345                 return drm_get_edid(&intel_connector->base,
4346                                     &intel_dp->aux.ddc);
4347 }
4348
4349 static void
4350 intel_dp_set_edid(struct intel_dp *intel_dp)
4351 {
4352         struct intel_connector *intel_connector = intel_dp->attached_connector;
4353         struct edid *edid;
4354
4355         edid = intel_dp_get_edid(intel_dp);
4356         intel_connector->detect_edid = edid;
4357
4358         if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4359                 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4360         else
4361                 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4362 }
4363
4364 static void
4365 intel_dp_unset_edid(struct intel_dp *intel_dp)
4366 {
4367         struct intel_connector *intel_connector = intel_dp->attached_connector;
4368
4369         kfree(intel_connector->detect_edid);
4370         intel_connector->detect_edid = NULL;
4371
4372         intel_dp->has_audio = false;
4373 }
4374
4375 static enum intel_display_power_domain
4376 intel_dp_power_get(struct intel_dp *dp)
4377 {
4378         struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4379         enum intel_display_power_domain power_domain;
4380
4381         power_domain = intel_display_port_power_domain(encoder);
4382         intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4383
4384         return power_domain;
4385 }
4386
4387 static void
4388 intel_dp_power_put(struct intel_dp *dp,
4389                    enum intel_display_power_domain power_domain)
4390 {
4391         struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4392         intel_display_power_put(to_i915(encoder->base.dev), power_domain);
4393 }
4394
4395 static enum drm_connector_status
4396 intel_dp_detect(struct drm_connector *connector, bool force)
4397 {
4398         struct intel_dp *intel_dp = intel_attached_dp(connector);
4399         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4400         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4401         struct drm_device *dev = connector->dev;
4402         enum drm_connector_status status;
4403         enum intel_display_power_domain power_domain;
4404         bool ret;
4405
4406         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4407                       connector->base.id, connector->name);
4408         intel_dp_unset_edid(intel_dp);
4409
4410         if (intel_dp->is_mst) {
4411                 /* MST devices are disconnected from a monitor POV */
4412                 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4413                         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4414                 return connector_status_disconnected;
4415         }
4416
4417         power_domain = intel_dp_power_get(intel_dp);
4418
4419         /* Can't disconnect eDP, but you can close the lid... */
4420         if (is_edp(intel_dp))
4421                 status = edp_detect(intel_dp);
4422         else if (HAS_PCH_SPLIT(dev))
4423                 status = ironlake_dp_detect(intel_dp);
4424         else
4425                 status = g4x_dp_detect(intel_dp);
4426         if (status != connector_status_connected)
4427                 goto out;
4428
4429         intel_dp_probe_oui(intel_dp);
4430
4431         ret = intel_dp_probe_mst(intel_dp);
4432         if (ret) {
4433                 /* if we are in MST mode then this connector
4434                    won't appear connected or have anything with EDID on it */
4435                 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4436                         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4437                 status = connector_status_disconnected;
4438                 goto out;
4439         }
4440
4441         intel_dp_set_edid(intel_dp);
4442
4443         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4444                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4445         status = connector_status_connected;
4446
4447 out:
4448         intel_dp_power_put(intel_dp, power_domain);
4449         return status;
4450 }
4451
4452 static void
4453 intel_dp_force(struct drm_connector *connector)
4454 {
4455         struct intel_dp *intel_dp = intel_attached_dp(connector);
4456         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4457         enum intel_display_power_domain power_domain;
4458
4459         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4460                       connector->base.id, connector->name);
4461         intel_dp_unset_edid(intel_dp);
4462
4463         if (connector->status != connector_status_connected)
4464                 return;
4465
4466         power_domain = intel_dp_power_get(intel_dp);
4467
4468         intel_dp_set_edid(intel_dp);
4469
4470         intel_dp_power_put(intel_dp, power_domain);
4471
4472         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4473                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4474 }
4475
4476 static int intel_dp_get_modes(struct drm_connector *connector)
4477 {
4478         struct intel_connector *intel_connector = to_intel_connector(connector);
4479         struct edid *edid;
4480
4481         edid = intel_connector->detect_edid;
4482         if (edid) {
4483                 int ret = intel_connector_update_modes(connector, edid);
4484                 if (ret)
4485                         return ret;
4486         }
4487
4488         /* if eDP has no EDID, fall back to fixed mode */
4489         if (is_edp(intel_attached_dp(connector)) &&
4490             intel_connector->panel.fixed_mode) {
4491                 struct drm_display_mode *mode;
4492
4493                 mode = drm_mode_duplicate(connector->dev,
4494                                           intel_connector->panel.fixed_mode);
4495                 if (mode) {
4496                         drm_mode_probed_add(connector, mode);
4497                         return 1;
4498                 }
4499         }
4500
4501         return 0;
4502 }
4503
4504 static bool
4505 intel_dp_detect_audio(struct drm_connector *connector)
4506 {
4507         bool has_audio = false;
4508         struct edid *edid;
4509
4510         edid = to_intel_connector(connector)->detect_edid;
4511         if (edid)
4512                 has_audio = drm_detect_monitor_audio(edid);
4513
4514         return has_audio;
4515 }
4516
4517 static int
4518 intel_dp_set_property(struct drm_connector *connector,
4519                       struct drm_property *property,
4520                       uint64_t val)
4521 {
4522         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4523         struct intel_connector *intel_connector = to_intel_connector(connector);
4524         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4525         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4526         int ret;
4527
4528         ret = drm_object_property_set_value(&connector->base, property, val);
4529         if (ret)
4530                 return ret;
4531
4532         if (property == dev_priv->force_audio_property) {
4533                 int i = val;
4534                 bool has_audio;
4535
4536                 if (i == intel_dp->force_audio)
4537                         return 0;
4538
4539                 intel_dp->force_audio = i;
4540
4541                 if (i == HDMI_AUDIO_AUTO)
4542                         has_audio = intel_dp_detect_audio(connector);
4543                 else
4544                         has_audio = (i == HDMI_AUDIO_ON);
4545
4546                 if (has_audio == intel_dp->has_audio)
4547                         return 0;
4548
4549                 intel_dp->has_audio = has_audio;
4550                 goto done;
4551         }
4552
4553         if (property == dev_priv->broadcast_rgb_property) {
4554                 bool old_auto = intel_dp->color_range_auto;
4555                 uint32_t old_range = intel_dp->color_range;
4556
4557                 switch (val) {
4558                 case INTEL_BROADCAST_RGB_AUTO:
4559                         intel_dp->color_range_auto = true;
4560                         break;
4561                 case INTEL_BROADCAST_RGB_FULL:
4562                         intel_dp->color_range_auto = false;
4563                         intel_dp->color_range = 0;
4564                         break;
4565                 case INTEL_BROADCAST_RGB_LIMITED:
4566                         intel_dp->color_range_auto = false;
4567                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
4568                         break;
4569                 default:
4570                         return -EINVAL;
4571                 }
4572
4573                 if (old_auto == intel_dp->color_range_auto &&
4574                     old_range == intel_dp->color_range)
4575                         return 0;
4576
4577                 goto done;
4578         }
4579
4580         if (is_edp(intel_dp) &&
4581             property == connector->dev->mode_config.scaling_mode_property) {
4582                 if (val == DRM_MODE_SCALE_NONE) {
4583                         DRM_DEBUG_KMS("no scaling not supported\n");
4584                         return -EINVAL;
4585                 }
4586
4587                 if (intel_connector->panel.fitting_mode == val) {
4588                         /* the eDP scaling property is not changed */
4589                         return 0;
4590                 }
4591                 intel_connector->panel.fitting_mode = val;
4592
4593                 goto done;
4594         }
4595
4596         return -EINVAL;
4597
4598 done:
4599         if (intel_encoder->base.crtc)
4600                 intel_crtc_restore_mode(intel_encoder->base.crtc);
4601
4602         return 0;
4603 }
4604
4605 static void
4606 intel_dp_connector_destroy(struct drm_connector *connector)
4607 {
4608         struct intel_connector *intel_connector = to_intel_connector(connector);
4609
4610         kfree(intel_connector->detect_edid);
4611
4612         if (!IS_ERR_OR_NULL(intel_connector->edid))
4613                 kfree(intel_connector->edid);
4614
4615         /* Can't call is_edp() since the encoder may have been destroyed
4616          * already. */
4617         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4618                 intel_panel_fini(&intel_connector->panel);
4619
4620         drm_connector_cleanup(connector);
4621         kfree(connector);
4622 }
4623
4624 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4625 {
4626         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4627         struct intel_dp *intel_dp = &intel_dig_port->dp;
4628
4629         drm_dp_aux_unregister(&intel_dp->aux);
4630         intel_dp_mst_encoder_cleanup(intel_dig_port);
4631         drm_encoder_cleanup(encoder);
4632         if (is_edp(intel_dp)) {
4633                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4634                 /*
4635                  * vdd might still be enabled do to the delayed vdd off.
4636                  * Make sure vdd is actually turned off here.
4637                  */
4638                 pps_lock(intel_dp);
4639                 edp_panel_vdd_off_sync(intel_dp);
4640                 pps_unlock(intel_dp);
4641
4642                 if (intel_dp->edp_notifier.notifier_call) {
4643                         unregister_reboot_notifier(&intel_dp->edp_notifier);
4644                         intel_dp->edp_notifier.notifier_call = NULL;
4645                 }
4646         }
4647         kfree(intel_dig_port);
4648 }
4649
4650 static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4651 {
4652         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4653
4654         if (!is_edp(intel_dp))
4655                 return;
4656
4657         /*
4658          * vdd might still be enabled do to the delayed vdd off.
4659          * Make sure vdd is actually turned off here.
4660          */
4661         pps_lock(intel_dp);
4662         edp_panel_vdd_off_sync(intel_dp);
4663         pps_unlock(intel_dp);
4664 }
4665
4666 static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4667 {
4668         intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4669 }
4670
4671 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4672         .dpms = intel_connector_dpms,
4673         .detect = intel_dp_detect,
4674         .force = intel_dp_force,
4675         .fill_modes = drm_helper_probe_single_connector_modes,
4676         .set_property = intel_dp_set_property,
4677         .destroy = intel_dp_connector_destroy,
4678 };
4679
4680 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4681         .get_modes = intel_dp_get_modes,
4682         .mode_valid = intel_dp_mode_valid,
4683         .best_encoder = intel_best_encoder,
4684 };
4685
4686 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4687         .reset = intel_dp_encoder_reset,
4688         .destroy = intel_dp_encoder_destroy,
4689 };
4690
4691 void
4692 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
4693 {
4694         return;
4695 }
4696
4697 bool
4698 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4699 {
4700         struct intel_dp *intel_dp = &intel_dig_port->dp;
4701         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4702         struct drm_device *dev = intel_dig_port->base.base.dev;
4703         struct drm_i915_private *dev_priv = dev->dev_private;
4704         enum intel_display_power_domain power_domain;
4705         bool ret = true;
4706
4707         if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4708                 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
4709
4710         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4711                       port_name(intel_dig_port->port),
4712                       long_hpd ? "long" : "short");
4713
4714         power_domain = intel_display_port_power_domain(intel_encoder);
4715         intel_display_power_get(dev_priv, power_domain);
4716
4717         if (long_hpd) {
4718
4719                 if (HAS_PCH_SPLIT(dev)) {
4720                         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4721                                 goto mst_fail;
4722                 } else {
4723                         if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4724                                 goto mst_fail;
4725                 }
4726
4727                 if (!intel_dp_get_dpcd(intel_dp)) {
4728                         goto mst_fail;
4729                 }
4730
4731                 intel_dp_probe_oui(intel_dp);
4732
4733                 if (!intel_dp_probe_mst(intel_dp))
4734                         goto mst_fail;
4735
4736         } else {
4737                 if (intel_dp->is_mst) {
4738                         if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
4739                                 goto mst_fail;
4740                 }
4741
4742                 if (!intel_dp->is_mst) {
4743                         /*
4744                          * we'll check the link status via the normal hot plug path later -
4745                          * but for short hpds we should check it now
4746                          */
4747                         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4748                         intel_dp_check_link_status(intel_dp);
4749                         drm_modeset_unlock(&dev->mode_config.connection_mutex);
4750                 }
4751         }
4752         ret = false;
4753         goto put_power;
4754 mst_fail:
4755         /* if we were in MST mode, and device is not there get out of MST mode */
4756         if (intel_dp->is_mst) {
4757                 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4758                 intel_dp->is_mst = false;
4759                 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4760         }
4761 put_power:
4762         intel_display_power_put(dev_priv, power_domain);
4763
4764         return ret;
4765 }
4766
4767 /* Return which DP Port should be selected for Transcoder DP control */
4768 int
4769 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4770 {
4771         struct drm_device *dev = crtc->dev;
4772         struct intel_encoder *intel_encoder;
4773         struct intel_dp *intel_dp;
4774
4775         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4776                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4777
4778                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4779                     intel_encoder->type == INTEL_OUTPUT_EDP)
4780                         return intel_dp->output_reg;
4781         }
4782
4783         return -1;
4784 }
4785
4786 /* check the VBT to see whether the eDP is on DP-D port */
4787 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
4788 {
4789         struct drm_i915_private *dev_priv = dev->dev_private;
4790         union child_device_config *p_child;
4791         int i;
4792         static const short port_mapping[] = {
4793                 [PORT_B] = PORT_IDPB,
4794                 [PORT_C] = PORT_IDPC,
4795                 [PORT_D] = PORT_IDPD,
4796         };
4797
4798         if (port == PORT_A)
4799                 return true;
4800
4801         if (!dev_priv->vbt.child_dev_num)
4802                 return false;
4803
4804         for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4805                 p_child = dev_priv->vbt.child_dev + i;
4806
4807                 if (p_child->common.dvo_port == port_mapping[port] &&
4808                     (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4809                     (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
4810                         return true;
4811         }
4812         return false;
4813 }
4814
4815 void
4816 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4817 {
4818         struct intel_connector *intel_connector = to_intel_connector(connector);
4819
4820         intel_attach_force_audio_property(connector);
4821         intel_attach_broadcast_rgb_property(connector);
4822         intel_dp->color_range_auto = true;
4823
4824         if (is_edp(intel_dp)) {
4825                 drm_mode_create_scaling_mode_property(connector->dev);
4826                 drm_object_attach_property(
4827                         &connector->base,
4828                         connector->dev->mode_config.scaling_mode_property,
4829                         DRM_MODE_SCALE_ASPECT);
4830                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
4831         }
4832 }
4833
4834 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4835 {
4836         intel_dp->last_power_cycle = jiffies;
4837         intel_dp->last_power_on = jiffies;
4838         intel_dp->last_backlight_off = jiffies;
4839 }
4840
4841 static void
4842 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4843                                     struct intel_dp *intel_dp)
4844 {
4845         struct drm_i915_private *dev_priv = dev->dev_private;
4846         struct edp_power_seq cur, vbt, spec,
4847                 *final = &intel_dp->pps_delays;
4848         u32 pp_on, pp_off, pp_div, pp;
4849         int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
4850
4851         lockdep_assert_held(&dev_priv->pps_mutex);
4852
4853         /* already initialized? */
4854         if (final->t11_t12 != 0)
4855                 return;
4856
4857         if (HAS_PCH_SPLIT(dev)) {
4858                 pp_ctrl_reg = PCH_PP_CONTROL;
4859                 pp_on_reg = PCH_PP_ON_DELAYS;
4860                 pp_off_reg = PCH_PP_OFF_DELAYS;
4861                 pp_div_reg = PCH_PP_DIVISOR;
4862         } else {
4863                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4864
4865                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4866                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4867                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4868                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4869         }
4870
4871         /* Workaround: Need to write PP_CONTROL with the unlock key as
4872          * the very first thing. */
4873         pp = ironlake_get_pp_control(intel_dp);
4874         I915_WRITE(pp_ctrl_reg, pp);
4875
4876         pp_on = I915_READ(pp_on_reg);
4877         pp_off = I915_READ(pp_off_reg);
4878         pp_div = I915_READ(pp_div_reg);
4879
4880         /* Pull timing values out of registers */
4881         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4882                 PANEL_POWER_UP_DELAY_SHIFT;
4883
4884         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4885                 PANEL_LIGHT_ON_DELAY_SHIFT;
4886
4887         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4888                 PANEL_LIGHT_OFF_DELAY_SHIFT;
4889
4890         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4891                 PANEL_POWER_DOWN_DELAY_SHIFT;
4892
4893         cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4894                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4895
4896         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4897                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4898
4899         vbt = dev_priv->vbt.edp_pps;
4900
4901         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4902          * our hw here, which are all in 100usec. */
4903         spec.t1_t3 = 210 * 10;
4904         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4905         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4906         spec.t10 = 500 * 10;
4907         /* This one is special and actually in units of 100ms, but zero
4908          * based in the hw (so we need to add 100 ms). But the sw vbt
4909          * table multiplies it with 1000 to make it in units of 100usec,
4910          * too. */
4911         spec.t11_t12 = (510 + 100) * 10;
4912
4913         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4914                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4915
4916         /* Use the max of the register settings and vbt. If both are
4917          * unset, fall back to the spec limits. */
4918 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
4919                                        spec.field : \
4920                                        max(cur.field, vbt.field))
4921         assign_final(t1_t3);
4922         assign_final(t8);
4923         assign_final(t9);
4924         assign_final(t10);
4925         assign_final(t11_t12);
4926 #undef assign_final
4927
4928 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
4929         intel_dp->panel_power_up_delay = get_delay(t1_t3);
4930         intel_dp->backlight_on_delay = get_delay(t8);
4931         intel_dp->backlight_off_delay = get_delay(t9);
4932         intel_dp->panel_power_down_delay = get_delay(t10);
4933         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4934 #undef get_delay
4935
4936         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4937                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4938                       intel_dp->panel_power_cycle_delay);
4939
4940         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4941                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4942 }
4943
4944 static void
4945 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4946                                               struct intel_dp *intel_dp)
4947 {
4948         struct drm_i915_private *dev_priv = dev->dev_private;
4949         u32 pp_on, pp_off, pp_div, port_sel = 0;
4950         int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4951         int pp_on_reg, pp_off_reg, pp_div_reg;
4952         enum port port = dp_to_dig_port(intel_dp)->port;
4953         const struct edp_power_seq *seq = &intel_dp->pps_delays;
4954
4955         lockdep_assert_held(&dev_priv->pps_mutex);
4956
4957         if (HAS_PCH_SPLIT(dev)) {
4958                 pp_on_reg = PCH_PP_ON_DELAYS;
4959                 pp_off_reg = PCH_PP_OFF_DELAYS;
4960                 pp_div_reg = PCH_PP_DIVISOR;
4961         } else {
4962                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4963
4964                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4965                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4966                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4967         }
4968
4969         /*
4970          * And finally store the new values in the power sequencer. The
4971          * backlight delays are set to 1 because we do manual waits on them. For
4972          * T8, even BSpec recommends doing it. For T9, if we don't do this,
4973          * we'll end up waiting for the backlight off delay twice: once when we
4974          * do the manual sleep, and once when we disable the panel and wait for
4975          * the PP_STATUS bit to become zero.
4976          */
4977         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
4978                 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4979         pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
4980                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
4981         /* Compute the divisor for the pp clock, simply match the Bspec
4982          * formula. */
4983         pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
4984         pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
4985                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
4986
4987         /* Haswell doesn't have any port selection bits for the panel
4988          * power sequencer any more. */
4989         if (IS_VALLEYVIEW(dev)) {
4990                 port_sel = PANEL_PORT_SELECT_VLV(port);
4991         } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
4992                 if (port == PORT_A)
4993                         port_sel = PANEL_PORT_SELECT_DPA;
4994                 else
4995                         port_sel = PANEL_PORT_SELECT_DPD;
4996         }
4997
4998         pp_on |= port_sel;
4999
5000         I915_WRITE(pp_on_reg, pp_on);
5001         I915_WRITE(pp_off_reg, pp_off);
5002         I915_WRITE(pp_div_reg, pp_div);
5003
5004         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5005                       I915_READ(pp_on_reg),
5006                       I915_READ(pp_off_reg),
5007                       I915_READ(pp_div_reg));
5008 }
5009
5010 void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
5011 {
5012         struct drm_i915_private *dev_priv = dev->dev_private;
5013         struct intel_encoder *encoder;
5014         struct intel_dp *intel_dp = NULL;
5015         struct intel_crtc_config *config = NULL;
5016         struct intel_crtc *intel_crtc = NULL;
5017         struct intel_connector *intel_connector = dev_priv->drrs.connector;
5018         u32 reg, val;
5019         enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
5020
5021         if (refresh_rate <= 0) {
5022                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5023                 return;
5024         }
5025
5026         if (intel_connector == NULL) {
5027                 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
5028                 return;
5029         }
5030
5031         /*
5032          * FIXME: This needs proper synchronization with psr state. But really
5033          * hard to tell without seeing the user of this function of this code.
5034          * Check locking and ordering once that lands.
5035          */
5036         if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
5037                 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
5038                 return;
5039         }
5040
5041         encoder = intel_attached_encoder(&intel_connector->base);
5042         intel_dp = enc_to_intel_dp(&encoder->base);
5043         intel_crtc = encoder->new_crtc;
5044
5045         if (!intel_crtc) {
5046                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5047                 return;
5048         }
5049
5050         config = &intel_crtc->config;
5051
5052         if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
5053                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5054                 return;
5055         }
5056
5057         if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
5058                 index = DRRS_LOW_RR;
5059
5060         if (index == intel_dp->drrs_state.refresh_rate_type) {
5061                 DRM_DEBUG_KMS(
5062                         "DRRS requested for previously set RR...ignoring\n");
5063                 return;
5064         }
5065
5066         if (!intel_crtc->active) {
5067                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5068                 return;
5069         }
5070
5071         if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
5072                 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
5073                 val = I915_READ(reg);
5074                 if (index > DRRS_HIGH_RR) {
5075                         val |= PIPECONF_EDP_RR_MODE_SWITCH;
5076                         intel_dp_set_m_n(intel_crtc);
5077                 } else {
5078                         val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5079                 }
5080                 I915_WRITE(reg, val);
5081         }
5082
5083         /*
5084          * mutex taken to ensure that there is no race between differnt
5085          * drrs calls trying to update refresh rate. This scenario may occur
5086          * in future when idleness detection based DRRS in kernel and
5087          * possible calls from user space to set differnt RR are made.
5088          */
5089
5090         mutex_lock(&intel_dp->drrs_state.mutex);
5091
5092         intel_dp->drrs_state.refresh_rate_type = index;
5093
5094         mutex_unlock(&intel_dp->drrs_state.mutex);
5095
5096         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5097 }
5098
5099 static struct drm_display_mode *
5100 intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
5101                         struct intel_connector *intel_connector,
5102                         struct drm_display_mode *fixed_mode)
5103 {
5104         struct drm_connector *connector = &intel_connector->base;
5105         struct intel_dp *intel_dp = &intel_dig_port->dp;
5106         struct drm_device *dev = intel_dig_port->base.base.dev;
5107         struct drm_i915_private *dev_priv = dev->dev_private;
5108         struct drm_display_mode *downclock_mode = NULL;
5109
5110         if (INTEL_INFO(dev)->gen <= 6) {
5111                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5112                 return NULL;
5113         }
5114
5115         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5116                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5117                 return NULL;
5118         }
5119
5120         downclock_mode = intel_find_panel_downclock
5121                                         (dev, fixed_mode, connector);
5122
5123         if (!downclock_mode) {
5124                 DRM_DEBUG_KMS("DRRS not supported\n");
5125                 return NULL;
5126         }
5127
5128         dev_priv->drrs.connector = intel_connector;
5129
5130         mutex_init(&intel_dp->drrs_state.mutex);
5131
5132         intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
5133
5134         intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
5135         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5136         return downclock_mode;
5137 }
5138
5139 void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
5140 {
5141         struct drm_device *dev = intel_encoder->base.dev;
5142         struct drm_i915_private *dev_priv = dev->dev_private;
5143         struct intel_dp *intel_dp;
5144         enum intel_display_power_domain power_domain;
5145
5146         if (intel_encoder->type != INTEL_OUTPUT_EDP)
5147                 return;
5148
5149         intel_dp = enc_to_intel_dp(&intel_encoder->base);
5150
5151         pps_lock(intel_dp);
5152
5153         if (!edp_have_panel_vdd(intel_dp))
5154                 goto out;
5155         /*
5156          * The VDD bit needs a power domain reference, so if the bit is
5157          * already enabled when we boot or resume, grab this reference and
5158          * schedule a vdd off, so we don't hold on to the reference
5159          * indefinitely.
5160          */
5161         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5162         power_domain = intel_display_port_power_domain(intel_encoder);
5163         intel_display_power_get(dev_priv, power_domain);
5164
5165         edp_panel_vdd_schedule_off(intel_dp);
5166  out:
5167         pps_unlock(intel_dp);
5168 }
5169
5170 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5171                                      struct intel_connector *intel_connector)
5172 {
5173         struct drm_connector *connector = &intel_connector->base;
5174         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5175         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5176         struct drm_device *dev = intel_encoder->base.dev;
5177         struct drm_i915_private *dev_priv = dev->dev_private;
5178         struct drm_display_mode *fixed_mode = NULL;
5179         struct drm_display_mode *downclock_mode = NULL;
5180         bool has_dpcd;
5181         struct drm_display_mode *scan;
5182         struct edid *edid;
5183
5184         intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
5185
5186         if (!is_edp(intel_dp))
5187                 return true;
5188
5189         intel_edp_panel_vdd_sanitize(intel_encoder);
5190
5191         /* Cache DPCD and EDID for edp. */
5192         has_dpcd = intel_dp_get_dpcd(intel_dp);
5193
5194         if (has_dpcd) {
5195                 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5196                         dev_priv->no_aux_handshake =
5197                                 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5198                                 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5199         } else {
5200                 /* if this fails, presume the device is a ghost */
5201                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5202                 return false;
5203         }
5204
5205         /* We now know it's not a ghost, init power sequence regs. */
5206         pps_lock(intel_dp);
5207         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
5208         pps_unlock(intel_dp);
5209
5210         mutex_lock(&dev->mode_config.mutex);
5211         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5212         if (edid) {
5213                 if (drm_add_edid_modes(connector, edid)) {
5214                         drm_mode_connector_update_edid_property(connector,
5215                                                                 edid);
5216                         drm_edid_to_eld(connector, edid);
5217                 } else {
5218                         kfree(edid);
5219                         edid = ERR_PTR(-EINVAL);
5220                 }
5221         } else {
5222                 edid = ERR_PTR(-ENOENT);
5223         }
5224         intel_connector->edid = edid;
5225
5226         /* prefer fixed mode from EDID if available */
5227         list_for_each_entry(scan, &connector->probed_modes, head) {
5228                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5229                         fixed_mode = drm_mode_duplicate(dev, scan);
5230                         downclock_mode = intel_dp_drrs_init(
5231                                                 intel_dig_port,
5232                                                 intel_connector, fixed_mode);
5233                         break;
5234                 }
5235         }
5236
5237         /* fallback to VBT if available for eDP */
5238         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5239                 fixed_mode = drm_mode_duplicate(dev,
5240                                         dev_priv->vbt.lfp_lvds_vbt_mode);
5241                 if (fixed_mode)
5242                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5243         }
5244         mutex_unlock(&dev->mode_config.mutex);
5245
5246         if (IS_VALLEYVIEW(dev)) {
5247                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5248                 register_reboot_notifier(&intel_dp->edp_notifier);
5249         }
5250
5251         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5252         intel_connector->panel.backlight_power = intel_edp_backlight_power;
5253         intel_panel_setup_backlight(connector);
5254
5255         return true;
5256 }
5257
5258 bool
5259 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5260                         struct intel_connector *intel_connector)
5261 {
5262         struct drm_connector *connector = &intel_connector->base;
5263         struct intel_dp *intel_dp = &intel_dig_port->dp;
5264         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5265         struct drm_device *dev = intel_encoder->base.dev;
5266         struct drm_i915_private *dev_priv = dev->dev_private;
5267         enum port port = intel_dig_port->port;
5268         int type;
5269
5270         intel_dp->pps_pipe = INVALID_PIPE;
5271
5272         /* intel_dp vfuncs */
5273         if (INTEL_INFO(dev)->gen >= 9)
5274                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5275         else if (IS_VALLEYVIEW(dev))
5276                 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5277         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5278                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5279         else if (HAS_PCH_SPLIT(dev))
5280                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5281         else
5282                 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5283
5284         if (INTEL_INFO(dev)->gen >= 9)
5285                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5286         else
5287                 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
5288
5289         /* Preserve the current hw state. */
5290         intel_dp->DP = I915_READ(intel_dp->output_reg);
5291         intel_dp->attached_connector = intel_connector;
5292
5293         if (intel_dp_is_edp(dev, port))
5294                 type = DRM_MODE_CONNECTOR_eDP;
5295         else
5296                 type = DRM_MODE_CONNECTOR_DisplayPort;
5297
5298         /*
5299          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5300          * for DP the encoder type can be set by the caller to
5301          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5302          */
5303         if (type == DRM_MODE_CONNECTOR_eDP)
5304                 intel_encoder->type = INTEL_OUTPUT_EDP;
5305
5306         /* eDP only on port B and/or C on vlv/chv */
5307         if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
5308                     port != PORT_B && port != PORT_C))
5309                 return false;
5310
5311         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5312                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5313                         port_name(port));
5314
5315         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5316         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5317
5318         connector->interlace_allowed = true;
5319         connector->doublescan_allowed = 0;
5320
5321         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
5322                           edp_panel_vdd_work);
5323
5324         intel_connector_attach_encoder(intel_connector, intel_encoder);
5325         drm_connector_register(connector);
5326
5327         if (HAS_DDI(dev))
5328                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5329         else
5330                 intel_connector->get_hw_state = intel_connector_get_hw_state;
5331         intel_connector->unregister = intel_dp_connector_unregister;
5332
5333         /* Set up the hotplug pin. */
5334         switch (port) {
5335         case PORT_A:
5336                 intel_encoder->hpd_pin = HPD_PORT_A;
5337                 break;
5338         case PORT_B:
5339                 intel_encoder->hpd_pin = HPD_PORT_B;
5340                 break;
5341         case PORT_C:
5342                 intel_encoder->hpd_pin = HPD_PORT_C;
5343                 break;
5344         case PORT_D:
5345                 intel_encoder->hpd_pin = HPD_PORT_D;
5346                 break;
5347         default:
5348                 BUG();
5349         }
5350
5351         if (is_edp(intel_dp)) {
5352                 pps_lock(intel_dp);
5353                 if (IS_VALLEYVIEW(dev)) {
5354                         vlv_initial_power_sequencer_setup(intel_dp);
5355                 } else {
5356                         intel_dp_init_panel_power_timestamps(intel_dp);
5357                         intel_dp_init_panel_power_sequencer(dev, intel_dp);
5358                 }
5359                 pps_unlock(intel_dp);
5360         }
5361
5362         intel_dp_aux_init(intel_dp, intel_connector);
5363
5364         /* init MST on ports that can support it */
5365         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5366                 if (port == PORT_B || port == PORT_C || port == PORT_D) {
5367                         intel_dp_mst_encoder_init(intel_dig_port,
5368                                                   intel_connector->base.base.id);
5369                 }
5370         }
5371
5372         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5373                 drm_dp_aux_unregister(&intel_dp->aux);
5374                 if (is_edp(intel_dp)) {
5375                         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5376                         /*
5377                          * vdd might still be enabled do to the delayed vdd off.
5378                          * Make sure vdd is actually turned off here.
5379                          */
5380                         pps_lock(intel_dp);
5381                         edp_panel_vdd_off_sync(intel_dp);
5382                         pps_unlock(intel_dp);
5383                 }
5384                 drm_connector_unregister(connector);
5385                 drm_connector_cleanup(connector);
5386                 return false;
5387         }
5388
5389         intel_dp_add_properties(intel_dp, connector);
5390
5391         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5392          * 0xd.  Failure to do so will result in spurious interrupts being
5393          * generated on the port when a cable is not attached.
5394          */
5395         if (IS_G4X(dev) && !IS_GM45(dev)) {
5396                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5397                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5398         }
5399
5400         return true;
5401 }
5402
5403 void
5404 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5405 {
5406         struct drm_i915_private *dev_priv = dev->dev_private;
5407         struct intel_digital_port *intel_dig_port;
5408         struct intel_encoder *intel_encoder;
5409         struct drm_encoder *encoder;
5410         struct intel_connector *intel_connector;
5411
5412         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
5413         if (!intel_dig_port)
5414                 return;
5415
5416         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
5417         if (!intel_connector) {
5418                 kfree(intel_dig_port);
5419                 return;
5420         }
5421
5422         intel_encoder = &intel_dig_port->base;
5423         encoder = &intel_encoder->base;
5424
5425         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5426                          DRM_MODE_ENCODER_TMDS);
5427
5428         intel_encoder->compute_config = intel_dp_compute_config;
5429         intel_encoder->disable = intel_disable_dp;
5430         intel_encoder->get_hw_state = intel_dp_get_hw_state;
5431         intel_encoder->get_config = intel_dp_get_config;
5432         intel_encoder->suspend = intel_dp_encoder_suspend;
5433         if (IS_CHERRYVIEW(dev)) {
5434                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
5435                 intel_encoder->pre_enable = chv_pre_enable_dp;
5436                 intel_encoder->enable = vlv_enable_dp;
5437                 intel_encoder->post_disable = chv_post_disable_dp;
5438         } else if (IS_VALLEYVIEW(dev)) {
5439                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
5440                 intel_encoder->pre_enable = vlv_pre_enable_dp;
5441                 intel_encoder->enable = vlv_enable_dp;
5442                 intel_encoder->post_disable = vlv_post_disable_dp;
5443         } else {
5444                 intel_encoder->pre_enable = g4x_pre_enable_dp;
5445                 intel_encoder->enable = g4x_enable_dp;
5446                 if (INTEL_INFO(dev)->gen >= 5)
5447                         intel_encoder->post_disable = ilk_post_disable_dp;
5448         }
5449
5450         intel_dig_port->port = port;
5451         intel_dig_port->dp.output_reg = output_reg;
5452
5453         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
5454         if (IS_CHERRYVIEW(dev)) {
5455                 if (port == PORT_D)
5456                         intel_encoder->crtc_mask = 1 << 2;
5457                 else
5458                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5459         } else {
5460                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5461         }
5462         intel_encoder->cloneable = 0;
5463         intel_encoder->hot_plug = intel_dp_hot_plug;
5464
5465         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5466         dev_priv->hpd_irq_port[port] = intel_dig_port;
5467
5468         if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5469                 drm_encoder_cleanup(encoder);
5470                 kfree(intel_dig_port);
5471                 kfree(intel_connector);
5472         }
5473 }
5474
5475 void intel_dp_mst_suspend(struct drm_device *dev)
5476 {
5477         struct drm_i915_private *dev_priv = dev->dev_private;
5478         int i;
5479
5480         /* disable MST */
5481         for (i = 0; i < I915_MAX_PORTS; i++) {
5482                 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5483                 if (!intel_dig_port)
5484                         continue;
5485
5486                 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5487                         if (!intel_dig_port->dp.can_mst)
5488                                 continue;
5489                         if (intel_dig_port->dp.is_mst)
5490                                 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5491                 }
5492         }
5493 }
5494
5495 void intel_dp_mst_resume(struct drm_device *dev)
5496 {
5497         struct drm_i915_private *dev_priv = dev->dev_private;
5498         int i;
5499
5500         for (i = 0; i < I915_MAX_PORTS; i++) {
5501                 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5502                 if (!intel_dig_port)
5503                         continue;
5504                 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5505                         int ret;
5506
5507                         if (!intel_dig_port->dp.can_mst)
5508                                 continue;
5509
5510                         ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5511                         if (ret != 0) {
5512                                 intel_dp_check_mst_status(&intel_dig_port->dp);
5513                         }
5514                 }
5515         }
5516 }