drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <drm/drm_plane_helper.h>
  43 #include <drm/drm_rect.h>
  44 #include <linux/dma_remapping.h>
  45
  46 /* Primary plane formats supported by all gen */
  47 #define COMMON_PRIMARY_FORMATS \
  48         DRM_FORMAT_C8, \
  49         DRM_FORMAT_RGB565, \
  50         DRM_FORMAT_XRGB8888, \
  51         DRM_FORMAT_ARGB8888
  52
  53 /* Primary plane formats for gen <= 3 */
  54 static const uint32_t intel_primary_formats_gen2[] = {
  55         COMMON_PRIMARY_FORMATS,
  56         DRM_FORMAT_XRGB1555,
  57         DRM_FORMAT_ARGB1555,
  58 };
  59
  60 /* Primary plane formats for gen >= 4 */
  61 static const uint32_t intel_primary_formats_gen4[] = {
  62         COMMON_PRIMARY_FORMATS, \
  63         DRM_FORMAT_XBGR8888,
  64         DRM_FORMAT_ABGR8888,
  65         DRM_FORMAT_XRGB2101010,
  66         DRM_FORMAT_ARGB2101010,
  67         DRM_FORMAT_XBGR2101010,
  68         DRM_FORMAT_ABGR2101010,
  69 };
  70
  71 /* Cursor formats */
  72 static const uint32_t intel_cursor_formats[] = {
  73         DRM_FORMAT_ARGB8888,
  74 };
  75
  76 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  77
  78 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  79                                 struct intel_crtc_config *pipe_config);
  80 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  81                                    struct intel_crtc_config *pipe_config);
  82
  83 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  84                           int x, int y, struct drm_framebuffer *old_fb);
  85 static int intel_framebuffer_init(struct drm_device *dev,
  86                                   struct intel_framebuffer *ifb,
  87                                   struct drm_mode_fb_cmd2 *mode_cmd,
  88                                   struct drm_i915_gem_object *obj);
  89 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  90 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  91 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  92                                          struct intel_link_m_n *m_n,
  93                                          struct intel_link_m_n *m2_n2);
  94 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
  95 static void haswell_set_pipeconf(struct drm_crtc *crtc);
  96 static void intel_set_pipe_csc(struct drm_crtc *crtc);
  97 static void vlv_prepare_pll(struct intel_crtc *crtc);
  98 static void chv_prepare_pll(struct intel_crtc *crtc);
  99
 100 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
 101 {
 102         if (!connector->mst_port)
 103                 return connector->encoder;
 104         else
 105                 return &connector->mst_port->mst_encoders[pipe]->base;
 106 }
 107
 108 typedef struct {
 109         int     min, max;
 110 } intel_range_t;
 111
 112 typedef struct {
 113         int     dot_limit;
 114         int     p2_slow, p2_fast;
 115 } intel_p2_t;
 116
 117 typedef struct intel_limit intel_limit_t;
 118 struct intel_limit {
 119         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 120         intel_p2_t          p2;
 121 };
 122
 123 int
 124 intel_pch_rawclk(struct drm_device *dev)
 125 {
 126         struct drm_i915_private *dev_priv = dev->dev_private;
 127
 128         WARN_ON(!HAS_PCH_SPLIT(dev));
 129
 130         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 131 }
 132
 133 static inline u32 /* units of 100MHz */
 134 intel_fdi_link_freq(struct drm_device *dev)
 135 {
 136         if (IS_GEN5(dev)) {
 137                 struct drm_i915_private *dev_priv = dev->dev_private;
 138                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 139         } else
 140                 return 27;
 141 }
 142
 143 static const intel_limit_t intel_limits_i8xx_dac = {
 144         .dot = { .min = 25000, .max = 350000 },
 145         .vco = { .min = 908000, .max = 1512000 },
 146         .n = { .min = 2, .max = 16 },
 147         .m = { .min = 96, .max = 140 },
 148         .m1 = { .min = 18, .max = 26 },
 149         .m2 = { .min = 6, .max = 16 },
 150         .p = { .min = 4, .max = 128 },
 151         .p1 = { .min = 2, .max = 33 },
 152         .p2 = { .dot_limit = 165000,
 153                 .p2_slow = 4, .p2_fast = 2 },
 154 };
 155
 156 static const intel_limit_t intel_limits_i8xx_dvo = {
 157         .dot = { .min = 25000, .max = 350000 },
 158         .vco = { .min = 908000, .max = 1512000 },
 159         .n = { .min = 2, .max = 16 },
 160         .m = { .min = 96, .max = 140 },
 161         .m1 = { .min = 18, .max = 26 },
 162         .m2 = { .min = 6, .max = 16 },
 163         .p = { .min = 4, .max = 128 },
 164         .p1 = { .min = 2, .max = 33 },
 165         .p2 = { .dot_limit = 165000,
 166                 .p2_slow = 4, .p2_fast = 4 },
 167 };
 168
 169 static const intel_limit_t intel_limits_i8xx_lvds = {
 170         .dot = { .min = 25000, .max = 350000 },
 171         .vco = { .min = 908000, .max = 1512000 },
 172         .n = { .min = 2, .max = 16 },
 173         .m = { .min = 96, .max = 140 },
 174         .m1 = { .min = 18, .max = 26 },
 175         .m2 = { .min = 6, .max = 16 },
 176         .p = { .min = 4, .max = 128 },
 177         .p1 = { .min = 1, .max = 6 },
 178         .p2 = { .dot_limit = 165000,
 179                 .p2_slow = 14, .p2_fast = 7 },
 180 };
 181
 182 static const intel_limit_t intel_limits_i9xx_sdvo = {
 183         .dot = { .min = 20000, .max = 400000 },
 184         .vco = { .min = 1400000, .max = 2800000 },
 185         .n = { .min = 1, .max = 6 },
 186         .m = { .min = 70, .max = 120 },
 187         .m1 = { .min = 8, .max = 18 },
 188         .m2 = { .min = 3, .max = 7 },
 189         .p = { .min = 5, .max = 80 },
 190         .p1 = { .min = 1, .max = 8 },
 191         .p2 = { .dot_limit = 200000,
 192                 .p2_slow = 10, .p2_fast = 5 },
 193 };
 194
 195 static const intel_limit_t intel_limits_i9xx_lvds = {
 196         .dot = { .min = 20000, .max = 400000 },
 197         .vco = { .min = 1400000, .max = 2800000 },
 198         .n = { .min = 1, .max = 6 },
 199         .m = { .min = 70, .max = 120 },
 200         .m1 = { .min = 8, .max = 18 },
 201         .m2 = { .min = 3, .max = 7 },
 202         .p = { .min = 7, .max = 98 },
 203         .p1 = { .min = 1, .max = 8 },
 204         .p2 = { .dot_limit = 112000,
 205                 .p2_slow = 14, .p2_fast = 7 },
 206 };
 207
 208
 209 static const intel_limit_t intel_limits_g4x_sdvo = {
 210         .dot = { .min = 25000, .max = 270000 },
 211         .vco = { .min = 1750000, .max = 3500000},
 212         .n = { .min = 1, .max = 4 },
 213         .m = { .min = 104, .max = 138 },
 214         .m1 = { .min = 17, .max = 23 },
 215         .m2 = { .min = 5, .max = 11 },
 216         .p = { .min = 10, .max = 30 },
 217         .p1 = { .min = 1, .max = 3},
 218         .p2 = { .dot_limit = 270000,
 219                 .p2_slow = 10,
 220                 .p2_fast = 10
 221         },
 222 };
 223
 224 static const intel_limit_t intel_limits_g4x_hdmi = {
 225         .dot = { .min = 22000, .max = 400000 },
 226         .vco = { .min = 1750000, .max = 3500000},
 227         .n = { .min = 1, .max = 4 },
 228         .m = { .min = 104, .max = 138 },
 229         .m1 = { .min = 16, .max = 23 },
 230         .m2 = { .min = 5, .max = 11 },
 231         .p = { .min = 5, .max = 80 },
 232         .p1 = { .min = 1, .max = 8},
 233         .p2 = { .dot_limit = 165000,
 234                 .p2_slow = 10, .p2_fast = 5 },
 235 };
 236
 237 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 238         .dot = { .min = 20000, .max = 115000 },
 239         .vco = { .min = 1750000, .max = 3500000 },
 240         .n = { .min = 1, .max = 3 },
 241         .m = { .min = 104, .max = 138 },
 242         .m1 = { .min = 17, .max = 23 },
 243         .m2 = { .min = 5, .max = 11 },
 244         .p = { .min = 28, .max = 112 },
 245         .p1 = { .min = 2, .max = 8 },
 246         .p2 = { .dot_limit = 0,
 247                 .p2_slow = 14, .p2_fast = 14
 248         },
 249 };
 250
 251 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 252         .dot = { .min = 80000, .max = 224000 },
 253         .vco = { .min = 1750000, .max = 3500000 },
 254         .n = { .min = 1, .max = 3 },
 255         .m = { .min = 104, .max = 138 },
 256         .m1 = { .min = 17, .max = 23 },
 257         .m2 = { .min = 5, .max = 11 },
 258         .p = { .min = 14, .max = 42 },
 259         .p1 = { .min = 2, .max = 6 },
 260         .p2 = { .dot_limit = 0,
 261                 .p2_slow = 7, .p2_fast = 7
 262         },
 263 };
 264
 265 static const intel_limit_t intel_limits_pineview_sdvo = {
 266         .dot = { .min = 20000, .max = 400000},
 267         .vco = { .min = 1700000, .max = 3500000 },
 268         /* Pineview's Ncounter is a ring counter */
 269         .n = { .min = 3, .max = 6 },
 270         .m = { .min = 2, .max = 256 },
 271         /* Pineview only has one combined m divider, which we treat as m2. */
 272         .m1 = { .min = 0, .max = 0 },
 273         .m2 = { .min = 0, .max = 254 },
 274         .p = { .min = 5, .max = 80 },
 275         .p1 = { .min = 1, .max = 8 },
 276         .p2 = { .dot_limit = 200000,
 277                 .p2_slow = 10, .p2_fast = 5 },
 278 };
 279
 280 static const intel_limit_t intel_limits_pineview_lvds = {
 281         .dot = { .min = 20000, .max = 400000 },
 282         .vco = { .min = 1700000, .max = 3500000 },
 283         .n = { .min = 3, .max = 6 },
 284         .m = { .min = 2, .max = 256 },
 285         .m1 = { .min = 0, .max = 0 },
 286         .m2 = { .min = 0, .max = 254 },
 287         .p = { .min = 7, .max = 112 },
 288         .p1 = { .min = 1, .max = 8 },
 289         .p2 = { .dot_limit = 112000,
 290                 .p2_slow = 14, .p2_fast = 14 },
 291 };
 292
 293 /* Ironlake / Sandybridge
 294  *
 295  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 296  * the range value for them is (actual_value - 2).
 297  */
 298 static const intel_limit_t intel_limits_ironlake_dac = {
 299         .dot = { .min = 25000, .max = 350000 },
 300         .vco = { .min = 1760000, .max = 3510000 },
 301         .n = { .min = 1, .max = 5 },
 302         .m = { .min = 79, .max = 127 },
 303         .m1 = { .min = 12, .max = 22 },
 304         .m2 = { .min = 5, .max = 9 },
 305         .p = { .min = 5, .max = 80 },
 306         .p1 = { .min = 1, .max = 8 },
 307         .p2 = { .dot_limit = 225000,
 308                 .p2_slow = 10, .p2_fast = 5 },
 309 };
 310
 311 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 312         .dot = { .min = 25000, .max = 350000 },
 313         .vco = { .min = 1760000, .max = 3510000 },
 314         .n = { .min = 1, .max = 3 },
 315         .m = { .min = 79, .max = 118 },
 316         .m1 = { .min = 12, .max = 22 },
 317         .m2 = { .min = 5, .max = 9 },
 318         .p = { .min = 28, .max = 112 },
 319         .p1 = { .min = 2, .max = 8 },
 320         .p2 = { .dot_limit = 225000,
 321                 .p2_slow = 14, .p2_fast = 14 },
 322 };
 323
 324 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 325         .dot = { .min = 25000, .max = 350000 },
 326         .vco = { .min = 1760000, .max = 3510000 },
 327         .n = { .min = 1, .max = 3 },
 328         .m = { .min = 79, .max = 127 },
 329         .m1 = { .min = 12, .max = 22 },
 330         .m2 = { .min = 5, .max = 9 },
 331         .p = { .min = 14, .max = 56 },
 332         .p1 = { .min = 2, .max = 8 },
 333         .p2 = { .dot_limit = 225000,
 334                 .p2_slow = 7, .p2_fast = 7 },
 335 };
 336
 337 /* LVDS 100mhz refclk limits. */
 338 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 339         .dot = { .min = 25000, .max = 350000 },
 340         .vco = { .min = 1760000, .max = 3510000 },
 341         .n = { .min = 1, .max = 2 },
 342         .m = { .min = 79, .max = 126 },
 343         .m1 = { .min = 12, .max = 22 },
 344         .m2 = { .min = 5, .max = 9 },
 345         .p = { .min = 28, .max = 112 },
 346         .p1 = { .min = 2, .max = 8 },
 347         .p2 = { .dot_limit = 225000,
 348                 .p2_slow = 14, .p2_fast = 14 },
 349 };
 350
 351 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 352         .dot = { .min = 25000, .max = 350000 },
 353         .vco = { .min = 1760000, .max = 3510000 },
 354         .n = { .min = 1, .max = 3 },
 355         .m = { .min = 79, .max = 126 },
 356         .m1 = { .min = 12, .max = 22 },
 357         .m2 = { .min = 5, .max = 9 },
 358         .p = { .min = 14, .max = 42 },
 359         .p1 = { .min = 2, .max = 6 },
 360         .p2 = { .dot_limit = 225000,
 361                 .p2_slow = 7, .p2_fast = 7 },
 362 };
 363
 364 static const intel_limit_t intel_limits_vlv = {
 365          /*
 366           * These are the data rate limits (measured in fast clocks)
 367           * since those are the strictest limits we have. The fast
 368           * clock and actual rate limits are more relaxed, so checking
 369           * them would make no difference.
 370           */
 371         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 372         .vco = { .min = 4000000, .max = 6000000 },
 373         .n = { .min = 1, .max = 7 },
 374         .m1 = { .min = 2, .max = 3 },
 375         .m2 = { .min = 11, .max = 156 },
 376         .p1 = { .min = 2, .max = 3 },
 377         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 378 };
 379
 380 static const intel_limit_t intel_limits_chv = {
 381         /*
 382          * These are the data rate limits (measured in fast clocks)
 383          * since those are the strictest limits we have.  The fast
 384          * clock and actual rate limits are more relaxed, so checking
 385          * them would make no difference.
 386          */
 387         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 388         .vco = { .min = 4860000, .max = 6700000 },
 389         .n = { .min = 1, .max = 1 },
 390         .m1 = { .min = 2, .max = 2 },
 391         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 392         .p1 = { .min = 2, .max = 4 },
 393         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 394 };
 395
 396 static void vlv_clock(int refclk, intel_clock_t *clock)
 397 {
 398         clock->m = clock->m1 * clock->m2;
 399         clock->p = clock->p1 * clock->p2;
 400         if (WARN_ON(clock->n == 0 || clock->p == 0))
 401                 return;
 402         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 403         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 404 }
 405
 406 /**
 407  * Returns whether any output on the specified pipe is of the specified type
 408  */
 409 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 410 {
 411         struct drm_device *dev = crtc->dev;
 412         struct intel_encoder *encoder;
 413
 414         for_each_encoder_on_crtc(dev, crtc, encoder)
 415                 if (encoder->type == type)
 416                         return true;
 417
 418         return false;
 419 }
 420
 421 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 422                                                 int refclk)
 423 {
 424         struct drm_device *dev = crtc->dev;
 425         const intel_limit_t *limit;
 426
 427         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 428                 if (intel_is_dual_link_lvds(dev)) {
 429                         if (refclk == 100000)
 430                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 431                         else
 432                                 limit = &intel_limits_ironlake_dual_lvds;
 433                 } else {
 434                         if (refclk == 100000)
 435                                 limit = &intel_limits_ironlake_single_lvds_100m;
 436                         else
 437                                 limit = &intel_limits_ironlake_single_lvds;
 438                 }
 439         } else
 440                 limit = &intel_limits_ironlake_dac;
 441
 442         return limit;
 443 }
 444
 445 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 446 {
 447         struct drm_device *dev = crtc->dev;
 448         const intel_limit_t *limit;
 449
 450         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 451                 if (intel_is_dual_link_lvds(dev))
 452                         limit = &intel_limits_g4x_dual_channel_lvds;
 453                 else
 454                         limit = &intel_limits_g4x_single_channel_lvds;
 455         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 456                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 457                 limit = &intel_limits_g4x_hdmi;
 458         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 459                 limit = &intel_limits_g4x_sdvo;
 460         } else /* The option is for other outputs */
 461                 limit = &intel_limits_i9xx_sdvo;
 462
 463         return limit;
 464 }
 465
 466 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 467 {
 468         struct drm_device *dev = crtc->dev;
 469         const intel_limit_t *limit;
 470
 471         if (HAS_PCH_SPLIT(dev))
 472                 limit = intel_ironlake_limit(crtc, refclk);
 473         else if (IS_G4X(dev)) {
 474                 limit = intel_g4x_limit(crtc);
 475         } else if (IS_PINEVIEW(dev)) {
 476                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 477                         limit = &intel_limits_pineview_lvds;
 478                 else
 479                         limit = &intel_limits_pineview_sdvo;
 480         } else if (IS_CHERRYVIEW(dev)) {
 481                 limit = &intel_limits_chv;
 482         } else if (IS_VALLEYVIEW(dev)) {
 483                 limit = &intel_limits_vlv;
 484         } else if (!IS_GEN2(dev)) {
 485                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 486                         limit = &intel_limits_i9xx_lvds;
 487                 else
 488                         limit = &intel_limits_i9xx_sdvo;
 489         } else {
 490                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 491                         limit = &intel_limits_i8xx_lvds;
 492                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 493                         limit = &intel_limits_i8xx_dvo;
 494                 else
 495                         limit = &intel_limits_i8xx_dac;
 496         }
 497         return limit;
 498 }
 499
 500 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 501 static void pineview_clock(int refclk, intel_clock_t *clock)
 502 {
 503         clock->m = clock->m2 + 2;
 504         clock->p = clock->p1 * clock->p2;
 505         if (WARN_ON(clock->n == 0 || clock->p == 0))
 506                 return;
 507         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 508         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 509 }
 510
 511 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 512 {
 513         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 514 }
 515
 516 static void i9xx_clock(int refclk, intel_clock_t *clock)
 517 {
 518         clock->m = i9xx_dpll_compute_m(clock);
 519         clock->p = clock->p1 * clock->p2;
 520         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 521                 return;
 522         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 523         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 524 }
 525
 526 static void chv_clock(int refclk, intel_clock_t *clock)
 527 {
 528         clock->m = clock->m1 * clock->m2;
 529         clock->p = clock->p1 * clock->p2;
 530         if (WARN_ON(clock->n == 0 || clock->p == 0))
 531                 return;
 532         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 533                         clock->n << 22);
 534         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 535 }
 536
 537 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 538 /**
 539  * Returns whether the given set of divisors are valid for a given refclk with
 540  * the given connectors.
 541  */
 542
 543 static bool intel_PLL_is_valid(struct drm_device *dev,
 544                                const intel_limit_t *limit,
 545                                const intel_clock_t *clock)
 546 {
 547         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 548                 INTELPllInvalid("n out of range\n");
 549         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 550                 INTELPllInvalid("p1 out of range\n");
 551         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 552                 INTELPllInvalid("m2 out of range\n");
 553         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 554                 INTELPllInvalid("m1 out of range\n");
 555
 556         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 557                 if (clock->m1 <= clock->m2)
 558                         INTELPllInvalid("m1 <= m2\n");
 559
 560         if (!IS_VALLEYVIEW(dev)) {
 561                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 562                         INTELPllInvalid("p out of range\n");
 563                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 564                         INTELPllInvalid("m out of range\n");
 565         }
 566
 567         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 568                 INTELPllInvalid("vco out of range\n");
 569         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 570          * connector, etc., rather than just a single range.
 571          */
 572         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 573                 INTELPllInvalid("dot out of range\n");
 574
 575         return true;
 576 }
 577
 578 static bool
 579 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 580                     int target, int refclk, intel_clock_t *match_clock,
 581                     intel_clock_t *best_clock)
 582 {
 583         struct drm_device *dev = crtc->dev;
 584         intel_clock_t clock;
 585         int err = target;
 586
 587         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 588                 /*
 589                  * For LVDS just rely on its current settings for dual-channel.
 590                  * We haven't figured out how to reliably set up different
 591                  * single/dual channel state, if we even can.
 592                  */
 593                 if (intel_is_dual_link_lvds(dev))
 594                         clock.p2 = limit->p2.p2_fast;
 595                 else
 596                         clock.p2 = limit->p2.p2_slow;
 597         } else {
 598                 if (target < limit->p2.dot_limit)
 599                         clock.p2 = limit->p2.p2_slow;
 600                 else
 601                         clock.p2 = limit->p2.p2_fast;
 602         }
 603
 604         memset(best_clock, 0, sizeof(*best_clock));
 605
 606         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 607              clock.m1++) {
 608                 for (clock.m2 = limit->m2.min;
 609                      clock.m2 <= limit->m2.max; clock.m2++) {
 610                         if (clock.m2 >= clock.m1)
 611                                 break;
 612                         for (clock.n = limit->n.min;
 613                              clock.n <= limit->n.max; clock.n++) {
 614                                 for (clock.p1 = limit->p1.min;
 615                                         clock.p1 <= limit->p1.max; clock.p1++) {
 616                                         int this_err;
 617
 618                                         i9xx_clock(refclk, &clock);
 619                                         if (!intel_PLL_is_valid(dev, limit,
 620                                                                 &clock))
 621                                                 continue;
 622                                         if (match_clock &&
 623                                             clock.p != match_clock->p)
 624                                                 continue;
 625
 626                                         this_err = abs(clock.dot - target);
 627                                         if (this_err < err) {
 628                                                 *best_clock = clock;
 629                                                 err = this_err;
 630                                         }
 631                                 }
 632                         }
 633                 }
 634         }
 635
 636         return (err != target);
 637 }
 638
 639 static bool
 640 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 641                    int target, int refclk, intel_clock_t *match_clock,
 642                    intel_clock_t *best_clock)
 643 {
 644         struct drm_device *dev = crtc->dev;
 645         intel_clock_t clock;
 646         int err = target;
 647
 648         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 649                 /*
 650                  * For LVDS just rely on its current settings for dual-channel.
 651                  * We haven't figured out how to reliably set up different
 652                  * single/dual channel state, if we even can.
 653                  */
 654                 if (intel_is_dual_link_lvds(dev))
 655                         clock.p2 = limit->p2.p2_fast;
 656                 else
 657                         clock.p2 = limit->p2.p2_slow;
 658         } else {
 659                 if (target < limit->p2.dot_limit)
 660                         clock.p2 = limit->p2.p2_slow;
 661                 else
 662                         clock.p2 = limit->p2.p2_fast;
 663         }
 664
 665         memset(best_clock, 0, sizeof(*best_clock));
 666
 667         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 668              clock.m1++) {
 669                 for (clock.m2 = limit->m2.min;
 670                      clock.m2 <= limit->m2.max; clock.m2++) {
 671                         for (clock.n = limit->n.min;
 672                              clock.n <= limit->n.max; clock.n++) {
 673                                 for (clock.p1 = limit->p1.min;
 674                                         clock.p1 <= limit->p1.max; clock.p1++) {
 675                                         int this_err;
 676
 677                                         pineview_clock(refclk, &clock);
 678                                         if (!intel_PLL_is_valid(dev, limit,
 679                                                                 &clock))
 680                                                 continue;
 681                                         if (match_clock &&
 682                                             clock.p != match_clock->p)
 683                                                 continue;
 684
 685                                         this_err = abs(clock.dot - target);
 686                                         if (this_err < err) {
 687                                                 *best_clock = clock;
 688                                                 err = this_err;
 689                                         }
 690                                 }
 691                         }
 692                 }
 693         }
 694
 695         return (err != target);
 696 }
 697
 698 static bool
 699 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 700                    int target, int refclk, intel_clock_t *match_clock,
 701                    intel_clock_t *best_clock)
 702 {
 703         struct drm_device *dev = crtc->dev;
 704         intel_clock_t clock;
 705         int max_n;
 706         bool found;
 707         /* approximately equals target * 0.00585 */
 708         int err_most = (target >> 8) + (target >> 9);
 709         found = false;
 710
 711         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 712                 if (intel_is_dual_link_lvds(dev))
 713                         clock.p2 = limit->p2.p2_fast;
 714                 else
 715                         clock.p2 = limit->p2.p2_slow;
 716         } else {
 717                 if (target < limit->p2.dot_limit)
 718                         clock.p2 = limit->p2.p2_slow;
 719                 else
 720                         clock.p2 = limit->p2.p2_fast;
 721         }
 722
 723         memset(best_clock, 0, sizeof(*best_clock));
 724         max_n = limit->n.max;
 725         /* based on hardware requirement, prefer smaller n to precision */
 726         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 727                 /* based on hardware requirement, prefere larger m1,m2 */
 728                 for (clock.m1 = limit->m1.max;
 729                      clock.m1 >= limit->m1.min; clock.m1--) {
 730                         for (clock.m2 = limit->m2.max;
 731                              clock.m2 >= limit->m2.min; clock.m2--) {
 732                                 for (clock.p1 = limit->p1.max;
 733                                      clock.p1 >= limit->p1.min; clock.p1--) {
 734                                         int this_err;
 735
 736                                         i9xx_clock(refclk, &clock);
 737                                         if (!intel_PLL_is_valid(dev, limit,
 738                                                                 &clock))
 739                                                 continue;
 740
 741                                         this_err = abs(clock.dot - target);
 742                                         if (this_err < err_most) {
 743                                                 *best_clock = clock;
 744                                                 err_most = this_err;
 745                                                 max_n = clock.n;
 746                                                 found = true;
 747                                         }
 748                                 }
 749                         }
 750                 }
 751         }
 752         return found;
 753 }
 754
 755 static bool
 756 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 757                    int target, int refclk, intel_clock_t *match_clock,
 758                    intel_clock_t *best_clock)
 759 {
 760         struct drm_device *dev = crtc->dev;
 761         intel_clock_t clock;
 762         unsigned int bestppm = 1000000;
 763         /* min update 19.2 MHz */
 764         int max_n = min(limit->n.max, refclk / 19200);
 765         bool found = false;
 766
 767         target *= 5; /* fast clock */
 768
 769         memset(best_clock, 0, sizeof(*best_clock));
 770
 771         /* based on hardware requirement, prefer smaller n to precision */
 772         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 773                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 774                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 775                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 776                                 clock.p = clock.p1 * clock.p2;
 777                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 778                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 779                                         unsigned int ppm, diff;
 780
 781                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 782                                                                      refclk * clock.m1);
 783
 784                                         vlv_clock(refclk, &clock);
 785
 786                                         if (!intel_PLL_is_valid(dev, limit,
 787                                                                 &clock))
 788                                                 continue;
 789
 790                                         diff = abs(clock.dot - target);
 791                                         ppm = div_u64(1000000ULL * diff, target);
 792
 793                                         if (ppm < 100 && clock.p > best_clock->p) {
 794                                                 bestppm = 0;
 795                                                 *best_clock = clock;
 796                                                 found = true;
 797                                         }
 798
 799                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 800                                                 bestppm = ppm;
 801                                                 *best_clock = clock;
 802                                                 found = true;
 803                                         }
 804                                 }
 805                         }
 806                 }
 807         }
 808
 809         return found;
 810 }
 811
 812 static bool
 813 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 814                    int target, int refclk, intel_clock_t *match_clock,
 815                    intel_clock_t *best_clock)
 816 {
 817         struct drm_device *dev = crtc->dev;
 818         intel_clock_t clock;
 819         uint64_t m2;
 820         int found = false;
 821
 822         memset(best_clock, 0, sizeof(*best_clock));
 823
 824         /*
 825          * Based on hardware doc, the n always set to 1, and m1 always
 826          * set to 2.  If requires to support 200Mhz refclk, we need to
 827          * revisit this because n may not 1 anymore.
 828          */
 829         clock.n = 1, clock.m1 = 2;
 830         target *= 5;    /* fast clock */
 831
 832         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 833                 for (clock.p2 = limit->p2.p2_fast;
 834                                 clock.p2 >= limit->p2.p2_slow;
 835                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 836
 837                         clock.p = clock.p1 * clock.p2;
 838
 839                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 840                                         clock.n) << 22, refclk * clock.m1);
 841
 842                         if (m2 > INT_MAX/clock.m1)
 843                                 continue;
 844
 845                         clock.m2 = m2;
 846
 847                         chv_clock(refclk, &clock);
 848
 849                         if (!intel_PLL_is_valid(dev, limit, &clock))
 850                                 continue;
 851
 852                         /* based on hardware requirement, prefer bigger p
 853                          */
 854                         if (clock.p > best_clock->p) {
 855                                 *best_clock = clock;
 856                                 found = true;
 857                         }
 858                 }
 859         }
 860
 861         return found;
 862 }
 863
 864 bool intel_crtc_active(struct drm_crtc *crtc)
 865 {
 866         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 867
 868         /* Be paranoid as we can arrive here with only partial
 869          * state retrieved from the hardware during setup.
 870          *
 871          * We can ditch the adjusted_mode.crtc_clock check as soon
 872          * as Haswell has gained clock readout/fastboot support.
 873          *
 874          * We can ditch the crtc->primary->fb check as soon as we can
 875          * properly reconstruct framebuffers.
 876          */
 877         return intel_crtc->active && crtc->primary->fb &&
 878                 intel_crtc->config.adjusted_mode.crtc_clock;
 879 }
 880
 881 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 882                                              enum pipe pipe)
 883 {
 884         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 885         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 886
 887         return intel_crtc->config.cpu_transcoder;
 888 }
 889
 890 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 891 {
 892         struct drm_i915_private *dev_priv = dev->dev_private;
 893         u32 reg = PIPEDSL(pipe);
 894         u32 line1, line2;
 895         u32 line_mask;
 896
 897         if (IS_GEN2(dev))
 898                 line_mask = DSL_LINEMASK_GEN2;
 899         else
 900                 line_mask = DSL_LINEMASK_GEN3;
 901
 902         line1 = I915_READ(reg) & line_mask;
 903         mdelay(5);
 904         line2 = I915_READ(reg) & line_mask;
 905
 906         return line1 == line2;
 907 }
 908
 909 /*
 910  * intel_wait_for_pipe_off - wait for pipe to turn off
 911  * @crtc: crtc whose pipe to wait for
 912  *
 913  * After disabling a pipe, we can't wait for vblank in the usual way,
 914  * spinning on the vblank interrupt status bit, since we won't actually
 915  * see an interrupt when the pipe is disabled.
 916  *
 917  * On Gen4 and above:
 918  *   wait for the pipe register state bit to turn off
 919  *
 920  * Otherwise:
 921  *   wait for the display line value to settle (it usually
 922  *   ends up stopping at the start of the next frame).
 923  *
 924  */
 925 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
 926 {
 927         struct drm_device *dev = crtc->base.dev;
 928         struct drm_i915_private *dev_priv = dev->dev_private;
 929         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
 930         enum pipe pipe = crtc->pipe;
 931
 932         if (INTEL_INFO(dev)->gen >= 4) {
 933                 int reg = PIPECONF(cpu_transcoder);
 934
 935                 /* Wait for the Pipe State to go off */
 936                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 937                              100))
 938                         WARN(1, "pipe_off wait timed out\n");
 939         } else {
 940                 /* Wait for the display line to settle */
 941                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 942                         WARN(1, "pipe_off wait timed out\n");
 943         }
 944 }
 945
 946 /*
 947  * ibx_digital_port_connected - is the specified port connected?
 948  * @dev_priv: i915 private structure
 949  * @port: the port to test
 950  *
 951  * Returns true if @port is connected, false otherwise.
 952  */
 953 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 954                                 struct intel_digital_port *port)
 955 {
 956         u32 bit;
 957
 958         if (HAS_PCH_IBX(dev_priv->dev)) {
 959                 switch (port->port) {
 960                 case PORT_B:
 961                         bit = SDE_PORTB_HOTPLUG;
 962                         break;
 963                 case PORT_C:
 964                         bit = SDE_PORTC_HOTPLUG;
 965                         break;
 966                 case PORT_D:
 967                         bit = SDE_PORTD_HOTPLUG;
 968                         break;
 969                 default:
 970                         return true;
 971                 }
 972         } else {
 973                 switch (port->port) {
 974                 case PORT_B:
 975                         bit = SDE_PORTB_HOTPLUG_CPT;
 976                         break;
 977                 case PORT_C:
 978                         bit = SDE_PORTC_HOTPLUG_CPT;
 979                         break;
 980                 case PORT_D:
 981                         bit = SDE_PORTD_HOTPLUG_CPT;
 982                         break;
 983                 default:
 984                         return true;
 985                 }
 986         }
 987
 988         return I915_READ(SDEISR) & bit;
 989 }
 990
 991 static const char *state_string(bool enabled)
 992 {
 993         return enabled ? "on" : "off";
 994 }
 995
 996 /* Only for pre-ILK configs */
 997 void assert_pll(struct drm_i915_private *dev_priv,
 998                 enum pipe pipe, bool state)
 999 {
1000         int reg;
1001         u32 val;
1002         bool cur_state;
1003
1004         reg = DPLL(pipe);
1005         val = I915_READ(reg);
1006         cur_state = !!(val & DPLL_VCO_ENABLE);
1007         WARN(cur_state != state,
1008              "PLL state assertion failure (expected %s, current %s)\n",
1009              state_string(state), state_string(cur_state));
1010 }
1011
1012 /* XXX: the dsi pll is shared between MIPI DSI ports */
1013 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1014 {
1015         u32 val;
1016         bool cur_state;
1017
1018         mutex_lock(&dev_priv->dpio_lock);
1019         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1020         mutex_unlock(&dev_priv->dpio_lock);
1021
1022         cur_state = val & DSI_PLL_VCO_EN;
1023         WARN(cur_state != state,
1024              "DSI PLL state assertion failure (expected %s, current %s)\n",
1025              state_string(state), state_string(cur_state));
1026 }
1027 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1028 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1029
1030 struct intel_shared_dpll *
1031 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1032 {
1033         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1034
1035         if (crtc->config.shared_dpll < 0)
1036                 return NULL;
1037
1038         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1039 }
1040
1041 /* For ILK+ */
1042 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1043                         struct intel_shared_dpll *pll,
1044                         bool state)
1045 {
1046         bool cur_state;
1047         struct intel_dpll_hw_state hw_state;
1048
1049         if (WARN (!pll,
1050                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1051                 return;
1052
1053         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1054         WARN(cur_state != state,
1055              "%s assertion failure (expected %s, current %s)\n",
1056              pll->name, state_string(state), state_string(cur_state));
1057 }
1058
1059 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1060                           enum pipe pipe, bool state)
1061 {
1062         int reg;
1063         u32 val;
1064         bool cur_state;
1065         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1066                                                                       pipe);
1067
1068         if (HAS_DDI(dev_priv->dev)) {
1069                 /* DDI does not have a specific FDI_TX register */
1070                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1071                 val = I915_READ(reg);
1072                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1073         } else {
1074                 reg = FDI_TX_CTL(pipe);
1075                 val = I915_READ(reg);
1076                 cur_state = !!(val & FDI_TX_ENABLE);
1077         }
1078         WARN(cur_state != state,
1079              "FDI TX state assertion failure (expected %s, current %s)\n",
1080              state_string(state), state_string(cur_state));
1081 }
1082 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1083 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1084
1085 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1086                           enum pipe pipe, bool state)
1087 {
1088         int reg;
1089         u32 val;
1090         bool cur_state;
1091
1092         reg = FDI_RX_CTL(pipe);
1093         val = I915_READ(reg);
1094         cur_state = !!(val & FDI_RX_ENABLE);
1095         WARN(cur_state != state,
1096              "FDI RX state assertion failure (expected %s, current %s)\n",
1097              state_string(state), state_string(cur_state));
1098 }
1099 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1100 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1101
1102 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1103                                       enum pipe pipe)
1104 {
1105         int reg;
1106         u32 val;
1107
1108         /* ILK FDI PLL is always enabled */
1109         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1110                 return;
1111
1112         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1113         if (HAS_DDI(dev_priv->dev))
1114                 return;
1115
1116         reg = FDI_TX_CTL(pipe);
1117         val = I915_READ(reg);
1118         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1119 }
1120
1121 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1122                        enum pipe pipe, bool state)
1123 {
1124         int reg;
1125         u32 val;
1126         bool cur_state;
1127
1128         reg = FDI_RX_CTL(pipe);
1129         val = I915_READ(reg);
1130         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1131         WARN(cur_state != state,
1132              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1133              state_string(state), state_string(cur_state));
1134 }
1135
1136 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1137                            enum pipe pipe)
1138 {
1139         struct drm_device *dev = dev_priv->dev;
1140         int pp_reg;
1141         u32 val;
1142         enum pipe panel_pipe = PIPE_A;
1143         bool locked = true;
1144
1145         if (WARN_ON(HAS_DDI(dev)))
1146                 return;
1147
1148         if (HAS_PCH_SPLIT(dev)) {
1149                 u32 port_sel;
1150
1151                 pp_reg = PCH_PP_CONTROL;
1152                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1153
1154                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1155                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1156                         panel_pipe = PIPE_B;
1157                 /* XXX: else fix for eDP */
1158         } else if (IS_VALLEYVIEW(dev)) {
1159                 /* presumably write lock depends on pipe, not port select */
1160                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1161                 panel_pipe = pipe;
1162         } else {
1163                 pp_reg = PP_CONTROL;
1164                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1165                         panel_pipe = PIPE_B;
1166         }
1167
1168         val = I915_READ(pp_reg);
1169         if (!(val & PANEL_POWER_ON) ||
1170             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1171                 locked = false;
1172
1173         WARN(panel_pipe == pipe && locked,
1174              "panel assertion failure, pipe %c regs locked\n",
1175              pipe_name(pipe));
1176 }
1177
1178 static void assert_cursor(struct drm_i915_private *dev_priv,
1179                           enum pipe pipe, bool state)
1180 {
1181         struct drm_device *dev = dev_priv->dev;
1182         bool cur_state;
1183
1184         if (IS_845G(dev) || IS_I865G(dev))
1185                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1186         else
1187                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1188
1189         WARN(cur_state != state,
1190              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1191              pipe_name(pipe), state_string(state), state_string(cur_state));
1192 }
1193 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1194 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1195
1196 void assert_pipe(struct drm_i915_private *dev_priv,
1197                  enum pipe pipe, bool state)
1198 {
1199         int reg;
1200         u32 val;
1201         bool cur_state;
1202         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1203                                                                       pipe);
1204
1205         /* if we need the pipe quirk it must be always on */
1206         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1207             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1208                 state = true;
1209
1210         if (!intel_display_power_is_enabled(dev_priv,
1211                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1212                 cur_state = false;
1213         } else {
1214                 reg = PIPECONF(cpu_transcoder);
1215                 val = I915_READ(reg);
1216                 cur_state = !!(val & PIPECONF_ENABLE);
1217         }
1218
1219         WARN(cur_state != state,
1220              "pipe %c assertion failure (expected %s, current %s)\n",
1221              pipe_name(pipe), state_string(state), state_string(cur_state));
1222 }
1223
1224 static void assert_plane(struct drm_i915_private *dev_priv,
1225                          enum plane plane, bool state)
1226 {
1227         int reg;
1228         u32 val;
1229         bool cur_state;
1230
1231         reg = DSPCNTR(plane);
1232         val = I915_READ(reg);
1233         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1234         WARN(cur_state != state,
1235              "plane %c assertion failure (expected %s, current %s)\n",
1236              plane_name(plane), state_string(state), state_string(cur_state));
1237 }
1238
1239 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1240 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1241
1242 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1243                                    enum pipe pipe)
1244 {
1245         struct drm_device *dev = dev_priv->dev;
1246         int reg, i;
1247         u32 val;
1248         int cur_pipe;
1249
1250         /* Primary planes are fixed to pipes on gen4+ */
1251         if (INTEL_INFO(dev)->gen >= 4) {
1252                 reg = DSPCNTR(pipe);
1253                 val = I915_READ(reg);
1254                 WARN(val & DISPLAY_PLANE_ENABLE,
1255                      "plane %c assertion failure, should be disabled but not\n",
1256                      plane_name(pipe));
1257                 return;
1258         }
1259
1260         /* Need to check both planes against the pipe */
1261         for_each_pipe(dev_priv, i) {
1262                 reg = DSPCNTR(i);
1263                 val = I915_READ(reg);
1264                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1265                         DISPPLANE_SEL_PIPE_SHIFT;
1266                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1267                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1268                      plane_name(i), pipe_name(pipe));
1269         }
1270 }
1271
1272 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1273                                     enum pipe pipe)
1274 {
1275         struct drm_device *dev = dev_priv->dev;
1276         int reg, sprite;
1277         u32 val;
1278
1279         if (INTEL_INFO(dev)->gen >= 9) {
1280                 for_each_sprite(pipe, sprite) {
1281                         val = I915_READ(PLANE_CTL(pipe, sprite));
1282                         WARN(val & PLANE_CTL_ENABLE,
1283                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1284                              sprite, pipe_name(pipe));
1285                 }
1286         } else if (IS_VALLEYVIEW(dev)) {
1287                 for_each_sprite(pipe, sprite) {
1288                         reg = SPCNTR(pipe, sprite);
1289                         val = I915_READ(reg);
1290                         WARN(val & SP_ENABLE,
1291                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1292                              sprite_name(pipe, sprite), pipe_name(pipe));
1293                 }
1294         } else if (INTEL_INFO(dev)->gen >= 7) {
1295                 reg = SPRCTL(pipe);
1296                 val = I915_READ(reg);
1297                 WARN(val & SPRITE_ENABLE,
1298                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1299                      plane_name(pipe), pipe_name(pipe));
1300         } else if (INTEL_INFO(dev)->gen >= 5) {
1301                 reg = DVSCNTR(pipe);
1302                 val = I915_READ(reg);
1303                 WARN(val & DVS_ENABLE,
1304                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1305                      plane_name(pipe), pipe_name(pipe));
1306         }
1307 }
1308
1309 static void assert_vblank_disabled(struct drm_crtc *crtc)
1310 {
1311         if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1312                 drm_crtc_vblank_put(crtc);
1313 }
1314
1315 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1316 {
1317         u32 val;
1318         bool enabled;
1319
1320         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1321
1322         val = I915_READ(PCH_DREF_CONTROL);
1323         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1324                             DREF_SUPERSPREAD_SOURCE_MASK));
1325         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1326 }
1327
1328 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1329                                            enum pipe pipe)
1330 {
1331         int reg;
1332         u32 val;
1333         bool enabled;
1334
1335         reg = PCH_TRANSCONF(pipe);
1336         val = I915_READ(reg);
1337         enabled = !!(val & TRANS_ENABLE);
1338         WARN(enabled,
1339              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1340              pipe_name(pipe));
1341 }
1342
1343 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1344                             enum pipe pipe, u32 port_sel, u32 val)
1345 {
1346         if ((val & DP_PORT_EN) == 0)
1347                 return false;
1348
1349         if (HAS_PCH_CPT(dev_priv->dev)) {
1350                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1351                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1352                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1353                         return false;
1354         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1355                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1356                         return false;
1357         } else {
1358                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1359                         return false;
1360         }
1361         return true;
1362 }
1363
1364 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1365                               enum pipe pipe, u32 val)
1366 {
1367         if ((val & SDVO_ENABLE) == 0)
1368                 return false;
1369
1370         if (HAS_PCH_CPT(dev_priv->dev)) {
1371                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1372                         return false;
1373         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1374                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1375                         return false;
1376         } else {
1377                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1378                         return false;
1379         }
1380         return true;
1381 }
1382
1383 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1384                               enum pipe pipe, u32 val)
1385 {
1386         if ((val & LVDS_PORT_EN) == 0)
1387                 return false;
1388
1389         if (HAS_PCH_CPT(dev_priv->dev)) {
1390                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1391                         return false;
1392         } else {
1393                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1394                         return false;
1395         }
1396         return true;
1397 }
1398
1399 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1400                               enum pipe pipe, u32 val)
1401 {
1402         if ((val & ADPA_DAC_ENABLE) == 0)
1403                 return false;
1404         if (HAS_PCH_CPT(dev_priv->dev)) {
1405                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1406                         return false;
1407         } else {
1408                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1409                         return false;
1410         }
1411         return true;
1412 }
1413
1414 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1415                                    enum pipe pipe, int reg, u32 port_sel)
1416 {
1417         u32 val = I915_READ(reg);
1418         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1419              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1420              reg, pipe_name(pipe));
1421
1422         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1423              && (val & DP_PIPEB_SELECT),
1424              "IBX PCH dp port still using transcoder B\n");
1425 }
1426
1427 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1428                                      enum pipe pipe, int reg)
1429 {
1430         u32 val = I915_READ(reg);
1431         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1432              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1433              reg, pipe_name(pipe));
1434
1435         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1436              && (val & SDVO_PIPE_B_SELECT),
1437              "IBX PCH hdmi port still using transcoder B\n");
1438 }
1439
1440 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1441                                       enum pipe pipe)
1442 {
1443         int reg;
1444         u32 val;
1445
1446         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1447         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1448         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1449
1450         reg = PCH_ADPA;
1451         val = I915_READ(reg);
1452         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1453              "PCH VGA enabled on transcoder %c, should be disabled\n",
1454              pipe_name(pipe));
1455
1456         reg = PCH_LVDS;
1457         val = I915_READ(reg);
1458         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1459              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1460              pipe_name(pipe));
1461
1462         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1463         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1464         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1465 }
1466
1467 static void intel_init_dpio(struct drm_device *dev)
1468 {
1469         struct drm_i915_private *dev_priv = dev->dev_private;
1470
1471         if (!IS_VALLEYVIEW(dev))
1472                 return;
1473
1474         /*
1475          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1476          * CHV x1 PHY (DP/HDMI D)
1477          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1478          */
1479         if (IS_CHERRYVIEW(dev)) {
1480                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1481                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1482         } else {
1483                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1484         }
1485 }
1486
1487 static void vlv_enable_pll(struct intel_crtc *crtc)
1488 {
1489         struct drm_device *dev = crtc->base.dev;
1490         struct drm_i915_private *dev_priv = dev->dev_private;
1491         int reg = DPLL(crtc->pipe);
1492         u32 dpll = crtc->config.dpll_hw_state.dpll;
1493
1494         assert_pipe_disabled(dev_priv, crtc->pipe);
1495
1496         /* No really, not for ILK+ */
1497         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1498
1499         /* PLL is protected by panel, make sure we can write it */
1500         if (IS_MOBILE(dev_priv->dev))
1501                 assert_panel_unlocked(dev_priv, crtc->pipe);
1502
1503         I915_WRITE(reg, dpll);
1504         POSTING_READ(reg);
1505         udelay(150);
1506
1507         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1508                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1509
1510         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1511         POSTING_READ(DPLL_MD(crtc->pipe));
1512
1513         /* We do this three times for luck */
1514         I915_WRITE(reg, dpll);
1515         POSTING_READ(reg);
1516         udelay(150); /* wait for warmup */
1517         I915_WRITE(reg, dpll);
1518         POSTING_READ(reg);
1519         udelay(150); /* wait for warmup */
1520         I915_WRITE(reg, dpll);
1521         POSTING_READ(reg);
1522         udelay(150); /* wait for warmup */
1523 }
1524
1525 static void chv_enable_pll(struct intel_crtc *crtc)
1526 {
1527         struct drm_device *dev = crtc->base.dev;
1528         struct drm_i915_private *dev_priv = dev->dev_private;
1529         int pipe = crtc->pipe;
1530         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1531         u32 tmp;
1532
1533         assert_pipe_disabled(dev_priv, crtc->pipe);
1534
1535         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1536
1537         mutex_lock(&dev_priv->dpio_lock);
1538
1539         /* Enable back the 10bit clock to display controller */
1540         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1541         tmp |= DPIO_DCLKP_EN;
1542         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1543
1544         /*
1545          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1546          */
1547         udelay(1);
1548
1549         /* Enable PLL */
1550         I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1551
1552         /* Check PLL is locked */
1553         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1554                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1555
1556         /* not sure when this should be written */
1557         I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1558         POSTING_READ(DPLL_MD(pipe));
1559
1560         mutex_unlock(&dev_priv->dpio_lock);
1561 }
1562
1563 static int intel_num_dvo_pipes(struct drm_device *dev)
1564 {
1565         struct intel_crtc *crtc;
1566         int count = 0;
1567
1568         for_each_intel_crtc(dev, crtc)
1569                 count += crtc->active &&
1570                         intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO);
1571
1572         return count;
1573 }
1574
1575 static void i9xx_enable_pll(struct intel_crtc *crtc)
1576 {
1577         struct drm_device *dev = crtc->base.dev;
1578         struct drm_i915_private *dev_priv = dev->dev_private;
1579         int reg = DPLL(crtc->pipe);
1580         u32 dpll = crtc->config.dpll_hw_state.dpll;
1581
1582         assert_pipe_disabled(dev_priv, crtc->pipe);
1583
1584         /* No really, not for ILK+ */
1585         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1586
1587         /* PLL is protected by panel, make sure we can write it */
1588         if (IS_MOBILE(dev) && !IS_I830(dev))
1589                 assert_panel_unlocked(dev_priv, crtc->pipe);
1590
1591         /* Enable DVO 2x clock on both PLLs if necessary */
1592         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1593                 /*
1594                  * It appears to be important that we don't enable this
1595                  * for the current pipe before otherwise configuring the
1596                  * PLL. No idea how this should be handled if multiple
1597                  * DVO outputs are enabled simultaneosly.
1598                  */
1599                 dpll |= DPLL_DVO_2X_MODE;
1600                 I915_WRITE(DPLL(!crtc->pipe),
1601                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1602         }
1603
1604         /* Wait for the clocks to stabilize. */
1605         POSTING_READ(reg);
1606         udelay(150);
1607
1608         if (INTEL_INFO(dev)->gen >= 4) {
1609                 I915_WRITE(DPLL_MD(crtc->pipe),
1610                            crtc->config.dpll_hw_state.dpll_md);
1611         } else {
1612                 /* The pixel multiplier can only be updated once the
1613                  * DPLL is enabled and the clocks are stable.
1614                  *
1615                  * So write it again.
1616                  */
1617                 I915_WRITE(reg, dpll);
1618         }
1619
1620         /* We do this three times for luck */
1621         I915_WRITE(reg, dpll);
1622         POSTING_READ(reg);
1623         udelay(150); /* wait for warmup */
1624         I915_WRITE(reg, dpll);
1625         POSTING_READ(reg);
1626         udelay(150); /* wait for warmup */
1627         I915_WRITE(reg, dpll);
1628         POSTING_READ(reg);
1629         udelay(150); /* wait for warmup */
1630 }
1631
1632 /**
1633  * i9xx_disable_pll - disable a PLL
1634  * @dev_priv: i915 private structure
1635  * @pipe: pipe PLL to disable
1636  *
1637  * Disable the PLL for @pipe, making sure the pipe is off first.
1638  *
1639  * Note!  This is for pre-ILK only.
1640  */
1641 static void i9xx_disable_pll(struct intel_crtc *crtc)
1642 {
1643         struct drm_device *dev = crtc->base.dev;
1644         struct drm_i915_private *dev_priv = dev->dev_private;
1645         enum pipe pipe = crtc->pipe;
1646
1647         /* Disable DVO 2x clock on both PLLs if necessary */
1648         if (IS_I830(dev) &&
1649             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO) &&
1650             intel_num_dvo_pipes(dev) == 1) {
1651                 I915_WRITE(DPLL(PIPE_B),
1652                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1653                 I915_WRITE(DPLL(PIPE_A),
1654                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1655         }
1656
1657         /* Don't disable pipe or pipe PLLs if needed */
1658         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1659             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1660                 return;
1661
1662         /* Make sure the pipe isn't still relying on us */
1663         assert_pipe_disabled(dev_priv, pipe);
1664
1665         I915_WRITE(DPLL(pipe), 0);
1666         POSTING_READ(DPLL(pipe));
1667 }
1668
1669 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1670 {
1671         u32 val = 0;
1672
1673         /* Make sure the pipe isn't still relying on us */
1674         assert_pipe_disabled(dev_priv, pipe);
1675
1676         /*
1677          * Leave integrated clock source and reference clock enabled for pipe B.
1678          * The latter is needed for VGA hotplug / manual detection.
1679          */
1680         if (pipe == PIPE_B)
1681                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1682         I915_WRITE(DPLL(pipe), val);
1683         POSTING_READ(DPLL(pipe));
1684
1685 }
1686
1687 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1688 {
1689         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1690         u32 val;
1691
1692         /* Make sure the pipe isn't still relying on us */
1693         assert_pipe_disabled(dev_priv, pipe);
1694
1695         /* Set PLL en = 0 */
1696         val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1697         if (pipe != PIPE_A)
1698                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1699         I915_WRITE(DPLL(pipe), val);
1700         POSTING_READ(DPLL(pipe));
1701
1702         mutex_lock(&dev_priv->dpio_lock);
1703
1704         /* Disable 10bit clock to display controller */
1705         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1706         val &= ~DPIO_DCLKP_EN;
1707         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1708
1709         /* disable left/right clock distribution */
1710         if (pipe != PIPE_B) {
1711                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1712                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1713                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1714         } else {
1715                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1716                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1717                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1718         }
1719
1720         mutex_unlock(&dev_priv->dpio_lock);
1721 }
1722
1723 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1724                 struct intel_digital_port *dport)
1725 {
1726         u32 port_mask;
1727         int dpll_reg;
1728
1729         switch (dport->port) {
1730         case PORT_B:
1731                 port_mask = DPLL_PORTB_READY_MASK;
1732                 dpll_reg = DPLL(0);
1733                 break;
1734         case PORT_C:
1735                 port_mask = DPLL_PORTC_READY_MASK;
1736                 dpll_reg = DPLL(0);
1737                 break;
1738         case PORT_D:
1739                 port_mask = DPLL_PORTD_READY_MASK;
1740                 dpll_reg = DPIO_PHY_STATUS;
1741                 break;
1742         default:
1743                 BUG();
1744         }
1745
1746         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1747                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1748                      port_name(dport->port), I915_READ(dpll_reg));
1749 }
1750
1751 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1752 {
1753         struct drm_device *dev = crtc->base.dev;
1754         struct drm_i915_private *dev_priv = dev->dev_private;
1755         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1756
1757         if (WARN_ON(pll == NULL))
1758                 return;
1759
1760         WARN_ON(!pll->refcount);
1761         if (pll->active == 0) {
1762                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1763                 WARN_ON(pll->on);
1764                 assert_shared_dpll_disabled(dev_priv, pll);
1765
1766                 pll->mode_set(dev_priv, pll);
1767         }
1768 }
1769
1770 /**
1771  * intel_enable_shared_dpll - enable PCH PLL
1772  * @dev_priv: i915 private structure
1773  * @pipe: pipe PLL to enable
1774  *
1775  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1776  * drives the transcoder clock.
1777  */
1778 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1779 {
1780         struct drm_device *dev = crtc->base.dev;
1781         struct drm_i915_private *dev_priv = dev->dev_private;
1782         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1783
1784         if (WARN_ON(pll == NULL))
1785                 return;
1786
1787         if (WARN_ON(pll->refcount == 0))
1788                 return;
1789
1790         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1791                       pll->name, pll->active, pll->on,
1792                       crtc->base.base.id);
1793
1794         if (pll->active++) {
1795                 WARN_ON(!pll->on);
1796                 assert_shared_dpll_enabled(dev_priv, pll);
1797                 return;
1798         }
1799         WARN_ON(pll->on);
1800
1801         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1802
1803         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1804         pll->enable(dev_priv, pll);
1805         pll->on = true;
1806 }
1807
1808 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1809 {
1810         struct drm_device *dev = crtc->base.dev;
1811         struct drm_i915_private *dev_priv = dev->dev_private;
1812         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1813
1814         /* PCH only available on ILK+ */
1815         BUG_ON(INTEL_INFO(dev)->gen < 5);
1816         if (WARN_ON(pll == NULL))
1817                return;
1818
1819         if (WARN_ON(pll->refcount == 0))
1820                 return;
1821
1822         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1823                       pll->name, pll->active, pll->on,
1824                       crtc->base.base.id);
1825
1826         if (WARN_ON(pll->active == 0)) {
1827                 assert_shared_dpll_disabled(dev_priv, pll);
1828                 return;
1829         }
1830
1831         assert_shared_dpll_enabled(dev_priv, pll);
1832         WARN_ON(!pll->on);
1833         if (--pll->active)
1834                 return;
1835
1836         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1837         pll->disable(dev_priv, pll);
1838         pll->on = false;
1839
1840         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1841 }
1842
1843 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1844                                            enum pipe pipe)
1845 {
1846         struct drm_device *dev = dev_priv->dev;
1847         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1848         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1849         uint32_t reg, val, pipeconf_val;
1850
1851         /* PCH only available on ILK+ */
1852         BUG_ON(!HAS_PCH_SPLIT(dev));
1853
1854         /* Make sure PCH DPLL is enabled */
1855         assert_shared_dpll_enabled(dev_priv,
1856                                    intel_crtc_to_shared_dpll(intel_crtc));
1857
1858         /* FDI must be feeding us bits for PCH ports */
1859         assert_fdi_tx_enabled(dev_priv, pipe);
1860         assert_fdi_rx_enabled(dev_priv, pipe);
1861
1862         if (HAS_PCH_CPT(dev)) {
1863                 /* Workaround: Set the timing override bit before enabling the
1864                  * pch transcoder. */
1865                 reg = TRANS_CHICKEN2(pipe);
1866                 val = I915_READ(reg);
1867                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1868                 I915_WRITE(reg, val);
1869         }
1870
1871         reg = PCH_TRANSCONF(pipe);
1872         val = I915_READ(reg);
1873         pipeconf_val = I915_READ(PIPECONF(pipe));
1874
1875         if (HAS_PCH_IBX(dev_priv->dev)) {
1876                 /*
1877                  * make the BPC in transcoder be consistent with
1878                  * that in pipeconf reg.
1879                  */
1880                 val &= ~PIPECONF_BPC_MASK;
1881                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1882         }
1883
1884         val &= ~TRANS_INTERLACE_MASK;
1885         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1886                 if (HAS_PCH_IBX(dev_priv->dev) &&
1887                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1888                         val |= TRANS_LEGACY_INTERLACED_ILK;
1889                 else
1890                         val |= TRANS_INTERLACED;
1891         else
1892                 val |= TRANS_PROGRESSIVE;
1893
1894         I915_WRITE(reg, val | TRANS_ENABLE);
1895         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1896                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1897 }
1898
1899 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1900                                       enum transcoder cpu_transcoder)
1901 {
1902         u32 val, pipeconf_val;
1903
1904         /* PCH only available on ILK+ */
1905         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1906
1907         /* FDI must be feeding us bits for PCH ports */
1908         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1909         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1910
1911         /* Workaround: set timing override bit. */
1912         val = I915_READ(_TRANSA_CHICKEN2);
1913         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1914         I915_WRITE(_TRANSA_CHICKEN2, val);
1915
1916         val = TRANS_ENABLE;
1917         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1918
1919         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1920             PIPECONF_INTERLACED_ILK)
1921                 val |= TRANS_INTERLACED;
1922         else
1923                 val |= TRANS_PROGRESSIVE;
1924
1925         I915_WRITE(LPT_TRANSCONF, val);
1926         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1927                 DRM_ERROR("Failed to enable PCH transcoder\n");
1928 }
1929
1930 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1931                                             enum pipe pipe)
1932 {
1933         struct drm_device *dev = dev_priv->dev;
1934         uint32_t reg, val;
1935
1936         /* FDI relies on the transcoder */
1937         assert_fdi_tx_disabled(dev_priv, pipe);
1938         assert_fdi_rx_disabled(dev_priv, pipe);
1939
1940         /* Ports must be off as well */
1941         assert_pch_ports_disabled(dev_priv, pipe);
1942
1943         reg = PCH_TRANSCONF(pipe);
1944         val = I915_READ(reg);
1945         val &= ~TRANS_ENABLE;
1946         I915_WRITE(reg, val);
1947         /* wait for PCH transcoder off, transcoder state */
1948         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1949                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1950
1951         if (!HAS_PCH_IBX(dev)) {
1952                 /* Workaround: Clear the timing override chicken bit again. */
1953                 reg = TRANS_CHICKEN2(pipe);
1954                 val = I915_READ(reg);
1955                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1956                 I915_WRITE(reg, val);
1957         }
1958 }
1959
1960 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1961 {
1962         u32 val;
1963
1964         val = I915_READ(LPT_TRANSCONF);
1965         val &= ~TRANS_ENABLE;
1966         I915_WRITE(LPT_TRANSCONF, val);
1967         /* wait for PCH transcoder off, transcoder state */
1968         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1969                 DRM_ERROR("Failed to disable PCH transcoder\n");
1970
1971         /* Workaround: clear timing override bit. */
1972         val = I915_READ(_TRANSA_CHICKEN2);
1973         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1974         I915_WRITE(_TRANSA_CHICKEN2, val);
1975 }
1976
1977 /**
1978  * intel_enable_pipe - enable a pipe, asserting requirements
1979  * @crtc: crtc responsible for the pipe
1980  *
1981  * Enable @crtc's pipe, making sure that various hardware specific requirements
1982  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1983  */
1984 static void intel_enable_pipe(struct intel_crtc *crtc)
1985 {
1986         struct drm_device *dev = crtc->base.dev;
1987         struct drm_i915_private *dev_priv = dev->dev_private;
1988         enum pipe pipe = crtc->pipe;
1989         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1990                                                                       pipe);
1991         enum pipe pch_transcoder;
1992         int reg;
1993         u32 val;
1994
1995         assert_planes_disabled(dev_priv, pipe);
1996         assert_cursor_disabled(dev_priv, pipe);
1997         assert_sprites_disabled(dev_priv, pipe);
1998
1999         if (HAS_PCH_LPT(dev_priv->dev))
2000                 pch_transcoder = TRANSCODER_A;
2001         else
2002                 pch_transcoder = pipe;
2003
2004         /*
2005          * A pipe without a PLL won't actually be able to drive bits from
2006          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2007          * need the check.
2008          */
2009         if (!HAS_PCH_SPLIT(dev_priv->dev))
2010                 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
2011                         assert_dsi_pll_enabled(dev_priv);
2012                 else
2013                         assert_pll_enabled(dev_priv, pipe);
2014         else {
2015                 if (crtc->config.has_pch_encoder) {
2016                         /* if driving the PCH, we need FDI enabled */
2017                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2018                         assert_fdi_tx_pll_enabled(dev_priv,
2019                                                   (enum pipe) cpu_transcoder);
2020                 }
2021                 /* FIXME: assert CPU port conditions for SNB+ */
2022         }
2023
2024         reg = PIPECONF(cpu_transcoder);
2025         val = I915_READ(reg);
2026         if (val & PIPECONF_ENABLE) {
2027                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2028                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2029                 return;
2030         }
2031
2032         I915_WRITE(reg, val | PIPECONF_ENABLE);
2033         POSTING_READ(reg);
2034 }
2035
2036 /**
2037  * intel_disable_pipe - disable a pipe, asserting requirements
2038  * @crtc: crtc whose pipes is to be disabled
2039  *
2040  * Disable the pipe of @crtc, making sure that various hardware
2041  * specific requirements are met, if applicable, e.g. plane
2042  * disabled, panel fitter off, etc.
2043  *
2044  * Will wait until the pipe has shut down before returning.
2045  */
2046 static void intel_disable_pipe(struct intel_crtc *crtc)
2047 {
2048         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2049         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2050         enum pipe pipe = crtc->pipe;
2051         int reg;
2052         u32 val;
2053
2054         /*
2055          * Make sure planes won't keep trying to pump pixels to us,
2056          * or we might hang the display.
2057          */
2058         assert_planes_disabled(dev_priv, pipe);
2059         assert_cursor_disabled(dev_priv, pipe);
2060         assert_sprites_disabled(dev_priv, pipe);
2061
2062         reg = PIPECONF(cpu_transcoder);
2063         val = I915_READ(reg);
2064         if ((val & PIPECONF_ENABLE) == 0)
2065                 return;
2066
2067         /*
2068          * Double wide has implications for planes
2069          * so best keep it disabled when not needed.
2070          */
2071         if (crtc->config.double_wide)
2072                 val &= ~PIPECONF_DOUBLE_WIDE;
2073
2074         /* Don't disable pipe or pipe PLLs if needed */
2075         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2076             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2077                 val &= ~PIPECONF_ENABLE;
2078
2079         I915_WRITE(reg, val);
2080         if ((val & PIPECONF_ENABLE) == 0)
2081                 intel_wait_for_pipe_off(crtc);
2082 }
2083
2084 /*
2085  * Plane regs are double buffered, going from enabled->disabled needs a
2086  * trigger in order to latch.  The display address reg provides this.
2087  */
2088 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2089                                enum plane plane)
2090 {
2091         struct drm_device *dev = dev_priv->dev;
2092         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2093
2094         I915_WRITE(reg, I915_READ(reg));
2095         POSTING_READ(reg);
2096 }
2097
2098 /**
2099  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2100  * @plane:  plane to be enabled
2101  * @crtc: crtc for the plane
2102  *
2103  * Enable @plane on @crtc, making sure that the pipe is running first.
2104  */
2105 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2106                                           struct drm_crtc *crtc)
2107 {
2108         struct drm_device *dev = plane->dev;
2109         struct drm_i915_private *dev_priv = dev->dev_private;
2110         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2111
2112         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2113         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2114
2115         if (intel_crtc->primary_enabled)
2116                 return;
2117
2118         intel_crtc->primary_enabled = true;
2119
2120         dev_priv->display.update_primary_plane(crtc, plane->fb,
2121                                                crtc->x, crtc->y);
2122
2123         /*
2124          * BDW signals flip done immediately if the plane
2125          * is disabled, even if the plane enable is already
2126          * armed to occur at the next vblank :(
2127          */
2128         if (IS_BROADWELL(dev))
2129                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2130 }
2131
2132 /**
2133  * intel_disable_primary_hw_plane - disable the primary hardware plane
2134  * @plane: plane to be disabled
2135  * @crtc: crtc for the plane
2136  *
2137  * Disable @plane on @crtc, making sure that the pipe is running first.
2138  */
2139 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2140                                            struct drm_crtc *crtc)
2141 {
2142         struct drm_device *dev = plane->dev;
2143         struct drm_i915_private *dev_priv = dev->dev_private;
2144         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2145
2146         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2147
2148         if (!intel_crtc->primary_enabled)
2149                 return;
2150
2151         intel_crtc->primary_enabled = false;
2152
2153         dev_priv->display.update_primary_plane(crtc, plane->fb,
2154                                                crtc->x, crtc->y);
2155 }
2156
2157 static bool need_vtd_wa(struct drm_device *dev)
2158 {
2159 #ifdef CONFIG_INTEL_IOMMU
2160         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2161                 return true;
2162 #endif
2163         return false;
2164 }
2165
2166 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2167 {
2168         int tile_height;
2169
2170         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2171         return ALIGN(height, tile_height);
2172 }
2173
2174 int
2175 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2176                            struct drm_i915_gem_object *obj,
2177                            struct intel_engine_cs *pipelined)
2178 {
2179         struct drm_i915_private *dev_priv = dev->dev_private;
2180         u32 alignment;
2181         int ret;
2182
2183         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2184
2185         switch (obj->tiling_mode) {
2186         case I915_TILING_NONE:
2187                 if (INTEL_INFO(dev)->gen >= 9)
2188                         alignment = 256 * 1024;
2189                 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2190                         alignment = 128 * 1024;
2191                 else if (INTEL_INFO(dev)->gen >= 4)
2192                         alignment = 4 * 1024;
2193                 else
2194                         alignment = 64 * 1024;
2195                 break;
2196         case I915_TILING_X:
2197                 if (INTEL_INFO(dev)->gen >= 9)
2198                         alignment = 256 * 1024;
2199                 else {
2200                         /* pin() will align the object as required by fence */
2201                         alignment = 0;
2202                 }
2203                 break;
2204         case I915_TILING_Y:
2205                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2206                 return -EINVAL;
2207         default:
2208                 BUG();
2209         }
2210
2211         /* Note that the w/a also requires 64 PTE of padding following the
2212          * bo. We currently fill all unused PTE with the shadow page and so
2213          * we should always have valid PTE following the scanout preventing
2214          * the VT-d warning.
2215          */
2216         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2217                 alignment = 256 * 1024;
2218
2219         /*
2220          * Global gtt pte registers are special registers which actually forward
2221          * writes to a chunk of system memory. Which means that there is no risk
2222          * that the register values disappear as soon as we call
2223          * intel_runtime_pm_put(), so it is correct to wrap only the
2224          * pin/unpin/fence and not more.
2225          */
2226         intel_runtime_pm_get(dev_priv);
2227
2228         dev_priv->mm.interruptible = false;
2229         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2230         if (ret)
2231                 goto err_interruptible;
2232
2233         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2234          * fence, whereas 965+ only requires a fence if using
2235          * framebuffer compression.  For simplicity, we always install
2236          * a fence as the cost is not that onerous.
2237          */
2238         ret = i915_gem_object_get_fence(obj);
2239         if (ret)
2240                 goto err_unpin;
2241
2242         i915_gem_object_pin_fence(obj);
2243
2244         dev_priv->mm.interruptible = true;
2245         intel_runtime_pm_put(dev_priv);
2246         return 0;
2247
2248 err_unpin:
2249         i915_gem_object_unpin_from_display_plane(obj);
2250 err_interruptible:
2251         dev_priv->mm.interruptible = true;
2252         intel_runtime_pm_put(dev_priv);
2253         return ret;
2254 }
2255
2256 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2257 {
2258         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2259
2260         i915_gem_object_unpin_fence(obj);
2261         i915_gem_object_unpin_from_display_plane(obj);
2262 }
2263
2264 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2265  * is assumed to be a power-of-two. */
2266 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2267                                              unsigned int tiling_mode,
2268                                              unsigned int cpp,
2269                                              unsigned int pitch)
2270 {
2271         if (tiling_mode != I915_TILING_NONE) {
2272                 unsigned int tile_rows, tiles;
2273
2274                 tile_rows = *y / 8;
2275                 *y %= 8;
2276
2277                 tiles = *x / (512/cpp);
2278                 *x %= 512/cpp;
2279
2280                 return tile_rows * pitch * 8 + tiles * 4096;
2281         } else {
2282                 unsigned int offset;
2283
2284                 offset = *y * pitch + *x * cpp;
2285                 *y = 0;
2286                 *x = (offset & 4095) / cpp;
2287                 return offset & -4096;
2288         }
2289 }
2290
2291 int intel_format_to_fourcc(int format)
2292 {
2293         switch (format) {
2294         case DISPPLANE_8BPP:
2295                 return DRM_FORMAT_C8;
2296         case DISPPLANE_BGRX555:
2297                 return DRM_FORMAT_XRGB1555;
2298         case DISPPLANE_BGRX565:
2299                 return DRM_FORMAT_RGB565;
2300         default:
2301         case DISPPLANE_BGRX888:
2302                 return DRM_FORMAT_XRGB8888;
2303         case DISPPLANE_RGBX888:
2304                 return DRM_FORMAT_XBGR8888;
2305         case DISPPLANE_BGRX101010:
2306                 return DRM_FORMAT_XRGB2101010;
2307         case DISPPLANE_RGBX101010:
2308                 return DRM_FORMAT_XBGR2101010;
2309         }
2310 }
2311
2312 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2313                                   struct intel_plane_config *plane_config)
2314 {
2315         struct drm_device *dev = crtc->base.dev;
2316         struct drm_i915_gem_object *obj = NULL;
2317         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2318         u32 base = plane_config->base;
2319
2320         if (plane_config->size == 0)
2321                 return false;
2322
2323         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2324                                                              plane_config->size);
2325         if (!obj)
2326                 return false;
2327
2328         if (plane_config->tiled) {
2329                 obj->tiling_mode = I915_TILING_X;
2330                 obj->stride = crtc->base.primary->fb->pitches[0];
2331         }
2332
2333         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2334         mode_cmd.width = crtc->base.primary->fb->width;
2335         mode_cmd.height = crtc->base.primary->fb->height;
2336         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2337
2338         mutex_lock(&dev->struct_mutex);
2339
2340         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2341                                    &mode_cmd, obj)) {
2342                 DRM_DEBUG_KMS("intel fb init failed\n");
2343                 goto out_unref_obj;
2344         }
2345
2346         obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2347         mutex_unlock(&dev->struct_mutex);
2348
2349         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2350         return true;
2351
2352 out_unref_obj:
2353         drm_gem_object_unreference(&obj->base);
2354         mutex_unlock(&dev->struct_mutex);
2355         return false;
2356 }
2357
2358 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2359                                  struct intel_plane_config *plane_config)
2360 {
2361         struct drm_device *dev = intel_crtc->base.dev;
2362         struct drm_crtc *c;
2363         struct intel_crtc *i;
2364         struct drm_i915_gem_object *obj;
2365
2366         if (!intel_crtc->base.primary->fb)
2367                 return;
2368
2369         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2370                 return;
2371
2372         kfree(intel_crtc->base.primary->fb);
2373         intel_crtc->base.primary->fb = NULL;
2374
2375         /*
2376          * Failed to alloc the obj, check to see if we should share
2377          * an fb with another CRTC instead
2378          */
2379         for_each_crtc(dev, c) {
2380                 i = to_intel_crtc(c);
2381
2382                 if (c == &intel_crtc->base)
2383                         continue;
2384
2385                 if (!i->active)
2386                         continue;
2387
2388                 obj = intel_fb_obj(c->primary->fb);
2389                 if (obj == NULL)
2390                         continue;
2391
2392                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2393                         drm_framebuffer_reference(c->primary->fb);
2394                         intel_crtc->base.primary->fb = c->primary->fb;
2395                         obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2396                         break;
2397                 }
2398         }
2399 }
2400
2401 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2402                                       struct drm_framebuffer *fb,
2403                                       int x, int y)
2404 {
2405         struct drm_device *dev = crtc->dev;
2406         struct drm_i915_private *dev_priv = dev->dev_private;
2407         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2408         struct drm_i915_gem_object *obj;
2409         int plane = intel_crtc->plane;
2410         unsigned long linear_offset;
2411         u32 dspcntr;
2412         u32 reg = DSPCNTR(plane);
2413         int pixel_size;
2414
2415         if (!intel_crtc->primary_enabled) {
2416                 I915_WRITE(reg, 0);
2417                 if (INTEL_INFO(dev)->gen >= 4)
2418                         I915_WRITE(DSPSURF(plane), 0);
2419                 else
2420                         I915_WRITE(DSPADDR(plane), 0);
2421                 POSTING_READ(reg);
2422                 return;
2423         }
2424
2425         obj = intel_fb_obj(fb);
2426         if (WARN_ON(obj == NULL))
2427                 return;
2428
2429         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2430
2431         dspcntr = DISPPLANE_GAMMA_ENABLE;
2432
2433         dspcntr |= DISPLAY_PLANE_ENABLE;
2434
2435         if (INTEL_INFO(dev)->gen < 4) {
2436                 if (intel_crtc->pipe == PIPE_B)
2437                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2438
2439                 /* pipesrc and dspsize control the size that is scaled from,
2440                  * which should always be the user's requested size.
2441                  */
2442                 I915_WRITE(DSPSIZE(plane),
2443                            ((intel_crtc->config.pipe_src_h - 1) << 16) |
2444                            (intel_crtc->config.pipe_src_w - 1));
2445                 I915_WRITE(DSPPOS(plane), 0);
2446         }
2447
2448         switch (fb->pixel_format) {
2449         case DRM_FORMAT_C8:
2450                 dspcntr |= DISPPLANE_8BPP;
2451                 break;
2452         case DRM_FORMAT_XRGB1555:
2453         case DRM_FORMAT_ARGB1555:
2454                 dspcntr |= DISPPLANE_BGRX555;
2455                 break;
2456         case DRM_FORMAT_RGB565:
2457                 dspcntr |= DISPPLANE_BGRX565;
2458                 break;
2459         case DRM_FORMAT_XRGB8888:
2460         case DRM_FORMAT_ARGB8888:
2461                 dspcntr |= DISPPLANE_BGRX888;
2462                 break;
2463         case DRM_FORMAT_XBGR8888:
2464         case DRM_FORMAT_ABGR8888:
2465                 dspcntr |= DISPPLANE_RGBX888;
2466                 break;
2467         case DRM_FORMAT_XRGB2101010:
2468         case DRM_FORMAT_ARGB2101010:
2469                 dspcntr |= DISPPLANE_BGRX101010;
2470                 break;
2471         case DRM_FORMAT_XBGR2101010:
2472         case DRM_FORMAT_ABGR2101010:
2473                 dspcntr |= DISPPLANE_RGBX101010;
2474                 break;
2475         default:
2476                 BUG();
2477         }
2478
2479         if (INTEL_INFO(dev)->gen >= 4 &&
2480             obj->tiling_mode != I915_TILING_NONE)
2481                 dspcntr |= DISPPLANE_TILED;
2482
2483         if (IS_G4X(dev))
2484                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2485
2486         linear_offset = y * fb->pitches[0] + x * pixel_size;
2487
2488         if (INTEL_INFO(dev)->gen >= 4) {
2489                 intel_crtc->dspaddr_offset =
2490                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2491                                                        pixel_size,
2492                                                        fb->pitches[0]);
2493                 linear_offset -= intel_crtc->dspaddr_offset;
2494         } else {
2495                 intel_crtc->dspaddr_offset = linear_offset;
2496         }
2497
2498         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2499                 dspcntr |= DISPPLANE_ROTATE_180;
2500
2501                 x += (intel_crtc->config.pipe_src_w - 1);
2502                 y += (intel_crtc->config.pipe_src_h - 1);
2503
2504                 /* Finding the last pixel of the last line of the display
2505                 data and adding to linear_offset*/
2506                 linear_offset +=
2507                         (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2508                         (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2509         }
2510
2511         I915_WRITE(reg, dspcntr);
2512
2513         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2514                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2515                       fb->pitches[0]);
2516         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2517         if (INTEL_INFO(dev)->gen >= 4) {
2518                 I915_WRITE(DSPSURF(plane),
2519                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2520                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2521                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2522         } else
2523                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2524         POSTING_READ(reg);
2525 }
2526
2527 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2528                                           struct drm_framebuffer *fb,
2529                                           int x, int y)
2530 {
2531         struct drm_device *dev = crtc->dev;
2532         struct drm_i915_private *dev_priv = dev->dev_private;
2533         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2534         struct drm_i915_gem_object *obj;
2535         int plane = intel_crtc->plane;
2536         unsigned long linear_offset;
2537         u32 dspcntr;
2538         u32 reg = DSPCNTR(plane);
2539         int pixel_size;
2540
2541         if (!intel_crtc->primary_enabled) {
2542                 I915_WRITE(reg, 0);
2543                 I915_WRITE(DSPSURF(plane), 0);
2544                 POSTING_READ(reg);
2545                 return;
2546         }
2547
2548         obj = intel_fb_obj(fb);
2549         if (WARN_ON(obj == NULL))
2550                 return;
2551
2552         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2553
2554         dspcntr = DISPPLANE_GAMMA_ENABLE;
2555
2556         dspcntr |= DISPLAY_PLANE_ENABLE;
2557
2558         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2559                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2560
2561         switch (fb->pixel_format) {
2562         case DRM_FORMAT_C8:
2563                 dspcntr |= DISPPLANE_8BPP;
2564                 break;
2565         case DRM_FORMAT_RGB565:
2566                 dspcntr |= DISPPLANE_BGRX565;
2567                 break;
2568         case DRM_FORMAT_XRGB8888:
2569         case DRM_FORMAT_ARGB8888:
2570                 dspcntr |= DISPPLANE_BGRX888;
2571                 break;
2572         case DRM_FORMAT_XBGR8888:
2573         case DRM_FORMAT_ABGR8888:
2574                 dspcntr |= DISPPLANE_RGBX888;
2575                 break;
2576         case DRM_FORMAT_XRGB2101010:
2577         case DRM_FORMAT_ARGB2101010:
2578                 dspcntr |= DISPPLANE_BGRX101010;
2579                 break;
2580         case DRM_FORMAT_XBGR2101010:
2581         case DRM_FORMAT_ABGR2101010:
2582                 dspcntr |= DISPPLANE_RGBX101010;
2583                 break;
2584         default:
2585                 BUG();
2586         }
2587
2588         if (obj->tiling_mode != I915_TILING_NONE)
2589                 dspcntr |= DISPPLANE_TILED;
2590
2591         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2592                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2593
2594         linear_offset = y * fb->pitches[0] + x * pixel_size;
2595         intel_crtc->dspaddr_offset =
2596                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2597                                                pixel_size,
2598                                                fb->pitches[0]);
2599         linear_offset -= intel_crtc->dspaddr_offset;
2600         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2601                 dspcntr |= DISPPLANE_ROTATE_180;
2602
2603                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2604                         x += (intel_crtc->config.pipe_src_w - 1);
2605                         y += (intel_crtc->config.pipe_src_h - 1);
2606
2607                         /* Finding the last pixel of the last line of the display
2608                         data and adding to linear_offset*/
2609                         linear_offset +=
2610                                 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2611                                 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2612                 }
2613         }
2614
2615         I915_WRITE(reg, dspcntr);
2616
2617         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2618                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2619                       fb->pitches[0]);
2620         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2621         I915_WRITE(DSPSURF(plane),
2622                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2623         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2624                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2625         } else {
2626                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2627                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2628         }
2629         POSTING_READ(reg);
2630 }
2631
2632 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2633                                          struct drm_framebuffer *fb,
2634                                          int x, int y)
2635 {
2636         struct drm_device *dev = crtc->dev;
2637         struct drm_i915_private *dev_priv = dev->dev_private;
2638         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2639         struct intel_framebuffer *intel_fb;
2640         struct drm_i915_gem_object *obj;
2641         int pipe = intel_crtc->pipe;
2642         u32 plane_ctl, stride;
2643
2644         if (!intel_crtc->primary_enabled) {
2645                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2646                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2647                 POSTING_READ(PLANE_CTL(pipe, 0));
2648                 return;
2649         }
2650
2651         plane_ctl = PLANE_CTL_ENABLE |
2652                     PLANE_CTL_PIPE_GAMMA_ENABLE |
2653                     PLANE_CTL_PIPE_CSC_ENABLE;
2654
2655         switch (fb->pixel_format) {
2656         case DRM_FORMAT_RGB565:
2657                 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2658                 break;
2659         case DRM_FORMAT_XRGB8888:
2660                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2661                 break;
2662         case DRM_FORMAT_XBGR8888:
2663                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2664                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2665                 break;
2666         case DRM_FORMAT_XRGB2101010:
2667                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2668                 break;
2669         case DRM_FORMAT_XBGR2101010:
2670                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2671                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2672                 break;
2673         default:
2674                 BUG();
2675         }
2676
2677         intel_fb = to_intel_framebuffer(fb);
2678         obj = intel_fb->obj;
2679
2680         /*
2681          * The stride is either expressed as a multiple of 64 bytes chunks for
2682          * linear buffers or in number of tiles for tiled buffers.
2683          */
2684         switch (obj->tiling_mode) {
2685         case I915_TILING_NONE:
2686                 stride = fb->pitches[0] >> 6;
2687                 break;
2688         case I915_TILING_X:
2689                 plane_ctl |= PLANE_CTL_TILED_X;
2690                 stride = fb->pitches[0] >> 9;
2691                 break;
2692         default:
2693                 BUG();
2694         }
2695
2696         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2697
2698         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2699
2700         DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2701                       i915_gem_obj_ggtt_offset(obj),
2702                       x, y, fb->width, fb->height,
2703                       fb->pitches[0]);
2704
2705         I915_WRITE(PLANE_POS(pipe, 0), 0);
2706         I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2707         I915_WRITE(PLANE_SIZE(pipe, 0),
2708                    (intel_crtc->config.pipe_src_h - 1) << 16 |
2709                    (intel_crtc->config.pipe_src_w - 1));
2710         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2711         I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2712
2713         POSTING_READ(PLANE_SURF(pipe, 0));
2714 }
2715
2716 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2717 static int
2718 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2719                            int x, int y, enum mode_set_atomic state)
2720 {
2721         struct drm_device *dev = crtc->dev;
2722         struct drm_i915_private *dev_priv = dev->dev_private;
2723
2724         if (dev_priv->display.disable_fbc)
2725                 dev_priv->display.disable_fbc(dev);
2726
2727         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2728
2729         return 0;
2730 }
2731
2732 void intel_display_handle_reset(struct drm_device *dev)
2733 {
2734         struct drm_i915_private *dev_priv = dev->dev_private;
2735         struct drm_crtc *crtc;
2736
2737         /*
2738          * Flips in the rings have been nuked by the reset,
2739          * so complete all pending flips so that user space
2740          * will get its events and not get stuck.
2741          *
2742          * Also update the base address of all primary
2743          * planes to the the last fb to make sure we're
2744          * showing the correct fb after a reset.
2745          *
2746          * Need to make two loops over the crtcs so that we
2747          * don't try to grab a crtc mutex before the
2748          * pending_flip_queue really got woken up.
2749          */
2750
2751         for_each_crtc(dev, crtc) {
2752                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2753                 enum plane plane = intel_crtc->plane;
2754
2755                 intel_prepare_page_flip(dev, plane);
2756                 intel_finish_page_flip_plane(dev, plane);
2757         }
2758
2759         for_each_crtc(dev, crtc) {
2760                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2761
2762                 drm_modeset_lock(&crtc->mutex, NULL);
2763                 /*
2764                  * FIXME: Once we have proper support for primary planes (and
2765                  * disabling them without disabling the entire crtc) allow again
2766                  * a NULL crtc->primary->fb.
2767                  */
2768                 if (intel_crtc->active && crtc->primary->fb)
2769                         dev_priv->display.update_primary_plane(crtc,
2770                                                                crtc->primary->fb,
2771                                                                crtc->x,
2772                                                                crtc->y);
2773                 drm_modeset_unlock(&crtc->mutex);
2774         }
2775 }
2776
2777 static int
2778 intel_finish_fb(struct drm_framebuffer *old_fb)
2779 {
2780         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2781         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2782         bool was_interruptible = dev_priv->mm.interruptible;
2783         int ret;
2784
2785         /* Big Hammer, we also need to ensure that any pending
2786          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2787          * current scanout is retired before unpinning the old
2788          * framebuffer.
2789          *
2790          * This should only fail upon a hung GPU, in which case we
2791          * can safely continue.
2792          */
2793         dev_priv->mm.interruptible = false;
2794         ret = i915_gem_object_finish_gpu(obj);
2795         dev_priv->mm.interruptible = was_interruptible;
2796
2797         return ret;
2798 }
2799
2800 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2801 {
2802         struct drm_device *dev = crtc->dev;
2803         struct drm_i915_private *dev_priv = dev->dev_private;
2804         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2805         bool pending;
2806
2807         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2808             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2809                 return false;
2810
2811         spin_lock_irq(&dev->event_lock);
2812         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2813         spin_unlock_irq(&dev->event_lock);
2814
2815         return pending;
2816 }
2817
2818 static void intel_update_pipe_size(struct intel_crtc *crtc)
2819 {
2820         struct drm_device *dev = crtc->base.dev;
2821         struct drm_i915_private *dev_priv = dev->dev_private;
2822         const struct drm_display_mode *adjusted_mode;
2823
2824         if (!i915.fastboot)
2825                 return;
2826
2827         /*
2828          * Update pipe size and adjust fitter if needed: the reason for this is
2829          * that in compute_mode_changes we check the native mode (not the pfit
2830          * mode) to see if we can flip rather than do a full mode set. In the
2831          * fastboot case, we'll flip, but if we don't update the pipesrc and
2832          * pfit state, we'll end up with a big fb scanned out into the wrong
2833          * sized surface.
2834          *
2835          * To fix this properly, we need to hoist the checks up into
2836          * compute_mode_changes (or above), check the actual pfit state and
2837          * whether the platform allows pfit disable with pipe active, and only
2838          * then update the pipesrc and pfit state, even on the flip path.
2839          */
2840
2841         adjusted_mode = &crtc->config.adjusted_mode;
2842
2843         I915_WRITE(PIPESRC(crtc->pipe),
2844                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2845                    (adjusted_mode->crtc_vdisplay - 1));
2846         if (!crtc->config.pch_pfit.enabled &&
2847             (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) ||
2848              intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))) {
2849                 I915_WRITE(PF_CTL(crtc->pipe), 0);
2850                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
2851                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
2852         }
2853         crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2854         crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2855 }
2856
2857 static int
2858 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2859                     struct drm_framebuffer *fb)
2860 {
2861         struct drm_device *dev = crtc->dev;
2862         struct drm_i915_private *dev_priv = dev->dev_private;
2863         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2864         enum pipe pipe = intel_crtc->pipe;
2865         struct drm_framebuffer *old_fb = crtc->primary->fb;
2866         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2867         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2868         int ret;
2869
2870         if (intel_crtc_has_pending_flip(crtc)) {
2871                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2872                 return -EBUSY;
2873         }
2874
2875         /* no fb bound */
2876         if (!fb) {
2877                 DRM_ERROR("No FB bound\n");
2878                 return 0;
2879         }
2880
2881         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2882                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2883                           plane_name(intel_crtc->plane),
2884                           INTEL_INFO(dev)->num_pipes);
2885                 return -EINVAL;
2886         }
2887
2888         mutex_lock(&dev->struct_mutex);
2889         ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2890         if (ret == 0)
2891                 i915_gem_track_fb(old_obj, obj,
2892                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
2893         mutex_unlock(&dev->struct_mutex);
2894         if (ret != 0) {
2895                 DRM_ERROR("pin & fence failed\n");
2896                 return ret;
2897         }
2898
2899         intel_update_pipe_size(intel_crtc);
2900
2901         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2902
2903         if (intel_crtc->active)
2904                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2905
2906         crtc->primary->fb = fb;
2907         crtc->x = x;
2908         crtc->y = y;
2909
2910         if (old_fb) {
2911                 if (intel_crtc->active && old_fb != fb)
2912                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2913                 mutex_lock(&dev->struct_mutex);
2914                 intel_unpin_fb_obj(old_obj);
2915                 mutex_unlock(&dev->struct_mutex);
2916         }
2917
2918         mutex_lock(&dev->struct_mutex);
2919         intel_update_fbc(dev);
2920         mutex_unlock(&dev->struct_mutex);
2921
2922         return 0;
2923 }
2924
2925 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2926 {
2927         struct drm_device *dev = crtc->dev;
2928         struct drm_i915_private *dev_priv = dev->dev_private;
2929         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2930         int pipe = intel_crtc->pipe;
2931         u32 reg, temp;
2932
2933         /* enable normal train */
2934         reg = FDI_TX_CTL(pipe);
2935         temp = I915_READ(reg);
2936         if (IS_IVYBRIDGE(dev)) {
2937                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2938                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2939         } else {
2940                 temp &= ~FDI_LINK_TRAIN_NONE;
2941                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2942         }
2943         I915_WRITE(reg, temp);
2944
2945         reg = FDI_RX_CTL(pipe);
2946         temp = I915_READ(reg);
2947         if (HAS_PCH_CPT(dev)) {
2948                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2949                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2950         } else {
2951                 temp &= ~FDI_LINK_TRAIN_NONE;
2952                 temp |= FDI_LINK_TRAIN_NONE;
2953         }
2954         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2955
2956         /* wait one idle pattern time */
2957         POSTING_READ(reg);
2958         udelay(1000);
2959
2960         /* IVB wants error correction enabled */
2961         if (IS_IVYBRIDGE(dev))
2962                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2963                            FDI_FE_ERRC_ENABLE);
2964 }
2965
2966 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2967 {
2968         return crtc->base.enabled && crtc->active &&
2969                 crtc->config.has_pch_encoder;
2970 }
2971
2972 static void ivb_modeset_global_resources(struct drm_device *dev)
2973 {
2974         struct drm_i915_private *dev_priv = dev->dev_private;
2975         struct intel_crtc *pipe_B_crtc =
2976                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2977         struct intel_crtc *pipe_C_crtc =
2978                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2979         uint32_t temp;
2980
2981         /*
2982          * When everything is off disable fdi C so that we could enable fdi B
2983          * with all lanes. Note that we don't care about enabled pipes without
2984          * an enabled pch encoder.
2985          */
2986         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2987             !pipe_has_enabled_pch(pipe_C_crtc)) {
2988                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2989                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2990
2991                 temp = I915_READ(SOUTH_CHICKEN1);
2992                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2993                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2994                 I915_WRITE(SOUTH_CHICKEN1, temp);
2995         }
2996 }
2997
2998 /* The FDI link training functions for ILK/Ibexpeak. */
2999 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3000 {
3001         struct drm_device *dev = crtc->dev;
3002         struct drm_i915_private *dev_priv = dev->dev_private;
3003         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3004         int pipe = intel_crtc->pipe;
3005         u32 reg, temp, tries;
3006
3007         /* FDI needs bits from pipe first */
3008         assert_pipe_enabled(dev_priv, pipe);
3009
3010         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3011            for train result */
3012         reg = FDI_RX_IMR(pipe);
3013         temp = I915_READ(reg);
3014         temp &= ~FDI_RX_SYMBOL_LOCK;
3015         temp &= ~FDI_RX_BIT_LOCK;
3016         I915_WRITE(reg, temp);
3017         I915_READ(reg);
3018         udelay(150);
3019
3020         /* enable CPU FDI TX and PCH FDI RX */
3021         reg = FDI_TX_CTL(pipe);
3022         temp = I915_READ(reg);
3023         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3024         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3025         temp &= ~FDI_LINK_TRAIN_NONE;
3026         temp |= FDI_LINK_TRAIN_PATTERN_1;
3027         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3028
3029         reg = FDI_RX_CTL(pipe);
3030         temp = I915_READ(reg);
3031         temp &= ~FDI_LINK_TRAIN_NONE;
3032         temp |= FDI_LINK_TRAIN_PATTERN_1;
3033         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3034
3035         POSTING_READ(reg);
3036         udelay(150);
3037
3038         /* Ironlake workaround, enable clock pointer after FDI enable*/
3039         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3040         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3041                    FDI_RX_PHASE_SYNC_POINTER_EN);
3042
3043         reg = FDI_RX_IIR(pipe);
3044         for (tries = 0; tries < 5; tries++) {
3045                 temp = I915_READ(reg);
3046                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3047
3048                 if ((temp & FDI_RX_BIT_LOCK)) {
3049                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3050                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3051                         break;
3052                 }
3053         }
3054         if (tries == 5)
3055                 DRM_ERROR("FDI train 1 fail!\n");
3056
3057         /* Train 2 */
3058         reg = FDI_TX_CTL(pipe);
3059         temp = I915_READ(reg);
3060         temp &= ~FDI_LINK_TRAIN_NONE;
3061         temp |= FDI_LINK_TRAIN_PATTERN_2;
3062         I915_WRITE(reg, temp);
3063
3064         reg = FDI_RX_CTL(pipe);
3065         temp = I915_READ(reg);
3066         temp &= ~FDI_LINK_TRAIN_NONE;
3067         temp |= FDI_LINK_TRAIN_PATTERN_2;
3068         I915_WRITE(reg, temp);
3069
3070         POSTING_READ(reg);
3071         udelay(150);
3072
3073         reg = FDI_RX_IIR(pipe);
3074         for (tries = 0; tries < 5; tries++) {
3075                 temp = I915_READ(reg);
3076                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3077
3078                 if (temp & FDI_RX_SYMBOL_LOCK) {
3079                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3080                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3081                         break;
3082                 }
3083         }
3084         if (tries == 5)
3085                 DRM_ERROR("FDI train 2 fail!\n");
3086
3087         DRM_DEBUG_KMS("FDI train done\n");
3088
3089 }
3090
3091 static const int snb_b_fdi_train_param[] = {
3092         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3093         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3094         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3095         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3096 };
3097
3098 /* The FDI link training functions for SNB/Cougarpoint. */
3099 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3100 {
3101         struct drm_device *dev = crtc->dev;
3102         struct drm_i915_private *dev_priv = dev->dev_private;
3103         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3104         int pipe = intel_crtc->pipe;
3105         u32 reg, temp, i, retry;
3106
3107         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3108            for train result */
3109         reg = FDI_RX_IMR(pipe);
3110         temp = I915_READ(reg);
3111         temp &= ~FDI_RX_SYMBOL_LOCK;
3112         temp &= ~FDI_RX_BIT_LOCK;
3113         I915_WRITE(reg, temp);
3114
3115         POSTING_READ(reg);
3116         udelay(150);
3117
3118         /* enable CPU FDI TX and PCH FDI RX */
3119         reg = FDI_TX_CTL(pipe);
3120         temp = I915_READ(reg);
3121         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3122         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3123         temp &= ~FDI_LINK_TRAIN_NONE;
3124         temp |= FDI_LINK_TRAIN_PATTERN_1;
3125         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3126         /* SNB-B */
3127         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3128         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3129
3130         I915_WRITE(FDI_RX_MISC(pipe),
3131                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3132
3133         reg = FDI_RX_CTL(pipe);
3134         temp = I915_READ(reg);
3135         if (HAS_PCH_CPT(dev)) {
3136                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3137                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3138         } else {
3139                 temp &= ~FDI_LINK_TRAIN_NONE;
3140                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3141         }
3142         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3143
3144         POSTING_READ(reg);
3145         udelay(150);
3146
3147         for (i = 0; i < 4; i++) {
3148                 reg = FDI_TX_CTL(pipe);
3149                 temp = I915_READ(reg);
3150                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3151                 temp |= snb_b_fdi_train_param[i];
3152                 I915_WRITE(reg, temp);
3153
3154                 POSTING_READ(reg);
3155                 udelay(500);
3156
3157                 for (retry = 0; retry < 5; retry++) {
3158                         reg = FDI_RX_IIR(pipe);
3159                         temp = I915_READ(reg);
3160                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3161                         if (temp & FDI_RX_BIT_LOCK) {
3162                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3163                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3164                                 break;
3165                         }
3166                         udelay(50);
3167                 }
3168                 if (retry < 5)
3169                         break;
3170         }
3171         if (i == 4)
3172                 DRM_ERROR("FDI train 1 fail!\n");
3173
3174         /* Train 2 */
3175         reg = FDI_TX_CTL(pipe);
3176         temp = I915_READ(reg);
3177         temp &= ~FDI_LINK_TRAIN_NONE;
3178         temp |= FDI_LINK_TRAIN_PATTERN_2;
3179         if (IS_GEN6(dev)) {
3180                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3181                 /* SNB-B */
3182                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3183         }
3184         I915_WRITE(reg, temp);
3185
3186         reg = FDI_RX_CTL(pipe);
3187         temp = I915_READ(reg);
3188         if (HAS_PCH_CPT(dev)) {
3189                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3190                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3191         } else {
3192                 temp &= ~FDI_LINK_TRAIN_NONE;
3193                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3194         }
3195         I915_WRITE(reg, temp);
3196
3197         POSTING_READ(reg);
3198         udelay(150);
3199
3200         for (i = 0; i < 4; i++) {
3201                 reg = FDI_TX_CTL(pipe);
3202                 temp = I915_READ(reg);
3203                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3204                 temp |= snb_b_fdi_train_param[i];
3205                 I915_WRITE(reg, temp);
3206
3207                 POSTING_READ(reg);
3208                 udelay(500);
3209
3210                 for (retry = 0; retry < 5; retry++) {
3211                         reg = FDI_RX_IIR(pipe);
3212                         temp = I915_READ(reg);
3213                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3214                         if (temp & FDI_RX_SYMBOL_LOCK) {
3215                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3216                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3217                                 break;
3218                         }
3219                         udelay(50);
3220                 }
3221                 if (retry < 5)
3222                         break;
3223         }
3224         if (i == 4)
3225                 DRM_ERROR("FDI train 2 fail!\n");
3226
3227         DRM_DEBUG_KMS("FDI train done.\n");
3228 }
3229
3230 /* Manual link training for Ivy Bridge A0 parts */
3231 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3232 {
3233         struct drm_device *dev = crtc->dev;
3234         struct drm_i915_private *dev_priv = dev->dev_private;
3235         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3236         int pipe = intel_crtc->pipe;
3237         u32 reg, temp, i, j;
3238
3239         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3240            for train result */
3241         reg = FDI_RX_IMR(pipe);
3242         temp = I915_READ(reg);
3243         temp &= ~FDI_RX_SYMBOL_LOCK;
3244         temp &= ~FDI_RX_BIT_LOCK;
3245         I915_WRITE(reg, temp);
3246
3247         POSTING_READ(reg);
3248         udelay(150);
3249
3250         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3251                       I915_READ(FDI_RX_IIR(pipe)));
3252
3253         /* Try each vswing and preemphasis setting twice before moving on */
3254         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3255                 /* disable first in case we need to retry */
3256                 reg = FDI_TX_CTL(pipe);
3257                 temp = I915_READ(reg);
3258                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3259                 temp &= ~FDI_TX_ENABLE;
3260                 I915_WRITE(reg, temp);
3261
3262                 reg = FDI_RX_CTL(pipe);
3263                 temp = I915_READ(reg);
3264                 temp &= ~FDI_LINK_TRAIN_AUTO;
3265                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3266                 temp &= ~FDI_RX_ENABLE;
3267                 I915_WRITE(reg, temp);
3268
3269                 /* enable CPU FDI TX and PCH FDI RX */
3270                 reg = FDI_TX_CTL(pipe);
3271                 temp = I915_READ(reg);
3272                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3273                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3274                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3275                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3276                 temp |= snb_b_fdi_train_param[j/2];
3277                 temp |= FDI_COMPOSITE_SYNC;
3278                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3279
3280                 I915_WRITE(FDI_RX_MISC(pipe),
3281                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3282
3283                 reg = FDI_RX_CTL(pipe);
3284                 temp = I915_READ(reg);
3285                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3286                 temp |= FDI_COMPOSITE_SYNC;
3287                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3288
3289                 POSTING_READ(reg);
3290                 udelay(1); /* should be 0.5us */
3291
3292                 for (i = 0; i < 4; i++) {
3293                         reg = FDI_RX_IIR(pipe);
3294                         temp = I915_READ(reg);
3295                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3296
3297                         if (temp & FDI_RX_BIT_LOCK ||
3298                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3299                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3300                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3301                                               i);
3302                                 break;
3303                         }
3304                         udelay(1); /* should be 0.5us */
3305                 }
3306                 if (i == 4) {
3307                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3308                         continue;
3309                 }
3310
3311                 /* Train 2 */
3312                 reg = FDI_TX_CTL(pipe);
3313                 temp = I915_READ(reg);
3314                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3315                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3316                 I915_WRITE(reg, temp);
3317
3318                 reg = FDI_RX_CTL(pipe);
3319                 temp = I915_READ(reg);
3320                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3321                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3322                 I915_WRITE(reg, temp);
3323
3324                 POSTING_READ(reg);
3325                 udelay(2); /* should be 1.5us */
3326
3327                 for (i = 0; i < 4; i++) {
3328                         reg = FDI_RX_IIR(pipe);
3329                         temp = I915_READ(reg);
3330                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3331
3332                         if (temp & FDI_RX_SYMBOL_LOCK ||
3333                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3334                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3335                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3336                                               i);
3337                                 goto train_done;
3338                         }
3339                         udelay(2); /* should be 1.5us */
3340                 }
3341                 if (i == 4)
3342                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3343         }
3344
3345 train_done:
3346         DRM_DEBUG_KMS("FDI train done.\n");
3347 }
3348
3349 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3350 {
3351         struct drm_device *dev = intel_crtc->base.dev;
3352         struct drm_i915_private *dev_priv = dev->dev_private;
3353         int pipe = intel_crtc->pipe;
3354         u32 reg, temp;
3355
3356
3357         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3358         reg = FDI_RX_CTL(pipe);
3359         temp = I915_READ(reg);
3360         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3361         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3362         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3363         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3364
3365         POSTING_READ(reg);
3366         udelay(200);
3367
3368         /* Switch from Rawclk to PCDclk */
3369         temp = I915_READ(reg);
3370         I915_WRITE(reg, temp | FDI_PCDCLK);
3371
3372         POSTING_READ(reg);
3373         udelay(200);
3374
3375         /* Enable CPU FDI TX PLL, always on for Ironlake */
3376         reg = FDI_TX_CTL(pipe);
3377         temp = I915_READ(reg);
3378         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3379                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3380
3381                 POSTING_READ(reg);
3382                 udelay(100);
3383         }
3384 }
3385
3386 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3387 {
3388         struct drm_device *dev = intel_crtc->base.dev;
3389         struct drm_i915_private *dev_priv = dev->dev_private;
3390         int pipe = intel_crtc->pipe;
3391         u32 reg, temp;
3392
3393         /* Switch from PCDclk to Rawclk */
3394         reg = FDI_RX_CTL(pipe);
3395         temp = I915_READ(reg);
3396         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3397
3398         /* Disable CPU FDI TX PLL */
3399         reg = FDI_TX_CTL(pipe);
3400         temp = I915_READ(reg);
3401         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3402
3403         POSTING_READ(reg);
3404         udelay(100);
3405
3406         reg = FDI_RX_CTL(pipe);
3407         temp = I915_READ(reg);
3408         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3409
3410         /* Wait for the clocks to turn off. */
3411         POSTING_READ(reg);
3412         udelay(100);
3413 }
3414
3415 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3416 {
3417         struct drm_device *dev = crtc->dev;
3418         struct drm_i915_private *dev_priv = dev->dev_private;
3419         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3420         int pipe = intel_crtc->pipe;
3421         u32 reg, temp;
3422
3423         /* disable CPU FDI tx and PCH FDI rx */
3424         reg = FDI_TX_CTL(pipe);
3425         temp = I915_READ(reg);
3426         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3427         POSTING_READ(reg);
3428
3429         reg = FDI_RX_CTL(pipe);
3430         temp = I915_READ(reg);
3431         temp &= ~(0x7 << 16);
3432         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3433         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3434
3435         POSTING_READ(reg);
3436         udelay(100);
3437
3438         /* Ironlake workaround, disable clock pointer after downing FDI */
3439         if (HAS_PCH_IBX(dev))
3440                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3441
3442         /* still set train pattern 1 */
3443         reg = FDI_TX_CTL(pipe);
3444         temp = I915_READ(reg);
3445         temp &= ~FDI_LINK_TRAIN_NONE;
3446         temp |= FDI_LINK_TRAIN_PATTERN_1;
3447         I915_WRITE(reg, temp);
3448
3449         reg = FDI_RX_CTL(pipe);
3450         temp = I915_READ(reg);
3451         if (HAS_PCH_CPT(dev)) {
3452                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3453                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3454         } else {
3455                 temp &= ~FDI_LINK_TRAIN_NONE;
3456                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3457         }
3458         /* BPC in FDI rx is consistent with that in PIPECONF */
3459         temp &= ~(0x07 << 16);
3460         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3461         I915_WRITE(reg, temp);
3462
3463         POSTING_READ(reg);
3464         udelay(100);
3465 }
3466
3467 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3468 {
3469         struct intel_crtc *crtc;
3470
3471         /* Note that we don't need to be called with mode_config.lock here
3472          * as our list of CRTC objects is static for the lifetime of the
3473          * device and so cannot disappear as we iterate. Similarly, we can
3474          * happily treat the predicates as racy, atomic checks as userspace
3475          * cannot claim and pin a new fb without at least acquring the
3476          * struct_mutex and so serialising with us.
3477          */
3478         for_each_intel_crtc(dev, crtc) {
3479                 if (atomic_read(&crtc->unpin_work_count) == 0)
3480                         continue;
3481
3482                 if (crtc->unpin_work)
3483                         intel_wait_for_vblank(dev, crtc->pipe);
3484
3485                 return true;
3486         }
3487
3488         return false;
3489 }
3490
3491 static void page_flip_completed(struct intel_crtc *intel_crtc)
3492 {
3493         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3494         struct intel_unpin_work *work = intel_crtc->unpin_work;
3495
3496         /* ensure that the unpin work is consistent wrt ->pending. */
3497         smp_rmb();
3498         intel_crtc->unpin_work = NULL;
3499
3500         if (work->event)
3501                 drm_send_vblank_event(intel_crtc->base.dev,
3502                                       intel_crtc->pipe,
3503                                       work->event);
3504
3505         drm_crtc_vblank_put(&intel_crtc->base);
3506
3507         wake_up_all(&dev_priv->pending_flip_queue);
3508         queue_work(dev_priv->wq, &work->work);
3509
3510         trace_i915_flip_complete(intel_crtc->plane,
3511                                  work->pending_flip_obj);
3512 }
3513
3514 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3515 {
3516         struct drm_device *dev = crtc->dev;
3517         struct drm_i915_private *dev_priv = dev->dev_private;
3518
3519         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3520         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3521                                        !intel_crtc_has_pending_flip(crtc),
3522                                        60*HZ) == 0)) {
3523                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3524
3525                 spin_lock_irq(&dev->event_lock);
3526                 if (intel_crtc->unpin_work) {
3527                         WARN_ONCE(1, "Removing stuck page flip\n");
3528                         page_flip_completed(intel_crtc);
3529                 }
3530                 spin_unlock_irq(&dev->event_lock);
3531         }
3532
3533         if (crtc->primary->fb) {
3534                 mutex_lock(&dev->struct_mutex);
3535                 intel_finish_fb(crtc->primary->fb);
3536                 mutex_unlock(&dev->struct_mutex);
3537         }
3538 }
3539
3540 /* Program iCLKIP clock to the desired frequency */
3541 static void lpt_program_iclkip(struct drm_crtc *crtc)
3542 {
3543         struct drm_device *dev = crtc->dev;
3544         struct drm_i915_private *dev_priv = dev->dev_private;
3545         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3546         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3547         u32 temp;
3548
3549         mutex_lock(&dev_priv->dpio_lock);
3550
3551         /* It is necessary to ungate the pixclk gate prior to programming
3552          * the divisors, and gate it back when it is done.
3553          */
3554         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3555
3556         /* Disable SSCCTL */
3557         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3558                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3559                                 SBI_SSCCTL_DISABLE,
3560                         SBI_ICLK);
3561
3562         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3563         if (clock == 20000) {
3564                 auxdiv = 1;
3565                 divsel = 0x41;
3566                 phaseinc = 0x20;
3567         } else {
3568                 /* The iCLK virtual clock root frequency is in MHz,
3569                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3570                  * divisors, it is necessary to divide one by another, so we
3571                  * convert the virtual clock precision to KHz here for higher
3572                  * precision.
3573                  */
3574                 u32 iclk_virtual_root_freq = 172800 * 1000;
3575                 u32 iclk_pi_range = 64;
3576                 u32 desired_divisor, msb_divisor_value, pi_value;
3577
3578                 desired_divisor = (iclk_virtual_root_freq / clock);
3579                 msb_divisor_value = desired_divisor / iclk_pi_range;
3580                 pi_value = desired_divisor % iclk_pi_range;
3581
3582                 auxdiv = 0;
3583                 divsel = msb_divisor_value - 2;
3584                 phaseinc = pi_value;
3585         }
3586
3587         /* This should not happen with any sane values */
3588         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3589                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3590         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3591                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3592
3593         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3594                         clock,
3595                         auxdiv,
3596                         divsel,
3597                         phasedir,
3598                         phaseinc);
3599
3600         /* Program SSCDIVINTPHASE6 */
3601         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3602         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3603         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3604         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3605         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3606         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3607         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3608         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3609
3610         /* Program SSCAUXDIV */
3611         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3612         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3613         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3614         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3615
3616         /* Enable modulator and associated divider */
3617         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3618         temp &= ~SBI_SSCCTL_DISABLE;
3619         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3620
3621         /* Wait for initialization time */
3622         udelay(24);
3623
3624         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3625
3626         mutex_unlock(&dev_priv->dpio_lock);
3627 }
3628
3629 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3630                                                 enum pipe pch_transcoder)
3631 {
3632         struct drm_device *dev = crtc->base.dev;
3633         struct drm_i915_private *dev_priv = dev->dev_private;
3634         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3635
3636         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3637                    I915_READ(HTOTAL(cpu_transcoder)));
3638         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3639                    I915_READ(HBLANK(cpu_transcoder)));
3640         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3641                    I915_READ(HSYNC(cpu_transcoder)));
3642
3643         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3644                    I915_READ(VTOTAL(cpu_transcoder)));
3645         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3646                    I915_READ(VBLANK(cpu_transcoder)));
3647         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3648                    I915_READ(VSYNC(cpu_transcoder)));
3649         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3650                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3651 }
3652
3653 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3654 {
3655         struct drm_i915_private *dev_priv = dev->dev_private;
3656         uint32_t temp;
3657
3658         temp = I915_READ(SOUTH_CHICKEN1);
3659         if (temp & FDI_BC_BIFURCATION_SELECT)
3660                 return;
3661
3662         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3663         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3664
3665         temp |= FDI_BC_BIFURCATION_SELECT;
3666         DRM_DEBUG_KMS("enabling fdi C rx\n");
3667         I915_WRITE(SOUTH_CHICKEN1, temp);
3668         POSTING_READ(SOUTH_CHICKEN1);
3669 }
3670
3671 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3672 {
3673         struct drm_device *dev = intel_crtc->base.dev;
3674         struct drm_i915_private *dev_priv = dev->dev_private;
3675
3676         switch (intel_crtc->pipe) {
3677         case PIPE_A:
3678                 break;
3679         case PIPE_B:
3680                 if (intel_crtc->config.fdi_lanes > 2)
3681                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3682                 else
3683                         cpt_enable_fdi_bc_bifurcation(dev);
3684
3685                 break;
3686         case PIPE_C:
3687                 cpt_enable_fdi_bc_bifurcation(dev);
3688
3689                 break;
3690         default:
3691                 BUG();
3692         }
3693 }
3694
3695 /*
3696  * Enable PCH resources required for PCH ports:
3697  *   - PCH PLLs
3698  *   - FDI training & RX/TX
3699  *   - update transcoder timings
3700  *   - DP transcoding bits
3701  *   - transcoder
3702  */
3703 static void ironlake_pch_enable(struct drm_crtc *crtc)
3704 {
3705         struct drm_device *dev = crtc->dev;
3706         struct drm_i915_private *dev_priv = dev->dev_private;
3707         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3708         int pipe = intel_crtc->pipe;
3709         u32 reg, temp;
3710
3711         assert_pch_transcoder_disabled(dev_priv, pipe);
3712
3713         if (IS_IVYBRIDGE(dev))
3714                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3715
3716         /* Write the TU size bits before fdi link training, so that error
3717          * detection works. */
3718         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3719                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3720
3721         /* For PCH output, training FDI link */
3722         dev_priv->display.fdi_link_train(crtc);
3723
3724         /* We need to program the right clock selection before writing the pixel
3725          * mutliplier into the DPLL. */
3726         if (HAS_PCH_CPT(dev)) {
3727                 u32 sel;
3728
3729                 temp = I915_READ(PCH_DPLL_SEL);
3730                 temp |= TRANS_DPLL_ENABLE(pipe);
3731                 sel = TRANS_DPLLB_SEL(pipe);
3732                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3733                         temp |= sel;
3734                 else
3735                         temp &= ~sel;
3736                 I915_WRITE(PCH_DPLL_SEL, temp);
3737         }
3738
3739         /* XXX: pch pll's can be enabled any time before we enable the PCH
3740          * transcoder, and we actually should do this to not upset any PCH
3741          * transcoder that already use the clock when we share it.
3742          *
3743          * Note that enable_shared_dpll tries to do the right thing, but
3744          * get_shared_dpll unconditionally resets the pll - we need that to have
3745          * the right LVDS enable sequence. */
3746         intel_enable_shared_dpll(intel_crtc);
3747
3748         /* set transcoder timing, panel must allow it */
3749         assert_panel_unlocked(dev_priv, pipe);
3750         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3751
3752         intel_fdi_normal_train(crtc);
3753
3754         /* For PCH DP, enable TRANS_DP_CTL */
3755         if (HAS_PCH_CPT(dev) &&
3756             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3757              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3758                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3759                 reg = TRANS_DP_CTL(pipe);
3760                 temp = I915_READ(reg);
3761                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3762                           TRANS_DP_SYNC_MASK |
3763                           TRANS_DP_BPC_MASK);
3764                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3765                          TRANS_DP_ENH_FRAMING);
3766                 temp |= bpc << 9; /* same format but at 11:9 */
3767
3768                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3769                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3770                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3771                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3772
3773                 switch (intel_trans_dp_port_sel(crtc)) {
3774                 case PCH_DP_B:
3775                         temp |= TRANS_DP_PORT_SEL_B;
3776                         break;
3777                 case PCH_DP_C:
3778                         temp |= TRANS_DP_PORT_SEL_C;
3779                         break;
3780                 case PCH_DP_D:
3781                         temp |= TRANS_DP_PORT_SEL_D;
3782                         break;
3783                 default:
3784                         BUG();
3785                 }
3786
3787                 I915_WRITE(reg, temp);
3788         }
3789
3790         ironlake_enable_pch_transcoder(dev_priv, pipe);
3791 }
3792
3793 static void lpt_pch_enable(struct drm_crtc *crtc)
3794 {
3795         struct drm_device *dev = crtc->dev;
3796         struct drm_i915_private *dev_priv = dev->dev_private;
3797         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3798         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3799
3800         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3801
3802         lpt_program_iclkip(crtc);
3803
3804         /* Set transcoder timing. */
3805         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3806
3807         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3808 }
3809
3810 void intel_put_shared_dpll(struct intel_crtc *crtc)
3811 {
3812         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3813
3814         if (pll == NULL)
3815                 return;
3816
3817         if (pll->refcount == 0) {
3818                 WARN(1, "bad %s refcount\n", pll->name);
3819                 return;
3820         }
3821
3822         if (--pll->refcount == 0) {
3823                 WARN_ON(pll->on);
3824                 WARN_ON(pll->active);
3825         }
3826
3827         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3828 }
3829
3830 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3831 {
3832         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3833         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3834         enum intel_dpll_id i;
3835
3836         if (pll) {
3837                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3838                               crtc->base.base.id, pll->name);
3839                 intel_put_shared_dpll(crtc);
3840         }
3841
3842         if (HAS_PCH_IBX(dev_priv->dev)) {
3843                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3844                 i = (enum intel_dpll_id) crtc->pipe;
3845                 pll = &dev_priv->shared_dplls[i];
3846
3847                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3848                               crtc->base.base.id, pll->name);
3849
3850                 WARN_ON(pll->refcount);
3851
3852                 goto found;
3853         }
3854
3855         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3856                 pll = &dev_priv->shared_dplls[i];
3857
3858                 /* Only want to check enabled timings first */
3859                 if (pll->refcount == 0)
3860                         continue;
3861
3862                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3863                            sizeof(pll->hw_state)) == 0) {
3864                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3865                                       crtc->base.base.id,
3866                                       pll->name, pll->refcount, pll->active);
3867
3868                         goto found;
3869                 }
3870         }
3871
3872         /* Ok no matching timings, maybe there's a free one? */
3873         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3874                 pll = &dev_priv->shared_dplls[i];
3875                 if (pll->refcount == 0) {
3876                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3877                                       crtc->base.base.id, pll->name);
3878                         goto found;
3879                 }
3880         }
3881
3882         return NULL;
3883
3884 found:
3885         if (pll->refcount == 0)
3886                 pll->hw_state = crtc->config.dpll_hw_state;
3887
3888         crtc->config.shared_dpll = i;
3889         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3890                          pipe_name(crtc->pipe));
3891
3892         pll->refcount++;
3893
3894         return pll;
3895 }
3896
3897 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3898 {
3899         struct drm_i915_private *dev_priv = dev->dev_private;
3900         int dslreg = PIPEDSL(pipe);
3901         u32 temp;
3902
3903         temp = I915_READ(dslreg);
3904         udelay(500);
3905         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3906                 if (wait_for(I915_READ(dslreg) != temp, 5))
3907                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3908         }
3909 }
3910
3911 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3912 {
3913         struct drm_device *dev = crtc->base.dev;
3914         struct drm_i915_private *dev_priv = dev->dev_private;
3915         int pipe = crtc->pipe;
3916
3917         if (crtc->config.pch_pfit.enabled) {
3918                 /* Force use of hard-coded filter coefficients
3919                  * as some pre-programmed values are broken,
3920                  * e.g. x201.
3921                  */
3922                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3923                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3924                                                  PF_PIPE_SEL_IVB(pipe));
3925                 else
3926                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3927                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3928                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3929         }
3930 }
3931
3932 static void intel_enable_planes(struct drm_crtc *crtc)
3933 {
3934         struct drm_device *dev = crtc->dev;
3935         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3936         struct drm_plane *plane;
3937         struct intel_plane *intel_plane;
3938
3939         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3940                 intel_plane = to_intel_plane(plane);
3941                 if (intel_plane->pipe == pipe)
3942                         intel_plane_restore(&intel_plane->base);
3943         }
3944 }
3945
3946 static void intel_disable_planes(struct drm_crtc *crtc)
3947 {
3948         struct drm_device *dev = crtc->dev;
3949         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3950         struct drm_plane *plane;
3951         struct intel_plane *intel_plane;
3952
3953         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3954                 intel_plane = to_intel_plane(plane);
3955                 if (intel_plane->pipe == pipe)
3956                         intel_plane_disable(&intel_plane->base);
3957         }
3958 }
3959
3960 void hsw_enable_ips(struct intel_crtc *crtc)
3961 {
3962         struct drm_device *dev = crtc->base.dev;
3963         struct drm_i915_private *dev_priv = dev->dev_private;
3964
3965         if (!crtc->config.ips_enabled)
3966                 return;
3967
3968         /* We can only enable IPS after we enable a plane and wait for a vblank */
3969         intel_wait_for_vblank(dev, crtc->pipe);
3970
3971         assert_plane_enabled(dev_priv, crtc->plane);
3972         if (IS_BROADWELL(dev)) {
3973                 mutex_lock(&dev_priv->rps.hw_lock);
3974                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3975                 mutex_unlock(&dev_priv->rps.hw_lock);
3976                 /* Quoting Art Runyan: "its not safe to expect any particular
3977                  * value in IPS_CTL bit 31 after enabling IPS through the
3978                  * mailbox." Moreover, the mailbox may return a bogus state,
3979                  * so we need to just enable it and continue on.
3980                  */
3981         } else {
3982                 I915_WRITE(IPS_CTL, IPS_ENABLE);
3983                 /* The bit only becomes 1 in the next vblank, so this wait here
3984                  * is essentially intel_wait_for_vblank. If we don't have this
3985                  * and don't wait for vblanks until the end of crtc_enable, then
3986                  * the HW state readout code will complain that the expected
3987                  * IPS_CTL value is not the one we read. */
3988                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3989                         DRM_ERROR("Timed out waiting for IPS enable\n");
3990         }
3991 }
3992
3993 void hsw_disable_ips(struct intel_crtc *crtc)
3994 {
3995         struct drm_device *dev = crtc->base.dev;
3996         struct drm_i915_private *dev_priv = dev->dev_private;
3997
3998         if (!crtc->config.ips_enabled)
3999                 return;
4000
4001         assert_plane_enabled(dev_priv, crtc->plane);
4002         if (IS_BROADWELL(dev)) {
4003                 mutex_lock(&dev_priv->rps.hw_lock);
4004                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4005                 mutex_unlock(&dev_priv->rps.hw_lock);
4006                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4007                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4008                         DRM_ERROR("Timed out waiting for IPS disable\n");
4009         } else {
4010                 I915_WRITE(IPS_CTL, 0);
4011                 POSTING_READ(IPS_CTL);
4012         }
4013
4014         /* We need to wait for a vblank before we can disable the plane. */
4015         intel_wait_for_vblank(dev, crtc->pipe);
4016 }
4017
4018 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4019 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4020 {
4021         struct drm_device *dev = crtc->dev;
4022         struct drm_i915_private *dev_priv = dev->dev_private;
4023         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4024         enum pipe pipe = intel_crtc->pipe;
4025         int palreg = PALETTE(pipe);
4026         int i;
4027         bool reenable_ips = false;
4028
4029         /* The clocks have to be on to load the palette. */
4030         if (!crtc->enabled || !intel_crtc->active)
4031                 return;
4032
4033         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4034                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
4035                         assert_dsi_pll_enabled(dev_priv);
4036                 else
4037                         assert_pll_enabled(dev_priv, pipe);
4038         }
4039
4040         /* use legacy palette for Ironlake */
4041         if (!HAS_GMCH_DISPLAY(dev))
4042                 palreg = LGC_PALETTE(pipe);
4043
4044         /* Workaround : Do not read or write the pipe palette/gamma data while
4045          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4046          */
4047         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
4048             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4049              GAMMA_MODE_MODE_SPLIT)) {
4050                 hsw_disable_ips(intel_crtc);
4051                 reenable_ips = true;
4052         }
4053
4054         for (i = 0; i < 256; i++) {
4055                 I915_WRITE(palreg + 4 * i,
4056                            (intel_crtc->lut_r[i] << 16) |
4057                            (intel_crtc->lut_g[i] << 8) |
4058                            intel_crtc->lut_b[i]);
4059         }
4060
4061         if (reenable_ips)
4062                 hsw_enable_ips(intel_crtc);
4063 }
4064
4065 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4066 {
4067         if (!enable && intel_crtc->overlay) {
4068                 struct drm_device *dev = intel_crtc->base.dev;
4069                 struct drm_i915_private *dev_priv = dev->dev_private;
4070
4071                 mutex_lock(&dev->struct_mutex);
4072                 dev_priv->mm.interruptible = false;
4073                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4074                 dev_priv->mm.interruptible = true;
4075                 mutex_unlock(&dev->struct_mutex);
4076         }
4077
4078         /* Let userspace switch the overlay on again. In most cases userspace
4079          * has to recompute where to put it anyway.
4080          */
4081 }
4082
4083 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4084 {
4085         struct drm_device *dev = crtc->dev;
4086         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4087         int pipe = intel_crtc->pipe;
4088
4089         intel_enable_primary_hw_plane(crtc->primary, crtc);
4090         intel_enable_planes(crtc);
4091         intel_crtc_update_cursor(crtc, true);
4092         intel_crtc_dpms_overlay(intel_crtc, true);
4093
4094         hsw_enable_ips(intel_crtc);
4095
4096         mutex_lock(&dev->struct_mutex);
4097         intel_update_fbc(dev);
4098         mutex_unlock(&dev->struct_mutex);
4099
4100         /*
4101          * FIXME: Once we grow proper nuclear flip support out of this we need
4102          * to compute the mask of flip planes precisely. For the time being
4103          * consider this a flip from a NULL plane.
4104          */
4105         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4106 }
4107
4108 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4109 {
4110         struct drm_device *dev = crtc->dev;
4111         struct drm_i915_private *dev_priv = dev->dev_private;
4112         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4113         int pipe = intel_crtc->pipe;
4114         int plane = intel_crtc->plane;
4115
4116         intel_crtc_wait_for_pending_flips(crtc);
4117
4118         if (dev_priv->fbc.plane == plane)
4119                 intel_disable_fbc(dev);
4120
4121         hsw_disable_ips(intel_crtc);
4122
4123         intel_crtc_dpms_overlay(intel_crtc, false);
4124         intel_crtc_update_cursor(crtc, false);
4125         intel_disable_planes(crtc);
4126         intel_disable_primary_hw_plane(crtc->primary, crtc);
4127
4128         /*
4129          * FIXME: Once we grow proper nuclear flip support out of this we need
4130          * to compute the mask of flip planes precisely. For the time being
4131          * consider this a flip to a NULL plane.
4132          */
4133         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4134 }
4135
4136 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4137 {
4138         struct drm_device *dev = crtc->dev;
4139         struct drm_i915_private *dev_priv = dev->dev_private;
4140         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4141         struct intel_encoder *encoder;
4142         int pipe = intel_crtc->pipe;
4143
4144         WARN_ON(!crtc->enabled);
4145
4146         if (intel_crtc->active)
4147                 return;
4148
4149         if (intel_crtc->config.has_pch_encoder)
4150                 intel_prepare_shared_dpll(intel_crtc);
4151
4152         if (intel_crtc->config.has_dp_encoder)
4153                 intel_dp_set_m_n(intel_crtc);
4154
4155         intel_set_pipe_timings(intel_crtc);
4156
4157         if (intel_crtc->config.has_pch_encoder) {
4158                 intel_cpu_transcoder_set_m_n(intel_crtc,
4159                                      &intel_crtc->config.fdi_m_n, NULL);
4160         }
4161
4162         ironlake_set_pipeconf(crtc);
4163
4164         intel_crtc->active = true;
4165
4166         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4167         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4168
4169         for_each_encoder_on_crtc(dev, crtc, encoder)
4170                 if (encoder->pre_enable)
4171                         encoder->pre_enable(encoder);
4172
4173         if (intel_crtc->config.has_pch_encoder) {
4174                 /* Note: FDI PLL enabling _must_ be done before we enable the
4175                  * cpu pipes, hence this is separate from all the other fdi/pch
4176                  * enabling. */
4177                 ironlake_fdi_pll_enable(intel_crtc);
4178         } else {
4179                 assert_fdi_tx_disabled(dev_priv, pipe);
4180                 assert_fdi_rx_disabled(dev_priv, pipe);
4181         }
4182
4183         ironlake_pfit_enable(intel_crtc);
4184
4185         /*
4186          * On ILK+ LUT must be loaded before the pipe is running but with
4187          * clocks enabled
4188          */
4189         intel_crtc_load_lut(crtc);
4190
4191         intel_update_watermarks(crtc);
4192         intel_enable_pipe(intel_crtc);
4193
4194         if (intel_crtc->config.has_pch_encoder)
4195                 ironlake_pch_enable(crtc);
4196
4197         for_each_encoder_on_crtc(dev, crtc, encoder)
4198                 encoder->enable(encoder);
4199
4200         if (HAS_PCH_CPT(dev))
4201                 cpt_verify_modeset(dev, intel_crtc->pipe);
4202
4203         assert_vblank_disabled(crtc);
4204         drm_crtc_vblank_on(crtc);
4205
4206         intel_crtc_enable_planes(crtc);
4207 }
4208
4209 /* IPS only exists on ULT machines and is tied to pipe A. */
4210 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4211 {
4212         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4213 }
4214
4215 /*
4216  * This implements the workaround described in the "notes" section of the mode
4217  * set sequence documentation. When going from no pipes or single pipe to
4218  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4219  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4220  */
4221 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4222 {
4223         struct drm_device *dev = crtc->base.dev;
4224         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4225
4226         /* We want to get the other_active_crtc only if there's only 1 other
4227          * active crtc. */
4228         for_each_intel_crtc(dev, crtc_it) {
4229                 if (!crtc_it->active || crtc_it == crtc)
4230                         continue;
4231
4232                 if (other_active_crtc)
4233                         return;
4234
4235                 other_active_crtc = crtc_it;
4236         }
4237         if (!other_active_crtc)
4238                 return;
4239
4240         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4241         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4242 }
4243
4244 static void haswell_crtc_enable(struct drm_crtc *crtc)
4245 {
4246         struct drm_device *dev = crtc->dev;
4247         struct drm_i915_private *dev_priv = dev->dev_private;
4248         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4249         struct intel_encoder *encoder;
4250         int pipe = intel_crtc->pipe;
4251
4252         WARN_ON(!crtc->enabled);
4253
4254         if (intel_crtc->active)
4255                 return;
4256
4257         if (intel_crtc_to_shared_dpll(intel_crtc))
4258                 intel_enable_shared_dpll(intel_crtc);
4259
4260         if (intel_crtc->config.has_dp_encoder)
4261                 intel_dp_set_m_n(intel_crtc);
4262
4263         intel_set_pipe_timings(intel_crtc);
4264
4265         if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) {
4266                 I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder),
4267                            intel_crtc->config.pixel_multiplier - 1);
4268         }
4269
4270         if (intel_crtc->config.has_pch_encoder) {
4271                 intel_cpu_transcoder_set_m_n(intel_crtc,
4272                                      &intel_crtc->config.fdi_m_n, NULL);
4273         }
4274
4275         haswell_set_pipeconf(crtc);
4276
4277         intel_set_pipe_csc(crtc);
4278
4279         intel_crtc->active = true;
4280
4281         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4282         for_each_encoder_on_crtc(dev, crtc, encoder)
4283                 if (encoder->pre_enable)
4284                         encoder->pre_enable(encoder);
4285
4286         if (intel_crtc->config.has_pch_encoder) {
4287                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4288                                                       true);
4289                 dev_priv->display.fdi_link_train(crtc);
4290         }
4291
4292         intel_ddi_enable_pipe_clock(intel_crtc);
4293
4294         ironlake_pfit_enable(intel_crtc);
4295
4296         /*
4297          * On ILK+ LUT must be loaded before the pipe is running but with
4298          * clocks enabled
4299          */
4300         intel_crtc_load_lut(crtc);
4301
4302         intel_ddi_set_pipe_settings(crtc);
4303         intel_ddi_enable_transcoder_func(crtc);
4304
4305         intel_update_watermarks(crtc);
4306         intel_enable_pipe(intel_crtc);
4307
4308         if (intel_crtc->config.has_pch_encoder)
4309                 lpt_pch_enable(crtc);
4310
4311         if (intel_crtc->config.dp_encoder_is_mst)
4312                 intel_ddi_set_vc_payload_alloc(crtc, true);
4313
4314         for_each_encoder_on_crtc(dev, crtc, encoder) {
4315                 encoder->enable(encoder);
4316                 intel_opregion_notify_encoder(encoder, true);
4317         }
4318
4319         assert_vblank_disabled(crtc);
4320         drm_crtc_vblank_on(crtc);
4321
4322         /* If we change the relative order between pipe/planes enabling, we need
4323          * to change the workaround. */
4324         haswell_mode_set_planes_workaround(intel_crtc);
4325         intel_crtc_enable_planes(crtc);
4326 }
4327
4328 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4329 {
4330         struct drm_device *dev = crtc->base.dev;
4331         struct drm_i915_private *dev_priv = dev->dev_private;
4332         int pipe = crtc->pipe;
4333
4334         /* To avoid upsetting the power well on haswell only disable the pfit if
4335          * it's in use. The hw state code will make sure we get this right. */
4336         if (crtc->config.pch_pfit.enabled) {
4337                 I915_WRITE(PF_CTL(pipe), 0);
4338                 I915_WRITE(PF_WIN_POS(pipe), 0);
4339                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4340         }
4341 }
4342
4343 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4344 {
4345         struct drm_device *dev = crtc->dev;
4346         struct drm_i915_private *dev_priv = dev->dev_private;
4347         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4348         struct intel_encoder *encoder;
4349         int pipe = intel_crtc->pipe;
4350         u32 reg, temp;
4351
4352         if (!intel_crtc->active)
4353                 return;
4354
4355         intel_crtc_disable_planes(crtc);
4356
4357         drm_crtc_vblank_off(crtc);
4358         assert_vblank_disabled(crtc);
4359
4360         for_each_encoder_on_crtc(dev, crtc, encoder)
4361                 encoder->disable(encoder);
4362
4363         if (intel_crtc->config.has_pch_encoder)
4364                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4365
4366         intel_disable_pipe(intel_crtc);
4367
4368         ironlake_pfit_disable(intel_crtc);
4369
4370         for_each_encoder_on_crtc(dev, crtc, encoder)
4371                 if (encoder->post_disable)
4372                         encoder->post_disable(encoder);
4373
4374         if (intel_crtc->config.has_pch_encoder) {
4375                 ironlake_fdi_disable(crtc);
4376
4377                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4378                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4379
4380                 if (HAS_PCH_CPT(dev)) {
4381                         /* disable TRANS_DP_CTL */
4382                         reg = TRANS_DP_CTL(pipe);
4383                         temp = I915_READ(reg);
4384                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4385                                   TRANS_DP_PORT_SEL_MASK);
4386                         temp |= TRANS_DP_PORT_SEL_NONE;
4387                         I915_WRITE(reg, temp);
4388
4389                         /* disable DPLL_SEL */
4390                         temp = I915_READ(PCH_DPLL_SEL);
4391                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4392                         I915_WRITE(PCH_DPLL_SEL, temp);
4393                 }
4394
4395                 /* disable PCH DPLL */
4396                 intel_disable_shared_dpll(intel_crtc);
4397
4398                 ironlake_fdi_pll_disable(intel_crtc);
4399         }
4400
4401         intel_crtc->active = false;
4402         intel_update_watermarks(crtc);
4403
4404         mutex_lock(&dev->struct_mutex);
4405         intel_update_fbc(dev);
4406         mutex_unlock(&dev->struct_mutex);
4407 }
4408
4409 static void haswell_crtc_disable(struct drm_crtc *crtc)
4410 {
4411         struct drm_device *dev = crtc->dev;
4412         struct drm_i915_private *dev_priv = dev->dev_private;
4413         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4414         struct intel_encoder *encoder;
4415         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4416
4417         if (!intel_crtc->active)
4418                 return;
4419
4420         intel_crtc_disable_planes(crtc);
4421
4422         drm_crtc_vblank_off(crtc);
4423         assert_vblank_disabled(crtc);
4424
4425         for_each_encoder_on_crtc(dev, crtc, encoder) {
4426                 intel_opregion_notify_encoder(encoder, false);
4427                 encoder->disable(encoder);
4428         }
4429
4430         if (intel_crtc->config.has_pch_encoder)
4431                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4432                                                       false);
4433         intel_disable_pipe(intel_crtc);
4434
4435         if (intel_crtc->config.dp_encoder_is_mst)
4436                 intel_ddi_set_vc_payload_alloc(crtc, false);
4437
4438         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4439
4440         ironlake_pfit_disable(intel_crtc);
4441
4442         intel_ddi_disable_pipe_clock(intel_crtc);
4443
4444         if (intel_crtc->config.has_pch_encoder) {
4445                 lpt_disable_pch_transcoder(dev_priv);
4446                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4447                                                       true);
4448                 intel_ddi_fdi_disable(crtc);
4449         }
4450
4451         for_each_encoder_on_crtc(dev, crtc, encoder)
4452                 if (encoder->post_disable)
4453                         encoder->post_disable(encoder);
4454
4455         intel_crtc->active = false;
4456         intel_update_watermarks(crtc);
4457
4458         mutex_lock(&dev->struct_mutex);
4459         intel_update_fbc(dev);
4460         mutex_unlock(&dev->struct_mutex);
4461
4462         if (intel_crtc_to_shared_dpll(intel_crtc))
4463                 intel_disable_shared_dpll(intel_crtc);
4464 }
4465
4466 static void ironlake_crtc_off(struct drm_crtc *crtc)
4467 {
4468         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4469         intel_put_shared_dpll(intel_crtc);
4470 }
4471
4472
4473 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4474 {
4475         struct drm_device *dev = crtc->base.dev;
4476         struct drm_i915_private *dev_priv = dev->dev_private;
4477         struct intel_crtc_config *pipe_config = &crtc->config;
4478
4479         if (!crtc->config.gmch_pfit.control)
4480                 return;
4481
4482         /*
4483          * The panel fitter should only be adjusted whilst the pipe is disabled,
4484          * according to register description and PRM.
4485          */
4486         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4487         assert_pipe_disabled(dev_priv, crtc->pipe);
4488
4489         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4490         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4491
4492         /* Border color in case we don't scale up to the full screen. Black by
4493          * default, change to something else for debugging. */
4494         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4495 }
4496
4497 static enum intel_display_power_domain port_to_power_domain(enum port port)
4498 {
4499         switch (port) {
4500         case PORT_A:
4501                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4502         case PORT_B:
4503                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4504         case PORT_C:
4505                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4506         case PORT_D:
4507                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4508         default:
4509                 WARN_ON_ONCE(1);
4510                 return POWER_DOMAIN_PORT_OTHER;
4511         }
4512 }
4513
4514 #define for_each_power_domain(domain, mask)                             \
4515         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4516                 if ((1 << (domain)) & (mask))
4517
4518 enum intel_display_power_domain
4519 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4520 {
4521         struct drm_device *dev = intel_encoder->base.dev;
4522         struct intel_digital_port *intel_dig_port;
4523
4524         switch (intel_encoder->type) {
4525         case INTEL_OUTPUT_UNKNOWN:
4526                 /* Only DDI platforms should ever use this output type */
4527                 WARN_ON_ONCE(!HAS_DDI(dev));
4528         case INTEL_OUTPUT_DISPLAYPORT:
4529         case INTEL_OUTPUT_HDMI:
4530         case INTEL_OUTPUT_EDP:
4531                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4532                 return port_to_power_domain(intel_dig_port->port);
4533         case INTEL_OUTPUT_DP_MST:
4534                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4535                 return port_to_power_domain(intel_dig_port->port);
4536         case INTEL_OUTPUT_ANALOG:
4537                 return POWER_DOMAIN_PORT_CRT;
4538         case INTEL_OUTPUT_DSI:
4539                 return POWER_DOMAIN_PORT_DSI;
4540         default:
4541                 return POWER_DOMAIN_PORT_OTHER;
4542         }
4543 }
4544
4545 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4546 {
4547         struct drm_device *dev = crtc->dev;
4548         struct intel_encoder *intel_encoder;
4549         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4550         enum pipe pipe = intel_crtc->pipe;
4551         unsigned long mask;
4552         enum transcoder transcoder;
4553
4554         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4555
4556         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4557         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4558         if (intel_crtc->config.pch_pfit.enabled ||
4559             intel_crtc->config.pch_pfit.force_thru)
4560                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4561
4562         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4563                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4564
4565         return mask;
4566 }
4567
4568 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4569 {
4570         struct drm_i915_private *dev_priv = dev->dev_private;
4571         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4572         struct intel_crtc *crtc;
4573
4574         /*
4575          * First get all needed power domains, then put all unneeded, to avoid
4576          * any unnecessary toggling of the power wells.
4577          */
4578         for_each_intel_crtc(dev, crtc) {
4579                 enum intel_display_power_domain domain;
4580
4581                 if (!crtc->base.enabled)
4582                         continue;
4583
4584                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4585
4586                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4587                         intel_display_power_get(dev_priv, domain);
4588         }
4589
4590         for_each_intel_crtc(dev, crtc) {
4591                 enum intel_display_power_domain domain;
4592
4593                 for_each_power_domain(domain, crtc->enabled_power_domains)
4594                         intel_display_power_put(dev_priv, domain);
4595
4596                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4597         }
4598
4599         intel_display_set_init_power(dev_priv, false);
4600 }
4601
4602 /* returns HPLL frequency in kHz */
4603 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4604 {
4605         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4606
4607         /* Obtain SKU information */
4608         mutex_lock(&dev_priv->dpio_lock);
4609         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4610                 CCK_FUSE_HPLL_FREQ_MASK;
4611         mutex_unlock(&dev_priv->dpio_lock);
4612
4613         return vco_freq[hpll_freq] * 1000;
4614 }
4615
4616 static void vlv_update_cdclk(struct drm_device *dev)
4617 {
4618         struct drm_i915_private *dev_priv = dev->dev_private;
4619
4620         dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4621         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4622                          dev_priv->vlv_cdclk_freq);
4623
4624         /*
4625          * Program the gmbus_freq based on the cdclk frequency.
4626          * BSpec erroneously claims we should aim for 4MHz, but
4627          * in fact 1MHz is the correct frequency.
4628          */
4629         I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4630 }
4631
4632 /* Adjust CDclk dividers to allow high res or save power if possible */
4633 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4634 {
4635         struct drm_i915_private *dev_priv = dev->dev_private;
4636         u32 val, cmd;
4637
4638         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4639
4640         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4641                 cmd = 2;
4642         else if (cdclk == 266667)
4643                 cmd = 1;
4644         else
4645                 cmd = 0;
4646
4647         mutex_lock(&dev_priv->rps.hw_lock);
4648         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4649         val &= ~DSPFREQGUAR_MASK;
4650         val |= (cmd << DSPFREQGUAR_SHIFT);
4651         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4652         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4653                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4654                      50)) {
4655                 DRM_ERROR("timed out waiting for CDclk change\n");
4656         }
4657         mutex_unlock(&dev_priv->rps.hw_lock);
4658
4659         if (cdclk == 400000) {
4660                 u32 divider, vco;
4661
4662                 vco = valleyview_get_vco(dev_priv);
4663                 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4664
4665                 mutex_lock(&dev_priv->dpio_lock);
4666                 /* adjust cdclk divider */
4667                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4668                 val &= ~DISPLAY_FREQUENCY_VALUES;
4669                 val |= divider;
4670                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4671
4672                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4673                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4674                              50))
4675                         DRM_ERROR("timed out waiting for CDclk change\n");
4676                 mutex_unlock(&dev_priv->dpio_lock);
4677         }
4678
4679         mutex_lock(&dev_priv->dpio_lock);
4680         /* adjust self-refresh exit latency value */
4681         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4682         val &= ~0x7f;
4683
4684         /*
4685          * For high bandwidth configs, we set a higher latency in the bunit
4686          * so that the core display fetch happens in time to avoid underruns.
4687          */
4688         if (cdclk == 400000)
4689                 val |= 4500 / 250; /* 4.5 usec */
4690         else
4691                 val |= 3000 / 250; /* 3.0 usec */
4692         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4693         mutex_unlock(&dev_priv->dpio_lock);
4694
4695         vlv_update_cdclk(dev);
4696 }
4697
4698 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4699 {
4700         struct drm_i915_private *dev_priv = dev->dev_private;
4701         u32 val, cmd;
4702
4703         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4704
4705         switch (cdclk) {
4706         case 400000:
4707                 cmd = 3;
4708                 break;
4709         case 333333:
4710         case 320000:
4711                 cmd = 2;
4712                 break;
4713         case 266667:
4714                 cmd = 1;
4715                 break;
4716         case 200000:
4717                 cmd = 0;
4718                 break;
4719         default:
4720                 WARN_ON(1);
4721                 return;
4722         }
4723
4724         mutex_lock(&dev_priv->rps.hw_lock);
4725         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4726         val &= ~DSPFREQGUAR_MASK_CHV;
4727         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4728         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4729         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4730                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4731                      50)) {
4732                 DRM_ERROR("timed out waiting for CDclk change\n");
4733         }
4734         mutex_unlock(&dev_priv->rps.hw_lock);
4735
4736         vlv_update_cdclk(dev);
4737 }
4738
4739 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4740                                  int max_pixclk)
4741 {
4742         int vco = valleyview_get_vco(dev_priv);
4743         int freq_320 = (vco <<  1) % 320000 != 0 ? 333333 : 320000;
4744
4745         /* FIXME: Punit isn't quite ready yet */
4746         if (IS_CHERRYVIEW(dev_priv->dev))
4747                 return 400000;
4748
4749         /*
4750          * Really only a few cases to deal with, as only 4 CDclks are supported:
4751          *   200MHz
4752          *   267MHz
4753          *   320/333MHz (depends on HPLL freq)
4754          *   400MHz
4755          * So we check to see whether we're above 90% of the lower bin and
4756          * adjust if needed.
4757          *
4758          * We seem to get an unstable or solid color picture at 200MHz.
4759          * Not sure what's wrong. For now use 200MHz only when all pipes
4760          * are off.
4761          */
4762         if (max_pixclk > freq_320*9/10)
4763                 return 400000;
4764         else if (max_pixclk > 266667*9/10)
4765                 return freq_320;
4766         else if (max_pixclk > 0)
4767                 return 266667;
4768         else
4769                 return 200000;
4770 }
4771
4772 /* compute the max pixel clock for new configuration */
4773 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4774 {
4775         struct drm_device *dev = dev_priv->dev;
4776         struct intel_crtc *intel_crtc;
4777         int max_pixclk = 0;
4778
4779         for_each_intel_crtc(dev, intel_crtc) {
4780                 if (intel_crtc->new_enabled)
4781                         max_pixclk = max(max_pixclk,
4782                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4783         }
4784
4785         return max_pixclk;
4786 }
4787
4788 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4789                                             unsigned *prepare_pipes)
4790 {
4791         struct drm_i915_private *dev_priv = dev->dev_private;
4792         struct intel_crtc *intel_crtc;
4793         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4794
4795         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4796             dev_priv->vlv_cdclk_freq)
4797                 return;
4798
4799         /* disable/enable all currently active pipes while we change cdclk */
4800         for_each_intel_crtc(dev, intel_crtc)
4801                 if (intel_crtc->base.enabled)
4802                         *prepare_pipes |= (1 << intel_crtc->pipe);
4803 }
4804
4805 static void valleyview_modeset_global_resources(struct drm_device *dev)
4806 {
4807         struct drm_i915_private *dev_priv = dev->dev_private;
4808         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4809         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4810
4811         if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4812                 if (IS_CHERRYVIEW(dev))
4813                         cherryview_set_cdclk(dev, req_cdclk);
4814                 else
4815                         valleyview_set_cdclk(dev, req_cdclk);
4816         }
4817
4818         modeset_update_crtc_power_domains(dev);
4819 }
4820
4821 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4822 {
4823         struct drm_device *dev = crtc->dev;
4824         struct drm_i915_private *dev_priv = to_i915(dev);
4825         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4826         struct intel_encoder *encoder;
4827         int pipe = intel_crtc->pipe;
4828         bool is_dsi;
4829
4830         WARN_ON(!crtc->enabled);
4831
4832         if (intel_crtc->active)
4833                 return;
4834
4835         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4836
4837         if (!is_dsi) {
4838                 if (IS_CHERRYVIEW(dev))
4839                         chv_prepare_pll(intel_crtc);
4840                 else
4841                         vlv_prepare_pll(intel_crtc);
4842         }
4843
4844         if (intel_crtc->config.has_dp_encoder)
4845                 intel_dp_set_m_n(intel_crtc);
4846
4847         intel_set_pipe_timings(intel_crtc);
4848
4849         i9xx_set_pipeconf(intel_crtc);
4850
4851         intel_crtc->active = true;
4852
4853         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4854
4855         for_each_encoder_on_crtc(dev, crtc, encoder)
4856                 if (encoder->pre_pll_enable)
4857                         encoder->pre_pll_enable(encoder);
4858
4859         if (!is_dsi) {
4860                 if (IS_CHERRYVIEW(dev))
4861                         chv_enable_pll(intel_crtc);
4862                 else
4863                         vlv_enable_pll(intel_crtc);
4864         }
4865
4866         for_each_encoder_on_crtc(dev, crtc, encoder)
4867                 if (encoder->pre_enable)
4868                         encoder->pre_enable(encoder);
4869
4870         i9xx_pfit_enable(intel_crtc);
4871
4872         intel_crtc_load_lut(crtc);
4873
4874         intel_update_watermarks(crtc);
4875         intel_enable_pipe(intel_crtc);
4876
4877         for_each_encoder_on_crtc(dev, crtc, encoder)
4878                 encoder->enable(encoder);
4879
4880         assert_vblank_disabled(crtc);
4881         drm_crtc_vblank_on(crtc);
4882
4883         intel_crtc_enable_planes(crtc);
4884
4885         /* Underruns don't raise interrupts, so check manually. */
4886         i9xx_check_fifo_underruns(dev_priv);
4887 }
4888
4889 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4890 {
4891         struct drm_device *dev = crtc->base.dev;
4892         struct drm_i915_private *dev_priv = dev->dev_private;
4893
4894         I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4895         I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4896 }
4897
4898 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4899 {
4900         struct drm_device *dev = crtc->dev;
4901         struct drm_i915_private *dev_priv = to_i915(dev);
4902         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4903         struct intel_encoder *encoder;
4904         int pipe = intel_crtc->pipe;
4905
4906         WARN_ON(!crtc->enabled);
4907
4908         if (intel_crtc->active)
4909                 return;
4910
4911         i9xx_set_pll_dividers(intel_crtc);
4912
4913         if (intel_crtc->config.has_dp_encoder)
4914                 intel_dp_set_m_n(intel_crtc);
4915
4916         intel_set_pipe_timings(intel_crtc);
4917
4918         i9xx_set_pipeconf(intel_crtc);
4919
4920         intel_crtc->active = true;
4921
4922         if (!IS_GEN2(dev))
4923                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4924
4925         for_each_encoder_on_crtc(dev, crtc, encoder)
4926                 if (encoder->pre_enable)
4927                         encoder->pre_enable(encoder);
4928
4929         i9xx_enable_pll(intel_crtc);
4930
4931         i9xx_pfit_enable(intel_crtc);
4932
4933         intel_crtc_load_lut(crtc);
4934
4935         intel_update_watermarks(crtc);
4936         intel_enable_pipe(intel_crtc);
4937
4938         for_each_encoder_on_crtc(dev, crtc, encoder)
4939                 encoder->enable(encoder);
4940
4941         assert_vblank_disabled(crtc);
4942         drm_crtc_vblank_on(crtc);
4943
4944         intel_crtc_enable_planes(crtc);
4945
4946         /*
4947          * Gen2 reports pipe underruns whenever all planes are disabled.
4948          * So don't enable underrun reporting before at least some planes
4949          * are enabled.
4950          * FIXME: Need to fix the logic to work when we turn off all planes
4951          * but leave the pipe running.
4952          */
4953         if (IS_GEN2(dev))
4954                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4955
4956         /* Underruns don't raise interrupts, so check manually. */
4957         i9xx_check_fifo_underruns(dev_priv);
4958 }
4959
4960 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4961 {
4962         struct drm_device *dev = crtc->base.dev;
4963         struct drm_i915_private *dev_priv = dev->dev_private;
4964
4965         if (!crtc->config.gmch_pfit.control)
4966                 return;
4967
4968         assert_pipe_disabled(dev_priv, crtc->pipe);
4969
4970         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4971                          I915_READ(PFIT_CONTROL));
4972         I915_WRITE(PFIT_CONTROL, 0);
4973 }
4974
4975 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4976 {
4977         struct drm_device *dev = crtc->dev;
4978         struct drm_i915_private *dev_priv = dev->dev_private;
4979         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4980         struct intel_encoder *encoder;
4981         int pipe = intel_crtc->pipe;
4982
4983         if (!intel_crtc->active)
4984                 return;
4985
4986         /*
4987          * Gen2 reports pipe underruns whenever all planes are disabled.
4988          * So diasble underrun reporting before all the planes get disabled.
4989          * FIXME: Need to fix the logic to work when we turn off all planes
4990          * but leave the pipe running.
4991          */
4992         if (IS_GEN2(dev))
4993                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4994
4995         /*
4996          * Vblank time updates from the shadow to live plane control register
4997          * are blocked if the memory self-refresh mode is active at that
4998          * moment. So to make sure the plane gets truly disabled, disable
4999          * first the self-refresh mode. The self-refresh enable bit in turn
5000          * will be checked/applied by the HW only at the next frame start
5001          * event which is after the vblank start event, so we need to have a
5002          * wait-for-vblank between disabling the plane and the pipe.
5003          */
5004         intel_set_memory_cxsr(dev_priv, false);
5005         intel_crtc_disable_planes(crtc);
5006
5007         /*
5008          * On gen2 planes are double buffered but the pipe isn't, so we must
5009          * wait for planes to fully turn off before disabling the pipe.
5010          * We also need to wait on all gmch platforms because of the
5011          * self-refresh mode constraint explained above.
5012          */
5013         intel_wait_for_vblank(dev, pipe);
5014
5015         drm_crtc_vblank_off(crtc);
5016         assert_vblank_disabled(crtc);
5017
5018         for_each_encoder_on_crtc(dev, crtc, encoder)
5019                 encoder->disable(encoder);
5020
5021         intel_disable_pipe(intel_crtc);
5022
5023         i9xx_pfit_disable(intel_crtc);
5024
5025         for_each_encoder_on_crtc(dev, crtc, encoder)
5026                 if (encoder->post_disable)
5027                         encoder->post_disable(encoder);
5028
5029         if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
5030                 if (IS_CHERRYVIEW(dev))
5031                         chv_disable_pll(dev_priv, pipe);
5032                 else if (IS_VALLEYVIEW(dev))
5033                         vlv_disable_pll(dev_priv, pipe);
5034                 else
5035                         i9xx_disable_pll(intel_crtc);
5036         }
5037
5038         if (!IS_GEN2(dev))
5039                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5040
5041         intel_crtc->active = false;
5042         intel_update_watermarks(crtc);
5043
5044         mutex_lock(&dev->struct_mutex);
5045         intel_update_fbc(dev);
5046         mutex_unlock(&dev->struct_mutex);
5047 }
5048
5049 static void i9xx_crtc_off(struct drm_crtc *crtc)
5050 {
5051 }
5052
5053 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
5054                                     bool enabled)
5055 {
5056         struct drm_device *dev = crtc->dev;
5057         struct drm_i915_master_private *master_priv;
5058         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5059         int pipe = intel_crtc->pipe;
5060
5061         if (!dev->primary->master)
5062                 return;
5063
5064         master_priv = dev->primary->master->driver_priv;
5065         if (!master_priv->sarea_priv)
5066                 return;
5067
5068         switch (pipe) {
5069         case 0:
5070                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
5071                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
5072                 break;
5073         case 1:
5074                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
5075                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
5076                 break;
5077         default:
5078                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
5079                 break;
5080         }
5081 }
5082
5083 /* Master function to enable/disable CRTC and corresponding power wells */
5084 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5085 {
5086         struct drm_device *dev = crtc->dev;
5087         struct drm_i915_private *dev_priv = dev->dev_private;
5088         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5089         enum intel_display_power_domain domain;
5090         unsigned long domains;
5091
5092         if (enable) {
5093                 if (!intel_crtc->active) {
5094                         domains = get_crtc_power_domains(crtc);
5095                         for_each_power_domain(domain, domains)
5096                                 intel_display_power_get(dev_priv, domain);
5097                         intel_crtc->enabled_power_domains = domains;
5098
5099                         dev_priv->display.crtc_enable(crtc);
5100                 }
5101         } else {
5102                 if (intel_crtc->active) {
5103                         dev_priv->display.crtc_disable(crtc);
5104
5105                         domains = intel_crtc->enabled_power_domains;
5106                         for_each_power_domain(domain, domains)
5107                                 intel_display_power_put(dev_priv, domain);
5108                         intel_crtc->enabled_power_domains = 0;
5109                 }
5110         }
5111 }
5112
5113 /**
5114  * Sets the power management mode of the pipe and plane.
5115  */
5116 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5117 {
5118         struct drm_device *dev = crtc->dev;
5119         struct intel_encoder *intel_encoder;
5120         bool enable = false;
5121
5122         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5123                 enable |= intel_encoder->connectors_active;
5124
5125         intel_crtc_control(crtc, enable);
5126
5127         intel_crtc_update_sarea(crtc, enable);
5128 }
5129
5130 static void intel_crtc_disable(struct drm_crtc *crtc)
5131 {
5132         struct drm_device *dev = crtc->dev;
5133         struct drm_connector *connector;
5134         struct drm_i915_private *dev_priv = dev->dev_private;
5135         struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
5136         enum pipe pipe = to_intel_crtc(crtc)->pipe;
5137
5138         /* crtc should still be enabled when we disable it. */
5139         WARN_ON(!crtc->enabled);
5140
5141         dev_priv->display.crtc_disable(crtc);
5142         intel_crtc_update_sarea(crtc, false);
5143         dev_priv->display.off(crtc);
5144
5145         if (crtc->primary->fb) {
5146                 mutex_lock(&dev->struct_mutex);
5147                 intel_unpin_fb_obj(old_obj);
5148                 i915_gem_track_fb(old_obj, NULL,
5149                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
5150                 mutex_unlock(&dev->struct_mutex);
5151                 crtc->primary->fb = NULL;
5152         }
5153
5154         /* Update computed state. */
5155         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5156                 if (!connector->encoder || !connector->encoder->crtc)
5157                         continue;
5158
5159                 if (connector->encoder->crtc != crtc)
5160                         continue;
5161
5162                 connector->dpms = DRM_MODE_DPMS_OFF;
5163                 to_intel_encoder(connector->encoder)->connectors_active = false;
5164         }
5165 }
5166
5167 void intel_encoder_destroy(struct drm_encoder *encoder)
5168 {
5169         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5170
5171         drm_encoder_cleanup(encoder);
5172         kfree(intel_encoder);
5173 }
5174
5175 /* Simple dpms helper for encoders with just one connector, no cloning and only
5176  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5177  * state of the entire output pipe. */
5178 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5179 {
5180         if (mode == DRM_MODE_DPMS_ON) {
5181                 encoder->connectors_active = true;
5182
5183                 intel_crtc_update_dpms(encoder->base.crtc);
5184         } else {
5185                 encoder->connectors_active = false;
5186
5187                 intel_crtc_update_dpms(encoder->base.crtc);
5188         }
5189 }
5190
5191 /* Cross check the actual hw state with our own modeset state tracking (and it's
5192  * internal consistency). */
5193 static void intel_connector_check_state(struct intel_connector *connector)
5194 {
5195         if (connector->get_hw_state(connector)) {
5196                 struct intel_encoder *encoder = connector->encoder;
5197                 struct drm_crtc *crtc;
5198                 bool encoder_enabled;
5199                 enum pipe pipe;
5200
5201                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5202                               connector->base.base.id,
5203                               connector->base.name);
5204
5205                 /* there is no real hw state for MST connectors */
5206                 if (connector->mst_port)
5207                         return;
5208
5209                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5210                      "wrong connector dpms state\n");
5211                 WARN(connector->base.encoder != &encoder->base,
5212                      "active connector not linked to encoder\n");
5213
5214                 if (encoder) {
5215                         WARN(!encoder->connectors_active,
5216                              "encoder->connectors_active not set\n");
5217
5218                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5219                         WARN(!encoder_enabled, "encoder not enabled\n");
5220                         if (WARN_ON(!encoder->base.crtc))
5221                                 return;
5222
5223                         crtc = encoder->base.crtc;
5224
5225                         WARN(!crtc->enabled, "crtc not enabled\n");
5226                         WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5227                         WARN(pipe != to_intel_crtc(crtc)->pipe,
5228                              "encoder active on the wrong pipe\n");
5229                 }
5230         }
5231 }
5232
5233 /* Even simpler default implementation, if there's really no special case to
5234  * consider. */
5235 void intel_connector_dpms(struct drm_connector *connector, int mode)
5236 {
5237         /* All the simple cases only support two dpms states. */
5238         if (mode != DRM_MODE_DPMS_ON)
5239                 mode = DRM_MODE_DPMS_OFF;
5240
5241         if (mode == connector->dpms)
5242                 return;
5243
5244         connector->dpms = mode;
5245
5246         /* Only need to change hw state when actually enabled */
5247         if (connector->encoder)
5248                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5249
5250         intel_modeset_check_state(connector->dev);
5251 }
5252
5253 /* Simple connector->get_hw_state implementation for encoders that support only
5254  * one connector and no cloning and hence the encoder state determines the state
5255  * of the connector. */
5256 bool intel_connector_get_hw_state(struct intel_connector *connector)
5257 {
5258         enum pipe pipe = 0;
5259         struct intel_encoder *encoder = connector->encoder;
5260
5261         return encoder->get_hw_state(encoder, &pipe);
5262 }
5263
5264 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5265                                      struct intel_crtc_config *pipe_config)
5266 {
5267         struct drm_i915_private *dev_priv = dev->dev_private;
5268         struct intel_crtc *pipe_B_crtc =
5269                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5270
5271         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5272                       pipe_name(pipe), pipe_config->fdi_lanes);
5273         if (pipe_config->fdi_lanes > 4) {
5274                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5275                               pipe_name(pipe), pipe_config->fdi_lanes);
5276                 return false;
5277         }
5278
5279         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5280                 if (pipe_config->fdi_lanes > 2) {
5281                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5282                                       pipe_config->fdi_lanes);
5283                         return false;
5284                 } else {
5285                         return true;
5286                 }
5287         }
5288
5289         if (INTEL_INFO(dev)->num_pipes == 2)
5290                 return true;
5291
5292         /* Ivybridge 3 pipe is really complicated */
5293         switch (pipe) {
5294         case PIPE_A:
5295                 return true;
5296         case PIPE_B:
5297                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5298                     pipe_config->fdi_lanes > 2) {
5299                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5300                                       pipe_name(pipe), pipe_config->fdi_lanes);
5301                         return false;
5302                 }
5303                 return true;
5304         case PIPE_C:
5305                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5306                     pipe_B_crtc->config.fdi_lanes <= 2) {
5307                         if (pipe_config->fdi_lanes > 2) {
5308                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5309                                               pipe_name(pipe), pipe_config->fdi_lanes);
5310                                 return false;
5311                         }
5312                 } else {
5313                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5314                         return false;
5315                 }
5316                 return true;
5317         default:
5318                 BUG();
5319         }
5320 }
5321
5322 #define RETRY 1
5323 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5324                                        struct intel_crtc_config *pipe_config)
5325 {
5326         struct drm_device *dev = intel_crtc->base.dev;
5327         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5328         int lane, link_bw, fdi_dotclock;
5329         bool setup_ok, needs_recompute = false;
5330
5331 retry:
5332         /* FDI is a binary signal running at ~2.7GHz, encoding
5333          * each output octet as 10 bits. The actual frequency
5334          * is stored as a divider into a 100MHz clock, and the
5335          * mode pixel clock is stored in units of 1KHz.
5336          * Hence the bw of each lane in terms of the mode signal
5337          * is:
5338          */
5339         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5340
5341         fdi_dotclock = adjusted_mode->crtc_clock;
5342
5343         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5344                                            pipe_config->pipe_bpp);
5345
5346         pipe_config->fdi_lanes = lane;
5347
5348         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5349                                link_bw, &pipe_config->fdi_m_n);
5350
5351         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5352                                             intel_crtc->pipe, pipe_config);
5353         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5354                 pipe_config->pipe_bpp -= 2*3;
5355                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5356                               pipe_config->pipe_bpp);
5357                 needs_recompute = true;
5358                 pipe_config->bw_constrained = true;
5359
5360                 goto retry;
5361         }
5362
5363         if (needs_recompute)
5364                 return RETRY;
5365
5366         return setup_ok ? 0 : -EINVAL;
5367 }
5368
5369 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5370                                    struct intel_crtc_config *pipe_config)
5371 {
5372         pipe_config->ips_enabled = i915.enable_ips &&
5373                                    hsw_crtc_supports_ips(crtc) &&
5374                                    pipe_config->pipe_bpp <= 24;
5375 }
5376
5377 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5378                                      struct intel_crtc_config *pipe_config)
5379 {
5380         struct drm_device *dev = crtc->base.dev;
5381         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5382
5383         /* FIXME should check pixel clock limits on all platforms */
5384         if (INTEL_INFO(dev)->gen < 4) {
5385                 struct drm_i915_private *dev_priv = dev->dev_private;
5386                 int clock_limit =
5387                         dev_priv->display.get_display_clock_speed(dev);
5388
5389                 /*
5390                  * Enable pixel doubling when the dot clock
5391                  * is > 90% of the (display) core speed.
5392                  *
5393                  * GDG double wide on either pipe,
5394                  * otherwise pipe A only.
5395                  */
5396                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5397                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5398                         clock_limit *= 2;
5399                         pipe_config->double_wide = true;
5400                 }
5401
5402                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5403                         return -EINVAL;
5404         }
5405
5406         /*
5407          * Pipe horizontal size must be even in:
5408          * - DVO ganged mode
5409          * - LVDS dual channel mode
5410          * - Double wide pipe
5411          */
5412         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5413              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5414                 pipe_config->pipe_src_w &= ~1;
5415
5416         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5417          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5418          */
5419         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5420                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5421                 return -EINVAL;
5422
5423         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5424                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5425         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5426                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5427                  * for lvds. */
5428                 pipe_config->pipe_bpp = 8*3;
5429         }
5430
5431         if (HAS_IPS(dev))
5432                 hsw_compute_ips_config(crtc, pipe_config);
5433
5434         /*
5435          * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5436          * old clock survives for now.
5437          */
5438         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
5439                 pipe_config->shared_dpll = crtc->config.shared_dpll;
5440
5441         if (pipe_config->has_pch_encoder)
5442                 return ironlake_fdi_compute_config(crtc, pipe_config);
5443
5444         return 0;
5445 }
5446
5447 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5448 {
5449         struct drm_i915_private *dev_priv = dev->dev_private;
5450         int vco = valleyview_get_vco(dev_priv);
5451         u32 val;
5452         int divider;
5453
5454         /* FIXME: Punit isn't quite ready yet */
5455         if (IS_CHERRYVIEW(dev))
5456                 return 400000;
5457
5458         mutex_lock(&dev_priv->dpio_lock);
5459         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5460         mutex_unlock(&dev_priv->dpio_lock);
5461
5462         divider = val & DISPLAY_FREQUENCY_VALUES;
5463
5464         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5465              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5466              "cdclk change in progress\n");
5467
5468         return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5469 }
5470
5471 static int i945_get_display_clock_speed(struct drm_device *dev)
5472 {
5473         return 400000;
5474 }
5475
5476 static int i915_get_display_clock_speed(struct drm_device *dev)
5477 {
5478         return 333000;
5479 }
5480
5481 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5482 {
5483         return 200000;
5484 }
5485
5486 static int pnv_get_display_clock_speed(struct drm_device *dev)
5487 {
5488         u16 gcfgc = 0;
5489
5490         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5491
5492         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5493         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5494                 return 267000;
5495         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5496                 return 333000;
5497         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5498                 return 444000;
5499         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5500                 return 200000;
5501         default:
5502                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5503         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5504                 return 133000;
5505         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5506                 return 167000;
5507         }
5508 }
5509
5510 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5511 {
5512         u16 gcfgc = 0;
5513
5514         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5515
5516         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5517                 return 133000;
5518         else {
5519                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5520                 case GC_DISPLAY_CLOCK_333_MHZ:
5521                         return 333000;
5522                 default:
5523                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5524                         return 190000;
5525                 }
5526         }
5527 }
5528
5529 static int i865_get_display_clock_speed(struct drm_device *dev)
5530 {
5531         return 266000;
5532 }
5533
5534 static int i855_get_display_clock_speed(struct drm_device *dev)
5535 {
5536         u16 hpllcc = 0;
5537         /* Assume that the hardware is in the high speed state.  This
5538          * should be the default.
5539          */
5540         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5541         case GC_CLOCK_133_200:
5542         case GC_CLOCK_100_200:
5543                 return 200000;
5544         case GC_CLOCK_166_250:
5545                 return 250000;
5546         case GC_CLOCK_100_133:
5547                 return 133000;
5548         }
5549
5550         /* Shouldn't happen */
5551         return 0;
5552 }
5553
5554 static int i830_get_display_clock_speed(struct drm_device *dev)
5555 {
5556         return 133000;
5557 }
5558
5559 static void
5560 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5561 {
5562         while (*num > DATA_LINK_M_N_MASK ||
5563                *den > DATA_LINK_M_N_MASK) {
5564                 *num >>= 1;
5565                 *den >>= 1;
5566         }
5567 }
5568
5569 static void compute_m_n(unsigned int m, unsigned int n,
5570                         uint32_t *ret_m, uint32_t *ret_n)
5571 {
5572         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5573         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5574         intel_reduce_m_n_ratio(ret_m, ret_n);
5575 }
5576
5577 void
5578 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5579                        int pixel_clock, int link_clock,
5580                        struct intel_link_m_n *m_n)
5581 {
5582         m_n->tu = 64;
5583
5584         compute_m_n(bits_per_pixel * pixel_clock,
5585                     link_clock * nlanes * 8,
5586                     &m_n->gmch_m, &m_n->gmch_n);
5587
5588         compute_m_n(pixel_clock, link_clock,
5589                     &m_n->link_m, &m_n->link_n);
5590 }
5591
5592 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5593 {
5594         if (i915.panel_use_ssc >= 0)
5595                 return i915.panel_use_ssc != 0;
5596         return dev_priv->vbt.lvds_use_ssc
5597                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5598 }
5599
5600 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5601 {
5602         struct drm_device *dev = crtc->dev;
5603         struct drm_i915_private *dev_priv = dev->dev_private;
5604         int refclk;
5605
5606         if (IS_VALLEYVIEW(dev)) {
5607                 refclk = 100000;
5608         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5609             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5610                 refclk = dev_priv->vbt.lvds_ssc_freq;
5611                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5612         } else if (!IS_GEN2(dev)) {
5613                 refclk = 96000;
5614         } else {
5615                 refclk = 48000;
5616         }
5617
5618         return refclk;
5619 }
5620
5621 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5622 {
5623         return (1 << dpll->n) << 16 | dpll->m2;
5624 }
5625
5626 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5627 {
5628         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5629 }
5630
5631 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5632                                      intel_clock_t *reduced_clock)
5633 {
5634         struct drm_device *dev = crtc->base.dev;
5635         u32 fp, fp2 = 0;
5636
5637         if (IS_PINEVIEW(dev)) {
5638                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5639                 if (reduced_clock)
5640                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5641         } else {
5642                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5643                 if (reduced_clock)
5644                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5645         }
5646
5647         crtc->config.dpll_hw_state.fp0 = fp;
5648
5649         crtc->lowfreq_avail = false;
5650         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5651             reduced_clock && i915.powersave) {
5652                 crtc->config.dpll_hw_state.fp1 = fp2;
5653                 crtc->lowfreq_avail = true;
5654         } else {
5655                 crtc->config.dpll_hw_state.fp1 = fp;
5656         }
5657 }
5658
5659 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5660                 pipe)
5661 {
5662         u32 reg_val;
5663
5664         /*
5665          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5666          * and set it to a reasonable value instead.
5667          */
5668         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5669         reg_val &= 0xffffff00;
5670         reg_val |= 0x00000030;
5671         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5672
5673         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5674         reg_val &= 0x8cffffff;
5675         reg_val = 0x8c000000;
5676         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5677
5678         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5679         reg_val &= 0xffffff00;
5680         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5681
5682         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5683         reg_val &= 0x00ffffff;
5684         reg_val |= 0xb0000000;
5685         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5686 }
5687
5688 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5689                                          struct intel_link_m_n *m_n)
5690 {
5691         struct drm_device *dev = crtc->base.dev;
5692         struct drm_i915_private *dev_priv = dev->dev_private;
5693         int pipe = crtc->pipe;
5694
5695         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5696         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5697         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5698         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5699 }
5700
5701 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5702                                          struct intel_link_m_n *m_n,
5703                                          struct intel_link_m_n *m2_n2)
5704 {
5705         struct drm_device *dev = crtc->base.dev;
5706         struct drm_i915_private *dev_priv = dev->dev_private;
5707         int pipe = crtc->pipe;
5708         enum transcoder transcoder = crtc->config.cpu_transcoder;
5709
5710         if (INTEL_INFO(dev)->gen >= 5) {
5711                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5712                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5713                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5714                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5715                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5716                  * for gen < 8) and if DRRS is supported (to make sure the
5717                  * registers are not unnecessarily accessed).
5718                  */
5719                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5720                         crtc->config.has_drrs) {
5721                         I915_WRITE(PIPE_DATA_M2(transcoder),
5722                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5723                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5724                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5725                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5726                 }
5727         } else {
5728                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5729                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5730                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5731                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5732         }
5733 }
5734
5735 void intel_dp_set_m_n(struct intel_crtc *crtc)
5736 {
5737         if (crtc->config.has_pch_encoder)
5738                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5739         else
5740                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5741                                                    &crtc->config.dp_m2_n2);
5742 }
5743
5744 static void vlv_update_pll(struct intel_crtc *crtc)
5745 {
5746         u32 dpll, dpll_md;
5747
5748         /*
5749          * Enable DPIO clock input. We should never disable the reference
5750          * clock for pipe B, since VGA hotplug / manual detection depends
5751          * on it.
5752          */
5753         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5754                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5755         /* We should never disable this, set it here for state tracking */
5756         if (crtc->pipe == PIPE_B)
5757                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5758         dpll |= DPLL_VCO_ENABLE;
5759         crtc->config.dpll_hw_state.dpll = dpll;
5760
5761         dpll_md = (crtc->config.pixel_multiplier - 1)
5762                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5763         crtc->config.dpll_hw_state.dpll_md = dpll_md;
5764 }
5765
5766 static void vlv_prepare_pll(struct intel_crtc *crtc)
5767 {
5768         struct drm_device *dev = crtc->base.dev;
5769         struct drm_i915_private *dev_priv = dev->dev_private;
5770         int pipe = crtc->pipe;
5771         u32 mdiv;
5772         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5773         u32 coreclk, reg_val;
5774
5775         mutex_lock(&dev_priv->dpio_lock);
5776
5777         bestn = crtc->config.dpll.n;
5778         bestm1 = crtc->config.dpll.m1;
5779         bestm2 = crtc->config.dpll.m2;
5780         bestp1 = crtc->config.dpll.p1;
5781         bestp2 = crtc->config.dpll.p2;
5782
5783         /* See eDP HDMI DPIO driver vbios notes doc */
5784
5785         /* PLL B needs special handling */
5786         if (pipe == PIPE_B)
5787                 vlv_pllb_recal_opamp(dev_priv, pipe);
5788
5789         /* Set up Tx target for periodic Rcomp update */
5790         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5791
5792         /* Disable target IRef on PLL */
5793         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5794         reg_val &= 0x00ffffff;
5795         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5796
5797         /* Disable fast lock */
5798         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5799
5800         /* Set idtafcrecal before PLL is enabled */
5801         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5802         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5803         mdiv |= ((bestn << DPIO_N_SHIFT));
5804         mdiv |= (1 << DPIO_K_SHIFT);
5805
5806         /*
5807          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5808          * but we don't support that).
5809          * Note: don't use the DAC post divider as it seems unstable.
5810          */
5811         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5812         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5813
5814         mdiv |= DPIO_ENABLE_CALIBRATION;
5815         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5816
5817         /* Set HBR and RBR LPF coefficients */
5818         if (crtc->config.port_clock == 162000 ||
5819             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5820             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5821                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5822                                  0x009f0003);
5823         else
5824                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5825                                  0x00d0000f);
5826
5827         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5828             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5829                 /* Use SSC source */
5830                 if (pipe == PIPE_A)
5831                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5832                                          0x0df40000);
5833                 else
5834                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5835                                          0x0df70000);
5836         } else { /* HDMI or VGA */
5837                 /* Use bend source */
5838                 if (pipe == PIPE_A)
5839                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5840                                          0x0df70000);
5841                 else
5842                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5843                                          0x0df40000);
5844         }
5845
5846         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5847         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5848         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5849             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5850                 coreclk |= 0x01000000;
5851         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5852
5853         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5854         mutex_unlock(&dev_priv->dpio_lock);
5855 }
5856
5857 static void chv_update_pll(struct intel_crtc *crtc)
5858 {
5859         crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5860                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5861                 DPLL_VCO_ENABLE;
5862         if (crtc->pipe != PIPE_A)
5863                 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5864
5865         crtc->config.dpll_hw_state.dpll_md =
5866                 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5867 }
5868
5869 static void chv_prepare_pll(struct intel_crtc *crtc)
5870 {
5871         struct drm_device *dev = crtc->base.dev;
5872         struct drm_i915_private *dev_priv = dev->dev_private;
5873         int pipe = crtc->pipe;
5874         int dpll_reg = DPLL(crtc->pipe);
5875         enum dpio_channel port = vlv_pipe_to_channel(pipe);
5876         u32 loopfilter, intcoeff;
5877         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5878         int refclk;
5879
5880         bestn = crtc->config.dpll.n;
5881         bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5882         bestm1 = crtc->config.dpll.m1;
5883         bestm2 = crtc->config.dpll.m2 >> 22;
5884         bestp1 = crtc->config.dpll.p1;
5885         bestp2 = crtc->config.dpll.p2;
5886
5887         /*
5888          * Enable Refclk and SSC
5889          */
5890         I915_WRITE(dpll_reg,
5891                    crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5892
5893         mutex_lock(&dev_priv->dpio_lock);
5894
5895         /* p1 and p2 divider */
5896         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5897                         5 << DPIO_CHV_S1_DIV_SHIFT |
5898                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5899                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5900                         1 << DPIO_CHV_K_DIV_SHIFT);
5901
5902         /* Feedback post-divider - m2 */
5903         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5904
5905         /* Feedback refclk divider - n and m1 */
5906         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5907                         DPIO_CHV_M1_DIV_BY_2 |
5908                         1 << DPIO_CHV_N_DIV_SHIFT);
5909
5910         /* M2 fraction division */
5911         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5912
5913         /* M2 fraction division enable */
5914         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5915                        DPIO_CHV_FRAC_DIV_EN |
5916                        (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5917
5918         /* Loop filter */
5919         refclk = i9xx_get_refclk(&crtc->base, 0);
5920         loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5921                 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5922         if (refclk == 100000)
5923                 intcoeff = 11;
5924         else if (refclk == 38400)
5925                 intcoeff = 10;
5926         else
5927                 intcoeff = 9;
5928         loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5929         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5930
5931         /* AFC Recal */
5932         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5933                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5934                         DPIO_AFC_RECAL);
5935
5936         mutex_unlock(&dev_priv->dpio_lock);
5937 }
5938
5939 static void i9xx_update_pll(struct intel_crtc *crtc,
5940                             intel_clock_t *reduced_clock,
5941                             int num_connectors)
5942 {
5943         struct drm_device *dev = crtc->base.dev;
5944         struct drm_i915_private *dev_priv = dev->dev_private;
5945         u32 dpll;
5946         bool is_sdvo;
5947         struct dpll *clock = &crtc->config.dpll;
5948
5949         i9xx_update_pll_dividers(crtc, reduced_clock);
5950
5951         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5952                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5953
5954         dpll = DPLL_VGA_MODE_DIS;
5955
5956         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5957                 dpll |= DPLLB_MODE_LVDS;
5958         else
5959                 dpll |= DPLLB_MODE_DAC_SERIAL;
5960
5961         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5962                 dpll |= (crtc->config.pixel_multiplier - 1)
5963                         << SDVO_MULTIPLIER_SHIFT_HIRES;
5964         }
5965
5966         if (is_sdvo)
5967                 dpll |= DPLL_SDVO_HIGH_SPEED;
5968
5969         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5970                 dpll |= DPLL_SDVO_HIGH_SPEED;
5971
5972         /* compute bitmask from p1 value */
5973         if (IS_PINEVIEW(dev))
5974                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5975         else {
5976                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5977                 if (IS_G4X(dev) && reduced_clock)
5978                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5979         }
5980         switch (clock->p2) {
5981         case 5:
5982                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5983                 break;
5984         case 7:
5985                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5986                 break;
5987         case 10:
5988                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5989                 break;
5990         case 14:
5991                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5992                 break;
5993         }
5994         if (INTEL_INFO(dev)->gen >= 4)
5995                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5996
5997         if (crtc->config.sdvo_tv_clock)
5998                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5999         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
6000                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6001                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6002         else
6003                 dpll |= PLL_REF_INPUT_DREFCLK;
6004
6005         dpll |= DPLL_VCO_ENABLE;
6006         crtc->config.dpll_hw_state.dpll = dpll;
6007
6008         if (INTEL_INFO(dev)->gen >= 4) {
6009                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
6010                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6011                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
6012         }
6013 }
6014
6015 static void i8xx_update_pll(struct intel_crtc *crtc,
6016                             intel_clock_t *reduced_clock,
6017                             int num_connectors)
6018 {
6019         struct drm_device *dev = crtc->base.dev;
6020         struct drm_i915_private *dev_priv = dev->dev_private;
6021         u32 dpll;
6022         struct dpll *clock = &crtc->config.dpll;
6023
6024         i9xx_update_pll_dividers(crtc, reduced_clock);
6025
6026         dpll = DPLL_VGA_MODE_DIS;
6027
6028         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
6029                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6030         } else {
6031                 if (clock->p1 == 2)
6032                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6033                 else
6034                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6035                 if (clock->p2 == 4)
6036                         dpll |= PLL_P2_DIVIDE_BY_4;
6037         }
6038
6039         if (!IS_I830(dev) && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
6040                 dpll |= DPLL_DVO_2X_MODE;
6041
6042         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
6043                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6044                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6045         else
6046                 dpll |= PLL_REF_INPUT_DREFCLK;
6047
6048         dpll |= DPLL_VCO_ENABLE;
6049         crtc->config.dpll_hw_state.dpll = dpll;
6050 }
6051
6052 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6053 {
6054         struct drm_device *dev = intel_crtc->base.dev;
6055         struct drm_i915_private *dev_priv = dev->dev_private;
6056         enum pipe pipe = intel_crtc->pipe;
6057         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6058         struct drm_display_mode *adjusted_mode =
6059                 &intel_crtc->config.adjusted_mode;
6060         uint32_t crtc_vtotal, crtc_vblank_end;
6061         int vsyncshift = 0;
6062
6063         /* We need to be careful not to changed the adjusted mode, for otherwise
6064          * the hw state checker will get angry at the mismatch. */
6065         crtc_vtotal = adjusted_mode->crtc_vtotal;
6066         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6067
6068         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6069                 /* the chip adds 2 halflines automatically */
6070                 crtc_vtotal -= 1;
6071                 crtc_vblank_end -= 1;
6072
6073                 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
6074                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6075                 else
6076                         vsyncshift = adjusted_mode->crtc_hsync_start -
6077                                 adjusted_mode->crtc_htotal / 2;
6078                 if (vsyncshift < 0)
6079                         vsyncshift += adjusted_mode->crtc_htotal;
6080         }
6081
6082         if (INTEL_INFO(dev)->gen > 3)
6083                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6084
6085         I915_WRITE(HTOTAL(cpu_transcoder),
6086                    (adjusted_mode->crtc_hdisplay - 1) |
6087                    ((adjusted_mode->crtc_htotal - 1) << 16));
6088         I915_WRITE(HBLANK(cpu_transcoder),
6089                    (adjusted_mode->crtc_hblank_start - 1) |
6090                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6091         I915_WRITE(HSYNC(cpu_transcoder),
6092                    (adjusted_mode->crtc_hsync_start - 1) |
6093                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6094
6095         I915_WRITE(VTOTAL(cpu_transcoder),
6096                    (adjusted_mode->crtc_vdisplay - 1) |
6097                    ((crtc_vtotal - 1) << 16));
6098         I915_WRITE(VBLANK(cpu_transcoder),
6099                    (adjusted_mode->crtc_vblank_start - 1) |
6100                    ((crtc_vblank_end - 1) << 16));
6101         I915_WRITE(VSYNC(cpu_transcoder),
6102                    (adjusted_mode->crtc_vsync_start - 1) |
6103                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6104
6105         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6106          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6107          * documented on the DDI_FUNC_CTL register description, EDP Input Select
6108          * bits. */
6109         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6110             (pipe == PIPE_B || pipe == PIPE_C))
6111                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6112
6113         /* pipesrc controls the size that is scaled from, which should
6114          * always be the user's requested size.
6115          */
6116         I915_WRITE(PIPESRC(pipe),
6117                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
6118                    (intel_crtc->config.pipe_src_h - 1));
6119 }
6120
6121 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6122                                    struct intel_crtc_config *pipe_config)
6123 {
6124         struct drm_device *dev = crtc->base.dev;
6125         struct drm_i915_private *dev_priv = dev->dev_private;
6126         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6127         uint32_t tmp;
6128
6129         tmp = I915_READ(HTOTAL(cpu_transcoder));
6130         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6131         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6132         tmp = I915_READ(HBLANK(cpu_transcoder));
6133         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6134         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6135         tmp = I915_READ(HSYNC(cpu_transcoder));
6136         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6137         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6138
6139         tmp = I915_READ(VTOTAL(cpu_transcoder));
6140         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6141         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6142         tmp = I915_READ(VBLANK(cpu_transcoder));
6143         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6144         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6145         tmp = I915_READ(VSYNC(cpu_transcoder));
6146         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6147         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6148
6149         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6150                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6151                 pipe_config->adjusted_mode.crtc_vtotal += 1;
6152                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
6153         }
6154
6155         tmp = I915_READ(PIPESRC(crtc->pipe));
6156         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6157         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6158
6159         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6160         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
6161 }
6162
6163 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6164                                  struct intel_crtc_config *pipe_config)
6165 {
6166         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6167         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6168         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6169         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
6170
6171         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6172         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6173         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6174         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
6175
6176         mode->flags = pipe_config->adjusted_mode.flags;
6177
6178         mode->clock = pipe_config->adjusted_mode.crtc_clock;
6179         mode->flags |= pipe_config->adjusted_mode.flags;
6180 }
6181
6182 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6183 {
6184         struct drm_device *dev = intel_crtc->base.dev;
6185         struct drm_i915_private *dev_priv = dev->dev_private;
6186         uint32_t pipeconf;
6187
6188         pipeconf = 0;
6189
6190         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6191             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6192                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6193
6194         if (intel_crtc->config.double_wide)
6195                 pipeconf |= PIPECONF_DOUBLE_WIDE;
6196
6197         /* only g4x and later have fancy bpc/dither controls */
6198         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6199                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6200                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6201                         pipeconf |= PIPECONF_DITHER_EN |
6202                                     PIPECONF_DITHER_TYPE_SP;
6203
6204                 switch (intel_crtc->config.pipe_bpp) {
6205                 case 18:
6206                         pipeconf |= PIPECONF_6BPC;
6207                         break;
6208                 case 24:
6209                         pipeconf |= PIPECONF_8BPC;
6210                         break;
6211                 case 30:
6212                         pipeconf |= PIPECONF_10BPC;
6213                         break;
6214                 default:
6215                         /* Case prevented by intel_choose_pipe_bpp_dither. */
6216                         BUG();
6217                 }
6218         }
6219
6220         if (HAS_PIPE_CXSR(dev)) {
6221                 if (intel_crtc->lowfreq_avail) {
6222                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6223                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6224                 } else {
6225                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6226                 }
6227         }
6228
6229         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6230                 if (INTEL_INFO(dev)->gen < 4 ||
6231                     intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
6232                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6233                 else
6234                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6235         } else
6236                 pipeconf |= PIPECONF_PROGRESSIVE;
6237
6238         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6239                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6240
6241         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6242         POSTING_READ(PIPECONF(intel_crtc->pipe));
6243 }
6244
6245 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
6246                               int x, int y,
6247                               struct drm_framebuffer *fb)
6248 {
6249         struct drm_device *dev = crtc->dev;
6250         struct drm_i915_private *dev_priv = dev->dev_private;
6251         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6252         int refclk, num_connectors = 0;
6253         intel_clock_t clock, reduced_clock;
6254         bool ok, has_reduced_clock = false;
6255         bool is_lvds = false, is_dsi = false;
6256         struct intel_encoder *encoder;
6257         const intel_limit_t *limit;
6258
6259         for_each_encoder_on_crtc(dev, crtc, encoder) {
6260                 switch (encoder->type) {
6261                 case INTEL_OUTPUT_LVDS:
6262                         is_lvds = true;
6263                         break;
6264                 case INTEL_OUTPUT_DSI:
6265                         is_dsi = true;
6266                         break;
6267                 }
6268
6269                 num_connectors++;
6270         }
6271
6272         if (is_dsi)
6273                 return 0;
6274
6275         if (!intel_crtc->config.clock_set) {
6276                 refclk = i9xx_get_refclk(crtc, num_connectors);
6277
6278                 /*
6279                  * Returns a set of divisors for the desired target clock with
6280                  * the given refclk, or FALSE.  The returned values represent
6281                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6282                  * 2) / p1 / p2.
6283                  */
6284                 limit = intel_limit(crtc, refclk);
6285                 ok = dev_priv->display.find_dpll(limit, crtc,
6286                                                  intel_crtc->config.port_clock,
6287                                                  refclk, NULL, &clock);
6288                 if (!ok) {
6289                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
6290                         return -EINVAL;
6291                 }
6292
6293                 if (is_lvds && dev_priv->lvds_downclock_avail) {
6294                         /*
6295                          * Ensure we match the reduced clock's P to the target
6296                          * clock.  If the clocks don't match, we can't switch
6297                          * the display clock by using the FP0/FP1. In such case
6298                          * we will disable the LVDS downclock feature.
6299                          */
6300                         has_reduced_clock =
6301                                 dev_priv->display.find_dpll(limit, crtc,
6302                                                             dev_priv->lvds_downclock,
6303                                                             refclk, &clock,
6304                                                             &reduced_clock);
6305                 }
6306                 /* Compat-code for transition, will disappear. */
6307                 intel_crtc->config.dpll.n = clock.n;
6308                 intel_crtc->config.dpll.m1 = clock.m1;
6309                 intel_crtc->config.dpll.m2 = clock.m2;
6310                 intel_crtc->config.dpll.p1 = clock.p1;
6311                 intel_crtc->config.dpll.p2 = clock.p2;
6312         }
6313
6314         if (IS_GEN2(dev)) {
6315                 i8xx_update_pll(intel_crtc,
6316                                 has_reduced_clock ? &reduced_clock : NULL,
6317                                 num_connectors);
6318         } else if (IS_CHERRYVIEW(dev)) {
6319                 chv_update_pll(intel_crtc);
6320         } else if (IS_VALLEYVIEW(dev)) {
6321                 vlv_update_pll(intel_crtc);
6322         } else {
6323                 i9xx_update_pll(intel_crtc,
6324                                 has_reduced_clock ? &reduced_clock : NULL,
6325                                 num_connectors);
6326         }
6327
6328         return 0;
6329 }
6330
6331 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6332                                  struct intel_crtc_config *pipe_config)
6333 {
6334         struct drm_device *dev = crtc->base.dev;
6335         struct drm_i915_private *dev_priv = dev->dev_private;
6336         uint32_t tmp;
6337
6338         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6339                 return;
6340
6341         tmp = I915_READ(PFIT_CONTROL);
6342         if (!(tmp & PFIT_ENABLE))
6343                 return;
6344
6345         /* Check whether the pfit is attached to our pipe. */
6346         if (INTEL_INFO(dev)->gen < 4) {
6347                 if (crtc->pipe != PIPE_B)
6348                         return;
6349         } else {
6350                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6351                         return;
6352         }
6353
6354         pipe_config->gmch_pfit.control = tmp;
6355         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6356         if (INTEL_INFO(dev)->gen < 5)
6357                 pipe_config->gmch_pfit.lvds_border_bits =
6358                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6359 }
6360
6361 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6362                                struct intel_crtc_config *pipe_config)
6363 {
6364         struct drm_device *dev = crtc->base.dev;
6365         struct drm_i915_private *dev_priv = dev->dev_private;
6366         int pipe = pipe_config->cpu_transcoder;
6367         intel_clock_t clock;
6368         u32 mdiv;
6369         int refclk = 100000;
6370
6371         /* In case of MIPI DPLL will not even be used */
6372         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6373                 return;
6374
6375         mutex_lock(&dev_priv->dpio_lock);
6376         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6377         mutex_unlock(&dev_priv->dpio_lock);
6378
6379         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6380         clock.m2 = mdiv & DPIO_M2DIV_MASK;
6381         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6382         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6383         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6384
6385         vlv_clock(refclk, &clock);
6386
6387         /* clock.dot is the fast clock */
6388         pipe_config->port_clock = clock.dot / 5;
6389 }
6390
6391 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6392                                   struct intel_plane_config *plane_config)
6393 {
6394         struct drm_device *dev = crtc->base.dev;
6395         struct drm_i915_private *dev_priv = dev->dev_private;
6396         u32 val, base, offset;
6397         int pipe = crtc->pipe, plane = crtc->plane;
6398         int fourcc, pixel_format;
6399         int aligned_height;
6400
6401         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6402         if (!crtc->base.primary->fb) {
6403                 DRM_DEBUG_KMS("failed to alloc fb\n");
6404                 return;
6405         }
6406
6407         val = I915_READ(DSPCNTR(plane));
6408
6409         if (INTEL_INFO(dev)->gen >= 4)
6410                 if (val & DISPPLANE_TILED)
6411                         plane_config->tiled = true;
6412
6413         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6414         fourcc = intel_format_to_fourcc(pixel_format);
6415         crtc->base.primary->fb->pixel_format = fourcc;
6416         crtc->base.primary->fb->bits_per_pixel =
6417                 drm_format_plane_cpp(fourcc, 0) * 8;
6418
6419         if (INTEL_INFO(dev)->gen >= 4) {
6420                 if (plane_config->tiled)
6421                         offset = I915_READ(DSPTILEOFF(plane));
6422                 else
6423                         offset = I915_READ(DSPLINOFF(plane));
6424                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6425         } else {
6426                 base = I915_READ(DSPADDR(plane));
6427         }
6428         plane_config->base = base;
6429
6430         val = I915_READ(PIPESRC(pipe));
6431         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6432         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6433
6434         val = I915_READ(DSPSTRIDE(pipe));
6435         crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6436
6437         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6438                                             plane_config->tiled);
6439
6440         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6441                                         aligned_height);
6442
6443         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6444                       pipe, plane, crtc->base.primary->fb->width,
6445                       crtc->base.primary->fb->height,
6446                       crtc->base.primary->fb->bits_per_pixel, base,
6447                       crtc->base.primary->fb->pitches[0],
6448                       plane_config->size);
6449
6450 }
6451
6452 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6453                                struct intel_crtc_config *pipe_config)
6454 {
6455         struct drm_device *dev = crtc->base.dev;
6456         struct drm_i915_private *dev_priv = dev->dev_private;
6457         int pipe = pipe_config->cpu_transcoder;
6458         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6459         intel_clock_t clock;
6460         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6461         int refclk = 100000;
6462
6463         mutex_lock(&dev_priv->dpio_lock);
6464         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6465         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6466         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6467         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6468         mutex_unlock(&dev_priv->dpio_lock);
6469
6470         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6471         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6472         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6473         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6474         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6475
6476         chv_clock(refclk, &clock);
6477
6478         /* clock.dot is the fast clock */
6479         pipe_config->port_clock = clock.dot / 5;
6480 }
6481
6482 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6483                                  struct intel_crtc_config *pipe_config)
6484 {
6485         struct drm_device *dev = crtc->base.dev;
6486         struct drm_i915_private *dev_priv = dev->dev_private;
6487         uint32_t tmp;
6488
6489         if (!intel_display_power_is_enabled(dev_priv,
6490                                             POWER_DOMAIN_PIPE(crtc->pipe)))
6491                 return false;
6492
6493         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6494         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6495
6496         tmp = I915_READ(PIPECONF(crtc->pipe));
6497         if (!(tmp & PIPECONF_ENABLE))
6498                 return false;
6499
6500         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6501                 switch (tmp & PIPECONF_BPC_MASK) {
6502                 case PIPECONF_6BPC:
6503                         pipe_config->pipe_bpp = 18;
6504                         break;
6505                 case PIPECONF_8BPC:
6506                         pipe_config->pipe_bpp = 24;
6507                         break;
6508                 case PIPECONF_10BPC:
6509                         pipe_config->pipe_bpp = 30;
6510                         break;
6511                 default:
6512                         break;
6513                 }
6514         }
6515
6516         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6517                 pipe_config->limited_color_range = true;
6518
6519         if (INTEL_INFO(dev)->gen < 4)
6520                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6521
6522         intel_get_pipe_timings(crtc, pipe_config);
6523
6524         i9xx_get_pfit_config(crtc, pipe_config);
6525
6526         if (INTEL_INFO(dev)->gen >= 4) {
6527                 tmp = I915_READ(DPLL_MD(crtc->pipe));
6528                 pipe_config->pixel_multiplier =
6529                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6530                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6531                 pipe_config->dpll_hw_state.dpll_md = tmp;
6532         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6533                 tmp = I915_READ(DPLL(crtc->pipe));
6534                 pipe_config->pixel_multiplier =
6535                         ((tmp & SDVO_MULTIPLIER_MASK)
6536                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6537         } else {
6538                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6539                  * port and will be fixed up in the encoder->get_config
6540                  * function. */
6541                 pipe_config->pixel_multiplier = 1;
6542         }
6543         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6544         if (!IS_VALLEYVIEW(dev)) {
6545                 /*
6546                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6547                  * on 830. Filter it out here so that we don't
6548                  * report errors due to that.
6549                  */
6550                 if (IS_I830(dev))
6551                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6552
6553                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6554                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6555         } else {
6556                 /* Mask out read-only status bits. */
6557                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6558                                                      DPLL_PORTC_READY_MASK |
6559                                                      DPLL_PORTB_READY_MASK);
6560         }
6561
6562         if (IS_CHERRYVIEW(dev))
6563                 chv_crtc_clock_get(crtc, pipe_config);
6564         else if (IS_VALLEYVIEW(dev))
6565                 vlv_crtc_clock_get(crtc, pipe_config);
6566         else
6567                 i9xx_crtc_clock_get(crtc, pipe_config);
6568
6569         return true;
6570 }
6571
6572 static void ironlake_init_pch_refclk(struct drm_device *dev)
6573 {
6574         struct drm_i915_private *dev_priv = dev->dev_private;
6575         struct intel_encoder *encoder;
6576         u32 val, final;
6577         bool has_lvds = false;
6578         bool has_cpu_edp = false;
6579         bool has_panel = false;
6580         bool has_ck505 = false;
6581         bool can_ssc = false;
6582
6583         /* We need to take the global config into account */
6584         for_each_intel_encoder(dev, encoder) {
6585                 switch (encoder->type) {
6586                 case INTEL_OUTPUT_LVDS:
6587                         has_panel = true;
6588                         has_lvds = true;
6589                         break;
6590                 case INTEL_OUTPUT_EDP:
6591                         has_panel = true;
6592                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6593                                 has_cpu_edp = true;
6594                         break;
6595                 }
6596         }
6597
6598         if (HAS_PCH_IBX(dev)) {
6599                 has_ck505 = dev_priv->vbt.display_clock_mode;
6600                 can_ssc = has_ck505;
6601         } else {
6602                 has_ck505 = false;
6603                 can_ssc = true;
6604         }
6605
6606         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6607                       has_panel, has_lvds, has_ck505);
6608
6609         /* Ironlake: try to setup display ref clock before DPLL
6610          * enabling. This is only under driver's control after
6611          * PCH B stepping, previous chipset stepping should be
6612          * ignoring this setting.
6613          */
6614         val = I915_READ(PCH_DREF_CONTROL);
6615
6616         /* As we must carefully and slowly disable/enable each source in turn,
6617          * compute the final state we want first and check if we need to
6618          * make any changes at all.
6619          */
6620         final = val;
6621         final &= ~DREF_NONSPREAD_SOURCE_MASK;
6622         if (has_ck505)
6623                 final |= DREF_NONSPREAD_CK505_ENABLE;
6624         else
6625                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6626
6627         final &= ~DREF_SSC_SOURCE_MASK;
6628         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6629         final &= ~DREF_SSC1_ENABLE;
6630
6631         if (has_panel) {
6632                 final |= DREF_SSC_SOURCE_ENABLE;
6633
6634                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6635                         final |= DREF_SSC1_ENABLE;
6636
6637                 if (has_cpu_edp) {
6638                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
6639                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6640                         else
6641                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6642                 } else
6643                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6644         } else {
6645                 final |= DREF_SSC_SOURCE_DISABLE;
6646                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6647         }
6648
6649         if (final == val)
6650                 return;
6651
6652         /* Always enable nonspread source */
6653         val &= ~DREF_NONSPREAD_SOURCE_MASK;
6654
6655         if (has_ck505)
6656                 val |= DREF_NONSPREAD_CK505_ENABLE;
6657         else
6658                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6659
6660         if (has_panel) {
6661                 val &= ~DREF_SSC_SOURCE_MASK;
6662                 val |= DREF_SSC_SOURCE_ENABLE;
6663
6664                 /* SSC must be turned on before enabling the CPU output  */
6665                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6666                         DRM_DEBUG_KMS("Using SSC on panel\n");
6667                         val |= DREF_SSC1_ENABLE;
6668                 } else
6669                         val &= ~DREF_SSC1_ENABLE;
6670
6671                 /* Get SSC going before enabling the outputs */
6672                 I915_WRITE(PCH_DREF_CONTROL, val);
6673                 POSTING_READ(PCH_DREF_CONTROL);
6674                 udelay(200);
6675
6676                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6677
6678                 /* Enable CPU source on CPU attached eDP */
6679                 if (has_cpu_edp) {
6680                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6681                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
6682                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6683                         } else
6684                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6685                 } else
6686                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6687
6688                 I915_WRITE(PCH_DREF_CONTROL, val);
6689                 POSTING_READ(PCH_DREF_CONTROL);
6690                 udelay(200);
6691         } else {
6692                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6693
6694                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6695
6696                 /* Turn off CPU output */
6697                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6698
6699                 I915_WRITE(PCH_DREF_CONTROL, val);
6700                 POSTING_READ(PCH_DREF_CONTROL);
6701                 udelay(200);
6702
6703                 /* Turn off the SSC source */
6704                 val &= ~DREF_SSC_SOURCE_MASK;
6705                 val |= DREF_SSC_SOURCE_DISABLE;
6706
6707                 /* Turn off SSC1 */
6708                 val &= ~DREF_SSC1_ENABLE;
6709
6710                 I915_WRITE(PCH_DREF_CONTROL, val);
6711                 POSTING_READ(PCH_DREF_CONTROL);
6712                 udelay(200);
6713         }
6714
6715         BUG_ON(val != final);
6716 }
6717
6718 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6719 {
6720         uint32_t tmp;
6721
6722         tmp = I915_READ(SOUTH_CHICKEN2);
6723         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6724         I915_WRITE(SOUTH_CHICKEN2, tmp);
6725
6726         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6727                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6728                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6729
6730         tmp = I915_READ(SOUTH_CHICKEN2);
6731         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6732         I915_WRITE(SOUTH_CHICKEN2, tmp);
6733
6734         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6735                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6736                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6737 }
6738
6739 /* WaMPhyProgramming:hsw */
6740 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6741 {
6742         uint32_t tmp;
6743
6744         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6745         tmp &= ~(0xFF << 24);
6746         tmp |= (0x12 << 24);
6747         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6748
6749         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6750         tmp |= (1 << 11);
6751         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6752
6753         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6754         tmp |= (1 << 11);
6755         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6756
6757         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6758         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6759         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6760
6761         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6762         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6763         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6764
6765         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6766         tmp &= ~(7 << 13);
6767         tmp |= (5 << 13);
6768         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6769
6770         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6771         tmp &= ~(7 << 13);
6772         tmp |= (5 << 13);
6773         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6774
6775         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6776         tmp &= ~0xFF;
6777         tmp |= 0x1C;
6778         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6779
6780         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6781         tmp &= ~0xFF;
6782         tmp |= 0x1C;
6783         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6784
6785         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6786         tmp &= ~(0xFF << 16);
6787         tmp |= (0x1C << 16);
6788         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6789
6790         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6791         tmp &= ~(0xFF << 16);
6792         tmp |= (0x1C << 16);
6793         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6794
6795         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6796         tmp |= (1 << 27);
6797         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6798
6799         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6800         tmp |= (1 << 27);
6801         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6802
6803         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6804         tmp &= ~(0xF << 28);
6805         tmp |= (4 << 28);
6806         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6807
6808         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6809         tmp &= ~(0xF << 28);
6810         tmp |= (4 << 28);
6811         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6812 }
6813
6814 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6815  * Programming" based on the parameters passed:
6816  * - Sequence to enable CLKOUT_DP
6817  * - Sequence to enable CLKOUT_DP without spread
6818  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6819  */
6820 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6821                                  bool with_fdi)
6822 {
6823         struct drm_i915_private *dev_priv = dev->dev_private;
6824         uint32_t reg, tmp;
6825
6826         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6827                 with_spread = true;
6828         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6829                  with_fdi, "LP PCH doesn't have FDI\n"))
6830                 with_fdi = false;
6831
6832         mutex_lock(&dev_priv->dpio_lock);
6833
6834         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6835         tmp &= ~SBI_SSCCTL_DISABLE;
6836         tmp |= SBI_SSCCTL_PATHALT;
6837         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6838
6839         udelay(24);
6840
6841         if (with_spread) {
6842                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6843                 tmp &= ~SBI_SSCCTL_PATHALT;
6844                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6845
6846                 if (with_fdi) {
6847                         lpt_reset_fdi_mphy(dev_priv);
6848                         lpt_program_fdi_mphy(dev_priv);
6849                 }
6850         }
6851
6852         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6853                SBI_GEN0 : SBI_DBUFF0;
6854         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6855         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6856         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6857
6858         mutex_unlock(&dev_priv->dpio_lock);
6859 }
6860
6861 /* Sequence to disable CLKOUT_DP */
6862 static void lpt_disable_clkout_dp(struct drm_device *dev)
6863 {
6864         struct drm_i915_private *dev_priv = dev->dev_private;
6865         uint32_t reg, tmp;
6866
6867         mutex_lock(&dev_priv->dpio_lock);
6868
6869         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6870                SBI_GEN0 : SBI_DBUFF0;
6871         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6872         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6873         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6874
6875         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6876         if (!(tmp & SBI_SSCCTL_DISABLE)) {
6877                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6878                         tmp |= SBI_SSCCTL_PATHALT;
6879                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6880                         udelay(32);
6881                 }
6882                 tmp |= SBI_SSCCTL_DISABLE;
6883                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6884         }
6885
6886         mutex_unlock(&dev_priv->dpio_lock);
6887 }
6888
6889 static void lpt_init_pch_refclk(struct drm_device *dev)
6890 {
6891         struct intel_encoder *encoder;
6892         bool has_vga = false;
6893
6894         for_each_intel_encoder(dev, encoder) {
6895                 switch (encoder->type) {
6896                 case INTEL_OUTPUT_ANALOG:
6897                         has_vga = true;
6898                         break;
6899                 }
6900         }
6901
6902         if (has_vga)
6903                 lpt_enable_clkout_dp(dev, true, true);
6904         else
6905                 lpt_disable_clkout_dp(dev);
6906 }
6907
6908 /*
6909  * Initialize reference clocks when the driver loads
6910  */
6911 void intel_init_pch_refclk(struct drm_device *dev)
6912 {
6913         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6914                 ironlake_init_pch_refclk(dev);
6915         else if (HAS_PCH_LPT(dev))
6916                 lpt_init_pch_refclk(dev);
6917 }
6918
6919 static int ironlake_get_refclk(struct drm_crtc *crtc)
6920 {
6921         struct drm_device *dev = crtc->dev;
6922         struct drm_i915_private *dev_priv = dev->dev_private;
6923         struct intel_encoder *encoder;
6924         int num_connectors = 0;
6925         bool is_lvds = false;
6926
6927         for_each_encoder_on_crtc(dev, crtc, encoder) {
6928                 switch (encoder->type) {
6929                 case INTEL_OUTPUT_LVDS:
6930                         is_lvds = true;
6931                         break;
6932                 }
6933                 num_connectors++;
6934         }
6935
6936         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6937                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6938                               dev_priv->vbt.lvds_ssc_freq);
6939                 return dev_priv->vbt.lvds_ssc_freq;
6940         }
6941
6942         return 120000;
6943 }
6944
6945 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6946 {
6947         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6948         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6949         int pipe = intel_crtc->pipe;
6950         uint32_t val;
6951
6952         val = 0;
6953
6954         switch (intel_crtc->config.pipe_bpp) {
6955         case 18:
6956                 val |= PIPECONF_6BPC;
6957                 break;
6958         case 24:
6959                 val |= PIPECONF_8BPC;
6960                 break;
6961         case 30:
6962                 val |= PIPECONF_10BPC;
6963                 break;
6964         case 36:
6965                 val |= PIPECONF_12BPC;
6966                 break;
6967         default:
6968                 /* Case prevented by intel_choose_pipe_bpp_dither. */
6969                 BUG();
6970         }
6971
6972         if (intel_crtc->config.dither)
6973                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6974
6975         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6976                 val |= PIPECONF_INTERLACED_ILK;
6977         else
6978                 val |= PIPECONF_PROGRESSIVE;
6979
6980         if (intel_crtc->config.limited_color_range)
6981                 val |= PIPECONF_COLOR_RANGE_SELECT;
6982
6983         I915_WRITE(PIPECONF(pipe), val);
6984         POSTING_READ(PIPECONF(pipe));
6985 }
6986
6987 /*
6988  * Set up the pipe CSC unit.
6989  *
6990  * Currently only full range RGB to limited range RGB conversion
6991  * is supported, but eventually this should handle various
6992  * RGB<->YCbCr scenarios as well.
6993  */
6994 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6995 {
6996         struct drm_device *dev = crtc->dev;
6997         struct drm_i915_private *dev_priv = dev->dev_private;
6998         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6999         int pipe = intel_crtc->pipe;
7000         uint16_t coeff = 0x7800; /* 1.0 */
7001
7002         /*
7003          * TODO: Check what kind of values actually come out of the pipe
7004          * with these coeff/postoff values and adjust to get the best
7005          * accuracy. Perhaps we even need to take the bpc value into
7006          * consideration.
7007          */
7008
7009         if (intel_crtc->config.limited_color_range)
7010                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7011
7012         /*
7013          * GY/GU and RY/RU should be the other way around according
7014          * to BSpec, but reality doesn't agree. Just set them up in
7015          * a way that results in the correct picture.
7016          */
7017         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7018         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7019
7020         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7021         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7022
7023         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7024         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7025
7026         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7027         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7028         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7029
7030         if (INTEL_INFO(dev)->gen > 6) {
7031                 uint16_t postoff = 0;
7032
7033                 if (intel_crtc->config.limited_color_range)
7034                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
7035
7036                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7037                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7038                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7039
7040                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7041         } else {
7042                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7043
7044                 if (intel_crtc->config.limited_color_range)
7045                         mode |= CSC_BLACK_SCREEN_OFFSET;
7046
7047                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7048         }
7049 }
7050
7051 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7052 {
7053         struct drm_device *dev = crtc->dev;
7054         struct drm_i915_private *dev_priv = dev->dev_private;
7055         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7056         enum pipe pipe = intel_crtc->pipe;
7057         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7058         uint32_t val;
7059
7060         val = 0;
7061
7062         if (IS_HASWELL(dev) && intel_crtc->config.dither)
7063                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7064
7065         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7066                 val |= PIPECONF_INTERLACED_ILK;
7067         else
7068                 val |= PIPECONF_PROGRESSIVE;
7069
7070         I915_WRITE(PIPECONF(cpu_transcoder), val);
7071         POSTING_READ(PIPECONF(cpu_transcoder));
7072
7073         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7074         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7075
7076         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7077                 val = 0;
7078
7079                 switch (intel_crtc->config.pipe_bpp) {
7080                 case 18:
7081                         val |= PIPEMISC_DITHER_6_BPC;
7082                         break;
7083                 case 24:
7084                         val |= PIPEMISC_DITHER_8_BPC;
7085                         break;
7086                 case 30:
7087                         val |= PIPEMISC_DITHER_10_BPC;
7088                         break;
7089                 case 36:
7090                         val |= PIPEMISC_DITHER_12_BPC;
7091                         break;
7092                 default:
7093                         /* Case prevented by pipe_config_set_bpp. */
7094                         BUG();
7095                 }
7096
7097                 if (intel_crtc->config.dither)
7098                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7099
7100                 I915_WRITE(PIPEMISC(pipe), val);
7101         }
7102 }
7103
7104 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7105                                     intel_clock_t *clock,
7106                                     bool *has_reduced_clock,
7107                                     intel_clock_t *reduced_clock)
7108 {
7109         struct drm_device *dev = crtc->dev;
7110         struct drm_i915_private *dev_priv = dev->dev_private;
7111         struct intel_encoder *intel_encoder;
7112         int refclk;
7113         const intel_limit_t *limit;
7114         bool ret, is_lvds = false;
7115
7116         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
7117                 switch (intel_encoder->type) {
7118                 case INTEL_OUTPUT_LVDS:
7119                         is_lvds = true;
7120                         break;
7121                 }
7122         }
7123
7124         refclk = ironlake_get_refclk(crtc);
7125
7126         /*
7127          * Returns a set of divisors for the desired target clock with the given
7128          * refclk, or FALSE.  The returned values represent the clock equation:
7129          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7130          */
7131         limit = intel_limit(crtc, refclk);
7132         ret = dev_priv->display.find_dpll(limit, crtc,
7133                                           to_intel_crtc(crtc)->config.port_clock,
7134                                           refclk, NULL, clock);
7135         if (!ret)
7136                 return false;
7137
7138         if (is_lvds && dev_priv->lvds_downclock_avail) {
7139                 /*
7140                  * Ensure we match the reduced clock's P to the target clock.
7141                  * If the clocks don't match, we can't switch the display clock
7142                  * by using the FP0/FP1. In such case we will disable the LVDS
7143                  * downclock feature.
7144                 */
7145                 *has_reduced_clock =
7146                         dev_priv->display.find_dpll(limit, crtc,
7147                                                     dev_priv->lvds_downclock,
7148                                                     refclk, clock,
7149                                                     reduced_clock);
7150         }
7151
7152         return true;
7153 }
7154
7155 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7156 {
7157         /*
7158          * Account for spread spectrum to avoid
7159          * oversubscribing the link. Max center spread
7160          * is 2.5%; use 5% for safety's sake.
7161          */
7162         u32 bps = target_clock * bpp * 21 / 20;
7163         return DIV_ROUND_UP(bps, link_bw * 8);
7164 }
7165
7166 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7167 {
7168         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7169 }
7170
7171 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7172                                       u32 *fp,
7173                                       intel_clock_t *reduced_clock, u32 *fp2)
7174 {
7175         struct drm_crtc *crtc = &intel_crtc->base;
7176         struct drm_device *dev = crtc->dev;
7177         struct drm_i915_private *dev_priv = dev->dev_private;
7178         struct intel_encoder *intel_encoder;
7179         uint32_t dpll;
7180         int factor, num_connectors = 0;
7181         bool is_lvds = false, is_sdvo = false;
7182
7183         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
7184                 switch (intel_encoder->type) {
7185                 case INTEL_OUTPUT_LVDS:
7186                         is_lvds = true;
7187                         break;
7188                 case INTEL_OUTPUT_SDVO:
7189                 case INTEL_OUTPUT_HDMI:
7190                         is_sdvo = true;
7191                         break;
7192                 }
7193
7194                 num_connectors++;
7195         }
7196
7197         /* Enable autotuning of the PLL clock (if permissible) */
7198         factor = 21;
7199         if (is_lvds) {
7200                 if ((intel_panel_use_ssc(dev_priv) &&
7201                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
7202                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7203                         factor = 25;
7204         } else if (intel_crtc->config.sdvo_tv_clock)
7205                 factor = 20;
7206
7207         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7208                 *fp |= FP_CB_TUNE;
7209
7210         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7211                 *fp2 |= FP_CB_TUNE;
7212
7213         dpll = 0;
7214
7215         if (is_lvds)
7216                 dpll |= DPLLB_MODE_LVDS;
7217         else
7218                 dpll |= DPLLB_MODE_DAC_SERIAL;
7219
7220         dpll |= (intel_crtc->config.pixel_multiplier - 1)
7221                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7222
7223         if (is_sdvo)
7224                 dpll |= DPLL_SDVO_HIGH_SPEED;
7225         if (intel_crtc->config.has_dp_encoder)
7226                 dpll |= DPLL_SDVO_HIGH_SPEED;
7227
7228         /* compute bitmask from p1 value */
7229         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7230         /* also FPA1 */
7231         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7232
7233         switch (intel_crtc->config.dpll.p2) {
7234         case 5:
7235                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7236                 break;
7237         case 7:
7238                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7239                 break;
7240         case 10:
7241                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7242                 break;
7243         case 14:
7244                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7245                 break;
7246         }
7247
7248         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7249                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7250         else
7251                 dpll |= PLL_REF_INPUT_DREFCLK;
7252
7253         return dpll | DPLL_VCO_ENABLE;
7254 }
7255
7256 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
7257                                   int x, int y,
7258                                   struct drm_framebuffer *fb)
7259 {
7260         struct drm_device *dev = crtc->dev;
7261         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7262         int num_connectors = 0;
7263         intel_clock_t clock, reduced_clock;
7264         u32 dpll = 0, fp = 0, fp2 = 0;
7265         bool ok, has_reduced_clock = false;
7266         bool is_lvds = false;
7267         struct intel_encoder *encoder;
7268         struct intel_shared_dpll *pll;
7269
7270         for_each_encoder_on_crtc(dev, crtc, encoder) {
7271                 switch (encoder->type) {
7272                 case INTEL_OUTPUT_LVDS:
7273                         is_lvds = true;
7274                         break;
7275                 }
7276
7277                 num_connectors++;
7278         }
7279
7280         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7281              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7282
7283         ok = ironlake_compute_clocks(crtc, &clock,
7284                                      &has_reduced_clock, &reduced_clock);
7285         if (!ok && !intel_crtc->config.clock_set) {
7286                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7287                 return -EINVAL;
7288         }
7289         /* Compat-code for transition, will disappear. */
7290         if (!intel_crtc->config.clock_set) {
7291                 intel_crtc->config.dpll.n = clock.n;
7292                 intel_crtc->config.dpll.m1 = clock.m1;
7293                 intel_crtc->config.dpll.m2 = clock.m2;
7294                 intel_crtc->config.dpll.p1 = clock.p1;
7295                 intel_crtc->config.dpll.p2 = clock.p2;
7296         }
7297
7298         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7299         if (intel_crtc->config.has_pch_encoder) {
7300                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
7301                 if (has_reduced_clock)
7302                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7303
7304                 dpll = ironlake_compute_dpll(intel_crtc,
7305                                              &fp, &reduced_clock,
7306                                              has_reduced_clock ? &fp2 : NULL);
7307
7308                 intel_crtc->config.dpll_hw_state.dpll = dpll;
7309                 intel_crtc->config.dpll_hw_state.fp0 = fp;
7310                 if (has_reduced_clock)
7311                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
7312                 else
7313                         intel_crtc->config.dpll_hw_state.fp1 = fp;
7314
7315                 pll = intel_get_shared_dpll(intel_crtc);
7316                 if (pll == NULL) {
7317                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7318                                          pipe_name(intel_crtc->pipe));
7319                         return -EINVAL;
7320                 }
7321         } else
7322                 intel_put_shared_dpll(intel_crtc);
7323
7324         if (is_lvds && has_reduced_clock && i915.powersave)
7325                 intel_crtc->lowfreq_avail = true;
7326         else
7327                 intel_crtc->lowfreq_avail = false;
7328
7329         return 0;
7330 }
7331
7332 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7333                                          struct intel_link_m_n *m_n)
7334 {
7335         struct drm_device *dev = crtc->base.dev;
7336         struct drm_i915_private *dev_priv = dev->dev_private;
7337         enum pipe pipe = crtc->pipe;
7338
7339         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7340         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7341         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7342                 & ~TU_SIZE_MASK;
7343         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7344         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7345                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7346 }
7347
7348 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7349                                          enum transcoder transcoder,
7350                                          struct intel_link_m_n *m_n,
7351                                          struct intel_link_m_n *m2_n2)
7352 {
7353         struct drm_device *dev = crtc->base.dev;
7354         struct drm_i915_private *dev_priv = dev->dev_private;
7355         enum pipe pipe = crtc->pipe;
7356
7357         if (INTEL_INFO(dev)->gen >= 5) {
7358                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7359                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7360                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7361                         & ~TU_SIZE_MASK;
7362                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7363                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7364                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7365                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7366                  * gen < 8) and if DRRS is supported (to make sure the
7367                  * registers are not unnecessarily read).
7368                  */
7369                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7370                         crtc->config.has_drrs) {
7371                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7372                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7373                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7374                                         & ~TU_SIZE_MASK;
7375                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7376                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7377                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7378                 }
7379         } else {
7380                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7381                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7382                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7383                         & ~TU_SIZE_MASK;
7384                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7385                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7386                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7387         }
7388 }
7389
7390 void intel_dp_get_m_n(struct intel_crtc *crtc,
7391                       struct intel_crtc_config *pipe_config)
7392 {
7393         if (crtc->config.has_pch_encoder)
7394                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7395         else
7396                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7397                                              &pipe_config->dp_m_n,
7398                                              &pipe_config->dp_m2_n2);
7399 }
7400
7401 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7402                                         struct intel_crtc_config *pipe_config)
7403 {
7404         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7405                                      &pipe_config->fdi_m_n, NULL);
7406 }
7407
7408 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7409                                      struct intel_crtc_config *pipe_config)
7410 {
7411         struct drm_device *dev = crtc->base.dev;
7412         struct drm_i915_private *dev_priv = dev->dev_private;
7413         uint32_t tmp;
7414
7415         tmp = I915_READ(PF_CTL(crtc->pipe));
7416
7417         if (tmp & PF_ENABLE) {
7418                 pipe_config->pch_pfit.enabled = true;
7419                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7420                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7421
7422                 /* We currently do not free assignements of panel fitters on
7423                  * ivb/hsw (since we don't use the higher upscaling modes which
7424                  * differentiates them) so just WARN about this case for now. */
7425                 if (IS_GEN7(dev)) {
7426                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7427                                 PF_PIPE_SEL_IVB(crtc->pipe));
7428                 }
7429         }
7430 }
7431
7432 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7433                                       struct intel_plane_config *plane_config)
7434 {
7435         struct drm_device *dev = crtc->base.dev;
7436         struct drm_i915_private *dev_priv = dev->dev_private;
7437         u32 val, base, offset;
7438         int pipe = crtc->pipe, plane = crtc->plane;
7439         int fourcc, pixel_format;
7440         int aligned_height;
7441
7442         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7443         if (!crtc->base.primary->fb) {
7444                 DRM_DEBUG_KMS("failed to alloc fb\n");
7445                 return;
7446         }
7447
7448         val = I915_READ(DSPCNTR(plane));
7449
7450         if (INTEL_INFO(dev)->gen >= 4)
7451                 if (val & DISPPLANE_TILED)
7452                         plane_config->tiled = true;
7453
7454         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7455         fourcc = intel_format_to_fourcc(pixel_format);
7456         crtc->base.primary->fb->pixel_format = fourcc;
7457         crtc->base.primary->fb->bits_per_pixel =
7458                 drm_format_plane_cpp(fourcc, 0) * 8;
7459
7460         base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7461         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7462                 offset = I915_READ(DSPOFFSET(plane));
7463         } else {
7464                 if (plane_config->tiled)
7465                         offset = I915_READ(DSPTILEOFF(plane));
7466                 else
7467                         offset = I915_READ(DSPLINOFF(plane));
7468         }
7469         plane_config->base = base;
7470
7471         val = I915_READ(PIPESRC(pipe));
7472         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7473         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7474
7475         val = I915_READ(DSPSTRIDE(pipe));
7476         crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7477
7478         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7479                                             plane_config->tiled);
7480
7481         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7482                                         aligned_height);
7483
7484         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7485                       pipe, plane, crtc->base.primary->fb->width,
7486                       crtc->base.primary->fb->height,
7487                       crtc->base.primary->fb->bits_per_pixel, base,
7488                       crtc->base.primary->fb->pitches[0],
7489                       plane_config->size);
7490 }
7491
7492 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7493                                      struct intel_crtc_config *pipe_config)
7494 {
7495         struct drm_device *dev = crtc->base.dev;
7496         struct drm_i915_private *dev_priv = dev->dev_private;
7497         uint32_t tmp;
7498
7499         if (!intel_display_power_is_enabled(dev_priv,
7500                                             POWER_DOMAIN_PIPE(crtc->pipe)))
7501                 return false;
7502
7503         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7504         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7505
7506         tmp = I915_READ(PIPECONF(crtc->pipe));
7507         if (!(tmp & PIPECONF_ENABLE))
7508                 return false;
7509
7510         switch (tmp & PIPECONF_BPC_MASK) {
7511         case PIPECONF_6BPC:
7512                 pipe_config->pipe_bpp = 18;
7513                 break;
7514         case PIPECONF_8BPC:
7515                 pipe_config->pipe_bpp = 24;
7516                 break;
7517         case PIPECONF_10BPC:
7518                 pipe_config->pipe_bpp = 30;
7519                 break;
7520         case PIPECONF_12BPC:
7521                 pipe_config->pipe_bpp = 36;
7522                 break;
7523         default:
7524                 break;
7525         }
7526
7527         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7528                 pipe_config->limited_color_range = true;
7529
7530         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7531                 struct intel_shared_dpll *pll;
7532
7533                 pipe_config->has_pch_encoder = true;
7534
7535                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7536                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7537                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7538
7539                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7540
7541                 if (HAS_PCH_IBX(dev_priv->dev)) {
7542                         pipe_config->shared_dpll =
7543                                 (enum intel_dpll_id) crtc->pipe;
7544                 } else {
7545                         tmp = I915_READ(PCH_DPLL_SEL);
7546                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7547                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7548                         else
7549                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7550                 }
7551
7552                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7553
7554                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7555                                            &pipe_config->dpll_hw_state));
7556
7557                 tmp = pipe_config->dpll_hw_state.dpll;
7558                 pipe_config->pixel_multiplier =
7559                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7560                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7561
7562                 ironlake_pch_clock_get(crtc, pipe_config);
7563         } else {
7564                 pipe_config->pixel_multiplier = 1;
7565         }
7566
7567         intel_get_pipe_timings(crtc, pipe_config);
7568
7569         ironlake_get_pfit_config(crtc, pipe_config);
7570
7571         return true;
7572 }
7573
7574 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7575 {
7576         struct drm_device *dev = dev_priv->dev;
7577         struct intel_crtc *crtc;
7578
7579         for_each_intel_crtc(dev, crtc)
7580                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7581                      pipe_name(crtc->pipe));
7582
7583         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7584         WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7585         WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7586         WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7587         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7588         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7589              "CPU PWM1 enabled\n");
7590         if (IS_HASWELL(dev))
7591                 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7592                      "CPU PWM2 enabled\n");
7593         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7594              "PCH PWM1 enabled\n");
7595         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7596              "Utility pin enabled\n");
7597         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7598
7599         /*
7600          * In theory we can still leave IRQs enabled, as long as only the HPD
7601          * interrupts remain enabled. We used to check for that, but since it's
7602          * gen-specific and since we only disable LCPLL after we fully disable
7603          * the interrupts, the check below should be enough.
7604          */
7605         WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7606 }
7607
7608 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7609 {
7610         struct drm_device *dev = dev_priv->dev;
7611
7612         if (IS_HASWELL(dev))
7613                 return I915_READ(D_COMP_HSW);
7614         else
7615                 return I915_READ(D_COMP_BDW);
7616 }
7617
7618 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7619 {
7620         struct drm_device *dev = dev_priv->dev;
7621
7622         if (IS_HASWELL(dev)) {
7623                 mutex_lock(&dev_priv->rps.hw_lock);
7624                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7625                                             val))
7626                         DRM_ERROR("Failed to write to D_COMP\n");
7627                 mutex_unlock(&dev_priv->rps.hw_lock);
7628         } else {
7629                 I915_WRITE(D_COMP_BDW, val);
7630                 POSTING_READ(D_COMP_BDW);
7631         }
7632 }
7633
7634 /*
7635  * This function implements pieces of two sequences from BSpec:
7636  * - Sequence for display software to disable LCPLL
7637  * - Sequence for display software to allow package C8+
7638  * The steps implemented here are just the steps that actually touch the LCPLL
7639  * register. Callers should take care of disabling all the display engine
7640  * functions, doing the mode unset, fixing interrupts, etc.
7641  */
7642 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7643                               bool switch_to_fclk, bool allow_power_down)
7644 {
7645         uint32_t val;
7646
7647         assert_can_disable_lcpll(dev_priv);
7648
7649         val = I915_READ(LCPLL_CTL);
7650
7651         if (switch_to_fclk) {
7652                 val |= LCPLL_CD_SOURCE_FCLK;
7653                 I915_WRITE(LCPLL_CTL, val);
7654
7655                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7656                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
7657                         DRM_ERROR("Switching to FCLK failed\n");
7658
7659                 val = I915_READ(LCPLL_CTL);
7660         }
7661
7662         val |= LCPLL_PLL_DISABLE;
7663         I915_WRITE(LCPLL_CTL, val);
7664         POSTING_READ(LCPLL_CTL);
7665
7666         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7667                 DRM_ERROR("LCPLL still locked\n");
7668
7669         val = hsw_read_dcomp(dev_priv);
7670         val |= D_COMP_COMP_DISABLE;
7671         hsw_write_dcomp(dev_priv, val);
7672         ndelay(100);
7673
7674         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7675                      1))
7676                 DRM_ERROR("D_COMP RCOMP still in progress\n");
7677
7678         if (allow_power_down) {
7679                 val = I915_READ(LCPLL_CTL);
7680                 val |= LCPLL_POWER_DOWN_ALLOW;
7681                 I915_WRITE(LCPLL_CTL, val);
7682                 POSTING_READ(LCPLL_CTL);
7683         }
7684 }
7685
7686 /*
7687  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7688  * source.
7689  */
7690 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7691 {
7692         uint32_t val;
7693
7694         val = I915_READ(LCPLL_CTL);
7695
7696         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7697                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7698                 return;
7699
7700         /*
7701          * Make sure we're not on PC8 state before disabling PC8, otherwise
7702          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7703          *
7704          * The other problem is that hsw_restore_lcpll() is called as part of
7705          * the runtime PM resume sequence, so we can't just call
7706          * gen6_gt_force_wake_get() because that function calls
7707          * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7708          * while we are on the resume sequence. So to solve this problem we have
7709          * to call special forcewake code that doesn't touch runtime PM and
7710          * doesn't enable the forcewake delayed work.
7711          */
7712         spin_lock_irq(&dev_priv->uncore.lock);
7713         if (dev_priv->uncore.forcewake_count++ == 0)
7714                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7715         spin_unlock_irq(&dev_priv->uncore.lock);
7716
7717         if (val & LCPLL_POWER_DOWN_ALLOW) {
7718                 val &= ~LCPLL_POWER_DOWN_ALLOW;
7719                 I915_WRITE(LCPLL_CTL, val);
7720                 POSTING_READ(LCPLL_CTL);
7721         }
7722
7723         val = hsw_read_dcomp(dev_priv);
7724         val |= D_COMP_COMP_FORCE;
7725         val &= ~D_COMP_COMP_DISABLE;
7726         hsw_write_dcomp(dev_priv, val);
7727
7728         val = I915_READ(LCPLL_CTL);
7729         val &= ~LCPLL_PLL_DISABLE;
7730         I915_WRITE(LCPLL_CTL, val);
7731
7732         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7733                 DRM_ERROR("LCPLL not locked yet\n");
7734
7735         if (val & LCPLL_CD_SOURCE_FCLK) {
7736                 val = I915_READ(LCPLL_CTL);
7737                 val &= ~LCPLL_CD_SOURCE_FCLK;
7738                 I915_WRITE(LCPLL_CTL, val);
7739
7740                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7741                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7742                         DRM_ERROR("Switching back to LCPLL failed\n");
7743         }
7744
7745         /* See the big comment above. */
7746         spin_lock_irq(&dev_priv->uncore.lock);
7747         if (--dev_priv->uncore.forcewake_count == 0)
7748                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7749         spin_unlock_irq(&dev_priv->uncore.lock);
7750 }
7751
7752 /*
7753  * Package states C8 and deeper are really deep PC states that can only be
7754  * reached when all the devices on the system allow it, so even if the graphics
7755  * device allows PC8+, it doesn't mean the system will actually get to these
7756  * states. Our driver only allows PC8+ when going into runtime PM.
7757  *
7758  * The requirements for PC8+ are that all the outputs are disabled, the power
7759  * well is disabled and most interrupts are disabled, and these are also
7760  * requirements for runtime PM. When these conditions are met, we manually do
7761  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7762  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7763  * hang the machine.
7764  *
7765  * When we really reach PC8 or deeper states (not just when we allow it) we lose
7766  * the state of some registers, so when we come back from PC8+ we need to
7767  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7768  * need to take care of the registers kept by RC6. Notice that this happens even
7769  * if we don't put the device in PCI D3 state (which is what currently happens
7770  * because of the runtime PM support).
7771  *
7772  * For more, read "Display Sequences for Package C8" on the hardware
7773  * documentation.
7774  */
7775 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7776 {
7777         struct drm_device *dev = dev_priv->dev;
7778         uint32_t val;
7779
7780         DRM_DEBUG_KMS("Enabling package C8+\n");
7781
7782         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7783                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7784                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7785                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7786         }
7787
7788         lpt_disable_clkout_dp(dev);
7789         hsw_disable_lcpll(dev_priv, true, true);
7790 }
7791
7792 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7793 {
7794         struct drm_device *dev = dev_priv->dev;
7795         uint32_t val;
7796
7797         DRM_DEBUG_KMS("Disabling package C8+\n");
7798
7799         hsw_restore_lcpll(dev_priv);
7800         lpt_init_pch_refclk(dev);
7801
7802         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7803                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7804                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7805                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7806         }
7807
7808         intel_prepare_ddi(dev);
7809 }
7810
7811 static void snb_modeset_global_resources(struct drm_device *dev)
7812 {
7813         modeset_update_crtc_power_domains(dev);
7814 }
7815
7816 static void haswell_modeset_global_resources(struct drm_device *dev)
7817 {
7818         modeset_update_crtc_power_domains(dev);
7819 }
7820
7821 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7822                                  int x, int y,
7823                                  struct drm_framebuffer *fb)
7824 {
7825         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7826
7827         if (!intel_ddi_pll_select(intel_crtc))
7828                 return -EINVAL;
7829
7830         intel_crtc->lowfreq_avail = false;
7831
7832         return 0;
7833 }
7834
7835 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7836                                 enum port port,
7837                                 struct intel_crtc_config *pipe_config)
7838 {
7839         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7840
7841         switch (pipe_config->ddi_pll_sel) {
7842         case PORT_CLK_SEL_WRPLL1:
7843                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7844                 break;
7845         case PORT_CLK_SEL_WRPLL2:
7846                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7847                 break;
7848         }
7849 }
7850
7851 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7852                                        struct intel_crtc_config *pipe_config)
7853 {
7854         struct drm_device *dev = crtc->base.dev;
7855         struct drm_i915_private *dev_priv = dev->dev_private;
7856         struct intel_shared_dpll *pll;
7857         enum port port;
7858         uint32_t tmp;
7859
7860         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7861
7862         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7863
7864         haswell_get_ddi_pll(dev_priv, port, pipe_config);
7865
7866         if (pipe_config->shared_dpll >= 0) {
7867                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7868
7869                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7870                                            &pipe_config->dpll_hw_state));
7871         }
7872
7873         /*
7874          * Haswell has only FDI/PCH transcoder A. It is which is connected to
7875          * DDI E. So just check whether this pipe is wired to DDI E and whether
7876          * the PCH transcoder is on.
7877          */
7878         if (INTEL_INFO(dev)->gen < 9 &&
7879             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7880                 pipe_config->has_pch_encoder = true;
7881
7882                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7883                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7884                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7885
7886                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7887         }
7888 }
7889
7890 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7891                                     struct intel_crtc_config *pipe_config)
7892 {
7893         struct drm_device *dev = crtc->base.dev;
7894         struct drm_i915_private *dev_priv = dev->dev_private;
7895         enum intel_display_power_domain pfit_domain;
7896         uint32_t tmp;
7897
7898         if (!intel_display_power_is_enabled(dev_priv,
7899                                          POWER_DOMAIN_PIPE(crtc->pipe)))
7900                 return false;
7901
7902         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7903         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7904
7905         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7906         if (tmp & TRANS_DDI_FUNC_ENABLE) {
7907                 enum pipe trans_edp_pipe;
7908                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7909                 default:
7910                         WARN(1, "unknown pipe linked to edp transcoder\n");
7911                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7912                 case TRANS_DDI_EDP_INPUT_A_ON:
7913                         trans_edp_pipe = PIPE_A;
7914                         break;
7915                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7916                         trans_edp_pipe = PIPE_B;
7917                         break;
7918                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7919                         trans_edp_pipe = PIPE_C;
7920                         break;
7921                 }
7922
7923                 if (trans_edp_pipe == crtc->pipe)
7924                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
7925         }
7926
7927         if (!intel_display_power_is_enabled(dev_priv,
7928                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7929                 return false;
7930
7931         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7932         if (!(tmp & PIPECONF_ENABLE))
7933                 return false;
7934
7935         haswell_get_ddi_port_state(crtc, pipe_config);
7936
7937         intel_get_pipe_timings(crtc, pipe_config);
7938
7939         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7940         if (intel_display_power_is_enabled(dev_priv, pfit_domain))
7941                 ironlake_get_pfit_config(crtc, pipe_config);
7942
7943         if (IS_HASWELL(dev))
7944                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7945                         (I915_READ(IPS_CTL) & IPS_ENABLE);
7946
7947         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
7948                 pipe_config->pixel_multiplier =
7949                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
7950         } else {
7951                 pipe_config->pixel_multiplier = 1;
7952         }
7953
7954         return true;
7955 }
7956
7957 static struct {
7958         int clock;
7959         u32 config;
7960 } hdmi_audio_clock[] = {
7961         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7962         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7963         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7964         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7965         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7966         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7967         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7968         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7969         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7970         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7971 };
7972
7973 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7974 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7975 {
7976         int i;
7977
7978         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7979                 if (mode->clock == hdmi_audio_clock[i].clock)
7980                         break;
7981         }
7982
7983         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7984                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7985                 i = 1;
7986         }
7987
7988         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7989                       hdmi_audio_clock[i].clock,
7990                       hdmi_audio_clock[i].config);
7991
7992         return hdmi_audio_clock[i].config;
7993 }
7994
7995 static bool intel_eld_uptodate(struct drm_connector *connector,
7996                                int reg_eldv, uint32_t bits_eldv,
7997                                int reg_elda, uint32_t bits_elda,
7998                                int reg_edid)
7999 {
8000         struct drm_i915_private *dev_priv = connector->dev->dev_private;
8001         uint8_t *eld = connector->eld;
8002         uint32_t i;
8003
8004         i = I915_READ(reg_eldv);
8005         i &= bits_eldv;
8006
8007         if (!eld[0])
8008                 return !i;
8009
8010         if (!i)
8011                 return false;
8012
8013         i = I915_READ(reg_elda);
8014         i &= ~bits_elda;
8015         I915_WRITE(reg_elda, i);
8016
8017         for (i = 0; i < eld[2]; i++)
8018                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
8019                         return false;
8020
8021         return true;
8022 }
8023
8024 static void g4x_write_eld(struct drm_connector *connector,
8025                           struct drm_crtc *crtc,
8026                           struct drm_display_mode *mode)
8027 {
8028         struct drm_i915_private *dev_priv = connector->dev->dev_private;
8029         uint8_t *eld = connector->eld;
8030         uint32_t eldv;
8031         uint32_t len;
8032         uint32_t i;
8033
8034         i = I915_READ(G4X_AUD_VID_DID);
8035
8036         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
8037                 eldv = G4X_ELDV_DEVCL_DEVBLC;
8038         else
8039                 eldv = G4X_ELDV_DEVCTG;
8040
8041         if (intel_eld_uptodate(connector,
8042                                G4X_AUD_CNTL_ST, eldv,
8043                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
8044                                G4X_HDMIW_HDMIEDID))
8045                 return;
8046
8047         i = I915_READ(G4X_AUD_CNTL_ST);
8048         i &= ~(eldv | G4X_ELD_ADDR);
8049         len = (i >> 9) & 0x1f;          /* ELD buffer size */
8050         I915_WRITE(G4X_AUD_CNTL_ST, i);
8051
8052         if (!eld[0])
8053                 return;
8054
8055         len = min_t(uint8_t, eld[2], len);
8056         DRM_DEBUG_DRIVER("ELD size %d\n", len);
8057         for (i = 0; i < len; i++)
8058                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
8059
8060         i = I915_READ(G4X_AUD_CNTL_ST);
8061         i |= eldv;
8062         I915_WRITE(G4X_AUD_CNTL_ST, i);
8063 }
8064
8065 static void haswell_write_eld(struct drm_connector *connector,
8066                               struct drm_crtc *crtc,
8067                               struct drm_display_mode *mode)
8068 {
8069         struct drm_i915_private *dev_priv = connector->dev->dev_private;
8070         uint8_t *eld = connector->eld;
8071         uint32_t eldv;
8072         uint32_t i;
8073         int len;
8074         int pipe = to_intel_crtc(crtc)->pipe;
8075         int tmp;
8076
8077         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
8078         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
8079         int aud_config = HSW_AUD_CFG(pipe);
8080         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
8081
8082         /* Audio output enable */
8083         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
8084         tmp = I915_READ(aud_cntrl_st2);
8085         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
8086         I915_WRITE(aud_cntrl_st2, tmp);
8087         POSTING_READ(aud_cntrl_st2);
8088
8089         assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
8090
8091         /* Set ELD valid state */
8092         tmp = I915_READ(aud_cntrl_st2);
8093         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
8094         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
8095         I915_WRITE(aud_cntrl_st2, tmp);
8096         tmp = I915_READ(aud_cntrl_st2);
8097         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
8098
8099         /* Enable HDMI mode */
8100         tmp = I915_READ(aud_config);
8101         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
8102         /* clear N_programing_enable and N_value_index */
8103         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
8104         I915_WRITE(aud_config, tmp);
8105
8106         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
8107
8108         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
8109
8110         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
8111                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8112                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
8113                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
8114         } else {
8115                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
8116         }
8117
8118         if (intel_eld_uptodate(connector,
8119                                aud_cntrl_st2, eldv,
8120                                aud_cntl_st, IBX_ELD_ADDRESS,
8121                                hdmiw_hdmiedid))
8122                 return;
8123
8124         i = I915_READ(aud_cntrl_st2);
8125         i &= ~eldv;
8126         I915_WRITE(aud_cntrl_st2, i);
8127
8128         if (!eld[0])
8129                 return;
8130
8131         i = I915_READ(aud_cntl_st);
8132         i &= ~IBX_ELD_ADDRESS;
8133         I915_WRITE(aud_cntl_st, i);
8134         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
8135         DRM_DEBUG_DRIVER("port num:%d\n", i);
8136
8137         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
8138         DRM_DEBUG_DRIVER("ELD size %d\n", len);
8139         for (i = 0; i < len; i++)
8140                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
8141
8142         i = I915_READ(aud_cntrl_st2);
8143         i |= eldv;
8144         I915_WRITE(aud_cntrl_st2, i);
8145
8146 }
8147
8148 static void ironlake_write_eld(struct drm_connector *connector,
8149                                struct drm_crtc *crtc,
8150                                struct drm_display_mode *mode)
8151 {
8152         struct drm_i915_private *dev_priv = connector->dev->dev_private;
8153         uint8_t *eld = connector->eld;
8154         uint32_t eldv;
8155         uint32_t i;
8156         int len;
8157         int hdmiw_hdmiedid;
8158         int aud_config;
8159         int aud_cntl_st;
8160         int aud_cntrl_st2;
8161         int pipe = to_intel_crtc(crtc)->pipe;
8162
8163         if (HAS_PCH_IBX(connector->dev)) {
8164                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
8165                 aud_config = IBX_AUD_CFG(pipe);
8166                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
8167                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
8168         } else if (IS_VALLEYVIEW(connector->dev)) {
8169                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
8170                 aud_config = VLV_AUD_CFG(pipe);
8171                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
8172                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
8173         } else {
8174                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
8175                 aud_config = CPT_AUD_CFG(pipe);
8176                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
8177                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
8178         }
8179
8180         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
8181
8182         if (IS_VALLEYVIEW(connector->dev))  {
8183                 struct intel_encoder *intel_encoder;
8184                 struct intel_digital_port *intel_dig_port;
8185
8186                 intel_encoder = intel_attached_encoder(connector);
8187                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
8188                 i = intel_dig_port->port;
8189         } else {
8190                 i = I915_READ(aud_cntl_st);
8191                 i = (i >> 29) & DIP_PORT_SEL_MASK;
8192                 /* DIP_Port_Select, 0x1 = PortB */
8193         }
8194
8195         if (!i) {
8196                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
8197                 /* operate blindly on all ports */
8198                 eldv = IBX_ELD_VALIDB;
8199                 eldv |= IBX_ELD_VALIDB << 4;
8200                 eldv |= IBX_ELD_VALIDB << 8;
8201         } else {
8202                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
8203                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
8204         }
8205
8206         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
8207                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8208                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
8209                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
8210         } else {
8211                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
8212         }
8213
8214         if (intel_eld_uptodate(connector,
8215                                aud_cntrl_st2, eldv,
8216                                aud_cntl_st, IBX_ELD_ADDRESS,
8217                                hdmiw_hdmiedid))
8218                 return;
8219
8220         i = I915_READ(aud_cntrl_st2);
8221         i &= ~eldv;
8222         I915_WRITE(aud_cntrl_st2, i);
8223
8224         if (!eld[0])
8225                 return;
8226
8227         i = I915_READ(aud_cntl_st);
8228         i &= ~IBX_ELD_ADDRESS;
8229         I915_WRITE(aud_cntl_st, i);
8230
8231         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
8232         DRM_DEBUG_DRIVER("ELD size %d\n", len);
8233         for (i = 0; i < len; i++)
8234                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
8235
8236         i = I915_READ(aud_cntrl_st2);
8237         i |= eldv;
8238         I915_WRITE(aud_cntrl_st2, i);
8239 }
8240
8241 void intel_write_eld(struct drm_encoder *encoder,
8242                      struct drm_display_mode *mode)
8243 {
8244         struct drm_crtc *crtc = encoder->crtc;
8245         struct drm_connector *connector;
8246         struct drm_device *dev = encoder->dev;
8247         struct drm_i915_private *dev_priv = dev->dev_private;
8248
8249         connector = drm_select_eld(encoder, mode);
8250         if (!connector)
8251                 return;
8252
8253         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8254                          connector->base.id,
8255                          connector->name,
8256                          connector->encoder->base.id,
8257                          connector->encoder->name);
8258
8259         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
8260
8261         if (dev_priv->display.write_eld)
8262                 dev_priv->display.write_eld(connector, crtc, mode);
8263 }
8264
8265 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8266 {
8267         struct drm_device *dev = crtc->dev;
8268         struct drm_i915_private *dev_priv = dev->dev_private;
8269         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8270         uint32_t cntl = 0, size = 0;
8271
8272         if (base) {
8273                 unsigned int width = intel_crtc->cursor_width;
8274                 unsigned int height = intel_crtc->cursor_height;
8275                 unsigned int stride = roundup_pow_of_two(width) * 4;
8276
8277                 switch (stride) {
8278                 default:
8279                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8280                                   width, stride);
8281                         stride = 256;
8282                         /* fallthrough */
8283                 case 256:
8284                 case 512:
8285                 case 1024:
8286                 case 2048:
8287                         break;
8288                 }
8289
8290                 cntl |= CURSOR_ENABLE |
8291                         CURSOR_GAMMA_ENABLE |
8292                         CURSOR_FORMAT_ARGB |
8293                         CURSOR_STRIDE(stride);
8294
8295                 size = (height << 12) | width;
8296         }
8297
8298         if (intel_crtc->cursor_cntl != 0 &&
8299             (intel_crtc->cursor_base != base ||
8300              intel_crtc->cursor_size != size ||
8301              intel_crtc->cursor_cntl != cntl)) {
8302                 /* On these chipsets we can only modify the base/size/stride
8303                  * whilst the cursor is disabled.
8304                  */
8305                 I915_WRITE(_CURACNTR, 0);
8306                 POSTING_READ(_CURACNTR);
8307                 intel_crtc->cursor_cntl = 0;
8308         }
8309
8310         if (intel_crtc->cursor_base != base) {
8311                 I915_WRITE(_CURABASE, base);
8312                 intel_crtc->cursor_base = base;
8313         }
8314
8315         if (intel_crtc->cursor_size != size) {
8316                 I915_WRITE(CURSIZE, size);
8317                 intel_crtc->cursor_size = size;
8318         }
8319
8320         if (intel_crtc->cursor_cntl != cntl) {
8321                 I915_WRITE(_CURACNTR, cntl);
8322                 POSTING_READ(_CURACNTR);
8323                 intel_crtc->cursor_cntl = cntl;
8324         }
8325 }
8326
8327 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8328 {
8329         struct drm_device *dev = crtc->dev;
8330         struct drm_i915_private *dev_priv = dev->dev_private;
8331         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8332         int pipe = intel_crtc->pipe;
8333         uint32_t cntl;
8334
8335         cntl = 0;
8336         if (base) {
8337                 cntl = MCURSOR_GAMMA_ENABLE;
8338                 switch (intel_crtc->cursor_width) {
8339                         case 64:
8340                                 cntl |= CURSOR_MODE_64_ARGB_AX;
8341                                 break;
8342                         case 128:
8343                                 cntl |= CURSOR_MODE_128_ARGB_AX;
8344                                 break;
8345                         case 256:
8346                                 cntl |= CURSOR_MODE_256_ARGB_AX;
8347                                 break;
8348                         default:
8349                                 WARN_ON(1);
8350                                 return;
8351                 }
8352                 cntl |= pipe << 28; /* Connect to correct pipe */
8353
8354                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8355                         cntl |= CURSOR_PIPE_CSC_ENABLE;
8356         }
8357
8358         if (intel_crtc->cursor_cntl != cntl) {
8359                 I915_WRITE(CURCNTR(pipe), cntl);
8360                 POSTING_READ(CURCNTR(pipe));
8361                 intel_crtc->cursor_cntl = cntl;
8362         }
8363
8364         /* and commit changes on next vblank */
8365         I915_WRITE(CURBASE(pipe), base);
8366         POSTING_READ(CURBASE(pipe));
8367
8368         intel_crtc->cursor_base = base;
8369 }
8370
8371 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8372 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8373                                      bool on)
8374 {
8375         struct drm_device *dev = crtc->dev;
8376         struct drm_i915_private *dev_priv = dev->dev_private;
8377         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8378         int pipe = intel_crtc->pipe;
8379         int x = crtc->cursor_x;
8380         int y = crtc->cursor_y;
8381         u32 base = 0, pos = 0;
8382
8383         if (on)
8384                 base = intel_crtc->cursor_addr;
8385
8386         if (x >= intel_crtc->config.pipe_src_w)
8387                 base = 0;
8388
8389         if (y >= intel_crtc->config.pipe_src_h)
8390                 base = 0;
8391
8392         if (x < 0) {
8393                 if (x + intel_crtc->cursor_width <= 0)
8394                         base = 0;
8395
8396                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8397                 x = -x;
8398         }
8399         pos |= x << CURSOR_X_SHIFT;
8400
8401         if (y < 0) {
8402                 if (y + intel_crtc->cursor_height <= 0)
8403                         base = 0;
8404
8405                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8406                 y = -y;
8407         }
8408         pos |= y << CURSOR_Y_SHIFT;
8409
8410         if (base == 0 && intel_crtc->cursor_base == 0)
8411                 return;
8412
8413         I915_WRITE(CURPOS(pipe), pos);
8414
8415         if (IS_845G(dev) || IS_I865G(dev))
8416                 i845_update_cursor(crtc, base);
8417         else
8418                 i9xx_update_cursor(crtc, base);
8419 }
8420
8421 static bool cursor_size_ok(struct drm_device *dev,
8422                            uint32_t width, uint32_t height)
8423 {
8424         if (width == 0 || height == 0)
8425                 return false;
8426
8427         /*
8428          * 845g/865g are special in that they are only limited by
8429          * the width of their cursors, the height is arbitrary up to
8430          * the precision of the register. Everything else requires
8431          * square cursors, limited to a few power-of-two sizes.
8432          */
8433         if (IS_845G(dev) || IS_I865G(dev)) {
8434                 if ((width & 63) != 0)
8435                         return false;
8436
8437                 if (width > (IS_845G(dev) ? 64 : 512))
8438                         return false;
8439
8440                 if (height > 1023)
8441                         return false;
8442         } else {
8443                 switch (width | height) {
8444                 case 256:
8445                 case 128:
8446                         if (IS_GEN2(dev))
8447                                 return false;
8448                 case 64:
8449                         break;
8450                 default:
8451                         return false;
8452                 }
8453         }
8454
8455         return true;
8456 }
8457
8458 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8459                                      struct drm_i915_gem_object *obj,
8460                                      uint32_t width, uint32_t height)
8461 {
8462         struct drm_device *dev = crtc->dev;
8463         struct drm_i915_private *dev_priv = dev->dev_private;
8464         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8465         enum pipe pipe = intel_crtc->pipe;
8466         unsigned old_width;
8467         uint32_t addr;
8468         int ret;
8469
8470         /* if we want to turn off the cursor ignore width and height */
8471         if (!obj) {
8472                 DRM_DEBUG_KMS("cursor off\n");
8473                 addr = 0;
8474                 mutex_lock(&dev->struct_mutex);
8475                 goto finish;
8476         }
8477
8478         /* we only need to pin inside GTT if cursor is non-phy */
8479         mutex_lock(&dev->struct_mutex);
8480         if (!INTEL_INFO(dev)->cursor_needs_physical) {
8481                 unsigned alignment;
8482
8483                 /*
8484                  * Global gtt pte registers are special registers which actually
8485                  * forward writes to a chunk of system memory. Which means that
8486                  * there is no risk that the register values disappear as soon
8487                  * as we call intel_runtime_pm_put(), so it is correct to wrap
8488                  * only the pin/unpin/fence and not more.
8489                  */
8490                 intel_runtime_pm_get(dev_priv);
8491
8492                 /* Note that the w/a also requires 2 PTE of padding following
8493                  * the bo. We currently fill all unused PTE with the shadow
8494                  * page and so we should always have valid PTE following the
8495                  * cursor preventing the VT-d warning.
8496                  */
8497                 alignment = 0;
8498                 if (need_vtd_wa(dev))
8499                         alignment = 64*1024;
8500
8501                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8502                 if (ret) {
8503                         DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8504                         intel_runtime_pm_put(dev_priv);
8505                         goto fail_locked;
8506                 }
8507
8508                 ret = i915_gem_object_put_fence(obj);
8509                 if (ret) {
8510                         DRM_DEBUG_KMS("failed to release fence for cursor");
8511                         intel_runtime_pm_put(dev_priv);
8512                         goto fail_unpin;
8513                 }
8514
8515                 addr = i915_gem_obj_ggtt_offset(obj);
8516
8517                 intel_runtime_pm_put(dev_priv);
8518         } else {
8519                 int align = IS_I830(dev) ? 16 * 1024 : 256;
8520                 ret = i915_gem_object_attach_phys(obj, align);
8521                 if (ret) {
8522                         DRM_DEBUG_KMS("failed to attach phys object\n");
8523                         goto fail_locked;
8524                 }
8525                 addr = obj->phys_handle->busaddr;
8526         }
8527
8528  finish:
8529         if (intel_crtc->cursor_bo) {
8530                 if (!INTEL_INFO(dev)->cursor_needs_physical)
8531                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8532         }
8533
8534         i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8535                           INTEL_FRONTBUFFER_CURSOR(pipe));
8536         mutex_unlock(&dev->struct_mutex);
8537
8538         old_width = intel_crtc->cursor_width;
8539
8540         intel_crtc->cursor_addr = addr;
8541         intel_crtc->cursor_bo = obj;
8542         intel_crtc->cursor_width = width;
8543         intel_crtc->cursor_height = height;
8544
8545         if (intel_crtc->active) {
8546                 if (old_width != width)
8547                         intel_update_watermarks(crtc);
8548                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8549         }
8550
8551         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8552
8553         return 0;
8554 fail_unpin:
8555         i915_gem_object_unpin_from_display_plane(obj);
8556 fail_locked:
8557         mutex_unlock(&dev->struct_mutex);
8558         return ret;
8559 }
8560
8561 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8562                                  u16 *blue, uint32_t start, uint32_t size)
8563 {
8564         int end = (start + size > 256) ? 256 : start + size, i;
8565         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8566
8567         for (i = start; i < end; i++) {
8568                 intel_crtc->lut_r[i] = red[i] >> 8;
8569                 intel_crtc->lut_g[i] = green[i] >> 8;
8570                 intel_crtc->lut_b[i] = blue[i] >> 8;
8571         }
8572
8573         intel_crtc_load_lut(crtc);
8574 }
8575
8576 /* VESA 640x480x72Hz mode to set on the pipe */
8577 static struct drm_display_mode load_detect_mode = {
8578         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8579                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8580 };
8581
8582 struct drm_framebuffer *
8583 __intel_framebuffer_create(struct drm_device *dev,
8584                            struct drm_mode_fb_cmd2 *mode_cmd,
8585                            struct drm_i915_gem_object *obj)
8586 {
8587         struct intel_framebuffer *intel_fb;
8588         int ret;
8589
8590         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8591         if (!intel_fb) {
8592                 drm_gem_object_unreference_unlocked(&obj->base);
8593                 return ERR_PTR(-ENOMEM);
8594         }
8595
8596         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8597         if (ret)
8598                 goto err;
8599
8600         return &intel_fb->base;
8601 err:
8602         drm_gem_object_unreference_unlocked(&obj->base);
8603         kfree(intel_fb);
8604
8605         return ERR_PTR(ret);
8606 }
8607
8608 static struct drm_framebuffer *
8609 intel_framebuffer_create(struct drm_device *dev,
8610                          struct drm_mode_fb_cmd2 *mode_cmd,
8611                          struct drm_i915_gem_object *obj)
8612 {
8613         struct drm_framebuffer *fb;
8614         int ret;
8615
8616         ret = i915_mutex_lock_interruptible(dev);
8617         if (ret)
8618                 return ERR_PTR(ret);
8619         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8620         mutex_unlock(&dev->struct_mutex);
8621
8622         return fb;
8623 }
8624
8625 static u32
8626 intel_framebuffer_pitch_for_width(int width, int bpp)
8627 {
8628         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8629         return ALIGN(pitch, 64);
8630 }
8631
8632 static u32
8633 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8634 {
8635         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8636         return PAGE_ALIGN(pitch * mode->vdisplay);
8637 }
8638
8639 static struct drm_framebuffer *
8640 intel_framebuffer_create_for_mode(struct drm_device *dev,
8641                                   struct drm_display_mode *mode,
8642                                   int depth, int bpp)
8643 {
8644         struct drm_i915_gem_object *obj;
8645         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8646
8647         obj = i915_gem_alloc_object(dev,
8648                                     intel_framebuffer_size_for_mode(mode, bpp));
8649         if (obj == NULL)
8650                 return ERR_PTR(-ENOMEM);
8651
8652         mode_cmd.width = mode->hdisplay;
8653         mode_cmd.height = mode->vdisplay;
8654         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8655                                                                 bpp);
8656         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8657
8658         return intel_framebuffer_create(dev, &mode_cmd, obj);
8659 }
8660
8661 static struct drm_framebuffer *
8662 mode_fits_in_fbdev(struct drm_device *dev,
8663                    struct drm_display_mode *mode)
8664 {
8665 #ifdef CONFIG_DRM_I915_FBDEV
8666         struct drm_i915_private *dev_priv = dev->dev_private;
8667         struct drm_i915_gem_object *obj;
8668         struct drm_framebuffer *fb;
8669
8670         if (!dev_priv->fbdev)
8671                 return NULL;
8672
8673         if (!dev_priv->fbdev->fb)
8674                 return NULL;
8675
8676         obj = dev_priv->fbdev->fb->obj;
8677         BUG_ON(!obj);
8678
8679         fb = &dev_priv->fbdev->fb->base;
8680         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8681                                                                fb->bits_per_pixel))
8682                 return NULL;
8683
8684         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8685                 return NULL;
8686
8687         return fb;
8688 #else
8689         return NULL;
8690 #endif
8691 }
8692
8693 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8694                                 struct drm_display_mode *mode,
8695                                 struct intel_load_detect_pipe *old,
8696                                 struct drm_modeset_acquire_ctx *ctx)
8697 {
8698         struct intel_crtc *intel_crtc;
8699         struct intel_encoder *intel_encoder =
8700                 intel_attached_encoder(connector);
8701         struct drm_crtc *possible_crtc;
8702         struct drm_encoder *encoder = &intel_encoder->base;
8703         struct drm_crtc *crtc = NULL;
8704         struct drm_device *dev = encoder->dev;
8705         struct drm_framebuffer *fb;
8706         struct drm_mode_config *config = &dev->mode_config;
8707         int ret, i = -1;
8708
8709         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8710                       connector->base.id, connector->name,
8711                       encoder->base.id, encoder->name);
8712
8713 retry:
8714         ret = drm_modeset_lock(&config->connection_mutex, ctx);
8715         if (ret)
8716                 goto fail_unlock;
8717
8718         /*
8719          * Algorithm gets a little messy:
8720          *
8721          *   - if the connector already has an assigned crtc, use it (but make
8722          *     sure it's on first)
8723          *
8724          *   - try to find the first unused crtc that can drive this connector,
8725          *     and use that if we find one
8726          */
8727
8728         /* See if we already have a CRTC for this connector */
8729         if (encoder->crtc) {
8730                 crtc = encoder->crtc;
8731
8732                 ret = drm_modeset_lock(&crtc->mutex, ctx);
8733                 if (ret)
8734                         goto fail_unlock;
8735
8736                 old->dpms_mode = connector->dpms;
8737                 old->load_detect_temp = false;
8738
8739                 /* Make sure the crtc and connector are running */
8740                 if (connector->dpms != DRM_MODE_DPMS_ON)
8741                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8742
8743                 return true;
8744         }
8745
8746         /* Find an unused one (if possible) */
8747         for_each_crtc(dev, possible_crtc) {
8748                 i++;
8749                 if (!(encoder->possible_crtcs & (1 << i)))
8750                         continue;
8751                 if (possible_crtc->enabled)
8752                         continue;
8753                 /* This can occur when applying the pipe A quirk on resume. */
8754                 if (to_intel_crtc(possible_crtc)->new_enabled)
8755                         continue;
8756
8757                 crtc = possible_crtc;
8758                 break;
8759         }
8760
8761         /*
8762          * If we didn't find an unused CRTC, don't use any.
8763          */
8764         if (!crtc) {
8765                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8766                 goto fail_unlock;
8767         }
8768
8769         ret = drm_modeset_lock(&crtc->mutex, ctx);
8770         if (ret)
8771                 goto fail_unlock;
8772         intel_encoder->new_crtc = to_intel_crtc(crtc);
8773         to_intel_connector(connector)->new_encoder = intel_encoder;
8774
8775         intel_crtc = to_intel_crtc(crtc);
8776         intel_crtc->new_enabled = true;
8777         intel_crtc->new_config = &intel_crtc->config;
8778         old->dpms_mode = connector->dpms;
8779         old->load_detect_temp = true;
8780         old->release_fb = NULL;
8781
8782         if (!mode)
8783                 mode = &load_detect_mode;
8784
8785         /* We need a framebuffer large enough to accommodate all accesses
8786          * that the plane may generate whilst we perform load detection.
8787          * We can not rely on the fbcon either being present (we get called
8788          * during its initialisation to detect all boot displays, or it may
8789          * not even exist) or that it is large enough to satisfy the
8790          * requested mode.
8791          */
8792         fb = mode_fits_in_fbdev(dev, mode);
8793         if (fb == NULL) {
8794                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8795                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8796                 old->release_fb = fb;
8797         } else
8798                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8799         if (IS_ERR(fb)) {
8800                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8801                 goto fail;
8802         }
8803
8804         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8805                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8806                 if (old->release_fb)
8807                         old->release_fb->funcs->destroy(old->release_fb);
8808                 goto fail;
8809         }
8810
8811         /* let the connector get through one full cycle before testing */
8812         intel_wait_for_vblank(dev, intel_crtc->pipe);
8813         return true;
8814
8815  fail:
8816         intel_crtc->new_enabled = crtc->enabled;
8817         if (intel_crtc->new_enabled)
8818                 intel_crtc->new_config = &intel_crtc->config;
8819         else
8820                 intel_crtc->new_config = NULL;
8821 fail_unlock:
8822         if (ret == -EDEADLK) {
8823                 drm_modeset_backoff(ctx);
8824                 goto retry;
8825         }
8826
8827         return false;
8828 }
8829
8830 void intel_release_load_detect_pipe(struct drm_connector *connector,
8831                                     struct intel_load_detect_pipe *old)
8832 {
8833         struct intel_encoder *intel_encoder =
8834                 intel_attached_encoder(connector);
8835         struct drm_encoder *encoder = &intel_encoder->base;
8836         struct drm_crtc *crtc = encoder->crtc;
8837         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8838
8839         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8840                       connector->base.id, connector->name,
8841                       encoder->base.id, encoder->name);
8842
8843         if (old->load_detect_temp) {
8844                 to_intel_connector(connector)->new_encoder = NULL;
8845                 intel_encoder->new_crtc = NULL;
8846                 intel_crtc->new_enabled = false;
8847                 intel_crtc->new_config = NULL;
8848                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8849
8850                 if (old->release_fb) {
8851                         drm_framebuffer_unregister_private(old->release_fb);
8852                         drm_framebuffer_unreference(old->release_fb);
8853                 }
8854
8855                 return;
8856         }
8857
8858         /* Switch crtc and encoder back off if necessary */
8859         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8860                 connector->funcs->dpms(connector, old->dpms_mode);
8861 }
8862
8863 static int i9xx_pll_refclk(struct drm_device *dev,
8864                            const struct intel_crtc_config *pipe_config)
8865 {
8866         struct drm_i915_private *dev_priv = dev->dev_private;
8867         u32 dpll = pipe_config->dpll_hw_state.dpll;
8868
8869         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8870                 return dev_priv->vbt.lvds_ssc_freq;
8871         else if (HAS_PCH_SPLIT(dev))
8872                 return 120000;
8873         else if (!IS_GEN2(dev))
8874                 return 96000;
8875         else
8876                 return 48000;
8877 }
8878
8879 /* Returns the clock of the currently programmed mode of the given pipe. */
8880 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8881                                 struct intel_crtc_config *pipe_config)
8882 {
8883         struct drm_device *dev = crtc->base.dev;
8884         struct drm_i915_private *dev_priv = dev->dev_private;
8885         int pipe = pipe_config->cpu_transcoder;
8886         u32 dpll = pipe_config->dpll_hw_state.dpll;
8887         u32 fp;
8888         intel_clock_t clock;
8889         int refclk = i9xx_pll_refclk(dev, pipe_config);
8890
8891         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8892                 fp = pipe_config->dpll_hw_state.fp0;
8893         else
8894                 fp = pipe_config->dpll_hw_state.fp1;
8895
8896         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8897         if (IS_PINEVIEW(dev)) {
8898                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8899                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8900         } else {
8901                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8902                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8903         }
8904
8905         if (!IS_GEN2(dev)) {
8906                 if (IS_PINEVIEW(dev))
8907                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8908                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8909                 else
8910                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8911                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8912
8913                 switch (dpll & DPLL_MODE_MASK) {
8914                 case DPLLB_MODE_DAC_SERIAL:
8915                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8916                                 5 : 10;
8917                         break;
8918                 case DPLLB_MODE_LVDS:
8919                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8920                                 7 : 14;
8921                         break;
8922                 default:
8923                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8924                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8925                         return;
8926                 }
8927
8928                 if (IS_PINEVIEW(dev))
8929                         pineview_clock(refclk, &clock);
8930                 else
8931                         i9xx_clock(refclk, &clock);
8932         } else {
8933                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8934                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8935
8936                 if (is_lvds) {
8937                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8938                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8939
8940                         if (lvds & LVDS_CLKB_POWER_UP)
8941                                 clock.p2 = 7;
8942                         else
8943                                 clock.p2 = 14;
8944                 } else {
8945                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8946                                 clock.p1 = 2;
8947                         else {
8948                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8949                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8950                         }
8951                         if (dpll & PLL_P2_DIVIDE_BY_4)
8952                                 clock.p2 = 4;
8953                         else
8954                                 clock.p2 = 2;
8955                 }
8956
8957                 i9xx_clock(refclk, &clock);
8958         }
8959
8960         /*
8961          * This value includes pixel_multiplier. We will use
8962          * port_clock to compute adjusted_mode.crtc_clock in the
8963          * encoder's get_config() function.
8964          */
8965         pipe_config->port_clock = clock.dot;
8966 }
8967
8968 int intel_dotclock_calculate(int link_freq,
8969                              const struct intel_link_m_n *m_n)
8970 {
8971         /*
8972          * The calculation for the data clock is:
8973          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8974          * But we want to avoid losing precison if possible, so:
8975          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8976          *
8977          * and the link clock is simpler:
8978          * link_clock = (m * link_clock) / n
8979          */
8980
8981         if (!m_n->link_n)
8982                 return 0;
8983
8984         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8985 }
8986
8987 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8988                                    struct intel_crtc_config *pipe_config)
8989 {
8990         struct drm_device *dev = crtc->base.dev;
8991
8992         /* read out port_clock from the DPLL */
8993         i9xx_crtc_clock_get(crtc, pipe_config);
8994
8995         /*
8996          * This value does not include pixel_multiplier.
8997          * We will check that port_clock and adjusted_mode.crtc_clock
8998          * agree once we know their relationship in the encoder's
8999          * get_config() function.
9000          */
9001         pipe_config->adjusted_mode.crtc_clock =
9002                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
9003                                          &pipe_config->fdi_m_n);
9004 }
9005
9006 /** Returns the currently programmed mode of the given pipe. */
9007 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9008                                              struct drm_crtc *crtc)
9009 {
9010         struct drm_i915_private *dev_priv = dev->dev_private;
9011         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9012         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
9013         struct drm_display_mode *mode;
9014         struct intel_crtc_config pipe_config;
9015         int htot = I915_READ(HTOTAL(cpu_transcoder));
9016         int hsync = I915_READ(HSYNC(cpu_transcoder));
9017         int vtot = I915_READ(VTOTAL(cpu_transcoder));
9018         int vsync = I915_READ(VSYNC(cpu_transcoder));
9019         enum pipe pipe = intel_crtc->pipe;
9020
9021         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9022         if (!mode)
9023                 return NULL;
9024
9025         /*
9026          * Construct a pipe_config sufficient for getting the clock info
9027          * back out of crtc_clock_get.
9028          *
9029          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9030          * to use a real value here instead.
9031          */
9032         pipe_config.cpu_transcoder = (enum transcoder) pipe;
9033         pipe_config.pixel_multiplier = 1;
9034         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9035         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9036         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9037         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9038
9039         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
9040         mode->hdisplay = (htot & 0xffff) + 1;
9041         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9042         mode->hsync_start = (hsync & 0xffff) + 1;
9043         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9044         mode->vdisplay = (vtot & 0xffff) + 1;
9045         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9046         mode->vsync_start = (vsync & 0xffff) + 1;
9047         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9048
9049         drm_mode_set_name(mode);
9050
9051         return mode;
9052 }
9053
9054 static void intel_decrease_pllclock(struct drm_crtc *crtc)
9055 {
9056         struct drm_device *dev = crtc->dev;
9057         struct drm_i915_private *dev_priv = dev->dev_private;
9058         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9059
9060         if (!HAS_GMCH_DISPLAY(dev))
9061                 return;
9062
9063         if (!dev_priv->lvds_downclock_avail)
9064                 return;
9065
9066         /*
9067          * Since this is called by a timer, we should never get here in
9068          * the manual case.
9069          */
9070         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9071                 int pipe = intel_crtc->pipe;
9072                 int dpll_reg = DPLL(pipe);
9073                 int dpll;
9074
9075                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9076
9077                 assert_panel_unlocked(dev_priv, pipe);
9078
9079                 dpll = I915_READ(dpll_reg);
9080                 dpll |= DISPLAY_RATE_SELECT_FPA1;
9081                 I915_WRITE(dpll_reg, dpll);
9082                 intel_wait_for_vblank(dev, pipe);
9083                 dpll = I915_READ(dpll_reg);
9084                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9085                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9086         }
9087
9088 }
9089
9090 void intel_mark_busy(struct drm_device *dev)
9091 {
9092         struct drm_i915_private *dev_priv = dev->dev_private;
9093
9094         if (dev_priv->mm.busy)
9095                 return;
9096
9097         intel_runtime_pm_get(dev_priv);
9098         i915_update_gfx_val(dev_priv);
9099         dev_priv->mm.busy = true;
9100 }
9101
9102 void intel_mark_idle(struct drm_device *dev)
9103 {
9104         struct drm_i915_private *dev_priv = dev->dev_private;
9105         struct drm_crtc *crtc;
9106
9107         if (!dev_priv->mm.busy)
9108                 return;
9109
9110         dev_priv->mm.busy = false;
9111
9112         if (!i915.powersave)
9113                 goto out;
9114
9115         for_each_crtc(dev, crtc) {
9116                 if (!crtc->primary->fb)
9117                         continue;
9118
9119                 intel_decrease_pllclock(crtc);
9120         }
9121
9122         if (INTEL_INFO(dev)->gen >= 6)
9123                 gen6_rps_idle(dev->dev_private);
9124
9125 out:
9126         intel_runtime_pm_put(dev_priv);
9127 }
9128
9129 static void intel_crtc_destroy(struct drm_crtc *crtc)
9130 {
9131         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9132         struct drm_device *dev = crtc->dev;
9133         struct intel_unpin_work *work;
9134
9135         spin_lock_irq(&dev->event_lock);
9136         work = intel_crtc->unpin_work;
9137         intel_crtc->unpin_work = NULL;
9138         spin_unlock_irq(&dev->event_lock);
9139
9140         if (work) {
9141                 cancel_work_sync(&work->work);
9142                 kfree(work);
9143         }
9144
9145         drm_crtc_cleanup(crtc);
9146
9147         kfree(intel_crtc);
9148 }
9149
9150 static void intel_unpin_work_fn(struct work_struct *__work)
9151 {
9152         struct intel_unpin_work *work =
9153                 container_of(__work, struct intel_unpin_work, work);
9154         struct drm_device *dev = work->crtc->dev;
9155         enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9156
9157         mutex_lock(&dev->struct_mutex);
9158         intel_unpin_fb_obj(work->old_fb_obj);
9159         drm_gem_object_unreference(&work->pending_flip_obj->base);
9160         drm_gem_object_unreference(&work->old_fb_obj->base);
9161
9162         intel_update_fbc(dev);
9163         mutex_unlock(&dev->struct_mutex);
9164
9165         intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9166
9167         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9168         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9169
9170         kfree(work);
9171 }
9172
9173 static void do_intel_finish_page_flip(struct drm_device *dev,
9174                                       struct drm_crtc *crtc)
9175 {
9176         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9177         struct intel_unpin_work *work;
9178         unsigned long flags;
9179
9180         /* Ignore early vblank irqs */
9181         if (intel_crtc == NULL)
9182                 return;
9183
9184         /*
9185          * This is called both by irq handlers and the reset code (to complete
9186          * lost pageflips) so needs the full irqsave spinlocks.
9187          */
9188         spin_lock_irqsave(&dev->event_lock, flags);
9189         work = intel_crtc->unpin_work;
9190
9191         /* Ensure we don't miss a work->pending update ... */
9192         smp_rmb();
9193
9194         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9195                 spin_unlock_irqrestore(&dev->event_lock, flags);
9196                 return;
9197         }
9198
9199         page_flip_completed(intel_crtc);
9200
9201         spin_unlock_irqrestore(&dev->event_lock, flags);
9202 }
9203
9204 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9205 {
9206         struct drm_i915_private *dev_priv = dev->dev_private;
9207         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9208
9209         do_intel_finish_page_flip(dev, crtc);
9210 }
9211
9212 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9213 {
9214         struct drm_i915_private *dev_priv = dev->dev_private;
9215         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9216
9217         do_intel_finish_page_flip(dev, crtc);
9218 }
9219
9220 /* Is 'a' after or equal to 'b'? */
9221 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9222 {
9223         return !((a - b) & 0x80000000);
9224 }
9225
9226 static bool page_flip_finished(struct intel_crtc *crtc)
9227 {
9228         struct drm_device *dev = crtc->base.dev;
9229         struct drm_i915_private *dev_priv = dev->dev_private;
9230
9231         /*
9232          * The relevant registers doen't exist on pre-ctg.
9233          * As the flip done interrupt doesn't trigger for mmio
9234          * flips on gmch platforms, a flip count check isn't
9235          * really needed there. But since ctg has the registers,
9236          * include it in the check anyway.
9237          */
9238         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9239                 return true;
9240
9241         /*
9242          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9243          * used the same base address. In that case the mmio flip might
9244          * have completed, but the CS hasn't even executed the flip yet.
9245          *
9246          * A flip count check isn't enough as the CS might have updated
9247          * the base address just after start of vblank, but before we
9248          * managed to process the interrupt. This means we'd complete the
9249          * CS flip too soon.
9250          *
9251          * Combining both checks should get us a good enough result. It may
9252          * still happen that the CS flip has been executed, but has not
9253          * yet actually completed. But in case the base address is the same
9254          * anyway, we don't really care.
9255          */
9256         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9257                 crtc->unpin_work->gtt_offset &&
9258                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9259                                     crtc->unpin_work->flip_count);
9260 }
9261
9262 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9263 {
9264         struct drm_i915_private *dev_priv = dev->dev_private;
9265         struct intel_crtc *intel_crtc =
9266                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9267         unsigned long flags;
9268
9269
9270         /*
9271          * This is called both by irq handlers and the reset code (to complete
9272          * lost pageflips) so needs the full irqsave spinlocks.
9273          *
9274          * NB: An MMIO update of the plane base pointer will also
9275          * generate a page-flip completion irq, i.e. every modeset
9276          * is also accompanied by a spurious intel_prepare_page_flip().
9277          */
9278         spin_lock_irqsave(&dev->event_lock, flags);
9279         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9280                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9281         spin_unlock_irqrestore(&dev->event_lock, flags);
9282 }
9283
9284 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9285 {
9286         /* Ensure that the work item is consistent when activating it ... */
9287         smp_wmb();
9288         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9289         /* and that it is marked active as soon as the irq could fire. */
9290         smp_wmb();
9291 }
9292
9293 static int intel_gen2_queue_flip(struct drm_device *dev,
9294                                  struct drm_crtc *crtc,
9295                                  struct drm_framebuffer *fb,
9296                                  struct drm_i915_gem_object *obj,
9297                                  struct intel_engine_cs *ring,
9298                                  uint32_t flags)
9299 {
9300         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9301         u32 flip_mask;
9302         int ret;
9303
9304         ret = intel_ring_begin(ring, 6);
9305         if (ret)
9306                 return ret;
9307
9308         /* Can't queue multiple flips, so wait for the previous
9309          * one to finish before executing the next.
9310          */
9311         if (intel_crtc->plane)
9312                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9313         else
9314                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9315         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9316         intel_ring_emit(ring, MI_NOOP);
9317         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9318                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9319         intel_ring_emit(ring, fb->pitches[0]);
9320         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9321         intel_ring_emit(ring, 0); /* aux display base address, unused */
9322
9323         intel_mark_page_flip_active(intel_crtc);
9324         __intel_ring_advance(ring);
9325         return 0;
9326 }
9327
9328 static int intel_gen3_queue_flip(struct drm_device *dev,
9329                                  struct drm_crtc *crtc,
9330                                  struct drm_framebuffer *fb,
9331                                  struct drm_i915_gem_object *obj,
9332                                  struct intel_engine_cs *ring,
9333                                  uint32_t flags)
9334 {
9335         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9336         u32 flip_mask;
9337         int ret;
9338
9339         ret = intel_ring_begin(ring, 6);
9340         if (ret)
9341                 return ret;
9342
9343         if (intel_crtc->plane)
9344                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9345         else
9346                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9347         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9348         intel_ring_emit(ring, MI_NOOP);
9349         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9350                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9351         intel_ring_emit(ring, fb->pitches[0]);
9352         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9353         intel_ring_emit(ring, MI_NOOP);
9354
9355         intel_mark_page_flip_active(intel_crtc);
9356         __intel_ring_advance(ring);
9357         return 0;
9358 }
9359
9360 static int intel_gen4_queue_flip(struct drm_device *dev,
9361                                  struct drm_crtc *crtc,
9362                                  struct drm_framebuffer *fb,
9363                                  struct drm_i915_gem_object *obj,
9364                                  struct intel_engine_cs *ring,
9365                                  uint32_t flags)
9366 {
9367         struct drm_i915_private *dev_priv = dev->dev_private;
9368         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9369         uint32_t pf, pipesrc;
9370         int ret;
9371
9372         ret = intel_ring_begin(ring, 4);
9373         if (ret)
9374                 return ret;
9375
9376         /* i965+ uses the linear or tiled offsets from the
9377          * Display Registers (which do not change across a page-flip)
9378          * so we need only reprogram the base address.
9379          */
9380         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9381                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9382         intel_ring_emit(ring, fb->pitches[0]);
9383         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9384                         obj->tiling_mode);
9385
9386         /* XXX Enabling the panel-fitter across page-flip is so far
9387          * untested on non-native modes, so ignore it for now.
9388          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9389          */
9390         pf = 0;
9391         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9392         intel_ring_emit(ring, pf | pipesrc);
9393
9394         intel_mark_page_flip_active(intel_crtc);
9395         __intel_ring_advance(ring);
9396         return 0;
9397 }
9398
9399 static int intel_gen6_queue_flip(struct drm_device *dev,
9400                                  struct drm_crtc *crtc,
9401                                  struct drm_framebuffer *fb,
9402                                  struct drm_i915_gem_object *obj,
9403                                  struct intel_engine_cs *ring,
9404                                  uint32_t flags)
9405 {
9406         struct drm_i915_private *dev_priv = dev->dev_private;
9407         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9408         uint32_t pf, pipesrc;
9409         int ret;
9410
9411         ret = intel_ring_begin(ring, 4);
9412         if (ret)
9413                 return ret;
9414
9415         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9416                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9417         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9418         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9419
9420         /* Contrary to the suggestions in the documentation,
9421          * "Enable Panel Fitter" does not seem to be required when page
9422          * flipping with a non-native mode, and worse causes a normal
9423          * modeset to fail.
9424          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9425          */
9426         pf = 0;
9427         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9428         intel_ring_emit(ring, pf | pipesrc);
9429
9430         intel_mark_page_flip_active(intel_crtc);
9431         __intel_ring_advance(ring);
9432         return 0;
9433 }
9434
9435 static int intel_gen7_queue_flip(struct drm_device *dev,
9436                                  struct drm_crtc *crtc,
9437                                  struct drm_framebuffer *fb,
9438                                  struct drm_i915_gem_object *obj,
9439                                  struct intel_engine_cs *ring,
9440                                  uint32_t flags)
9441 {
9442         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9443         uint32_t plane_bit = 0;
9444         int len, ret;
9445
9446         switch (intel_crtc->plane) {
9447         case PLANE_A:
9448                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9449                 break;
9450         case PLANE_B:
9451                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9452                 break;
9453         case PLANE_C:
9454                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9455                 break;
9456         default:
9457                 WARN_ONCE(1, "unknown plane in flip command\n");
9458                 return -ENODEV;
9459         }
9460
9461         len = 4;
9462         if (ring->id == RCS) {
9463                 len += 6;
9464                 /*
9465                  * On Gen 8, SRM is now taking an extra dword to accommodate
9466                  * 48bits addresses, and we need a NOOP for the batch size to
9467                  * stay even.
9468                  */
9469                 if (IS_GEN8(dev))
9470                         len += 2;
9471         }
9472
9473         /*
9474          * BSpec MI_DISPLAY_FLIP for IVB:
9475          * "The full packet must be contained within the same cache line."
9476          *
9477          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9478          * cacheline, if we ever start emitting more commands before
9479          * the MI_DISPLAY_FLIP we may need to first emit everything else,
9480          * then do the cacheline alignment, and finally emit the
9481          * MI_DISPLAY_FLIP.
9482          */
9483         ret = intel_ring_cacheline_align(ring);
9484         if (ret)
9485                 return ret;
9486
9487         ret = intel_ring_begin(ring, len);
9488         if (ret)
9489                 return ret;
9490
9491         /* Unmask the flip-done completion message. Note that the bspec says that
9492          * we should do this for both the BCS and RCS, and that we must not unmask
9493          * more than one flip event at any time (or ensure that one flip message
9494          * can be sent by waiting for flip-done prior to queueing new flips).
9495          * Experimentation says that BCS works despite DERRMR masking all
9496          * flip-done completion events and that unmasking all planes at once
9497          * for the RCS also doesn't appear to drop events. Setting the DERRMR
9498          * to zero does lead to lockups within MI_DISPLAY_FLIP.
9499          */
9500         if (ring->id == RCS) {
9501                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9502                 intel_ring_emit(ring, DERRMR);
9503                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9504                                         DERRMR_PIPEB_PRI_FLIP_DONE |
9505                                         DERRMR_PIPEC_PRI_FLIP_DONE));
9506                 if (IS_GEN8(dev))
9507                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9508                                               MI_SRM_LRM_GLOBAL_GTT);
9509                 else
9510                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9511                                               MI_SRM_LRM_GLOBAL_GTT);
9512                 intel_ring_emit(ring, DERRMR);
9513                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9514                 if (IS_GEN8(dev)) {
9515                         intel_ring_emit(ring, 0);
9516                         intel_ring_emit(ring, MI_NOOP);
9517                 }
9518         }
9519
9520         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9521         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9522         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9523         intel_ring_emit(ring, (MI_NOOP));
9524
9525         intel_mark_page_flip_active(intel_crtc);
9526         __intel_ring_advance(ring);
9527         return 0;
9528 }
9529
9530 static bool use_mmio_flip(struct intel_engine_cs *ring,
9531                           struct drm_i915_gem_object *obj)
9532 {
9533         /*
9534          * This is not being used for older platforms, because
9535          * non-availability of flip done interrupt forces us to use
9536          * CS flips. Older platforms derive flip done using some clever
9537          * tricks involving the flip_pending status bits and vblank irqs.
9538          * So using MMIO flips there would disrupt this mechanism.
9539          */
9540
9541         if (ring == NULL)
9542                 return true;
9543
9544         if (INTEL_INFO(ring->dev)->gen < 5)
9545                 return false;
9546
9547         if (i915.use_mmio_flip < 0)
9548                 return false;
9549         else if (i915.use_mmio_flip > 0)
9550                 return true;
9551         else if (i915.enable_execlists)
9552                 return true;
9553         else
9554                 return ring != obj->ring;
9555 }
9556
9557 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9558 {
9559         struct drm_device *dev = intel_crtc->base.dev;
9560         struct drm_i915_private *dev_priv = dev->dev_private;
9561         struct intel_framebuffer *intel_fb =
9562                 to_intel_framebuffer(intel_crtc->base.primary->fb);
9563         struct drm_i915_gem_object *obj = intel_fb->obj;
9564         u32 dspcntr;
9565         u32 reg;
9566
9567         intel_mark_page_flip_active(intel_crtc);
9568
9569         reg = DSPCNTR(intel_crtc->plane);
9570         dspcntr = I915_READ(reg);
9571
9572         if (INTEL_INFO(dev)->gen >= 4) {
9573                 if (obj->tiling_mode != I915_TILING_NONE)
9574                         dspcntr |= DISPPLANE_TILED;
9575                 else
9576                         dspcntr &= ~DISPPLANE_TILED;
9577         }
9578         I915_WRITE(reg, dspcntr);
9579
9580         I915_WRITE(DSPSURF(intel_crtc->plane),
9581                    intel_crtc->unpin_work->gtt_offset);
9582         POSTING_READ(DSPSURF(intel_crtc->plane));
9583 }
9584
9585 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9586 {
9587         struct intel_engine_cs *ring;
9588         int ret;
9589
9590         lockdep_assert_held(&obj->base.dev->struct_mutex);
9591
9592         if (!obj->last_write_seqno)
9593                 return 0;
9594
9595         ring = obj->ring;
9596
9597         if (i915_seqno_passed(ring->get_seqno(ring, true),
9598                               obj->last_write_seqno))
9599                 return 0;
9600
9601         ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9602         if (ret)
9603                 return ret;
9604
9605         if (WARN_ON(!ring->irq_get(ring)))
9606                 return 0;
9607
9608         return 1;
9609 }
9610
9611 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9612 {
9613         struct drm_i915_private *dev_priv = to_i915(ring->dev);
9614         struct intel_crtc *intel_crtc;
9615         unsigned long irq_flags;
9616         u32 seqno;
9617
9618         seqno = ring->get_seqno(ring, false);
9619
9620         spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9621         for_each_intel_crtc(ring->dev, intel_crtc) {
9622                 struct intel_mmio_flip *mmio_flip;
9623
9624                 mmio_flip = &intel_crtc->mmio_flip;
9625                 if (mmio_flip->seqno == 0)
9626                         continue;
9627
9628                 if (ring->id != mmio_flip->ring_id)
9629                         continue;
9630
9631                 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9632                         intel_do_mmio_flip(intel_crtc);
9633                         mmio_flip->seqno = 0;
9634                         ring->irq_put(ring);
9635                 }
9636         }
9637         spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9638 }
9639
9640 static int intel_queue_mmio_flip(struct drm_device *dev,
9641                                  struct drm_crtc *crtc,
9642                                  struct drm_framebuffer *fb,
9643                                  struct drm_i915_gem_object *obj,
9644                                  struct intel_engine_cs *ring,
9645                                  uint32_t flags)
9646 {
9647         struct drm_i915_private *dev_priv = dev->dev_private;
9648         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9649         int ret;
9650
9651         if (WARN_ON(intel_crtc->mmio_flip.seqno))
9652                 return -EBUSY;
9653
9654         ret = intel_postpone_flip(obj);
9655         if (ret < 0)
9656                 return ret;
9657         if (ret == 0) {
9658                 intel_do_mmio_flip(intel_crtc);
9659                 return 0;
9660         }
9661
9662         spin_lock_irq(&dev_priv->mmio_flip_lock);
9663         intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9664         intel_crtc->mmio_flip.ring_id = obj->ring->id;
9665         spin_unlock_irq(&dev_priv->mmio_flip_lock);
9666
9667         /*
9668          * Double check to catch cases where irq fired before
9669          * mmio flip data was ready
9670          */
9671         intel_notify_mmio_flip(obj->ring);
9672         return 0;
9673 }
9674
9675 static int intel_default_queue_flip(struct drm_device *dev,
9676                                     struct drm_crtc *crtc,
9677                                     struct drm_framebuffer *fb,
9678                                     struct drm_i915_gem_object *obj,
9679                                     struct intel_engine_cs *ring,
9680                                     uint32_t flags)
9681 {
9682         return -ENODEV;
9683 }
9684
9685 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9686                                          struct drm_crtc *crtc)
9687 {
9688         struct drm_i915_private *dev_priv = dev->dev_private;
9689         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9690         struct intel_unpin_work *work = intel_crtc->unpin_work;
9691         u32 addr;
9692
9693         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9694                 return true;
9695
9696         if (!work->enable_stall_check)
9697                 return false;
9698
9699         if (work->flip_ready_vblank == 0) {
9700                 if (work->flip_queued_ring &&
9701                     !i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
9702                                        work->flip_queued_seqno))
9703                         return false;
9704
9705                 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9706         }
9707
9708         if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9709                 return false;
9710
9711         /* Potential stall - if we see that the flip has happened,
9712          * assume a missed interrupt. */
9713         if (INTEL_INFO(dev)->gen >= 4)
9714                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9715         else
9716                 addr = I915_READ(DSPADDR(intel_crtc->plane));
9717
9718         /* There is a potential issue here with a false positive after a flip
9719          * to the same address. We could address this by checking for a
9720          * non-incrementing frame counter.
9721          */
9722         return addr == work->gtt_offset;
9723 }
9724
9725 void intel_check_page_flip(struct drm_device *dev, int pipe)
9726 {
9727         struct drm_i915_private *dev_priv = dev->dev_private;
9728         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9729         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9730
9731         WARN_ON(!in_irq());
9732
9733         if (crtc == NULL)
9734                 return;
9735
9736         spin_lock(&dev->event_lock);
9737         if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9738                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9739                          intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9740                 page_flip_completed(intel_crtc);
9741         }
9742         spin_unlock(&dev->event_lock);
9743 }
9744
9745 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9746                                 struct drm_framebuffer *fb,
9747                                 struct drm_pending_vblank_event *event,
9748                                 uint32_t page_flip_flags)
9749 {
9750         struct drm_device *dev = crtc->dev;
9751         struct drm_i915_private *dev_priv = dev->dev_private;
9752         struct drm_framebuffer *old_fb = crtc->primary->fb;
9753         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9754         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9755         enum pipe pipe = intel_crtc->pipe;
9756         struct intel_unpin_work *work;
9757         struct intel_engine_cs *ring;
9758         int ret;
9759
9760         /*
9761          * drm_mode_page_flip_ioctl() should already catch this, but double
9762          * check to be safe.  In the future we may enable pageflipping from
9763          * a disabled primary plane.
9764          */
9765         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9766                 return -EBUSY;
9767
9768         /* Can't change pixel format via MI display flips. */
9769         if (fb->pixel_format != crtc->primary->fb->pixel_format)
9770                 return -EINVAL;
9771
9772         /*
9773          * TILEOFF/LINOFF registers can't be changed via MI display flips.
9774          * Note that pitch changes could also affect these register.
9775          */
9776         if (INTEL_INFO(dev)->gen > 3 &&
9777             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9778              fb->pitches[0] != crtc->primary->fb->pitches[0]))
9779                 return -EINVAL;
9780
9781         if (i915_terminally_wedged(&dev_priv->gpu_error))
9782                 goto out_hang;
9783
9784         work = kzalloc(sizeof(*work), GFP_KERNEL);
9785         if (work == NULL)
9786                 return -ENOMEM;
9787
9788         work->event = event;
9789         work->crtc = crtc;
9790         work->old_fb_obj = intel_fb_obj(old_fb);
9791         INIT_WORK(&work->work, intel_unpin_work_fn);
9792
9793         ret = drm_crtc_vblank_get(crtc);
9794         if (ret)
9795                 goto free_work;
9796
9797         /* We borrow the event spin lock for protecting unpin_work */
9798         spin_lock_irq(&dev->event_lock);
9799         if (intel_crtc->unpin_work) {
9800                 /* Before declaring the flip queue wedged, check if
9801                  * the hardware completed the operation behind our backs.
9802                  */
9803                 if (__intel_pageflip_stall_check(dev, crtc)) {
9804                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9805                         page_flip_completed(intel_crtc);
9806                 } else {
9807                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9808                         spin_unlock_irq(&dev->event_lock);
9809
9810                         drm_crtc_vblank_put(crtc);
9811                         kfree(work);
9812                         return -EBUSY;
9813                 }
9814         }
9815         intel_crtc->unpin_work = work;
9816         spin_unlock_irq(&dev->event_lock);
9817
9818         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9819                 flush_workqueue(dev_priv->wq);
9820
9821         ret = i915_mutex_lock_interruptible(dev);
9822         if (ret)
9823                 goto cleanup;
9824
9825         /* Reference the objects for the scheduled work. */
9826         drm_gem_object_reference(&work->old_fb_obj->base);
9827         drm_gem_object_reference(&obj->base);
9828
9829         crtc->primary->fb = fb;
9830
9831         work->pending_flip_obj = obj;
9832
9833         atomic_inc(&intel_crtc->unpin_work_count);
9834         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9835
9836         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9837                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9838
9839         if (IS_VALLEYVIEW(dev)) {
9840                 ring = &dev_priv->ring[BCS];
9841                 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9842                         /* vlv: DISPLAY_FLIP fails to change tiling */
9843                         ring = NULL;
9844         } else if (IS_IVYBRIDGE(dev)) {
9845                 ring = &dev_priv->ring[BCS];
9846         } else if (INTEL_INFO(dev)->gen >= 7) {
9847                 ring = obj->ring;
9848                 if (ring == NULL || ring->id != RCS)
9849                         ring = &dev_priv->ring[BCS];
9850         } else {
9851                 ring = &dev_priv->ring[RCS];
9852         }
9853
9854         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9855         if (ret)
9856                 goto cleanup_pending;
9857
9858         work->gtt_offset =
9859                 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9860
9861         if (use_mmio_flip(ring, obj)) {
9862                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9863                                             page_flip_flags);
9864                 if (ret)
9865                         goto cleanup_unpin;
9866
9867                 work->flip_queued_seqno = obj->last_write_seqno;
9868                 work->flip_queued_ring = obj->ring;
9869         } else {
9870                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9871                                                    page_flip_flags);
9872                 if (ret)
9873                         goto cleanup_unpin;
9874
9875                 work->flip_queued_seqno = intel_ring_get_seqno(ring);
9876                 work->flip_queued_ring = ring;
9877         }
9878
9879         work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9880         work->enable_stall_check = true;
9881
9882         i915_gem_track_fb(work->old_fb_obj, obj,
9883                           INTEL_FRONTBUFFER_PRIMARY(pipe));
9884
9885         intel_disable_fbc(dev);
9886         intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9887         mutex_unlock(&dev->struct_mutex);
9888
9889         trace_i915_flip_request(intel_crtc->plane, obj);
9890
9891         return 0;
9892
9893 cleanup_unpin:
9894         intel_unpin_fb_obj(obj);
9895 cleanup_pending:
9896         atomic_dec(&intel_crtc->unpin_work_count);
9897         crtc->primary->fb = old_fb;
9898         drm_gem_object_unreference(&work->old_fb_obj->base);
9899         drm_gem_object_unreference(&obj->base);
9900         mutex_unlock(&dev->struct_mutex);
9901
9902 cleanup:
9903         spin_lock_irq(&dev->event_lock);
9904         intel_crtc->unpin_work = NULL;
9905         spin_unlock_irq(&dev->event_lock);
9906
9907         drm_crtc_vblank_put(crtc);
9908 free_work:
9909         kfree(work);
9910
9911         if (ret == -EIO) {
9912 out_hang:
9913                 intel_crtc_wait_for_pending_flips(crtc);
9914                 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9915                 if (ret == 0 && event) {
9916                         spin_lock_irq(&dev->event_lock);
9917                         drm_send_vblank_event(dev, pipe, event);
9918                         spin_unlock_irq(&dev->event_lock);
9919                 }
9920         }
9921         return ret;
9922 }
9923
9924 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9925         .mode_set_base_atomic = intel_pipe_set_base_atomic,
9926         .load_lut = intel_crtc_load_lut,
9927 };
9928
9929 /**
9930  * intel_modeset_update_staged_output_state
9931  *
9932  * Updates the staged output configuration state, e.g. after we've read out the
9933  * current hw state.
9934  */
9935 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9936 {
9937         struct intel_crtc *crtc;
9938         struct intel_encoder *encoder;
9939         struct intel_connector *connector;
9940
9941         list_for_each_entry(connector, &dev->mode_config.connector_list,
9942                             base.head) {
9943                 connector->new_encoder =
9944                         to_intel_encoder(connector->base.encoder);
9945         }
9946
9947         for_each_intel_encoder(dev, encoder) {
9948                 encoder->new_crtc =
9949                         to_intel_crtc(encoder->base.crtc);
9950         }
9951
9952         for_each_intel_crtc(dev, crtc) {
9953                 crtc->new_enabled = crtc->base.enabled;
9954
9955                 if (crtc->new_enabled)
9956                         crtc->new_config = &crtc->config;
9957                 else
9958                         crtc->new_config = NULL;
9959         }
9960 }
9961
9962 /**
9963  * intel_modeset_commit_output_state
9964  *
9965  * This function copies the stage display pipe configuration to the real one.
9966  */
9967 static void intel_modeset_commit_output_state(struct drm_device *dev)
9968 {
9969         struct intel_crtc *crtc;
9970         struct intel_encoder *encoder;
9971         struct intel_connector *connector;
9972
9973         list_for_each_entry(connector, &dev->mode_config.connector_list,
9974                             base.head) {
9975                 connector->base.encoder = &connector->new_encoder->base;
9976         }
9977
9978         for_each_intel_encoder(dev, encoder) {
9979                 encoder->base.crtc = &encoder->new_crtc->base;
9980         }
9981
9982         for_each_intel_crtc(dev, crtc) {
9983                 crtc->base.enabled = crtc->new_enabled;
9984         }
9985 }
9986
9987 static void
9988 connected_sink_compute_bpp(struct intel_connector *connector,
9989                            struct intel_crtc_config *pipe_config)
9990 {
9991         int bpp = pipe_config->pipe_bpp;
9992
9993         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9994                 connector->base.base.id,
9995                 connector->base.name);
9996
9997         /* Don't use an invalid EDID bpc value */
9998         if (connector->base.display_info.bpc &&
9999             connector->base.display_info.bpc * 3 < bpp) {
10000                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10001                               bpp, connector->base.display_info.bpc*3);
10002                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10003         }
10004
10005         /* Clamp bpp to 8 on screens without EDID 1.4 */
10006         if (connector->base.display_info.bpc == 0 && bpp > 24) {
10007                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10008                               bpp);
10009                 pipe_config->pipe_bpp = 24;
10010         }
10011 }
10012
10013 static int
10014 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10015                           struct drm_framebuffer *fb,
10016                           struct intel_crtc_config *pipe_config)
10017 {
10018         struct drm_device *dev = crtc->base.dev;
10019         struct intel_connector *connector;
10020         int bpp;
10021
10022         switch (fb->pixel_format) {
10023         case DRM_FORMAT_C8:
10024                 bpp = 8*3; /* since we go through a colormap */
10025                 break;
10026         case DRM_FORMAT_XRGB1555:
10027         case DRM_FORMAT_ARGB1555:
10028                 /* checked in intel_framebuffer_init already */
10029                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10030                         return -EINVAL;
10031         case DRM_FORMAT_RGB565:
10032                 bpp = 6*3; /* min is 18bpp */
10033                 break;
10034         case DRM_FORMAT_XBGR8888:
10035         case DRM_FORMAT_ABGR8888:
10036                 /* checked in intel_framebuffer_init already */
10037                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10038                         return -EINVAL;
10039         case DRM_FORMAT_XRGB8888:
10040         case DRM_FORMAT_ARGB8888:
10041                 bpp = 8*3;
10042                 break;
10043         case DRM_FORMAT_XRGB2101010:
10044         case DRM_FORMAT_ARGB2101010:
10045         case DRM_FORMAT_XBGR2101010:
10046         case DRM_FORMAT_ABGR2101010:
10047                 /* checked in intel_framebuffer_init already */
10048                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10049                         return -EINVAL;
10050                 bpp = 10*3;
10051                 break;
10052         /* TODO: gen4+ supports 16 bpc floating point, too. */
10053         default:
10054                 DRM_DEBUG_KMS("unsupported depth\n");
10055                 return -EINVAL;
10056         }
10057
10058         pipe_config->pipe_bpp = bpp;
10059
10060         /* Clamp display bpp to EDID value */
10061         list_for_each_entry(connector, &dev->mode_config.connector_list,
10062                             base.head) {
10063                 if (!connector->new_encoder ||
10064                     connector->new_encoder->new_crtc != crtc)
10065                         continue;
10066
10067                 connected_sink_compute_bpp(connector, pipe_config);
10068         }
10069
10070         return bpp;
10071 }
10072
10073 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10074 {
10075         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10076                         "type: 0x%x flags: 0x%x\n",
10077                 mode->crtc_clock,
10078                 mode->crtc_hdisplay, mode->crtc_hsync_start,
10079                 mode->crtc_hsync_end, mode->crtc_htotal,
10080                 mode->crtc_vdisplay, mode->crtc_vsync_start,
10081                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10082 }
10083
10084 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10085                                    struct intel_crtc_config *pipe_config,
10086                                    const char *context)
10087 {
10088         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10089                       context, pipe_name(crtc->pipe));
10090
10091         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10092         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10093                       pipe_config->pipe_bpp, pipe_config->dither);
10094         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10095                       pipe_config->has_pch_encoder,
10096                       pipe_config->fdi_lanes,
10097                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10098                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10099                       pipe_config->fdi_m_n.tu);
10100         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10101                       pipe_config->has_dp_encoder,
10102                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10103                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10104                       pipe_config->dp_m_n.tu);
10105
10106         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10107                       pipe_config->has_dp_encoder,
10108                       pipe_config->dp_m2_n2.gmch_m,
10109                       pipe_config->dp_m2_n2.gmch_n,
10110                       pipe_config->dp_m2_n2.link_m,
10111                       pipe_config->dp_m2_n2.link_n,
10112                       pipe_config->dp_m2_n2.tu);
10113
10114         DRM_DEBUG_KMS("requested mode:\n");
10115         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
10116         DRM_DEBUG_KMS("adjusted mode:\n");
10117         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
10118         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
10119         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10120         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10121                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10122         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10123                       pipe_config->gmch_pfit.control,
10124                       pipe_config->gmch_pfit.pgm_ratios,
10125                       pipe_config->gmch_pfit.lvds_border_bits);
10126         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10127                       pipe_config->pch_pfit.pos,
10128                       pipe_config->pch_pfit.size,
10129                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10130         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10131         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10132 }
10133
10134 static bool encoders_cloneable(const struct intel_encoder *a,
10135                                const struct intel_encoder *b)
10136 {
10137         /* masks could be asymmetric, so check both ways */
10138         return a == b || (a->cloneable & (1 << b->type) &&
10139                           b->cloneable & (1 << a->type));
10140 }
10141
10142 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10143                                          struct intel_encoder *encoder)
10144 {
10145         struct drm_device *dev = crtc->base.dev;
10146         struct intel_encoder *source_encoder;
10147
10148         for_each_intel_encoder(dev, source_encoder) {
10149                 if (source_encoder->new_crtc != crtc)
10150                         continue;
10151
10152                 if (!encoders_cloneable(encoder, source_encoder))
10153                         return false;
10154         }
10155
10156         return true;
10157 }
10158
10159 static bool check_encoder_cloning(struct intel_crtc *crtc)
10160 {
10161         struct drm_device *dev = crtc->base.dev;
10162         struct intel_encoder *encoder;
10163
10164         for_each_intel_encoder(dev, encoder) {
10165                 if (encoder->new_crtc != crtc)
10166                         continue;
10167
10168                 if (!check_single_encoder_cloning(crtc, encoder))
10169                         return false;
10170         }
10171
10172         return true;
10173 }
10174
10175 static struct intel_crtc_config *
10176 intel_modeset_pipe_config(struct drm_crtc *crtc,
10177                           struct drm_framebuffer *fb,
10178                           struct drm_display_mode *mode)
10179 {
10180         struct drm_device *dev = crtc->dev;
10181         struct intel_encoder *encoder;
10182         struct intel_crtc_config *pipe_config;
10183         int plane_bpp, ret = -EINVAL;
10184         bool retry = true;
10185
10186         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10187                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10188                 return ERR_PTR(-EINVAL);
10189         }
10190
10191         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10192         if (!pipe_config)
10193                 return ERR_PTR(-ENOMEM);
10194
10195         drm_mode_copy(&pipe_config->adjusted_mode, mode);
10196         drm_mode_copy(&pipe_config->requested_mode, mode);
10197
10198         pipe_config->cpu_transcoder =
10199                 (enum transcoder) to_intel_crtc(crtc)->pipe;
10200         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10201
10202         /*
10203          * Sanitize sync polarity flags based on requested ones. If neither
10204          * positive or negative polarity is requested, treat this as meaning
10205          * negative polarity.
10206          */
10207         if (!(pipe_config->adjusted_mode.flags &
10208               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10209                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10210
10211         if (!(pipe_config->adjusted_mode.flags &
10212               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10213                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10214
10215         /* Compute a starting value for pipe_config->pipe_bpp taking the source
10216          * plane pixel format and any sink constraints into account. Returns the
10217          * source plane bpp so that dithering can be selected on mismatches
10218          * after encoders and crtc also have had their say. */
10219         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10220                                               fb, pipe_config);
10221         if (plane_bpp < 0)
10222                 goto fail;
10223
10224         /*
10225          * Determine the real pipe dimensions. Note that stereo modes can
10226          * increase the actual pipe size due to the frame doubling and
10227          * insertion of additional space for blanks between the frame. This
10228          * is stored in the crtc timings. We use the requested mode to do this
10229          * computation to clearly distinguish it from the adjusted mode, which
10230          * can be changed by the connectors in the below retry loop.
10231          */
10232         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10233         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10234         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10235
10236 encoder_retry:
10237         /* Ensure the port clock defaults are reset when retrying. */
10238         pipe_config->port_clock = 0;
10239         pipe_config->pixel_multiplier = 1;
10240
10241         /* Fill in default crtc timings, allow encoders to overwrite them. */
10242         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10243
10244         /* Pass our mode to the connectors and the CRTC to give them a chance to
10245          * adjust it according to limitations or connector properties, and also
10246          * a chance to reject the mode entirely.
10247          */
10248         for_each_intel_encoder(dev, encoder) {
10249
10250                 if (&encoder->new_crtc->base != crtc)
10251                         continue;
10252
10253                 if (!(encoder->compute_config(encoder, pipe_config))) {
10254                         DRM_DEBUG_KMS("Encoder config failure\n");
10255                         goto fail;
10256                 }
10257         }
10258
10259         /* Set default port clock if not overwritten by the encoder. Needs to be
10260          * done afterwards in case the encoder adjusts the mode. */
10261         if (!pipe_config->port_clock)
10262                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10263                         * pipe_config->pixel_multiplier;
10264
10265         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10266         if (ret < 0) {
10267                 DRM_DEBUG_KMS("CRTC fixup failed\n");
10268                 goto fail;
10269         }
10270
10271         if (ret == RETRY) {
10272                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10273                         ret = -EINVAL;
10274                         goto fail;
10275                 }
10276
10277                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10278                 retry = false;
10279                 goto encoder_retry;
10280         }
10281
10282         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10283         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10284                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10285
10286         return pipe_config;
10287 fail:
10288         kfree(pipe_config);
10289         return ERR_PTR(ret);
10290 }
10291
10292 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10293  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10294 static void
10295 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10296                              unsigned *prepare_pipes, unsigned *disable_pipes)
10297 {
10298         struct intel_crtc *intel_crtc;
10299         struct drm_device *dev = crtc->dev;
10300         struct intel_encoder *encoder;
10301         struct intel_connector *connector;
10302         struct drm_crtc *tmp_crtc;
10303
10304         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10305
10306         /* Check which crtcs have changed outputs connected to them, these need
10307          * to be part of the prepare_pipes mask. We don't (yet) support global
10308          * modeset across multiple crtcs, so modeset_pipes will only have one
10309          * bit set at most. */
10310         list_for_each_entry(connector, &dev->mode_config.connector_list,
10311                             base.head) {
10312                 if (connector->base.encoder == &connector->new_encoder->base)
10313                         continue;
10314
10315                 if (connector->base.encoder) {
10316                         tmp_crtc = connector->base.encoder->crtc;
10317
10318                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10319                 }
10320
10321                 if (connector->new_encoder)
10322                         *prepare_pipes |=
10323                                 1 << connector->new_encoder->new_crtc->pipe;
10324         }
10325
10326         for_each_intel_encoder(dev, encoder) {
10327                 if (encoder->base.crtc == &encoder->new_crtc->base)
10328                         continue;
10329
10330                 if (encoder->base.crtc) {
10331                         tmp_crtc = encoder->base.crtc;
10332
10333                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10334                 }
10335
10336                 if (encoder->new_crtc)
10337                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10338         }
10339
10340         /* Check for pipes that will be enabled/disabled ... */
10341         for_each_intel_crtc(dev, intel_crtc) {
10342                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10343                         continue;
10344
10345                 if (!intel_crtc->new_enabled)
10346                         *disable_pipes |= 1 << intel_crtc->pipe;
10347                 else
10348                         *prepare_pipes |= 1 << intel_crtc->pipe;
10349         }
10350
10351
10352         /* set_mode is also used to update properties on life display pipes. */
10353         intel_crtc = to_intel_crtc(crtc);
10354         if (intel_crtc->new_enabled)
10355                 *prepare_pipes |= 1 << intel_crtc->pipe;
10356
10357         /*
10358          * For simplicity do a full modeset on any pipe where the output routing
10359          * changed. We could be more clever, but that would require us to be
10360          * more careful with calling the relevant encoder->mode_set functions.
10361          */
10362         if (*prepare_pipes)
10363                 *modeset_pipes = *prepare_pipes;
10364
10365         /* ... and mask these out. */
10366         *modeset_pipes &= ~(*disable_pipes);
10367         *prepare_pipes &= ~(*disable_pipes);
10368
10369         /*
10370          * HACK: We don't (yet) fully support global modesets. intel_set_config
10371          * obies this rule, but the modeset restore mode of
10372          * intel_modeset_setup_hw_state does not.
10373          */
10374         *modeset_pipes &= 1 << intel_crtc->pipe;
10375         *prepare_pipes &= 1 << intel_crtc->pipe;
10376
10377         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10378                       *modeset_pipes, *prepare_pipes, *disable_pipes);
10379 }
10380
10381 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10382 {
10383         struct drm_encoder *encoder;
10384         struct drm_device *dev = crtc->dev;
10385
10386         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10387                 if (encoder->crtc == crtc)
10388                         return true;
10389
10390         return false;
10391 }
10392
10393 static void
10394 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10395 {
10396         struct intel_encoder *intel_encoder;
10397         struct intel_crtc *intel_crtc;
10398         struct drm_connector *connector;
10399
10400         for_each_intel_encoder(dev, intel_encoder) {
10401                 if (!intel_encoder->base.crtc)
10402                         continue;
10403
10404                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10405
10406                 if (prepare_pipes & (1 << intel_crtc->pipe))
10407                         intel_encoder->connectors_active = false;
10408         }
10409
10410         intel_modeset_commit_output_state(dev);
10411
10412         /* Double check state. */
10413         for_each_intel_crtc(dev, intel_crtc) {
10414                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10415                 WARN_ON(intel_crtc->new_config &&
10416                         intel_crtc->new_config != &intel_crtc->config);
10417                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10418         }
10419
10420         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10421                 if (!connector->encoder || !connector->encoder->crtc)
10422                         continue;
10423
10424                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10425
10426                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10427                         struct drm_property *dpms_property =
10428                                 dev->mode_config.dpms_property;
10429
10430                         connector->dpms = DRM_MODE_DPMS_ON;
10431                         drm_object_property_set_value(&connector->base,
10432                                                          dpms_property,
10433                                                          DRM_MODE_DPMS_ON);
10434
10435                         intel_encoder = to_intel_encoder(connector->encoder);
10436                         intel_encoder->connectors_active = true;
10437                 }
10438         }
10439
10440 }
10441
10442 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10443 {
10444         int diff;
10445
10446         if (clock1 == clock2)
10447                 return true;
10448
10449         if (!clock1 || !clock2)
10450                 return false;
10451
10452         diff = abs(clock1 - clock2);
10453
10454         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10455                 return true;
10456
10457         return false;
10458 }
10459
10460 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10461         list_for_each_entry((intel_crtc), \
10462                             &(dev)->mode_config.crtc_list, \
10463                             base.head) \
10464                 if (mask & (1 <<(intel_crtc)->pipe))
10465
10466 static bool
10467 intel_pipe_config_compare(struct drm_device *dev,
10468                           struct intel_crtc_config *current_config,
10469                           struct intel_crtc_config *pipe_config)
10470 {
10471 #define PIPE_CONF_CHECK_X(name) \
10472         if (current_config->name != pipe_config->name) { \
10473                 DRM_ERROR("mismatch in " #name " " \
10474                           "(expected 0x%08x, found 0x%08x)\n", \
10475                           current_config->name, \
10476                           pipe_config->name); \
10477                 return false; \
10478         }
10479
10480 #define PIPE_CONF_CHECK_I(name) \
10481         if (current_config->name != pipe_config->name) { \
10482                 DRM_ERROR("mismatch in " #name " " \
10483                           "(expected %i, found %i)\n", \
10484                           current_config->name, \
10485                           pipe_config->name); \
10486                 return false; \
10487         }
10488
10489 /* This is required for BDW+ where there is only one set of registers for
10490  * switching between high and low RR.
10491  * This macro can be used whenever a comparison has to be made between one
10492  * hw state and multiple sw state variables.
10493  */
10494 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10495         if ((current_config->name != pipe_config->name) && \
10496                 (current_config->alt_name != pipe_config->name)) { \
10497                         DRM_ERROR("mismatch in " #name " " \
10498                                   "(expected %i or %i, found %i)\n", \
10499                                   current_config->name, \
10500                                   current_config->alt_name, \
10501                                   pipe_config->name); \
10502                         return false; \
10503         }
10504
10505 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
10506         if ((current_config->name ^ pipe_config->name) & (mask)) { \
10507                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
10508                           "(expected %i, found %i)\n", \
10509                           current_config->name & (mask), \
10510                           pipe_config->name & (mask)); \
10511                 return false; \
10512         }
10513
10514 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10515         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10516                 DRM_ERROR("mismatch in " #name " " \
10517                           "(expected %i, found %i)\n", \
10518                           current_config->name, \
10519                           pipe_config->name); \
10520                 return false; \
10521         }
10522
10523 #define PIPE_CONF_QUIRK(quirk)  \
10524         ((current_config->quirks | pipe_config->quirks) & (quirk))
10525
10526         PIPE_CONF_CHECK_I(cpu_transcoder);
10527
10528         PIPE_CONF_CHECK_I(has_pch_encoder);
10529         PIPE_CONF_CHECK_I(fdi_lanes);
10530         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10531         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10532         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10533         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10534         PIPE_CONF_CHECK_I(fdi_m_n.tu);
10535
10536         PIPE_CONF_CHECK_I(has_dp_encoder);
10537
10538         if (INTEL_INFO(dev)->gen < 8) {
10539                 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10540                 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10541                 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10542                 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10543                 PIPE_CONF_CHECK_I(dp_m_n.tu);
10544
10545                 if (current_config->has_drrs) {
10546                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10547                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10548                         PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10549                         PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10550                         PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10551                 }
10552         } else {
10553                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10554                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10555                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10556                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10557                 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10558         }
10559
10560         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10561         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10562         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10563         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10564         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10565         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10566
10567         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10568         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10569         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10570         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10571         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10572         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10573
10574         PIPE_CONF_CHECK_I(pixel_multiplier);
10575         PIPE_CONF_CHECK_I(has_hdmi_sink);
10576         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10577             IS_VALLEYVIEW(dev))
10578                 PIPE_CONF_CHECK_I(limited_color_range);
10579
10580         PIPE_CONF_CHECK_I(has_audio);
10581
10582         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10583                               DRM_MODE_FLAG_INTERLACE);
10584
10585         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10586                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10587                                       DRM_MODE_FLAG_PHSYNC);
10588                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10589                                       DRM_MODE_FLAG_NHSYNC);
10590                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10591                                       DRM_MODE_FLAG_PVSYNC);
10592                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10593                                       DRM_MODE_FLAG_NVSYNC);
10594         }
10595
10596         PIPE_CONF_CHECK_I(pipe_src_w);
10597         PIPE_CONF_CHECK_I(pipe_src_h);
10598
10599         /*
10600          * FIXME: BIOS likes to set up a cloned config with lvds+external
10601          * screen. Since we don't yet re-compute the pipe config when moving
10602          * just the lvds port away to another pipe the sw tracking won't match.
10603          *
10604          * Proper atomic modesets with recomputed global state will fix this.
10605          * Until then just don't check gmch state for inherited modes.
10606          */
10607         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10608                 PIPE_CONF_CHECK_I(gmch_pfit.control);
10609                 /* pfit ratios are autocomputed by the hw on gen4+ */
10610                 if (INTEL_INFO(dev)->gen < 4)
10611                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10612                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10613         }
10614
10615         PIPE_CONF_CHECK_I(pch_pfit.enabled);
10616         if (current_config->pch_pfit.enabled) {
10617                 PIPE_CONF_CHECK_I(pch_pfit.pos);
10618                 PIPE_CONF_CHECK_I(pch_pfit.size);
10619         }
10620
10621         /* BDW+ don't expose a synchronous way to read the state */
10622         if (IS_HASWELL(dev))
10623                 PIPE_CONF_CHECK_I(ips_enabled);
10624
10625         PIPE_CONF_CHECK_I(double_wide);
10626
10627         PIPE_CONF_CHECK_X(ddi_pll_sel);
10628
10629         PIPE_CONF_CHECK_I(shared_dpll);
10630         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10631         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10632         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10633         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10634         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10635
10636         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10637                 PIPE_CONF_CHECK_I(pipe_bpp);
10638
10639         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10640         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10641
10642 #undef PIPE_CONF_CHECK_X
10643 #undef PIPE_CONF_CHECK_I
10644 #undef PIPE_CONF_CHECK_I_ALT
10645 #undef PIPE_CONF_CHECK_FLAGS
10646 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10647 #undef PIPE_CONF_QUIRK
10648
10649         return true;
10650 }
10651
10652 static void
10653 check_connector_state(struct drm_device *dev)
10654 {
10655         struct intel_connector *connector;
10656
10657         list_for_each_entry(connector, &dev->mode_config.connector_list,
10658                             base.head) {
10659                 /* This also checks the encoder/connector hw state with the
10660                  * ->get_hw_state callbacks. */
10661                 intel_connector_check_state(connector);
10662
10663                 WARN(&connector->new_encoder->base != connector->base.encoder,
10664                      "connector's staged encoder doesn't match current encoder\n");
10665         }
10666 }
10667
10668 static void
10669 check_encoder_state(struct drm_device *dev)
10670 {
10671         struct intel_encoder *encoder;
10672         struct intel_connector *connector;
10673
10674         for_each_intel_encoder(dev, encoder) {
10675                 bool enabled = false;
10676                 bool active = false;
10677                 enum pipe pipe, tracked_pipe;
10678
10679                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10680                               encoder->base.base.id,
10681                               encoder->base.name);
10682
10683                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10684                      "encoder's stage crtc doesn't match current crtc\n");
10685                 WARN(encoder->connectors_active && !encoder->base.crtc,
10686                      "encoder's active_connectors set, but no crtc\n");
10687
10688                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10689                                     base.head) {
10690                         if (connector->base.encoder != &encoder->base)
10691                                 continue;
10692                         enabled = true;
10693                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10694                                 active = true;
10695                 }
10696                 /*
10697                  * for MST connectors if we unplug the connector is gone
10698                  * away but the encoder is still connected to a crtc
10699                  * until a modeset happens in response to the hotplug.
10700                  */
10701                 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10702                         continue;
10703
10704                 WARN(!!encoder->base.crtc != enabled,
10705                      "encoder's enabled state mismatch "
10706                      "(expected %i, found %i)\n",
10707                      !!encoder->base.crtc, enabled);
10708                 WARN(active && !encoder->base.crtc,
10709                      "active encoder with no crtc\n");
10710
10711                 WARN(encoder->connectors_active != active,
10712                      "encoder's computed active state doesn't match tracked active state "
10713                      "(expected %i, found %i)\n", active, encoder->connectors_active);
10714
10715                 active = encoder->get_hw_state(encoder, &pipe);
10716                 WARN(active != encoder->connectors_active,
10717                      "encoder's hw state doesn't match sw tracking "
10718                      "(expected %i, found %i)\n",
10719                      encoder->connectors_active, active);
10720
10721                 if (!encoder->base.crtc)
10722                         continue;
10723
10724                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10725                 WARN(active && pipe != tracked_pipe,
10726                      "active encoder's pipe doesn't match"
10727                      "(expected %i, found %i)\n",
10728                      tracked_pipe, pipe);
10729
10730         }
10731 }
10732
10733 static void
10734 check_crtc_state(struct drm_device *dev)
10735 {
10736         struct drm_i915_private *dev_priv = dev->dev_private;
10737         struct intel_crtc *crtc;
10738         struct intel_encoder *encoder;
10739         struct intel_crtc_config pipe_config;
10740
10741         for_each_intel_crtc(dev, crtc) {
10742                 bool enabled = false;
10743                 bool active = false;
10744
10745                 memset(&pipe_config, 0, sizeof(pipe_config));
10746
10747                 DRM_DEBUG_KMS("[CRTC:%d]\n",
10748                               crtc->base.base.id);
10749
10750                 WARN(crtc->active && !crtc->base.enabled,
10751                      "active crtc, but not enabled in sw tracking\n");
10752
10753                 for_each_intel_encoder(dev, encoder) {
10754                         if (encoder->base.crtc != &crtc->base)
10755                                 continue;
10756                         enabled = true;
10757                         if (encoder->connectors_active)
10758                                 active = true;
10759                 }
10760
10761                 WARN(active != crtc->active,
10762                      "crtc's computed active state doesn't match tracked active state "
10763                      "(expected %i, found %i)\n", active, crtc->active);
10764                 WARN(enabled != crtc->base.enabled,
10765                      "crtc's computed enabled state doesn't match tracked enabled state "
10766                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10767
10768                 active = dev_priv->display.get_pipe_config(crtc,
10769                                                            &pipe_config);
10770
10771                 /* hw state is inconsistent with the pipe quirk */
10772                 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10773                     (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10774                         active = crtc->active;
10775
10776                 for_each_intel_encoder(dev, encoder) {
10777                         enum pipe pipe;
10778                         if (encoder->base.crtc != &crtc->base)
10779                                 continue;
10780                         if (encoder->get_hw_state(encoder, &pipe))
10781                                 encoder->get_config(encoder, &pipe_config);
10782                 }
10783
10784                 WARN(crtc->active != active,
10785                      "crtc active state doesn't match with hw state "
10786                      "(expected %i, found %i)\n", crtc->active, active);
10787
10788                 if (active &&
10789                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10790                         WARN(1, "pipe state doesn't match!\n");
10791                         intel_dump_pipe_config(crtc, &pipe_config,
10792                                                "[hw state]");
10793                         intel_dump_pipe_config(crtc, &crtc->config,
10794                                                "[sw state]");
10795                 }
10796         }
10797 }
10798
10799 static void
10800 check_shared_dpll_state(struct drm_device *dev)
10801 {
10802         struct drm_i915_private *dev_priv = dev->dev_private;
10803         struct intel_crtc *crtc;
10804         struct intel_dpll_hw_state dpll_hw_state;
10805         int i;
10806
10807         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10808                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10809                 int enabled_crtcs = 0, active_crtcs = 0;
10810                 bool active;
10811
10812                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10813
10814                 DRM_DEBUG_KMS("%s\n", pll->name);
10815
10816                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10817
10818                 WARN(pll->active > pll->refcount,
10819                      "more active pll users than references: %i vs %i\n",
10820                      pll->active, pll->refcount);
10821                 WARN(pll->active && !pll->on,
10822                      "pll in active use but not on in sw tracking\n");
10823                 WARN(pll->on && !pll->active,
10824                      "pll in on but not on in use in sw tracking\n");
10825                 WARN(pll->on != active,
10826                      "pll on state mismatch (expected %i, found %i)\n",
10827                      pll->on, active);
10828
10829                 for_each_intel_crtc(dev, crtc) {
10830                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10831                                 enabled_crtcs++;
10832                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10833                                 active_crtcs++;
10834                 }
10835                 WARN(pll->active != active_crtcs,
10836                      "pll active crtcs mismatch (expected %i, found %i)\n",
10837                      pll->active, active_crtcs);
10838                 WARN(pll->refcount != enabled_crtcs,
10839                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
10840                      pll->refcount, enabled_crtcs);
10841
10842                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10843                                        sizeof(dpll_hw_state)),
10844                      "pll hw state mismatch\n");
10845         }
10846 }
10847
10848 void
10849 intel_modeset_check_state(struct drm_device *dev)
10850 {
10851         check_connector_state(dev);
10852         check_encoder_state(dev);
10853         check_crtc_state(dev);
10854         check_shared_dpll_state(dev);
10855 }
10856
10857 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10858                                      int dotclock)
10859 {
10860         /*
10861          * FDI already provided one idea for the dotclock.
10862          * Yell if the encoder disagrees.
10863          */
10864         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10865              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10866              pipe_config->adjusted_mode.crtc_clock, dotclock);
10867 }
10868
10869 static void update_scanline_offset(struct intel_crtc *crtc)
10870 {
10871         struct drm_device *dev = crtc->base.dev;
10872
10873         /*
10874          * The scanline counter increments at the leading edge of hsync.
10875          *
10876          * On most platforms it starts counting from vtotal-1 on the
10877          * first active line. That means the scanline counter value is
10878          * always one less than what we would expect. Ie. just after
10879          * start of vblank, which also occurs at start of hsync (on the
10880          * last active line), the scanline counter will read vblank_start-1.
10881          *
10882          * On gen2 the scanline counter starts counting from 1 instead
10883          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10884          * to keep the value positive), instead of adding one.
10885          *
10886          * On HSW+ the behaviour of the scanline counter depends on the output
10887          * type. For DP ports it behaves like most other platforms, but on HDMI
10888          * there's an extra 1 line difference. So we need to add two instead of
10889          * one to the value.
10890          */
10891         if (IS_GEN2(dev)) {
10892                 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10893                 int vtotal;
10894
10895                 vtotal = mode->crtc_vtotal;
10896                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10897                         vtotal /= 2;
10898
10899                 crtc->scanline_offset = vtotal - 1;
10900         } else if (HAS_DDI(dev) &&
10901                    intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
10902                 crtc->scanline_offset = 2;
10903         } else
10904                 crtc->scanline_offset = 1;
10905 }
10906
10907 static int __intel_set_mode(struct drm_crtc *crtc,
10908                             struct drm_display_mode *mode,
10909                             int x, int y, struct drm_framebuffer *fb)
10910 {
10911         struct drm_device *dev = crtc->dev;
10912         struct drm_i915_private *dev_priv = dev->dev_private;
10913         struct drm_display_mode *saved_mode;
10914         struct intel_crtc_config *pipe_config = NULL;
10915         struct intel_crtc *intel_crtc;
10916         unsigned disable_pipes, prepare_pipes, modeset_pipes;
10917         int ret = 0;
10918
10919         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10920         if (!saved_mode)
10921                 return -ENOMEM;
10922
10923         intel_modeset_affected_pipes(crtc, &modeset_pipes,
10924                                      &prepare_pipes, &disable_pipes);
10925
10926         *saved_mode = crtc->mode;
10927
10928         /* Hack: Because we don't (yet) support global modeset on multiple
10929          * crtcs, we don't keep track of the new mode for more than one crtc.
10930          * Hence simply check whether any bit is set in modeset_pipes in all the
10931          * pieces of code that are not yet converted to deal with mutliple crtcs
10932          * changing their mode at the same time. */
10933         if (modeset_pipes) {
10934                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10935                 if (IS_ERR(pipe_config)) {
10936                         ret = PTR_ERR(pipe_config);
10937                         pipe_config = NULL;
10938
10939                         goto out;
10940                 }
10941                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10942                                        "[modeset]");
10943                 to_intel_crtc(crtc)->new_config = pipe_config;
10944         }
10945
10946         /*
10947          * See if the config requires any additional preparation, e.g.
10948          * to adjust global state with pipes off.  We need to do this
10949          * here so we can get the modeset_pipe updated config for the new
10950          * mode set on this crtc.  For other crtcs we need to use the
10951          * adjusted_mode bits in the crtc directly.
10952          */
10953         if (IS_VALLEYVIEW(dev)) {
10954                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10955
10956                 /* may have added more to prepare_pipes than we should */
10957                 prepare_pipes &= ~disable_pipes;
10958         }
10959
10960         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10961                 intel_crtc_disable(&intel_crtc->base);
10962
10963         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10964                 if (intel_crtc->base.enabled)
10965                         dev_priv->display.crtc_disable(&intel_crtc->base);
10966         }
10967
10968         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10969          * to set it here already despite that we pass it down the callchain.
10970          */
10971         if (modeset_pipes) {
10972                 crtc->mode = *mode;
10973                 /* mode_set/enable/disable functions rely on a correct pipe
10974                  * config. */
10975                 to_intel_crtc(crtc)->config = *pipe_config;
10976                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10977
10978                 /*
10979                  * Calculate and store various constants which
10980                  * are later needed by vblank and swap-completion
10981                  * timestamping. They are derived from true hwmode.
10982                  */
10983                 drm_calc_timestamping_constants(crtc,
10984                                                 &pipe_config->adjusted_mode);
10985         }
10986
10987         /* Only after disabling all output pipelines that will be changed can we
10988          * update the the output configuration. */
10989         intel_modeset_update_state(dev, prepare_pipes);
10990
10991         if (dev_priv->display.modeset_global_resources)
10992                 dev_priv->display.modeset_global_resources(dev);
10993
10994         /* Set up the DPLL and any encoders state that needs to adjust or depend
10995          * on the DPLL.
10996          */
10997         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10998                 struct drm_framebuffer *old_fb = crtc->primary->fb;
10999                 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
11000                 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11001
11002                 mutex_lock(&dev->struct_mutex);
11003                 ret = intel_pin_and_fence_fb_obj(dev,
11004                                                  obj,
11005                                                  NULL);
11006                 if (ret != 0) {
11007                         DRM_ERROR("pin & fence failed\n");
11008                         mutex_unlock(&dev->struct_mutex);
11009                         goto done;
11010                 }
11011                 if (old_fb)
11012                         intel_unpin_fb_obj(old_obj);
11013                 i915_gem_track_fb(old_obj, obj,
11014                                   INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11015                 mutex_unlock(&dev->struct_mutex);
11016
11017                 crtc->primary->fb = fb;
11018                 crtc->x = x;
11019                 crtc->y = y;
11020
11021                 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
11022                                                       x, y, fb);
11023                 if (ret)
11024                         goto done;
11025         }
11026
11027         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11028         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11029                 update_scanline_offset(intel_crtc);
11030
11031                 dev_priv->display.crtc_enable(&intel_crtc->base);
11032         }
11033
11034         /* FIXME: add subpixel order */
11035 done:
11036         if (ret && crtc->enabled)
11037                 crtc->mode = *saved_mode;
11038
11039 out:
11040         kfree(pipe_config);
11041         kfree(saved_mode);
11042         return ret;
11043 }
11044
11045 static int intel_set_mode(struct drm_crtc *crtc,
11046                           struct drm_display_mode *mode,
11047                           int x, int y, struct drm_framebuffer *fb)
11048 {
11049         int ret;
11050
11051         ret = __intel_set_mode(crtc, mode, x, y, fb);
11052
11053         if (ret == 0)
11054                 intel_modeset_check_state(crtc->dev);
11055
11056         return ret;
11057 }
11058
11059 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11060 {
11061         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11062 }
11063
11064 #undef for_each_intel_crtc_masked
11065
11066 static void intel_set_config_free(struct intel_set_config *config)
11067 {
11068         if (!config)
11069                 return;
11070
11071         kfree(config->save_connector_encoders);
11072         kfree(config->save_encoder_crtcs);
11073         kfree(config->save_crtc_enabled);
11074         kfree(config);
11075 }
11076
11077 static int intel_set_config_save_state(struct drm_device *dev,
11078                                        struct intel_set_config *config)
11079 {
11080         struct drm_crtc *crtc;
11081         struct drm_encoder *encoder;
11082         struct drm_connector *connector;
11083         int count;
11084
11085         config->save_crtc_enabled =
11086                 kcalloc(dev->mode_config.num_crtc,
11087                         sizeof(bool), GFP_KERNEL);
11088         if (!config->save_crtc_enabled)
11089                 return -ENOMEM;
11090
11091         config->save_encoder_crtcs =
11092                 kcalloc(dev->mode_config.num_encoder,
11093                         sizeof(struct drm_crtc *), GFP_KERNEL);
11094         if (!config->save_encoder_crtcs)
11095                 return -ENOMEM;
11096
11097         config->save_connector_encoders =
11098                 kcalloc(dev->mode_config.num_connector,
11099                         sizeof(struct drm_encoder *), GFP_KERNEL);
11100         if (!config->save_connector_encoders)
11101                 return -ENOMEM;
11102
11103         /* Copy data. Note that driver private data is not affected.
11104          * Should anything bad happen only the expected state is
11105          * restored, not the drivers personal bookkeeping.
11106          */
11107         count = 0;
11108         for_each_crtc(dev, crtc) {
11109                 config->save_crtc_enabled[count++] = crtc->enabled;
11110         }
11111
11112         count = 0;
11113         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11114                 config->save_encoder_crtcs[count++] = encoder->crtc;
11115         }
11116
11117         count = 0;
11118         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11119                 config->save_connector_encoders[count++] = connector->encoder;
11120         }
11121
11122         return 0;
11123 }
11124
11125 static void intel_set_config_restore_state(struct drm_device *dev,
11126                                            struct intel_set_config *config)
11127 {
11128         struct intel_crtc *crtc;
11129         struct intel_encoder *encoder;
11130         struct intel_connector *connector;
11131         int count;
11132
11133         count = 0;
11134         for_each_intel_crtc(dev, crtc) {
11135                 crtc->new_enabled = config->save_crtc_enabled[count++];
11136
11137                 if (crtc->new_enabled)
11138                         crtc->new_config = &crtc->config;
11139                 else
11140                         crtc->new_config = NULL;
11141         }
11142
11143         count = 0;
11144         for_each_intel_encoder(dev, encoder) {
11145                 encoder->new_crtc =
11146                         to_intel_crtc(config->save_encoder_crtcs[count++]);
11147         }
11148
11149         count = 0;
11150         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11151                 connector->new_encoder =
11152                         to_intel_encoder(config->save_connector_encoders[count++]);
11153         }
11154 }
11155
11156 static bool
11157 is_crtc_connector_off(struct drm_mode_set *set)
11158 {
11159         int i;
11160
11161         if (set->num_connectors == 0)
11162                 return false;
11163
11164         if (WARN_ON(set->connectors == NULL))
11165                 return false;
11166
11167         for (i = 0; i < set->num_connectors; i++)
11168                 if (set->connectors[i]->encoder &&
11169                     set->connectors[i]->encoder->crtc == set->crtc &&
11170                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11171                         return true;
11172
11173         return false;
11174 }
11175
11176 static void
11177 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11178                                       struct intel_set_config *config)
11179 {
11180
11181         /* We should be able to check here if the fb has the same properties
11182          * and then just flip_or_move it */
11183         if (is_crtc_connector_off(set)) {
11184                 config->mode_changed = true;
11185         } else if (set->crtc->primary->fb != set->fb) {
11186                 /*
11187                  * If we have no fb, we can only flip as long as the crtc is
11188                  * active, otherwise we need a full mode set.  The crtc may
11189                  * be active if we've only disabled the primary plane, or
11190                  * in fastboot situations.
11191                  */
11192                 if (set->crtc->primary->fb == NULL) {
11193                         struct intel_crtc *intel_crtc =
11194                                 to_intel_crtc(set->crtc);
11195
11196                         if (intel_crtc->active) {
11197                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11198                                 config->fb_changed = true;
11199                         } else {
11200                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11201                                 config->mode_changed = true;
11202                         }
11203                 } else if (set->fb == NULL) {
11204                         config->mode_changed = true;
11205                 } else if (set->fb->pixel_format !=
11206                            set->crtc->primary->fb->pixel_format) {
11207                         config->mode_changed = true;
11208                 } else {
11209                         config->fb_changed = true;
11210                 }
11211         }
11212
11213         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11214                 config->fb_changed = true;
11215
11216         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11217                 DRM_DEBUG_KMS("modes are different, full mode set\n");
11218                 drm_mode_debug_printmodeline(&set->crtc->mode);
11219                 drm_mode_debug_printmodeline(set->mode);
11220                 config->mode_changed = true;
11221         }
11222
11223         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11224                         set->crtc->base.id, config->mode_changed, config->fb_changed);
11225 }
11226
11227 static int
11228 intel_modeset_stage_output_state(struct drm_device *dev,
11229                                  struct drm_mode_set *set,
11230                                  struct intel_set_config *config)
11231 {
11232         struct intel_connector *connector;
11233         struct intel_encoder *encoder;
11234         struct intel_crtc *crtc;
11235         int ro;
11236
11237         /* The upper layers ensure that we either disable a crtc or have a list
11238          * of connectors. For paranoia, double-check this. */
11239         WARN_ON(!set->fb && (set->num_connectors != 0));
11240         WARN_ON(set->fb && (set->num_connectors == 0));
11241
11242         list_for_each_entry(connector, &dev->mode_config.connector_list,
11243                             base.head) {
11244                 /* Otherwise traverse passed in connector list and get encoders
11245                  * for them. */
11246                 for (ro = 0; ro < set->num_connectors; ro++) {
11247                         if (set->connectors[ro] == &connector->base) {
11248                                 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11249                                 break;
11250                         }
11251                 }
11252
11253                 /* If we disable the crtc, disable all its connectors. Also, if
11254                  * the connector is on the changing crtc but not on the new
11255                  * connector list, disable it. */
11256                 if ((!set->fb || ro == set->num_connectors) &&
11257                     connector->base.encoder &&
11258                     connector->base.encoder->crtc == set->crtc) {
11259                         connector->new_encoder = NULL;
11260
11261                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11262                                 connector->base.base.id,
11263                                 connector->base.name);
11264                 }
11265
11266
11267                 if (&connector->new_encoder->base != connector->base.encoder) {
11268                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11269                         config->mode_changed = true;
11270                 }
11271         }
11272         /* connector->new_encoder is now updated for all connectors. */
11273
11274         /* Update crtc of enabled connectors. */
11275         list_for_each_entry(connector, &dev->mode_config.connector_list,
11276                             base.head) {
11277                 struct drm_crtc *new_crtc;
11278
11279                 if (!connector->new_encoder)
11280                         continue;
11281
11282                 new_crtc = connector->new_encoder->base.crtc;
11283
11284                 for (ro = 0; ro < set->num_connectors; ro++) {
11285                         if (set->connectors[ro] == &connector->base)
11286                                 new_crtc = set->crtc;
11287                 }
11288
11289                 /* Make sure the new CRTC will work with the encoder */
11290                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11291                                          new_crtc)) {
11292                         return -EINVAL;
11293                 }
11294                 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11295
11296                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11297                         connector->base.base.id,
11298                         connector->base.name,
11299                         new_crtc->base.id);
11300         }
11301
11302         /* Check for any encoders that needs to be disabled. */
11303         for_each_intel_encoder(dev, encoder) {
11304                 int num_connectors = 0;
11305                 list_for_each_entry(connector,
11306                                     &dev->mode_config.connector_list,
11307                                     base.head) {
11308                         if (connector->new_encoder == encoder) {
11309                                 WARN_ON(!connector->new_encoder->new_crtc);
11310                                 num_connectors++;
11311                         }
11312                 }
11313
11314                 if (num_connectors == 0)
11315                         encoder->new_crtc = NULL;
11316                 else if (num_connectors > 1)
11317                         return -EINVAL;
11318
11319                 /* Only now check for crtc changes so we don't miss encoders
11320                  * that will be disabled. */
11321                 if (&encoder->new_crtc->base != encoder->base.crtc) {
11322                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11323                         config->mode_changed = true;
11324                 }
11325         }
11326         /* Now we've also updated encoder->new_crtc for all encoders. */
11327         list_for_each_entry(connector, &dev->mode_config.connector_list,
11328                             base.head) {
11329                 if (connector->new_encoder)
11330                         if (connector->new_encoder != connector->encoder)
11331                                 connector->encoder = connector->new_encoder;
11332         }
11333         for_each_intel_crtc(dev, crtc) {
11334                 crtc->new_enabled = false;
11335
11336                 for_each_intel_encoder(dev, encoder) {
11337                         if (encoder->new_crtc == crtc) {
11338                                 crtc->new_enabled = true;
11339                                 break;
11340                         }
11341                 }
11342
11343                 if (crtc->new_enabled != crtc->base.enabled) {
11344                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11345                                       crtc->new_enabled ? "en" : "dis");
11346                         config->mode_changed = true;
11347                 }
11348
11349                 if (crtc->new_enabled)
11350                         crtc->new_config = &crtc->config;
11351                 else
11352                         crtc->new_config = NULL;
11353         }
11354
11355         return 0;
11356 }
11357
11358 static void disable_crtc_nofb(struct intel_crtc *crtc)
11359 {
11360         struct drm_device *dev = crtc->base.dev;
11361         struct intel_encoder *encoder;
11362         struct intel_connector *connector;
11363
11364         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11365                       pipe_name(crtc->pipe));
11366
11367         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11368                 if (connector->new_encoder &&
11369                     connector->new_encoder->new_crtc == crtc)
11370                         connector->new_encoder = NULL;
11371         }
11372
11373         for_each_intel_encoder(dev, encoder) {
11374                 if (encoder->new_crtc == crtc)
11375                         encoder->new_crtc = NULL;
11376         }
11377
11378         crtc->new_enabled = false;
11379         crtc->new_config = NULL;
11380 }
11381
11382 static int intel_crtc_set_config(struct drm_mode_set *set)
11383 {
11384         struct drm_device *dev;
11385         struct drm_mode_set save_set;
11386         struct intel_set_config *config;
11387         int ret;
11388
11389         BUG_ON(!set);
11390         BUG_ON(!set->crtc);
11391         BUG_ON(!set->crtc->helper_private);
11392
11393         /* Enforce sane interface api - has been abused by the fb helper. */
11394         BUG_ON(!set->mode && set->fb);
11395         BUG_ON(set->fb && set->num_connectors == 0);
11396
11397         if (set->fb) {
11398                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11399                                 set->crtc->base.id, set->fb->base.id,
11400                                 (int)set->num_connectors, set->x, set->y);
11401         } else {
11402                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11403         }
11404
11405         dev = set->crtc->dev;
11406
11407         ret = -ENOMEM;
11408         config = kzalloc(sizeof(*config), GFP_KERNEL);
11409         if (!config)
11410                 goto out_config;
11411
11412         ret = intel_set_config_save_state(dev, config);
11413         if (ret)
11414                 goto out_config;
11415
11416         save_set.crtc = set->crtc;
11417         save_set.mode = &set->crtc->mode;
11418         save_set.x = set->crtc->x;
11419         save_set.y = set->crtc->y;
11420         save_set.fb = set->crtc->primary->fb;
11421
11422         /* Compute whether we need a full modeset, only an fb base update or no
11423          * change at all. In the future we might also check whether only the
11424          * mode changed, e.g. for LVDS where we only change the panel fitter in
11425          * such cases. */
11426         intel_set_config_compute_mode_changes(set, config);
11427
11428         ret = intel_modeset_stage_output_state(dev, set, config);
11429         if (ret)
11430                 goto fail;
11431
11432         if (config->mode_changed) {
11433                 ret = intel_set_mode(set->crtc, set->mode,
11434                                      set->x, set->y, set->fb);
11435         } else if (config->fb_changed) {
11436                 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11437
11438                 intel_crtc_wait_for_pending_flips(set->crtc);
11439
11440                 ret = intel_pipe_set_base(set->crtc,
11441                                           set->x, set->y, set->fb);
11442
11443                 /*
11444                  * We need to make sure the primary plane is re-enabled if it
11445                  * has previously been turned off.
11446                  */
11447                 if (!intel_crtc->primary_enabled && ret == 0) {
11448                         WARN_ON(!intel_crtc->active);
11449                         intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11450                 }
11451
11452                 /*
11453                  * In the fastboot case this may be our only check of the
11454                  * state after boot.  It would be better to only do it on
11455                  * the first update, but we don't have a nice way of doing that
11456                  * (and really, set_config isn't used much for high freq page
11457                  * flipping, so increasing its cost here shouldn't be a big
11458                  * deal).
11459                  */
11460                 if (i915.fastboot && ret == 0)
11461                         intel_modeset_check_state(set->crtc->dev);
11462         }
11463
11464         if (ret) {
11465                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11466                               set->crtc->base.id, ret);
11467 fail:
11468                 intel_set_config_restore_state(dev, config);
11469
11470                 /*
11471                  * HACK: if the pipe was on, but we didn't have a framebuffer,
11472                  * force the pipe off to avoid oopsing in the modeset code
11473                  * due to fb==NULL. This should only happen during boot since
11474                  * we don't yet reconstruct the FB from the hardware state.
11475                  */
11476                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11477                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11478
11479                 /* Try to restore the config */
11480                 if (config->mode_changed &&
11481                     intel_set_mode(save_set.crtc, save_set.mode,
11482                                    save_set.x, save_set.y, save_set.fb))
11483                         DRM_ERROR("failed to restore config after modeset failure\n");
11484         }
11485
11486 out_config:
11487         intel_set_config_free(config);
11488         return ret;
11489 }
11490
11491 static const struct drm_crtc_funcs intel_crtc_funcs = {
11492         .gamma_set = intel_crtc_gamma_set,
11493         .set_config = intel_crtc_set_config,
11494         .destroy = intel_crtc_destroy,
11495         .page_flip = intel_crtc_page_flip,
11496 };
11497
11498 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11499                                       struct intel_shared_dpll *pll,
11500                                       struct intel_dpll_hw_state *hw_state)
11501 {
11502         uint32_t val;
11503
11504         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11505                 return false;
11506
11507         val = I915_READ(PCH_DPLL(pll->id));
11508         hw_state->dpll = val;
11509         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11510         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11511
11512         return val & DPLL_VCO_ENABLE;
11513 }
11514
11515 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11516                                   struct intel_shared_dpll *pll)
11517 {
11518         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11519         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11520 }
11521
11522 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11523                                 struct intel_shared_dpll *pll)
11524 {
11525         /* PCH refclock must be enabled first */
11526         ibx_assert_pch_refclk_enabled(dev_priv);
11527
11528         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11529
11530         /* Wait for the clocks to stabilize. */
11531         POSTING_READ(PCH_DPLL(pll->id));
11532         udelay(150);
11533
11534         /* The pixel multiplier can only be updated once the
11535          * DPLL is enabled and the clocks are stable.
11536          *
11537          * So write it again.
11538          */
11539         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11540         POSTING_READ(PCH_DPLL(pll->id));
11541         udelay(200);
11542 }
11543
11544 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11545                                  struct intel_shared_dpll *pll)
11546 {
11547         struct drm_device *dev = dev_priv->dev;
11548         struct intel_crtc *crtc;
11549
11550         /* Make sure no transcoder isn't still depending on us. */
11551         for_each_intel_crtc(dev, crtc) {
11552                 if (intel_crtc_to_shared_dpll(crtc) == pll)
11553                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11554         }
11555
11556         I915_WRITE(PCH_DPLL(pll->id), 0);
11557         POSTING_READ(PCH_DPLL(pll->id));
11558         udelay(200);
11559 }
11560
11561 static char *ibx_pch_dpll_names[] = {
11562         "PCH DPLL A",
11563         "PCH DPLL B",
11564 };
11565
11566 static void ibx_pch_dpll_init(struct drm_device *dev)
11567 {
11568         struct drm_i915_private *dev_priv = dev->dev_private;
11569         int i;
11570
11571         dev_priv->num_shared_dpll = 2;
11572
11573         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11574                 dev_priv->shared_dplls[i].id = i;
11575                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11576                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11577                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11578                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11579                 dev_priv->shared_dplls[i].get_hw_state =
11580                         ibx_pch_dpll_get_hw_state;
11581         }
11582 }
11583
11584 static void intel_shared_dpll_init(struct drm_device *dev)
11585 {
11586         struct drm_i915_private *dev_priv = dev->dev_private;
11587
11588         if (HAS_DDI(dev))
11589                 intel_ddi_pll_init(dev);
11590         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11591                 ibx_pch_dpll_init(dev);
11592         else
11593                 dev_priv->num_shared_dpll = 0;
11594
11595         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11596 }
11597
11598 static int
11599 intel_primary_plane_disable(struct drm_plane *plane)
11600 {
11601         struct drm_device *dev = plane->dev;
11602         struct intel_crtc *intel_crtc;
11603
11604         if (!plane->fb)
11605                 return 0;
11606
11607         BUG_ON(!plane->crtc);
11608
11609         intel_crtc = to_intel_crtc(plane->crtc);
11610
11611         /*
11612          * Even though we checked plane->fb above, it's still possible that
11613          * the primary plane has been implicitly disabled because the crtc
11614          * coordinates given weren't visible, or because we detected
11615          * that it was 100% covered by a sprite plane.  Or, the CRTC may be
11616          * off and we've set a fb, but haven't actually turned on the CRTC yet.
11617          * In either case, we need to unpin the FB and let the fb pointer get
11618          * updated, but otherwise we don't need to touch the hardware.
11619          */
11620         if (!intel_crtc->primary_enabled)
11621                 goto disable_unpin;
11622
11623         intel_crtc_wait_for_pending_flips(plane->crtc);
11624         intel_disable_primary_hw_plane(plane, plane->crtc);
11625
11626 disable_unpin:
11627         mutex_lock(&dev->struct_mutex);
11628         i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11629                           INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11630         intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11631         mutex_unlock(&dev->struct_mutex);
11632         plane->fb = NULL;
11633
11634         return 0;
11635 }
11636
11637 static int
11638 intel_check_primary_plane(struct drm_plane *plane,
11639                           struct intel_plane_state *state)
11640 {
11641         struct drm_crtc *crtc = state->crtc;
11642         struct drm_framebuffer *fb = state->fb;
11643         struct drm_rect *dest = &state->dst;
11644         struct drm_rect *src = &state->src;
11645         const struct drm_rect *clip = &state->clip;
11646         int ret;
11647
11648         ret = drm_plane_helper_check_update(plane, crtc, fb,
11649                                             src, dest, clip,
11650                                             DRM_PLANE_HELPER_NO_SCALING,
11651                                             DRM_PLANE_HELPER_NO_SCALING,
11652                                             false, true, &state->visible);
11653         if (ret)
11654                 return ret;
11655
11656         /* no fb bound */
11657         if (state->visible && !fb) {
11658                 DRM_ERROR("No FB bound\n");
11659                 return -EINVAL;
11660         }
11661
11662         return 0;
11663 }
11664
11665 static int
11666 intel_commit_primary_plane(struct drm_plane *plane,
11667                            struct intel_plane_state *state)
11668 {
11669         struct drm_crtc *crtc = state->crtc;
11670         struct drm_framebuffer *fb = state->fb;
11671         struct drm_device *dev = crtc->dev;
11672         struct drm_i915_private *dev_priv = dev->dev_private;
11673         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11674         enum pipe pipe = intel_crtc->pipe;
11675         struct drm_framebuffer *old_fb = plane->fb;
11676         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11677         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11678         struct intel_plane *intel_plane = to_intel_plane(plane);
11679         struct drm_rect *src = &state->src;
11680         int ret;
11681
11682         intel_crtc_wait_for_pending_flips(crtc);
11683
11684         if (intel_crtc_has_pending_flip(crtc)) {
11685                 DRM_ERROR("pipe is still busy with an old pageflip\n");
11686                 return -EBUSY;
11687         }
11688
11689         if (plane->fb != fb) {
11690                 mutex_lock(&dev->struct_mutex);
11691                 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11692                 if (ret == 0)
11693                         i915_gem_track_fb(old_obj, obj,
11694                                           INTEL_FRONTBUFFER_PRIMARY(pipe));
11695                 mutex_unlock(&dev->struct_mutex);
11696                 if (ret != 0) {
11697                         DRM_DEBUG_KMS("pin & fence failed\n");
11698                         return ret;
11699                 }
11700         }
11701
11702         crtc->primary->fb = fb;
11703         crtc->x = src->x1;
11704         crtc->y = src->y1;
11705
11706         intel_plane->crtc_x = state->orig_dst.x1;
11707         intel_plane->crtc_y = state->orig_dst.y1;
11708         intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11709         intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11710         intel_plane->src_x = state->orig_src.x1;
11711         intel_plane->src_y = state->orig_src.y1;
11712         intel_plane->src_w = drm_rect_width(&state->orig_src);
11713         intel_plane->src_h = drm_rect_height(&state->orig_src);
11714         intel_plane->obj = obj;
11715
11716         if (intel_crtc->active) {
11717                 /*
11718                  * FBC does not work on some platforms for rotated
11719                  * planes, so disable it when rotation is not 0 and
11720                  * update it when rotation is set back to 0.
11721                  *
11722                  * FIXME: This is redundant with the fbc update done in
11723                  * the primary plane enable function except that that
11724                  * one is done too late. We eventually need to unify
11725                  * this.
11726                  */
11727                 if (intel_crtc->primary_enabled &&
11728                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11729                     dev_priv->fbc.plane == intel_crtc->plane &&
11730                     intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11731                         intel_disable_fbc(dev);
11732                 }
11733
11734                 if (state->visible) {
11735                         bool was_enabled = intel_crtc->primary_enabled;
11736
11737                         /* FIXME: kill this fastboot hack */
11738                         intel_update_pipe_size(intel_crtc);
11739
11740                         intel_crtc->primary_enabled = true;
11741
11742                         dev_priv->display.update_primary_plane(crtc, plane->fb,
11743                                         crtc->x, crtc->y);
11744
11745                         /*
11746                          * BDW signals flip done immediately if the plane
11747                          * is disabled, even if the plane enable is already
11748                          * armed to occur at the next vblank :(
11749                          */
11750                         if (IS_BROADWELL(dev) && !was_enabled)
11751                                 intel_wait_for_vblank(dev, intel_crtc->pipe);
11752                 } else {
11753                         /*
11754                          * If clipping results in a non-visible primary plane,
11755                          * we'll disable the primary plane.  Note that this is
11756                          * a bit different than what happens if userspace
11757                          * explicitly disables the plane by passing fb=0
11758                          * because plane->fb still gets set and pinned.
11759                          */
11760                         intel_disable_primary_hw_plane(plane, crtc);
11761                 }
11762
11763                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11764
11765                 mutex_lock(&dev->struct_mutex);
11766                 intel_update_fbc(dev);
11767                 mutex_unlock(&dev->struct_mutex);
11768         }
11769
11770         if (old_fb && old_fb != fb) {
11771                 if (intel_crtc->active)
11772                         intel_wait_for_vblank(dev, intel_crtc->pipe);
11773
11774                 mutex_lock(&dev->struct_mutex);
11775                 intel_unpin_fb_obj(old_obj);
11776                 mutex_unlock(&dev->struct_mutex);
11777         }
11778
11779         return 0;
11780 }
11781
11782 static int
11783 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11784                              struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11785                              unsigned int crtc_w, unsigned int crtc_h,
11786                              uint32_t src_x, uint32_t src_y,
11787                              uint32_t src_w, uint32_t src_h)
11788 {
11789         struct intel_plane_state state;
11790         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11791         int ret;
11792
11793         state.crtc = crtc;
11794         state.fb = fb;
11795
11796         /* sample coordinates in 16.16 fixed point */
11797         state.src.x1 = src_x;
11798         state.src.x2 = src_x + src_w;
11799         state.src.y1 = src_y;
11800         state.src.y2 = src_y + src_h;
11801
11802         /* integer pixels */
11803         state.dst.x1 = crtc_x;
11804         state.dst.x2 = crtc_x + crtc_w;
11805         state.dst.y1 = crtc_y;
11806         state.dst.y2 = crtc_y + crtc_h;
11807
11808         state.clip.x1 = 0;
11809         state.clip.y1 = 0;
11810         state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11811         state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11812
11813         state.orig_src = state.src;
11814         state.orig_dst = state.dst;
11815
11816         ret = intel_check_primary_plane(plane, &state);
11817         if (ret)
11818                 return ret;
11819
11820         intel_commit_primary_plane(plane, &state);
11821
11822         return 0;
11823 }
11824
11825 /* Common destruction function for both primary and cursor planes */
11826 static void intel_plane_destroy(struct drm_plane *plane)
11827 {
11828         struct intel_plane *intel_plane = to_intel_plane(plane);
11829         drm_plane_cleanup(plane);
11830         kfree(intel_plane);
11831 }
11832
11833 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11834         .update_plane = intel_primary_plane_setplane,
11835         .disable_plane = intel_primary_plane_disable,
11836         .destroy = intel_plane_destroy,
11837         .set_property = intel_plane_set_property
11838 };
11839
11840 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11841                                                     int pipe)
11842 {
11843         struct intel_plane *primary;
11844         const uint32_t *intel_primary_formats;
11845         int num_formats;
11846
11847         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11848         if (primary == NULL)
11849                 return NULL;
11850
11851         primary->can_scale = false;
11852         primary->max_downscale = 1;
11853         primary->pipe = pipe;
11854         primary->plane = pipe;
11855         primary->rotation = BIT(DRM_ROTATE_0);
11856         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11857                 primary->plane = !pipe;
11858
11859         if (INTEL_INFO(dev)->gen <= 3) {
11860                 intel_primary_formats = intel_primary_formats_gen2;
11861                 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11862         } else {
11863                 intel_primary_formats = intel_primary_formats_gen4;
11864                 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11865         }
11866
11867         drm_universal_plane_init(dev, &primary->base, 0,
11868                                  &intel_primary_plane_funcs,
11869                                  intel_primary_formats, num_formats,
11870                                  DRM_PLANE_TYPE_PRIMARY);
11871
11872         if (INTEL_INFO(dev)->gen >= 4) {
11873                 if (!dev->mode_config.rotation_property)
11874                         dev->mode_config.rotation_property =
11875                                 drm_mode_create_rotation_property(dev,
11876                                                         BIT(DRM_ROTATE_0) |
11877                                                         BIT(DRM_ROTATE_180));
11878                 if (dev->mode_config.rotation_property)
11879                         drm_object_attach_property(&primary->base.base,
11880                                 dev->mode_config.rotation_property,
11881                                 primary->rotation);
11882         }
11883
11884         return &primary->base;
11885 }
11886
11887 static int
11888 intel_cursor_plane_disable(struct drm_plane *plane)
11889 {
11890         if (!plane->fb)
11891                 return 0;
11892
11893         BUG_ON(!plane->crtc);
11894
11895         return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11896 }
11897
11898 static int
11899 intel_check_cursor_plane(struct drm_plane *plane,
11900                          struct intel_plane_state *state)
11901 {
11902         struct drm_crtc *crtc = state->crtc;
11903         struct drm_device *dev = crtc->dev;
11904         struct drm_framebuffer *fb = state->fb;
11905         struct drm_rect *dest = &state->dst;
11906         struct drm_rect *src = &state->src;
11907         const struct drm_rect *clip = &state->clip;
11908         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11909         int crtc_w, crtc_h;
11910         unsigned stride;
11911         int ret;
11912
11913         ret = drm_plane_helper_check_update(plane, crtc, fb,
11914                                             src, dest, clip,
11915                                             DRM_PLANE_HELPER_NO_SCALING,
11916                                             DRM_PLANE_HELPER_NO_SCALING,
11917                                             true, true, &state->visible);
11918         if (ret)
11919                 return ret;
11920
11921
11922         /* if we want to turn off the cursor ignore width and height */
11923         if (!obj)
11924                 return 0;
11925
11926         /* Check for which cursor types we support */
11927         crtc_w = drm_rect_width(&state->orig_dst);
11928         crtc_h = drm_rect_height(&state->orig_dst);
11929         if (!cursor_size_ok(dev, crtc_w, crtc_h)) {
11930                 DRM_DEBUG("Cursor dimension not supported\n");
11931                 return -EINVAL;
11932         }
11933
11934         stride = roundup_pow_of_two(crtc_w) * 4;
11935         if (obj->base.size < stride * crtc_h) {
11936                 DRM_DEBUG_KMS("buffer is too small\n");
11937                 return -ENOMEM;
11938         }
11939
11940         if (fb == crtc->cursor->fb)
11941                 return 0;
11942
11943         /* we only need to pin inside GTT if cursor is non-phy */
11944         mutex_lock(&dev->struct_mutex);
11945         if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
11946                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
11947                 ret = -EINVAL;
11948         }
11949         mutex_unlock(&dev->struct_mutex);
11950
11951         return ret;
11952 }
11953
11954 static int
11955 intel_commit_cursor_plane(struct drm_plane *plane,
11956                           struct intel_plane_state *state)
11957 {
11958         struct drm_crtc *crtc = state->crtc;
11959         struct drm_framebuffer *fb = state->fb;
11960         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11961         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11962         struct drm_i915_gem_object *obj = intel_fb->obj;
11963         int crtc_w, crtc_h;
11964
11965         crtc->cursor_x = state->orig_dst.x1;
11966         crtc->cursor_y = state->orig_dst.y1;
11967         if (fb != crtc->cursor->fb) {
11968                 crtc_w = drm_rect_width(&state->orig_dst);
11969                 crtc_h = drm_rect_height(&state->orig_dst);
11970                 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11971         } else {
11972                 intel_crtc_update_cursor(crtc, state->visible);
11973
11974                 intel_frontbuffer_flip(crtc->dev,
11975                                        INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
11976
11977                 return 0;
11978         }
11979 }
11980
11981 static int
11982 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11983                           struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11984                           unsigned int crtc_w, unsigned int crtc_h,
11985                           uint32_t src_x, uint32_t src_y,
11986                           uint32_t src_w, uint32_t src_h)
11987 {
11988         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11989         struct intel_plane_state state;
11990         int ret;
11991
11992         state.crtc = crtc;
11993         state.fb = fb;
11994
11995         /* sample coordinates in 16.16 fixed point */
11996         state.src.x1 = src_x;
11997         state.src.x2 = src_x + src_w;
11998         state.src.y1 = src_y;
11999         state.src.y2 = src_y + src_h;
12000
12001         /* integer pixels */
12002         state.dst.x1 = crtc_x;
12003         state.dst.x2 = crtc_x + crtc_w;
12004         state.dst.y1 = crtc_y;
12005         state.dst.y2 = crtc_y + crtc_h;
12006
12007         state.clip.x1 = 0;
12008         state.clip.y1 = 0;
12009         state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
12010         state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
12011
12012         state.orig_src = state.src;
12013         state.orig_dst = state.dst;
12014
12015         ret = intel_check_cursor_plane(plane, &state);
12016         if (ret)
12017                 return ret;
12018
12019         return intel_commit_cursor_plane(plane, &state);
12020 }
12021
12022 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
12023         .update_plane = intel_cursor_plane_update,
12024         .disable_plane = intel_cursor_plane_disable,
12025         .destroy = intel_plane_destroy,
12026 };
12027
12028 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12029                                                    int pipe)
12030 {
12031         struct intel_plane *cursor;
12032
12033         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12034         if (cursor == NULL)
12035                 return NULL;
12036
12037         cursor->can_scale = false;
12038         cursor->max_downscale = 1;
12039         cursor->pipe = pipe;
12040         cursor->plane = pipe;
12041
12042         drm_universal_plane_init(dev, &cursor->base, 0,
12043                                  &intel_cursor_plane_funcs,
12044                                  intel_cursor_formats,
12045                                  ARRAY_SIZE(intel_cursor_formats),
12046                                  DRM_PLANE_TYPE_CURSOR);
12047         return &cursor->base;
12048 }
12049
12050 static void intel_crtc_init(struct drm_device *dev, int pipe)
12051 {
12052         struct drm_i915_private *dev_priv = dev->dev_private;
12053         struct intel_crtc *intel_crtc;
12054         struct drm_plane *primary = NULL;
12055         struct drm_plane *cursor = NULL;
12056         int i, ret;
12057
12058         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12059         if (intel_crtc == NULL)
12060                 return;
12061
12062         primary = intel_primary_plane_create(dev, pipe);
12063         if (!primary)
12064                 goto fail;
12065
12066         cursor = intel_cursor_plane_create(dev, pipe);
12067         if (!cursor)
12068                 goto fail;
12069
12070         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12071                                         cursor, &intel_crtc_funcs);
12072         if (ret)
12073                 goto fail;
12074
12075         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12076         for (i = 0; i < 256; i++) {
12077                 intel_crtc->lut_r[i] = i;
12078                 intel_crtc->lut_g[i] = i;
12079                 intel_crtc->lut_b[i] = i;
12080         }
12081
12082         /*
12083          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12084          * is hooked to pipe B. Hence we want plane A feeding pipe B.
12085          */
12086         intel_crtc->pipe = pipe;
12087         intel_crtc->plane = pipe;
12088         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12089                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12090                 intel_crtc->plane = !pipe;
12091         }
12092
12093         intel_crtc->cursor_base = ~0;
12094         intel_crtc->cursor_cntl = ~0;
12095         intel_crtc->cursor_size = ~0;
12096
12097         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12098                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12099         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12100         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12101
12102         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12103
12104         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12105         return;
12106
12107 fail:
12108         if (primary)
12109                 drm_plane_cleanup(primary);
12110         if (cursor)
12111                 drm_plane_cleanup(cursor);
12112         kfree(intel_crtc);
12113 }
12114
12115 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12116 {
12117         struct drm_encoder *encoder = connector->base.encoder;
12118         struct drm_device *dev = connector->base.dev;
12119
12120         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12121
12122         if (!encoder)
12123                 return INVALID_PIPE;
12124
12125         return to_intel_crtc(encoder->crtc)->pipe;
12126 }
12127
12128 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12129                                 struct drm_file *file)
12130 {
12131         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12132         struct drm_crtc *drmmode_crtc;
12133         struct intel_crtc *crtc;
12134
12135         if (!drm_core_check_feature(dev, DRIVER_MODESET))
12136                 return -ENODEV;
12137
12138         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12139
12140         if (!drmmode_crtc) {
12141                 DRM_ERROR("no such CRTC id\n");
12142                 return -ENOENT;
12143         }
12144
12145         crtc = to_intel_crtc(drmmode_crtc);
12146         pipe_from_crtc_id->pipe = crtc->pipe;
12147
12148         return 0;
12149 }
12150
12151 static int intel_encoder_clones(struct intel_encoder *encoder)
12152 {
12153         struct drm_device *dev = encoder->base.dev;
12154         struct intel_encoder *source_encoder;
12155         int index_mask = 0;
12156         int entry = 0;
12157
12158         for_each_intel_encoder(dev, source_encoder) {
12159                 if (encoders_cloneable(encoder, source_encoder))
12160                         index_mask |= (1 << entry);
12161
12162                 entry++;
12163         }
12164
12165         return index_mask;
12166 }
12167
12168 static bool has_edp_a(struct drm_device *dev)
12169 {
12170         struct drm_i915_private *dev_priv = dev->dev_private;
12171
12172         if (!IS_MOBILE(dev))
12173                 return false;
12174
12175         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12176                 return false;
12177
12178         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12179                 return false;
12180
12181         return true;
12182 }
12183
12184 const char *intel_output_name(int output)
12185 {
12186         static const char *names[] = {
12187                 [INTEL_OUTPUT_UNUSED] = "Unused",
12188                 [INTEL_OUTPUT_ANALOG] = "Analog",
12189                 [INTEL_OUTPUT_DVO] = "DVO",
12190                 [INTEL_OUTPUT_SDVO] = "SDVO",
12191                 [INTEL_OUTPUT_LVDS] = "LVDS",
12192                 [INTEL_OUTPUT_TVOUT] = "TV",
12193                 [INTEL_OUTPUT_HDMI] = "HDMI",
12194                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
12195                 [INTEL_OUTPUT_EDP] = "eDP",
12196                 [INTEL_OUTPUT_DSI] = "DSI",
12197                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
12198         };
12199
12200         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
12201                 return "Invalid";
12202
12203         return names[output];
12204 }
12205
12206 static bool intel_crt_present(struct drm_device *dev)
12207 {
12208         struct drm_i915_private *dev_priv = dev->dev_private;
12209
12210         if (INTEL_INFO(dev)->gen >= 9)
12211                 return false;
12212
12213         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12214                 return false;
12215
12216         if (IS_CHERRYVIEW(dev))
12217                 return false;
12218
12219         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12220                 return false;
12221
12222         return true;
12223 }
12224
12225 static void intel_setup_outputs(struct drm_device *dev)
12226 {
12227         struct drm_i915_private *dev_priv = dev->dev_private;
12228         struct intel_encoder *encoder;
12229         bool dpd_is_edp = false;
12230
12231         intel_lvds_init(dev);
12232
12233         if (intel_crt_present(dev))
12234                 intel_crt_init(dev);
12235
12236         if (HAS_DDI(dev)) {
12237                 int found;
12238
12239                 /* Haswell uses DDI functions to detect digital outputs */
12240                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12241                 /* DDI A only supports eDP */
12242                 if (found)
12243                         intel_ddi_init(dev, PORT_A);
12244
12245                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12246                  * register */
12247                 found = I915_READ(SFUSE_STRAP);
12248
12249                 if (found & SFUSE_STRAP_DDIB_DETECTED)
12250                         intel_ddi_init(dev, PORT_B);
12251                 if (found & SFUSE_STRAP_DDIC_DETECTED)
12252                         intel_ddi_init(dev, PORT_C);
12253                 if (found & SFUSE_STRAP_DDID_DETECTED)
12254                         intel_ddi_init(dev, PORT_D);
12255         } else if (HAS_PCH_SPLIT(dev)) {
12256                 int found;
12257                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12258
12259                 if (has_edp_a(dev))
12260                         intel_dp_init(dev, DP_A, PORT_A);
12261
12262                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12263                         /* PCH SDVOB multiplex with HDMIB */
12264                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
12265                         if (!found)
12266                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12267                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12268                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
12269                 }
12270
12271                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12272                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12273
12274                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12275                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12276
12277                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12278                         intel_dp_init(dev, PCH_DP_C, PORT_C);
12279
12280                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12281                         intel_dp_init(dev, PCH_DP_D, PORT_D);
12282         } else if (IS_VALLEYVIEW(dev)) {
12283                 /*
12284                  * The DP_DETECTED bit is the latched state of the DDC
12285                  * SDA pin at boot. However since eDP doesn't require DDC
12286                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
12287                  * eDP ports may have been muxed to an alternate function.
12288                  * Thus we can't rely on the DP_DETECTED bit alone to detect
12289                  * eDP ports. Consult the VBT as well as DP_DETECTED to
12290                  * detect eDP ports.
12291                  */
12292                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED)
12293                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12294                                         PORT_B);
12295                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12296                     intel_dp_is_edp(dev, PORT_B))
12297                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12298
12299                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED)
12300                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12301                                         PORT_C);
12302                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12303                     intel_dp_is_edp(dev, PORT_C))
12304                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12305
12306                 if (IS_CHERRYVIEW(dev)) {
12307                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12308                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12309                                                 PORT_D);
12310                         /* eDP not supported on port D, so don't check VBT */
12311                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12312                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12313                 }
12314
12315                 intel_dsi_init(dev);
12316         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12317                 bool found = false;
12318
12319                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12320                         DRM_DEBUG_KMS("probing SDVOB\n");
12321                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12322                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12323                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12324                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12325                         }
12326
12327                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
12328                                 intel_dp_init(dev, DP_B, PORT_B);
12329                 }
12330
12331                 /* Before G4X SDVOC doesn't have its own detect register */
12332
12333                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12334                         DRM_DEBUG_KMS("probing SDVOC\n");
12335                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12336                 }
12337
12338                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12339
12340                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12341                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12342                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12343                         }
12344                         if (SUPPORTS_INTEGRATED_DP(dev))
12345                                 intel_dp_init(dev, DP_C, PORT_C);
12346                 }
12347
12348                 if (SUPPORTS_INTEGRATED_DP(dev) &&
12349                     (I915_READ(DP_D) & DP_DETECTED))
12350                         intel_dp_init(dev, DP_D, PORT_D);
12351         } else if (IS_GEN2(dev))
12352                 intel_dvo_init(dev);
12353
12354         if (SUPPORTS_TV(dev))
12355                 intel_tv_init(dev);
12356
12357         intel_edp_psr_init(dev);
12358
12359         for_each_intel_encoder(dev, encoder) {
12360                 encoder->base.possible_crtcs = encoder->crtc_mask;
12361                 encoder->base.possible_clones =
12362                         intel_encoder_clones(encoder);
12363         }
12364
12365         intel_init_pch_refclk(dev);
12366
12367         drm_helper_move_panel_connectors_to_head(dev);
12368 }
12369
12370 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12371 {
12372         struct drm_device *dev = fb->dev;
12373         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12374
12375         drm_framebuffer_cleanup(fb);
12376         mutex_lock(&dev->struct_mutex);
12377         WARN_ON(!intel_fb->obj->framebuffer_references--);
12378         drm_gem_object_unreference(&intel_fb->obj->base);
12379         mutex_unlock(&dev->struct_mutex);
12380         kfree(intel_fb);
12381 }
12382
12383 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12384                                                 struct drm_file *file,
12385                                                 unsigned int *handle)
12386 {
12387         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12388         struct drm_i915_gem_object *obj = intel_fb->obj;
12389
12390         return drm_gem_handle_create(file, &obj->base, handle);
12391 }
12392
12393 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12394         .destroy = intel_user_framebuffer_destroy,
12395         .create_handle = intel_user_framebuffer_create_handle,
12396 };
12397
12398 static int intel_framebuffer_init(struct drm_device *dev,
12399                                   struct intel_framebuffer *intel_fb,
12400                                   struct drm_mode_fb_cmd2 *mode_cmd,
12401                                   struct drm_i915_gem_object *obj)
12402 {
12403         int aligned_height;
12404         int pitch_limit;
12405         int ret;
12406
12407         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12408
12409         if (obj->tiling_mode == I915_TILING_Y) {
12410                 DRM_DEBUG("hardware does not support tiling Y\n");
12411                 return -EINVAL;
12412         }
12413
12414         if (mode_cmd->pitches[0] & 63) {
12415                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12416                           mode_cmd->pitches[0]);
12417                 return -EINVAL;
12418         }
12419
12420         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12421                 pitch_limit = 32*1024;
12422         } else if (INTEL_INFO(dev)->gen >= 4) {
12423                 if (obj->tiling_mode)
12424                         pitch_limit = 16*1024;
12425                 else
12426                         pitch_limit = 32*1024;
12427         } else if (INTEL_INFO(dev)->gen >= 3) {
12428                 if (obj->tiling_mode)
12429                         pitch_limit = 8*1024;
12430                 else
12431                         pitch_limit = 16*1024;
12432         } else
12433                 /* XXX DSPC is limited to 4k tiled */
12434                 pitch_limit = 8*1024;
12435
12436         if (mode_cmd->pitches[0] > pitch_limit) {
12437                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12438                           obj->tiling_mode ? "tiled" : "linear",
12439                           mode_cmd->pitches[0], pitch_limit);
12440                 return -EINVAL;
12441         }
12442
12443         if (obj->tiling_mode != I915_TILING_NONE &&
12444             mode_cmd->pitches[0] != obj->stride) {
12445                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12446                           mode_cmd->pitches[0], obj->stride);
12447                 return -EINVAL;
12448         }
12449
12450         /* Reject formats not supported by any plane early. */
12451         switch (mode_cmd->pixel_format) {
12452         case DRM_FORMAT_C8:
12453         case DRM_FORMAT_RGB565:
12454         case DRM_FORMAT_XRGB8888:
12455         case DRM_FORMAT_ARGB8888:
12456                 break;
12457         case DRM_FORMAT_XRGB1555:
12458         case DRM_FORMAT_ARGB1555:
12459                 if (INTEL_INFO(dev)->gen > 3) {
12460                         DRM_DEBUG("unsupported pixel format: %s\n",
12461                                   drm_get_format_name(mode_cmd->pixel_format));
12462                         return -EINVAL;
12463                 }
12464                 break;
12465         case DRM_FORMAT_XBGR8888:
12466         case DRM_FORMAT_ABGR8888:
12467         case DRM_FORMAT_XRGB2101010:
12468         case DRM_FORMAT_ARGB2101010:
12469         case DRM_FORMAT_XBGR2101010:
12470         case DRM_FORMAT_ABGR2101010:
12471                 if (INTEL_INFO(dev)->gen < 4) {
12472                         DRM_DEBUG("unsupported pixel format: %s\n",
12473                                   drm_get_format_name(mode_cmd->pixel_format));
12474                         return -EINVAL;
12475                 }
12476                 break;
12477         case DRM_FORMAT_YUYV:
12478         case DRM_FORMAT_UYVY:
12479         case DRM_FORMAT_YVYU:
12480         case DRM_FORMAT_VYUY:
12481                 if (INTEL_INFO(dev)->gen < 5) {
12482                         DRM_DEBUG("unsupported pixel format: %s\n",
12483                                   drm_get_format_name(mode_cmd->pixel_format));
12484                         return -EINVAL;
12485                 }
12486                 break;
12487         default:
12488                 DRM_DEBUG("unsupported pixel format: %s\n",
12489                           drm_get_format_name(mode_cmd->pixel_format));
12490                 return -EINVAL;
12491         }
12492
12493         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12494         if (mode_cmd->offsets[0] != 0)
12495                 return -EINVAL;
12496
12497         aligned_height = intel_align_height(dev, mode_cmd->height,
12498                                             obj->tiling_mode);
12499         /* FIXME drm helper for size checks (especially planar formats)? */
12500         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12501                 return -EINVAL;
12502
12503         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12504         intel_fb->obj = obj;
12505         intel_fb->obj->framebuffer_references++;
12506
12507         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12508         if (ret) {
12509                 DRM_ERROR("framebuffer init failed %d\n", ret);
12510                 return ret;
12511         }
12512
12513         return 0;
12514 }
12515
12516 static struct drm_framebuffer *
12517 intel_user_framebuffer_create(struct drm_device *dev,
12518                               struct drm_file *filp,
12519                               struct drm_mode_fb_cmd2 *mode_cmd)
12520 {
12521         struct drm_i915_gem_object *obj;
12522
12523         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12524                                                 mode_cmd->handles[0]));
12525         if (&obj->base == NULL)
12526                 return ERR_PTR(-ENOENT);
12527
12528         return intel_framebuffer_create(dev, mode_cmd, obj);
12529 }
12530
12531 #ifndef CONFIG_DRM_I915_FBDEV
12532 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12533 {
12534 }
12535 #endif
12536
12537 static const struct drm_mode_config_funcs intel_mode_funcs = {
12538         .fb_create = intel_user_framebuffer_create,
12539         .output_poll_changed = intel_fbdev_output_poll_changed,
12540 };
12541
12542 /* Set up chip specific display functions */
12543 static void intel_init_display(struct drm_device *dev)
12544 {
12545         struct drm_i915_private *dev_priv = dev->dev_private;
12546
12547         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12548                 dev_priv->display.find_dpll = g4x_find_best_dpll;
12549         else if (IS_CHERRYVIEW(dev))
12550                 dev_priv->display.find_dpll = chv_find_best_dpll;
12551         else if (IS_VALLEYVIEW(dev))
12552                 dev_priv->display.find_dpll = vlv_find_best_dpll;
12553         else if (IS_PINEVIEW(dev))
12554                 dev_priv->display.find_dpll = pnv_find_best_dpll;
12555         else
12556                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12557
12558         if (HAS_DDI(dev)) {
12559                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12560                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12561                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
12562                 dev_priv->display.crtc_enable = haswell_crtc_enable;
12563                 dev_priv->display.crtc_disable = haswell_crtc_disable;
12564                 dev_priv->display.off = ironlake_crtc_off;
12565                 if (INTEL_INFO(dev)->gen >= 9)
12566                         dev_priv->display.update_primary_plane =
12567                                 skylake_update_primary_plane;
12568                 else
12569                         dev_priv->display.update_primary_plane =
12570                                 ironlake_update_primary_plane;
12571         } else if (HAS_PCH_SPLIT(dev)) {
12572                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12573                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12574                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
12575                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12576                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12577                 dev_priv->display.off = ironlake_crtc_off;
12578                 dev_priv->display.update_primary_plane =
12579                         ironlake_update_primary_plane;
12580         } else if (IS_VALLEYVIEW(dev)) {
12581                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12582                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12583                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12584                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12585                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12586                 dev_priv->display.off = i9xx_crtc_off;
12587                 dev_priv->display.update_primary_plane =
12588                         i9xx_update_primary_plane;
12589         } else {
12590                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12591                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12592                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12593                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12594                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12595                 dev_priv->display.off = i9xx_crtc_off;
12596                 dev_priv->display.update_primary_plane =
12597                         i9xx_update_primary_plane;
12598         }
12599
12600         /* Returns the core display clock speed */
12601         if (IS_VALLEYVIEW(dev))
12602                 dev_priv->display.get_display_clock_speed =
12603                         valleyview_get_display_clock_speed;
12604         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12605                 dev_priv->display.get_display_clock_speed =
12606                         i945_get_display_clock_speed;
12607         else if (IS_I915G(dev))
12608                 dev_priv->display.get_display_clock_speed =
12609                         i915_get_display_clock_speed;
12610         else if (IS_I945GM(dev) || IS_845G(dev))
12611                 dev_priv->display.get_display_clock_speed =
12612                         i9xx_misc_get_display_clock_speed;
12613         else if (IS_PINEVIEW(dev))
12614                 dev_priv->display.get_display_clock_speed =
12615                         pnv_get_display_clock_speed;
12616         else if (IS_I915GM(dev))
12617                 dev_priv->display.get_display_clock_speed =
12618                         i915gm_get_display_clock_speed;
12619         else if (IS_I865G(dev))
12620                 dev_priv->display.get_display_clock_speed =
12621                         i865_get_display_clock_speed;
12622         else if (IS_I85X(dev))
12623                 dev_priv->display.get_display_clock_speed =
12624                         i855_get_display_clock_speed;
12625         else /* 852, 830 */
12626                 dev_priv->display.get_display_clock_speed =
12627                         i830_get_display_clock_speed;
12628
12629         if (IS_G4X(dev)) {
12630                 dev_priv->display.write_eld = g4x_write_eld;
12631         } else if (IS_GEN5(dev)) {
12632                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12633                 dev_priv->display.write_eld = ironlake_write_eld;
12634         } else if (IS_GEN6(dev)) {
12635                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12636                 dev_priv->display.write_eld = ironlake_write_eld;
12637                 dev_priv->display.modeset_global_resources =
12638                         snb_modeset_global_resources;
12639         } else if (IS_IVYBRIDGE(dev)) {
12640                 /* FIXME: detect B0+ stepping and use auto training */
12641                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12642                 dev_priv->display.write_eld = ironlake_write_eld;
12643                 dev_priv->display.modeset_global_resources =
12644                         ivb_modeset_global_resources;
12645         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12646                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12647                 dev_priv->display.write_eld = haswell_write_eld;
12648                 dev_priv->display.modeset_global_resources =
12649                         haswell_modeset_global_resources;
12650         } else if (IS_VALLEYVIEW(dev)) {
12651                 dev_priv->display.modeset_global_resources =
12652                         valleyview_modeset_global_resources;
12653                 dev_priv->display.write_eld = ironlake_write_eld;
12654         } else if (INTEL_INFO(dev)->gen >= 9) {
12655                 dev_priv->display.write_eld = haswell_write_eld;
12656                 dev_priv->display.modeset_global_resources =
12657                         haswell_modeset_global_resources;
12658         }
12659
12660         /* Default just returns -ENODEV to indicate unsupported */
12661         dev_priv->display.queue_flip = intel_default_queue_flip;
12662
12663         switch (INTEL_INFO(dev)->gen) {
12664         case 2:
12665                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12666                 break;
12667
12668         case 3:
12669                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12670                 break;
12671
12672         case 4:
12673         case 5:
12674                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12675                 break;
12676
12677         case 6:
12678                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12679                 break;
12680         case 7:
12681         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12682                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12683                 break;
12684         }
12685
12686         intel_panel_init_backlight_funcs(dev);
12687
12688         mutex_init(&dev_priv->pps_mutex);
12689 }
12690
12691 /*
12692  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12693  * resume, or other times.  This quirk makes sure that's the case for
12694  * affected systems.
12695  */
12696 static void quirk_pipea_force(struct drm_device *dev)
12697 {
12698         struct drm_i915_private *dev_priv = dev->dev_private;
12699
12700         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12701         DRM_INFO("applying pipe a force quirk\n");
12702 }
12703
12704 static void quirk_pipeb_force(struct drm_device *dev)
12705 {
12706         struct drm_i915_private *dev_priv = dev->dev_private;
12707
12708         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12709         DRM_INFO("applying pipe b force quirk\n");
12710 }
12711
12712 /*
12713  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12714  */
12715 static void quirk_ssc_force_disable(struct drm_device *dev)
12716 {
12717         struct drm_i915_private *dev_priv = dev->dev_private;
12718         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12719         DRM_INFO("applying lvds SSC disable quirk\n");
12720 }
12721
12722 /*
12723  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12724  * brightness value
12725  */
12726 static void quirk_invert_brightness(struct drm_device *dev)
12727 {
12728         struct drm_i915_private *dev_priv = dev->dev_private;
12729         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12730         DRM_INFO("applying inverted panel brightness quirk\n");
12731 }
12732
12733 /* Some VBT's incorrectly indicate no backlight is present */
12734 static void quirk_backlight_present(struct drm_device *dev)
12735 {
12736         struct drm_i915_private *dev_priv = dev->dev_private;
12737         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12738         DRM_INFO("applying backlight present quirk\n");
12739 }
12740
12741 struct intel_quirk {
12742         int device;
12743         int subsystem_vendor;
12744         int subsystem_device;
12745         void (*hook)(struct drm_device *dev);
12746 };
12747
12748 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12749 struct intel_dmi_quirk {
12750         void (*hook)(struct drm_device *dev);
12751         const struct dmi_system_id (*dmi_id_list)[];
12752 };
12753
12754 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12755 {
12756         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12757         return 1;
12758 }
12759
12760 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12761         {
12762                 .dmi_id_list = &(const struct dmi_system_id[]) {
12763                         {
12764                                 .callback = intel_dmi_reverse_brightness,
12765                                 .ident = "NCR Corporation",
12766                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12767                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
12768                                 },
12769                         },
12770                         { }  /* terminating entry */
12771                 },
12772                 .hook = quirk_invert_brightness,
12773         },
12774 };
12775
12776 static struct intel_quirk intel_quirks[] = {
12777         /* HP Mini needs pipe A force quirk (LP: #322104) */
12778         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12779
12780         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12781         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12782
12783         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12784         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12785
12786         /* 830 needs to leave pipe A & dpll A up */
12787         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
12788
12789         /* 830 needs to leave pipe B & dpll B up */
12790         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
12791
12792         /* Lenovo U160 cannot use SSC on LVDS */
12793         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12794
12795         /* Sony Vaio Y cannot use SSC on LVDS */
12796         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12797
12798         /* Acer Aspire 5734Z must invert backlight brightness */
12799         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12800
12801         /* Acer/eMachines G725 */
12802         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12803
12804         /* Acer/eMachines e725 */
12805         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12806
12807         /* Acer/Packard Bell NCL20 */
12808         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12809
12810         /* Acer Aspire 4736Z */
12811         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12812
12813         /* Acer Aspire 5336 */
12814         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12815
12816         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12817         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12818
12819         /* Acer C720 Chromebook (Core i3 4005U) */
12820         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
12821
12822         /* Toshiba CB35 Chromebook (Celeron 2955U) */
12823         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12824
12825         /* HP Chromebook 14 (Celeron 2955U) */
12826         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12827 };
12828
12829 static void intel_init_quirks(struct drm_device *dev)
12830 {
12831         struct pci_dev *d = dev->pdev;
12832         int i;
12833
12834         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12835                 struct intel_quirk *q = &intel_quirks[i];
12836
12837                 if (d->device == q->device &&
12838                     (d->subsystem_vendor == q->subsystem_vendor ||
12839                      q->subsystem_vendor == PCI_ANY_ID) &&
12840                     (d->subsystem_device == q->subsystem_device ||
12841                      q->subsystem_device == PCI_ANY_ID))
12842                         q->hook(dev);
12843         }
12844         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12845                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12846                         intel_dmi_quirks[i].hook(dev);
12847         }
12848 }
12849
12850 /* Disable the VGA plane that we never use */
12851 static void i915_disable_vga(struct drm_device *dev)
12852 {
12853         struct drm_i915_private *dev_priv = dev->dev_private;
12854         u8 sr1;
12855         u32 vga_reg = i915_vgacntrl_reg(dev);
12856
12857         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12858         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12859         outb(SR01, VGA_SR_INDEX);
12860         sr1 = inb(VGA_SR_DATA);
12861         outb(sr1 | 1<<5, VGA_SR_DATA);
12862         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12863         udelay(300);
12864
12865         /*
12866          * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12867          * from S3 without preserving (some of?) the other bits.
12868          */
12869         I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
12870         POSTING_READ(vga_reg);
12871 }
12872
12873 void intel_modeset_init_hw(struct drm_device *dev)
12874 {
12875         intel_prepare_ddi(dev);
12876
12877         if (IS_VALLEYVIEW(dev))
12878                 vlv_update_cdclk(dev);
12879
12880         intel_init_clock_gating(dev);
12881
12882         intel_enable_gt_powersave(dev);
12883 }
12884
12885 void intel_modeset_init(struct drm_device *dev)
12886 {
12887         struct drm_i915_private *dev_priv = dev->dev_private;
12888         int sprite, ret;
12889         enum pipe pipe;
12890         struct intel_crtc *crtc;
12891
12892         drm_mode_config_init(dev);
12893
12894         dev->mode_config.min_width = 0;
12895         dev->mode_config.min_height = 0;
12896
12897         dev->mode_config.preferred_depth = 24;
12898         dev->mode_config.prefer_shadow = 1;
12899
12900         dev->mode_config.funcs = &intel_mode_funcs;
12901
12902         intel_init_quirks(dev);
12903
12904         intel_init_pm(dev);
12905
12906         if (INTEL_INFO(dev)->num_pipes == 0)
12907                 return;
12908
12909         intel_init_display(dev);
12910
12911         if (IS_GEN2(dev)) {
12912                 dev->mode_config.max_width = 2048;
12913                 dev->mode_config.max_height = 2048;
12914         } else if (IS_GEN3(dev)) {
12915                 dev->mode_config.max_width = 4096;
12916                 dev->mode_config.max_height = 4096;
12917         } else {
12918                 dev->mode_config.max_width = 8192;
12919                 dev->mode_config.max_height = 8192;
12920         }
12921
12922         if (IS_845G(dev) || IS_I865G(dev)) {
12923                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
12924                 dev->mode_config.cursor_height = 1023;
12925         } else if (IS_GEN2(dev)) {
12926                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12927                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12928         } else {
12929                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12930                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12931         }
12932
12933         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12934
12935         DRM_DEBUG_KMS("%d display pipe%s available.\n",
12936                       INTEL_INFO(dev)->num_pipes,
12937                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12938
12939         for_each_pipe(dev_priv, pipe) {
12940                 intel_crtc_init(dev, pipe);
12941                 for_each_sprite(pipe, sprite) {
12942                         ret = intel_plane_init(dev, pipe, sprite);
12943                         if (ret)
12944                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12945                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
12946                 }
12947         }
12948
12949         intel_init_dpio(dev);
12950
12951         intel_shared_dpll_init(dev);
12952
12953         /* save the BIOS value before clobbering it */
12954         dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
12955         /* Just disable it once at startup */
12956         i915_disable_vga(dev);
12957         intel_setup_outputs(dev);
12958
12959         /* Just in case the BIOS is doing something questionable. */
12960         intel_disable_fbc(dev);
12961
12962         drm_modeset_lock_all(dev);
12963         intel_modeset_setup_hw_state(dev, false);
12964         drm_modeset_unlock_all(dev);
12965
12966         for_each_intel_crtc(dev, crtc) {
12967                 if (!crtc->active)
12968                         continue;
12969
12970                 /*
12971                  * Note that reserving the BIOS fb up front prevents us
12972                  * from stuffing other stolen allocations like the ring
12973                  * on top.  This prevents some ugliness at boot time, and
12974                  * can even allow for smooth boot transitions if the BIOS
12975                  * fb is large enough for the active pipe configuration.
12976                  */
12977                 if (dev_priv->display.get_plane_config) {
12978                         dev_priv->display.get_plane_config(crtc,
12979                                                            &crtc->plane_config);
12980                         /*
12981                          * If the fb is shared between multiple heads, we'll
12982                          * just get the first one.
12983                          */
12984                         intel_find_plane_obj(crtc, &crtc->plane_config);
12985                 }
12986         }
12987 }
12988
12989 static void intel_enable_pipe_a(struct drm_device *dev)
12990 {
12991         struct intel_connector *connector;
12992         struct drm_connector *crt = NULL;
12993         struct intel_load_detect_pipe load_detect_temp;
12994         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
12995
12996         /* We can't just switch on the pipe A, we need to set things up with a
12997          * proper mode and output configuration. As a gross hack, enable pipe A
12998          * by enabling the load detect pipe once. */
12999         list_for_each_entry(connector,
13000                             &dev->mode_config.connector_list,
13001                             base.head) {
13002                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13003                         crt = &connector->base;
13004                         break;
13005                 }
13006         }
13007
13008         if (!crt)
13009                 return;
13010
13011         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13012                 intel_release_load_detect_pipe(crt, &load_detect_temp);
13013 }
13014
13015 static bool
13016 intel_check_plane_mapping(struct intel_crtc *crtc)
13017 {
13018         struct drm_device *dev = crtc->base.dev;
13019         struct drm_i915_private *dev_priv = dev->dev_private;
13020         u32 reg, val;
13021
13022         if (INTEL_INFO(dev)->num_pipes == 1)
13023                 return true;
13024
13025         reg = DSPCNTR(!crtc->plane);
13026         val = I915_READ(reg);
13027
13028         if ((val & DISPLAY_PLANE_ENABLE) &&
13029             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13030                 return false;
13031
13032         return true;
13033 }
13034
13035 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13036 {
13037         struct drm_device *dev = crtc->base.dev;
13038         struct drm_i915_private *dev_priv = dev->dev_private;
13039         u32 reg;
13040
13041         /* Clear any frame start delays used for debugging left by the BIOS */
13042         reg = PIPECONF(crtc->config.cpu_transcoder);
13043         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13044
13045         /* restore vblank interrupts to correct state */
13046         if (crtc->active) {
13047                 update_scanline_offset(crtc);
13048                 drm_vblank_on(dev, crtc->pipe);
13049         } else
13050                 drm_vblank_off(dev, crtc->pipe);
13051
13052         /* We need to sanitize the plane -> pipe mapping first because this will
13053          * disable the crtc (and hence change the state) if it is wrong. Note
13054          * that gen4+ has a fixed plane -> pipe mapping.  */
13055         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13056                 struct intel_connector *connector;
13057                 bool plane;
13058
13059                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13060                               crtc->base.base.id);
13061
13062                 /* Pipe has the wrong plane attached and the plane is active.
13063                  * Temporarily change the plane mapping and disable everything
13064                  * ...  */
13065                 plane = crtc->plane;
13066                 crtc->plane = !plane;
13067                 crtc->primary_enabled = true;
13068                 dev_priv->display.crtc_disable(&crtc->base);
13069                 crtc->plane = plane;
13070
13071                 /* ... and break all links. */
13072                 list_for_each_entry(connector, &dev->mode_config.connector_list,
13073                                     base.head) {
13074                         if (connector->encoder->base.crtc != &crtc->base)
13075                                 continue;
13076
13077                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13078                         connector->base.encoder = NULL;
13079                 }
13080                 /* multiple connectors may have the same encoder:
13081                  *  handle them and break crtc link separately */
13082                 list_for_each_entry(connector, &dev->mode_config.connector_list,
13083                                     base.head)
13084                         if (connector->encoder->base.crtc == &crtc->base) {
13085                                 connector->encoder->base.crtc = NULL;
13086                                 connector->encoder->connectors_active = false;
13087                         }
13088
13089                 WARN_ON(crtc->active);
13090                 crtc->base.enabled = false;
13091         }
13092
13093         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13094             crtc->pipe == PIPE_A && !crtc->active) {
13095                 /* BIOS forgot to enable pipe A, this mostly happens after
13096                  * resume. Force-enable the pipe to fix this, the update_dpms
13097                  * call below we restore the pipe to the right state, but leave
13098                  * the required bits on. */
13099                 intel_enable_pipe_a(dev);
13100         }
13101
13102         /* Adjust the state of the output pipe according to whether we
13103          * have active connectors/encoders. */
13104         intel_crtc_update_dpms(&crtc->base);
13105
13106         if (crtc->active != crtc->base.enabled) {
13107                 struct intel_encoder *encoder;
13108
13109                 /* This can happen either due to bugs in the get_hw_state
13110                  * functions or because the pipe is force-enabled due to the
13111                  * pipe A quirk. */
13112                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13113                               crtc->base.base.id,
13114                               crtc->base.enabled ? "enabled" : "disabled",
13115                               crtc->active ? "enabled" : "disabled");
13116
13117                 crtc->base.enabled = crtc->active;
13118
13119                 /* Because we only establish the connector -> encoder ->
13120                  * crtc links if something is active, this means the
13121                  * crtc is now deactivated. Break the links. connector
13122                  * -> encoder links are only establish when things are
13123                  *  actually up, hence no need to break them. */
13124                 WARN_ON(crtc->active);
13125
13126                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13127                         WARN_ON(encoder->connectors_active);
13128                         encoder->base.crtc = NULL;
13129                 }
13130         }
13131
13132         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13133                 /*
13134                  * We start out with underrun reporting disabled to avoid races.
13135                  * For correct bookkeeping mark this on active crtcs.
13136                  *
13137                  * Also on gmch platforms we dont have any hardware bits to
13138                  * disable the underrun reporting. Which means we need to start
13139                  * out with underrun reporting disabled also on inactive pipes,
13140                  * since otherwise we'll complain about the garbage we read when
13141                  * e.g. coming up after runtime pm.
13142                  *
13143                  * No protection against concurrent access is required - at
13144                  * worst a fifo underrun happens which also sets this to false.
13145                  */
13146                 crtc->cpu_fifo_underrun_disabled = true;
13147                 crtc->pch_fifo_underrun_disabled = true;
13148         }
13149 }
13150
13151 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13152 {
13153         struct intel_connector *connector;
13154         struct drm_device *dev = encoder->base.dev;
13155
13156         /* We need to check both for a crtc link (meaning that the
13157          * encoder is active and trying to read from a pipe) and the
13158          * pipe itself being active. */
13159         bool has_active_crtc = encoder->base.crtc &&
13160                 to_intel_crtc(encoder->base.crtc)->active;
13161
13162         if (encoder->connectors_active && !has_active_crtc) {
13163                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13164                               encoder->base.base.id,
13165                               encoder->base.name);
13166
13167                 /* Connector is active, but has no active pipe. This is
13168                  * fallout from our resume register restoring. Disable
13169                  * the encoder manually again. */
13170                 if (encoder->base.crtc) {
13171                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13172                                       encoder->base.base.id,
13173                                       encoder->base.name);
13174                         encoder->disable(encoder);
13175                         if (encoder->post_disable)
13176                                 encoder->post_disable(encoder);
13177                 }
13178                 encoder->base.crtc = NULL;
13179                 encoder->connectors_active = false;
13180
13181                 /* Inconsistent output/port/pipe state happens presumably due to
13182                  * a bug in one of the get_hw_state functions. Or someplace else
13183                  * in our code, like the register restore mess on resume. Clamp
13184                  * things to off as a safer default. */
13185                 list_for_each_entry(connector,
13186                                     &dev->mode_config.connector_list,
13187                                     base.head) {
13188                         if (connector->encoder != encoder)
13189                                 continue;
13190                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13191                         connector->base.encoder = NULL;
13192                 }
13193         }
13194         /* Enabled encoders without active connectors will be fixed in
13195          * the crtc fixup. */
13196 }
13197
13198 void i915_redisable_vga_power_on(struct drm_device *dev)
13199 {
13200         struct drm_i915_private *dev_priv = dev->dev_private;
13201         u32 vga_reg = i915_vgacntrl_reg(dev);
13202
13203         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13204                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13205                 i915_disable_vga(dev);
13206         }
13207 }
13208
13209 void i915_redisable_vga(struct drm_device *dev)
13210 {
13211         struct drm_i915_private *dev_priv = dev->dev_private;
13212
13213         /* This function can be called both from intel_modeset_setup_hw_state or
13214          * at a very early point in our resume sequence, where the power well
13215          * structures are not yet restored. Since this function is at a very
13216          * paranoid "someone might have enabled VGA while we were not looking"
13217          * level, just check if the power well is enabled instead of trying to
13218          * follow the "don't touch the power well if we don't need it" policy
13219          * the rest of the driver uses. */
13220         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13221                 return;
13222
13223         i915_redisable_vga_power_on(dev);
13224 }
13225
13226 static bool primary_get_hw_state(struct intel_crtc *crtc)
13227 {
13228         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13229
13230         if (!crtc->active)
13231                 return false;
13232
13233         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13234 }
13235
13236 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13237 {
13238         struct drm_i915_private *dev_priv = dev->dev_private;
13239         enum pipe pipe;
13240         struct intel_crtc *crtc;
13241         struct intel_encoder *encoder;
13242         struct intel_connector *connector;
13243         int i;
13244
13245         for_each_intel_crtc(dev, crtc) {
13246                 memset(&crtc->config, 0, sizeof(crtc->config));
13247
13248                 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13249
13250                 crtc->active = dev_priv->display.get_pipe_config(crtc,
13251                                                                  &crtc->config);
13252
13253                 crtc->base.enabled = crtc->active;
13254                 crtc->primary_enabled = primary_get_hw_state(crtc);
13255
13256                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13257                               crtc->base.base.id,
13258                               crtc->active ? "enabled" : "disabled");
13259         }
13260
13261         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13262                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13263
13264                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
13265                 pll->active = 0;
13266                 for_each_intel_crtc(dev, crtc) {
13267                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
13268                                 pll->active++;
13269                 }
13270                 pll->refcount = pll->active;
13271
13272                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
13273                               pll->name, pll->refcount, pll->on);
13274
13275                 if (pll->refcount)
13276                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13277         }
13278
13279         for_each_intel_encoder(dev, encoder) {
13280                 pipe = 0;
13281
13282                 if (encoder->get_hw_state(encoder, &pipe)) {
13283                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13284                         encoder->base.crtc = &crtc->base;
13285                         encoder->get_config(encoder, &crtc->config);
13286                 } else {
13287                         encoder->base.crtc = NULL;
13288                 }
13289
13290                 encoder->connectors_active = false;
13291                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13292                               encoder->base.base.id,
13293                               encoder->base.name,
13294                               encoder->base.crtc ? "enabled" : "disabled",
13295                               pipe_name(pipe));
13296         }
13297
13298         list_for_each_entry(connector, &dev->mode_config.connector_list,
13299                             base.head) {
13300                 if (connector->get_hw_state(connector)) {
13301                         connector->base.dpms = DRM_MODE_DPMS_ON;
13302                         connector->encoder->connectors_active = true;
13303                         connector->base.encoder = &connector->encoder->base;
13304                 } else {
13305                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13306                         connector->base.encoder = NULL;
13307                 }
13308                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13309                               connector->base.base.id,
13310                               connector->base.name,
13311                               connector->base.encoder ? "enabled" : "disabled");
13312         }
13313 }
13314
13315 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13316  * and i915 state tracking structures. */
13317 void intel_modeset_setup_hw_state(struct drm_device *dev,
13318                                   bool force_restore)
13319 {
13320         struct drm_i915_private *dev_priv = dev->dev_private;
13321         enum pipe pipe;
13322         struct intel_crtc *crtc;
13323         struct intel_encoder *encoder;
13324         int i;
13325
13326         intel_modeset_readout_hw_state(dev);
13327
13328         /*
13329          * Now that we have the config, copy it to each CRTC struct
13330          * Note that this could go away if we move to using crtc_config
13331          * checking everywhere.
13332          */
13333         for_each_intel_crtc(dev, crtc) {
13334                 if (crtc->active && i915.fastboot) {
13335                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13336                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13337                                       crtc->base.base.id);
13338                         drm_mode_debug_printmodeline(&crtc->base.mode);
13339                 }
13340         }
13341
13342         /* HW state is read out, now we need to sanitize this mess. */
13343         for_each_intel_encoder(dev, encoder) {
13344                 intel_sanitize_encoder(encoder);
13345         }
13346
13347         for_each_pipe(dev_priv, pipe) {
13348                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13349                 intel_sanitize_crtc(crtc);
13350                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13351         }
13352
13353         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13354                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13355
13356                 if (!pll->on || pll->active)
13357                         continue;
13358
13359                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13360
13361                 pll->disable(dev_priv, pll);
13362                 pll->on = false;
13363         }
13364
13365         if (HAS_PCH_SPLIT(dev))
13366                 ilk_wm_get_hw_state(dev);
13367
13368         if (force_restore) {
13369                 i915_redisable_vga(dev);
13370
13371                 /*
13372                  * We need to use raw interfaces for restoring state to avoid
13373                  * checking (bogus) intermediate states.
13374                  */
13375                 for_each_pipe(dev_priv, pipe) {
13376                         struct drm_crtc *crtc =
13377                                 dev_priv->pipe_to_crtc_mapping[pipe];
13378
13379                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13380                                          crtc->primary->fb);
13381                 }
13382         } else {
13383                 intel_modeset_update_staged_output_state(dev);
13384         }
13385
13386         intel_modeset_check_state(dev);
13387 }
13388
13389 void intel_modeset_gem_init(struct drm_device *dev)
13390 {
13391         struct drm_crtc *c;
13392         struct drm_i915_gem_object *obj;
13393
13394         mutex_lock(&dev->struct_mutex);
13395         intel_init_gt_powersave(dev);
13396         mutex_unlock(&dev->struct_mutex);
13397
13398         intel_modeset_init_hw(dev);
13399
13400         intel_setup_overlay(dev);
13401
13402         /*
13403          * Make sure any fbs we allocated at startup are properly
13404          * pinned & fenced.  When we do the allocation it's too early
13405          * for this.
13406          */
13407         mutex_lock(&dev->struct_mutex);
13408         for_each_crtc(dev, c) {
13409                 obj = intel_fb_obj(c->primary->fb);
13410                 if (obj == NULL)
13411                         continue;
13412
13413                 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
13414                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
13415                                   to_intel_crtc(c)->pipe);
13416                         drm_framebuffer_unreference(c->primary->fb);
13417                         c->primary->fb = NULL;
13418                 }
13419         }
13420         mutex_unlock(&dev->struct_mutex);
13421 }
13422
13423 void intel_connector_unregister(struct intel_connector *intel_connector)
13424 {
13425         struct drm_connector *connector = &intel_connector->base;
13426
13427         intel_panel_destroy_backlight(connector);
13428         drm_connector_unregister(connector);
13429 }
13430
13431 void intel_modeset_cleanup(struct drm_device *dev)
13432 {
13433         struct drm_i915_private *dev_priv = dev->dev_private;
13434         struct drm_connector *connector;
13435
13436         /*
13437          * Interrupts and polling as the first thing to avoid creating havoc.
13438          * Too much stuff here (turning of rps, connectors, ...) would
13439          * experience fancy races otherwise.
13440          */
13441         intel_irq_uninstall(dev_priv);
13442
13443         /*
13444          * Due to the hpd irq storm handling the hotplug work can re-arm the
13445          * poll handlers. Hence disable polling after hpd handling is shut down.
13446          */
13447         drm_kms_helper_poll_fini(dev);
13448
13449         mutex_lock(&dev->struct_mutex);
13450
13451         intel_unregister_dsm_handler();
13452
13453         intel_disable_fbc(dev);
13454
13455         intel_disable_gt_powersave(dev);
13456
13457         ironlake_teardown_rc6(dev);
13458
13459         mutex_unlock(&dev->struct_mutex);
13460
13461         /* flush any delayed tasks or pending work */
13462         flush_scheduled_work();
13463
13464         /* destroy the backlight and sysfs files before encoders/connectors */
13465         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13466                 struct intel_connector *intel_connector;
13467
13468                 intel_connector = to_intel_connector(connector);
13469                 intel_connector->unregister(intel_connector);
13470         }
13471
13472         drm_mode_config_cleanup(dev);
13473
13474         intel_cleanup_overlay(dev);
13475
13476         mutex_lock(&dev->struct_mutex);
13477         intel_cleanup_gt_powersave(dev);
13478         mutex_unlock(&dev->struct_mutex);
13479 }
13480
13481 /*
13482  * Return which encoder is currently attached for connector.
13483  */
13484 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13485 {
13486         return &intel_attached_encoder(connector)->base;
13487 }
13488
13489 void intel_connector_attach_encoder(struct intel_connector *connector,
13490                                     struct intel_encoder *encoder)
13491 {
13492         connector->encoder = encoder;
13493         drm_mode_connector_attach_encoder(&connector->base,
13494                                           &encoder->base);
13495 }
13496
13497 /*
13498  * set vga decode state - true == enable VGA decode
13499  */
13500 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13501 {
13502         struct drm_i915_private *dev_priv = dev->dev_private;
13503         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13504         u16 gmch_ctrl;
13505
13506         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13507                 DRM_ERROR("failed to read control word\n");
13508                 return -EIO;
13509         }
13510
13511         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13512                 return 0;
13513
13514         if (state)
13515                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13516         else
13517                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13518
13519         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13520                 DRM_ERROR("failed to write control word\n");
13521                 return -EIO;
13522         }
13523
13524         return 0;
13525 }
13526
13527 struct intel_display_error_state {
13528
13529         u32 power_well_driver;
13530
13531         int num_transcoders;
13532
13533         struct intel_cursor_error_state {
13534                 u32 control;
13535                 u32 position;
13536                 u32 base;
13537                 u32 size;
13538         } cursor[I915_MAX_PIPES];
13539
13540         struct intel_pipe_error_state {
13541                 bool power_domain_on;
13542                 u32 source;
13543                 u32 stat;
13544         } pipe[I915_MAX_PIPES];
13545
13546         struct intel_plane_error_state {
13547                 u32 control;
13548                 u32 stride;
13549                 u32 size;
13550                 u32 pos;
13551                 u32 addr;
13552                 u32 surface;
13553                 u32 tile_offset;
13554         } plane[I915_MAX_PIPES];
13555
13556         struct intel_transcoder_error_state {
13557                 bool power_domain_on;
13558                 enum transcoder cpu_transcoder;
13559
13560                 u32 conf;
13561
13562                 u32 htotal;
13563                 u32 hblank;
13564                 u32 hsync;
13565                 u32 vtotal;
13566                 u32 vblank;
13567                 u32 vsync;
13568         } transcoder[4];
13569 };
13570
13571 struct intel_display_error_state *
13572 intel_display_capture_error_state(struct drm_device *dev)
13573 {
13574         struct drm_i915_private *dev_priv = dev->dev_private;
13575         struct intel_display_error_state *error;
13576         int transcoders[] = {
13577                 TRANSCODER_A,
13578                 TRANSCODER_B,
13579                 TRANSCODER_C,
13580                 TRANSCODER_EDP,
13581         };
13582         int i;
13583
13584         if (INTEL_INFO(dev)->num_pipes == 0)
13585                 return NULL;
13586
13587         error = kzalloc(sizeof(*error), GFP_ATOMIC);
13588         if (error == NULL)
13589                 return NULL;
13590
13591         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13592                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13593
13594         for_each_pipe(dev_priv, i) {
13595                 error->pipe[i].power_domain_on =
13596                         __intel_display_power_is_enabled(dev_priv,
13597                                                          POWER_DOMAIN_PIPE(i));
13598                 if (!error->pipe[i].power_domain_on)
13599                         continue;
13600
13601                 error->cursor[i].control = I915_READ(CURCNTR(i));
13602                 error->cursor[i].position = I915_READ(CURPOS(i));
13603                 error->cursor[i].base = I915_READ(CURBASE(i));
13604
13605                 error->plane[i].control = I915_READ(DSPCNTR(i));
13606                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13607                 if (INTEL_INFO(dev)->gen <= 3) {
13608                         error->plane[i].size = I915_READ(DSPSIZE(i));
13609                         error->plane[i].pos = I915_READ(DSPPOS(i));
13610                 }
13611                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13612                         error->plane[i].addr = I915_READ(DSPADDR(i));
13613                 if (INTEL_INFO(dev)->gen >= 4) {
13614                         error->plane[i].surface = I915_READ(DSPSURF(i));
13615                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13616                 }
13617
13618                 error->pipe[i].source = I915_READ(PIPESRC(i));
13619
13620                 if (HAS_GMCH_DISPLAY(dev))
13621                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
13622         }
13623
13624         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13625         if (HAS_DDI(dev_priv->dev))
13626                 error->num_transcoders++; /* Account for eDP. */
13627
13628         for (i = 0; i < error->num_transcoders; i++) {
13629                 enum transcoder cpu_transcoder = transcoders[i];
13630
13631                 error->transcoder[i].power_domain_on =
13632                         __intel_display_power_is_enabled(dev_priv,
13633                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13634                 if (!error->transcoder[i].power_domain_on)
13635                         continue;
13636
13637                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13638
13639                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13640                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13641                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13642                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13643                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13644                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13645                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13646         }
13647
13648         return error;
13649 }
13650
13651 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13652
13653 void
13654 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13655                                 struct drm_device *dev,
13656                                 struct intel_display_error_state *error)
13657 {
13658         struct drm_i915_private *dev_priv = dev->dev_private;
13659         int i;
13660
13661         if (!error)
13662                 return;
13663
13664         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13665         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13666                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13667                            error->power_well_driver);
13668         for_each_pipe(dev_priv, i) {
13669                 err_printf(m, "Pipe [%d]:\n", i);
13670                 err_printf(m, "  Power: %s\n",
13671                            error->pipe[i].power_domain_on ? "on" : "off");
13672                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
13673                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
13674
13675                 err_printf(m, "Plane [%d]:\n", i);
13676                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
13677                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
13678                 if (INTEL_INFO(dev)->gen <= 3) {
13679                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
13680                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
13681                 }
13682                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13683                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
13684                 if (INTEL_INFO(dev)->gen >= 4) {
13685                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
13686                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
13687                 }
13688
13689                 err_printf(m, "Cursor [%d]:\n", i);
13690                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
13691                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
13692                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
13693         }
13694
13695         for (i = 0; i < error->num_transcoders; i++) {
13696                 err_printf(m, "CPU transcoder: %c\n",
13697                            transcoder_name(error->transcoder[i].cpu_transcoder));
13698                 err_printf(m, "  Power: %s\n",
13699                            error->transcoder[i].power_domain_on ? "on" : "off");
13700                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
13701                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
13702                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
13703                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
13704                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
13705                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
13706                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
13707         }
13708 }
13709
13710 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13711 {
13712         struct intel_crtc *crtc;
13713
13714         for_each_intel_crtc(dev, crtc) {
13715                 struct intel_unpin_work *work;
13716
13717                 spin_lock_irq(&dev->event_lock);
13718
13719                 work = crtc->unpin_work;
13720
13721                 if (work && work->event &&
13722                     work->event->base.file_priv == file) {
13723                         kfree(work->event);
13724                         work->event = NULL;
13725                 }
13726
13727                 spin_unlock_irq(&dev->event_lock);
13728         }
13729 }