2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/vgaarb.h>
34 #include "intel_drv.h"
37 #include "i915_trace.h"
38 #include "drm_dp_helper.h"
40 #include "drm_crtc_helper.h"
42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
45 static void intel_update_watermarks(struct drm_device *dev);
46 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
47 static void intel_crtc_update_cursor(struct drm_crtc *crtc);
70 #define INTEL_P2_NUM 2
71 typedef struct intel_limit intel_limit_t;
73 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
76 int, int, intel_clock_t *);
79 #define I8XX_DOT_MIN 25000
80 #define I8XX_DOT_MAX 350000
81 #define I8XX_VCO_MIN 930000
82 #define I8XX_VCO_MAX 1400000
86 #define I8XX_M_MAX 140
87 #define I8XX_M1_MIN 18
88 #define I8XX_M1_MAX 26
90 #define I8XX_M2_MAX 16
92 #define I8XX_P_MAX 128
94 #define I8XX_P1_MAX 33
95 #define I8XX_P1_LVDS_MIN 1
96 #define I8XX_P1_LVDS_MAX 6
97 #define I8XX_P2_SLOW 4
98 #define I8XX_P2_FAST 2
99 #define I8XX_P2_LVDS_SLOW 14
100 #define I8XX_P2_LVDS_FAST 7
101 #define I8XX_P2_SLOW_LIMIT 165000
103 #define I9XX_DOT_MIN 20000
104 #define I9XX_DOT_MAX 400000
105 #define I9XX_VCO_MIN 1400000
106 #define I9XX_VCO_MAX 2800000
107 #define PINEVIEW_VCO_MIN 1700000
108 #define PINEVIEW_VCO_MAX 3500000
111 /* Pineview's Ncounter is a ring counter */
112 #define PINEVIEW_N_MIN 3
113 #define PINEVIEW_N_MAX 6
114 #define I9XX_M_MIN 70
115 #define I9XX_M_MAX 120
116 #define PINEVIEW_M_MIN 2
117 #define PINEVIEW_M_MAX 256
118 #define I9XX_M1_MIN 10
119 #define I9XX_M1_MAX 22
120 #define I9XX_M2_MIN 5
121 #define I9XX_M2_MAX 9
122 /* Pineview M1 is reserved, and must be 0 */
123 #define PINEVIEW_M1_MIN 0
124 #define PINEVIEW_M1_MAX 0
125 #define PINEVIEW_M2_MIN 0
126 #define PINEVIEW_M2_MAX 254
127 #define I9XX_P_SDVO_DAC_MIN 5
128 #define I9XX_P_SDVO_DAC_MAX 80
129 #define I9XX_P_LVDS_MIN 7
130 #define I9XX_P_LVDS_MAX 98
131 #define PINEVIEW_P_LVDS_MIN 7
132 #define PINEVIEW_P_LVDS_MAX 112
133 #define I9XX_P1_MIN 1
134 #define I9XX_P1_MAX 8
135 #define I9XX_P2_SDVO_DAC_SLOW 10
136 #define I9XX_P2_SDVO_DAC_FAST 5
137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
138 #define I9XX_P2_LVDS_SLOW 14
139 #define I9XX_P2_LVDS_FAST 7
140 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
142 /*The parameter is for SDVO on G4x platform*/
143 #define G4X_DOT_SDVO_MIN 25000
144 #define G4X_DOT_SDVO_MAX 270000
145 #define G4X_VCO_MIN 1750000
146 #define G4X_VCO_MAX 3500000
147 #define G4X_N_SDVO_MIN 1
148 #define G4X_N_SDVO_MAX 4
149 #define G4X_M_SDVO_MIN 104
150 #define G4X_M_SDVO_MAX 138
151 #define G4X_M1_SDVO_MIN 17
152 #define G4X_M1_SDVO_MAX 23
153 #define G4X_M2_SDVO_MIN 5
154 #define G4X_M2_SDVO_MAX 11
155 #define G4X_P_SDVO_MIN 10
156 #define G4X_P_SDVO_MAX 30
157 #define G4X_P1_SDVO_MIN 1
158 #define G4X_P1_SDVO_MAX 3
159 #define G4X_P2_SDVO_SLOW 10
160 #define G4X_P2_SDVO_FAST 10
161 #define G4X_P2_SDVO_LIMIT 270000
163 /*The parameter is for HDMI_DAC on G4x platform*/
164 #define G4X_DOT_HDMI_DAC_MIN 22000
165 #define G4X_DOT_HDMI_DAC_MAX 400000
166 #define G4X_N_HDMI_DAC_MIN 1
167 #define G4X_N_HDMI_DAC_MAX 4
168 #define G4X_M_HDMI_DAC_MIN 104
169 #define G4X_M_HDMI_DAC_MAX 138
170 #define G4X_M1_HDMI_DAC_MIN 16
171 #define G4X_M1_HDMI_DAC_MAX 23
172 #define G4X_M2_HDMI_DAC_MIN 5
173 #define G4X_M2_HDMI_DAC_MAX 11
174 #define G4X_P_HDMI_DAC_MIN 5
175 #define G4X_P_HDMI_DAC_MAX 80
176 #define G4X_P1_HDMI_DAC_MIN 1
177 #define G4X_P1_HDMI_DAC_MAX 8
178 #define G4X_P2_HDMI_DAC_SLOW 10
179 #define G4X_P2_HDMI_DAC_FAST 5
180 #define G4X_P2_HDMI_DAC_LIMIT 165000
182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
220 /*The parameter is for DISPLAY PORT on G4x platform*/
221 #define G4X_DOT_DISPLAY_PORT_MIN 161670
222 #define G4X_DOT_DISPLAY_PORT_MAX 227000
223 #define G4X_N_DISPLAY_PORT_MIN 1
224 #define G4X_N_DISPLAY_PORT_MAX 2
225 #define G4X_M_DISPLAY_PORT_MIN 97
226 #define G4X_M_DISPLAY_PORT_MAX 108
227 #define G4X_M1_DISPLAY_PORT_MIN 0x10
228 #define G4X_M1_DISPLAY_PORT_MAX 0x12
229 #define G4X_M2_DISPLAY_PORT_MIN 0x05
230 #define G4X_M2_DISPLAY_PORT_MAX 0x06
231 #define G4X_P_DISPLAY_PORT_MIN 10
232 #define G4X_P_DISPLAY_PORT_MAX 20
233 #define G4X_P1_DISPLAY_PORT_MIN 1
234 #define G4X_P1_DISPLAY_PORT_MAX 2
235 #define G4X_P2_DISPLAY_PORT_SLOW 10
236 #define G4X_P2_DISPLAY_PORT_FAST 10
237 #define G4X_P2_DISPLAY_PORT_LIMIT 0
239 /* Ironlake / Sandybridge */
240 /* as we calculate clock using (register_value + 2) for
241 N/M1/M2, so here the range value for them is (actual_value-2).
243 #define IRONLAKE_DOT_MIN 25000
244 #define IRONLAKE_DOT_MAX 350000
245 #define IRONLAKE_VCO_MIN 1760000
246 #define IRONLAKE_VCO_MAX 3510000
247 #define IRONLAKE_M1_MIN 12
248 #define IRONLAKE_M1_MAX 22
249 #define IRONLAKE_M2_MIN 5
250 #define IRONLAKE_M2_MAX 9
251 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
253 /* We have parameter ranges for different type of outputs. */
255 /* DAC & HDMI Refclk 120Mhz */
256 #define IRONLAKE_DAC_N_MIN 1
257 #define IRONLAKE_DAC_N_MAX 5
258 #define IRONLAKE_DAC_M_MIN 79
259 #define IRONLAKE_DAC_M_MAX 127
260 #define IRONLAKE_DAC_P_MIN 5
261 #define IRONLAKE_DAC_P_MAX 80
262 #define IRONLAKE_DAC_P1_MIN 1
263 #define IRONLAKE_DAC_P1_MAX 8
264 #define IRONLAKE_DAC_P2_SLOW 10
265 #define IRONLAKE_DAC_P2_FAST 5
267 /* LVDS single-channel 120Mhz refclk */
268 #define IRONLAKE_LVDS_S_N_MIN 1
269 #define IRONLAKE_LVDS_S_N_MAX 3
270 #define IRONLAKE_LVDS_S_M_MIN 79
271 #define IRONLAKE_LVDS_S_M_MAX 118
272 #define IRONLAKE_LVDS_S_P_MIN 28
273 #define IRONLAKE_LVDS_S_P_MAX 112
274 #define IRONLAKE_LVDS_S_P1_MIN 2
275 #define IRONLAKE_LVDS_S_P1_MAX 8
276 #define IRONLAKE_LVDS_S_P2_SLOW 14
277 #define IRONLAKE_LVDS_S_P2_FAST 14
279 /* LVDS dual-channel 120Mhz refclk */
280 #define IRONLAKE_LVDS_D_N_MIN 1
281 #define IRONLAKE_LVDS_D_N_MAX 3
282 #define IRONLAKE_LVDS_D_M_MIN 79
283 #define IRONLAKE_LVDS_D_M_MAX 127
284 #define IRONLAKE_LVDS_D_P_MIN 14
285 #define IRONLAKE_LVDS_D_P_MAX 56
286 #define IRONLAKE_LVDS_D_P1_MIN 2
287 #define IRONLAKE_LVDS_D_P1_MAX 8
288 #define IRONLAKE_LVDS_D_P2_SLOW 7
289 #define IRONLAKE_LVDS_D_P2_FAST 7
291 /* LVDS single-channel 100Mhz refclk */
292 #define IRONLAKE_LVDS_S_SSC_N_MIN 1
293 #define IRONLAKE_LVDS_S_SSC_N_MAX 2
294 #define IRONLAKE_LVDS_S_SSC_M_MIN 79
295 #define IRONLAKE_LVDS_S_SSC_M_MAX 126
296 #define IRONLAKE_LVDS_S_SSC_P_MIN 28
297 #define IRONLAKE_LVDS_S_SSC_P_MAX 112
298 #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
299 #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
301 #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
303 /* LVDS dual-channel 100Mhz refclk */
304 #define IRONLAKE_LVDS_D_SSC_N_MIN 1
305 #define IRONLAKE_LVDS_D_SSC_N_MAX 3
306 #define IRONLAKE_LVDS_D_SSC_M_MIN 79
307 #define IRONLAKE_LVDS_D_SSC_M_MAX 126
308 #define IRONLAKE_LVDS_D_SSC_P_MIN 14
309 #define IRONLAKE_LVDS_D_SSC_P_MAX 42
310 #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
311 #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
313 #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
316 #define IRONLAKE_DP_N_MIN 1
317 #define IRONLAKE_DP_N_MAX 2
318 #define IRONLAKE_DP_M_MIN 81
319 #define IRONLAKE_DP_M_MAX 90
320 #define IRONLAKE_DP_P_MIN 10
321 #define IRONLAKE_DP_P_MAX 20
322 #define IRONLAKE_DP_P2_FAST 10
323 #define IRONLAKE_DP_P2_SLOW 10
324 #define IRONLAKE_DP_P2_LIMIT 0
325 #define IRONLAKE_DP_P1_MIN 1
326 #define IRONLAKE_DP_P1_MAX 2
329 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
333 int target, int refclk, intel_clock_t *best_clock);
335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
336 int target, int refclk, intel_clock_t *best_clock);
339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
340 int target, int refclk, intel_clock_t *best_clock);
342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
343 int target, int refclk, intel_clock_t *best_clock);
345 static const intel_limit_t intel_limits_i8xx_dvo = {
346 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
347 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
348 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
349 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
350 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
351 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
352 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
353 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
354 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
355 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
356 .find_pll = intel_find_best_PLL,
359 static const intel_limit_t intel_limits_i8xx_lvds = {
360 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
361 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
362 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
363 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
364 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
365 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
366 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
367 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
368 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
369 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
370 .find_pll = intel_find_best_PLL,
373 static const intel_limit_t intel_limits_i9xx_sdvo = {
374 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
375 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
376 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
377 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
378 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
379 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
380 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
381 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
382 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
383 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
384 .find_pll = intel_find_best_PLL,
387 static const intel_limit_t intel_limits_i9xx_lvds = {
388 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
389 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
390 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
391 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
392 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
393 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
394 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
395 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
396 /* The single-channel range is 25-112Mhz, and dual-channel
397 * is 80-224Mhz. Prefer single channel as much as possible.
399 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
400 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
401 .find_pll = intel_find_best_PLL,
404 /* below parameter and function is for G4X Chipset Family*/
405 static const intel_limit_t intel_limits_g4x_sdvo = {
406 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
407 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
408 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
409 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
410 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
411 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
412 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
413 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
414 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
415 .p2_slow = G4X_P2_SDVO_SLOW,
416 .p2_fast = G4X_P2_SDVO_FAST
418 .find_pll = intel_g4x_find_best_PLL,
421 static const intel_limit_t intel_limits_g4x_hdmi = {
422 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
423 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
424 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
425 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
426 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
427 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
428 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
429 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
430 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
431 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
432 .p2_fast = G4X_P2_HDMI_DAC_FAST
434 .find_pll = intel_g4x_find_best_PLL,
437 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
438 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
439 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
440 .vco = { .min = G4X_VCO_MIN,
441 .max = G4X_VCO_MAX },
442 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
443 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
444 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
445 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
446 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
447 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
448 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
449 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
450 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
451 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
452 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
453 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
454 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
455 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
456 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
458 .find_pll = intel_g4x_find_best_PLL,
461 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
462 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
463 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
464 .vco = { .min = G4X_VCO_MIN,
465 .max = G4X_VCO_MAX },
466 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
467 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
468 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
469 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
470 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
471 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
472 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
473 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
474 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
475 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
476 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
477 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
478 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
479 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
480 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
482 .find_pll = intel_g4x_find_best_PLL,
485 static const intel_limit_t intel_limits_g4x_display_port = {
486 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
487 .max = G4X_DOT_DISPLAY_PORT_MAX },
488 .vco = { .min = G4X_VCO_MIN,
490 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
491 .max = G4X_N_DISPLAY_PORT_MAX },
492 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
493 .max = G4X_M_DISPLAY_PORT_MAX },
494 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
495 .max = G4X_M1_DISPLAY_PORT_MAX },
496 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
497 .max = G4X_M2_DISPLAY_PORT_MAX },
498 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
499 .max = G4X_P_DISPLAY_PORT_MAX },
500 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
501 .max = G4X_P1_DISPLAY_PORT_MAX},
502 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
503 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
504 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
505 .find_pll = intel_find_pll_g4x_dp,
508 static const intel_limit_t intel_limits_pineview_sdvo = {
509 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
510 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
511 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
512 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
513 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
514 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
515 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
516 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
517 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
518 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
519 .find_pll = intel_find_best_PLL,
522 static const intel_limit_t intel_limits_pineview_lvds = {
523 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
524 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
525 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
526 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
527 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
528 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
529 .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
530 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
531 /* Pineview only supports single-channel mode. */
532 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
533 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
534 .find_pll = intel_find_best_PLL,
537 static const intel_limit_t intel_limits_ironlake_dac = {
538 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
539 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
540 .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
541 .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
542 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
543 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
544 .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
545 .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
546 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
547 .p2_slow = IRONLAKE_DAC_P2_SLOW,
548 .p2_fast = IRONLAKE_DAC_P2_FAST },
549 .find_pll = intel_g4x_find_best_PLL,
552 static const intel_limit_t intel_limits_ironlake_single_lvds = {
553 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
554 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
555 .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
556 .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
557 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
558 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
559 .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
560 .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
561 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
562 .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
563 .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
564 .find_pll = intel_g4x_find_best_PLL,
567 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
568 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
569 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
570 .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
571 .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
572 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
573 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
574 .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
575 .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
576 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
577 .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
578 .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
579 .find_pll = intel_g4x_find_best_PLL,
582 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
583 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
584 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
585 .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
586 .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
587 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
588 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
589 .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
590 .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
591 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
592 .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
593 .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
594 .find_pll = intel_g4x_find_best_PLL,
597 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
598 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
599 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
600 .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
601 .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
602 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
603 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
604 .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
605 .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
606 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
607 .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
608 .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
609 .find_pll = intel_g4x_find_best_PLL,
612 static const intel_limit_t intel_limits_ironlake_display_port = {
613 .dot = { .min = IRONLAKE_DOT_MIN,
614 .max = IRONLAKE_DOT_MAX },
615 .vco = { .min = IRONLAKE_VCO_MIN,
616 .max = IRONLAKE_VCO_MAX},
617 .n = { .min = IRONLAKE_DP_N_MIN,
618 .max = IRONLAKE_DP_N_MAX },
619 .m = { .min = IRONLAKE_DP_M_MIN,
620 .max = IRONLAKE_DP_M_MAX },
621 .m1 = { .min = IRONLAKE_M1_MIN,
622 .max = IRONLAKE_M1_MAX },
623 .m2 = { .min = IRONLAKE_M2_MIN,
624 .max = IRONLAKE_M2_MAX },
625 .p = { .min = IRONLAKE_DP_P_MIN,
626 .max = IRONLAKE_DP_P_MAX },
627 .p1 = { .min = IRONLAKE_DP_P1_MIN,
628 .max = IRONLAKE_DP_P1_MAX},
629 .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
630 .p2_slow = IRONLAKE_DP_P2_SLOW,
631 .p2_fast = IRONLAKE_DP_P2_FAST },
632 .find_pll = intel_find_pll_ironlake_dp,
635 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
637 struct drm_device *dev = crtc->dev;
638 struct drm_i915_private *dev_priv = dev->dev_private;
639 const intel_limit_t *limit;
642 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
643 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
646 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
647 LVDS_CLKB_POWER_UP) {
648 /* LVDS dual channel */
650 limit = &intel_limits_ironlake_dual_lvds_100m;
652 limit = &intel_limits_ironlake_dual_lvds;
655 limit = &intel_limits_ironlake_single_lvds_100m;
657 limit = &intel_limits_ironlake_single_lvds;
659 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
661 limit = &intel_limits_ironlake_display_port;
663 limit = &intel_limits_ironlake_dac;
668 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
670 struct drm_device *dev = crtc->dev;
671 struct drm_i915_private *dev_priv = dev->dev_private;
672 const intel_limit_t *limit;
674 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
675 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
677 /* LVDS with dual channel */
678 limit = &intel_limits_g4x_dual_channel_lvds;
680 /* LVDS with dual channel */
681 limit = &intel_limits_g4x_single_channel_lvds;
682 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
683 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
684 limit = &intel_limits_g4x_hdmi;
685 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
686 limit = &intel_limits_g4x_sdvo;
687 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
688 limit = &intel_limits_g4x_display_port;
689 } else /* The option is for other outputs */
690 limit = &intel_limits_i9xx_sdvo;
695 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
697 struct drm_device *dev = crtc->dev;
698 const intel_limit_t *limit;
700 if (HAS_PCH_SPLIT(dev))
701 limit = intel_ironlake_limit(crtc);
702 else if (IS_G4X(dev)) {
703 limit = intel_g4x_limit(crtc);
704 } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
705 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
706 limit = &intel_limits_i9xx_lvds;
708 limit = &intel_limits_i9xx_sdvo;
709 } else if (IS_PINEVIEW(dev)) {
710 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
711 limit = &intel_limits_pineview_lvds;
713 limit = &intel_limits_pineview_sdvo;
715 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
716 limit = &intel_limits_i8xx_lvds;
718 limit = &intel_limits_i8xx_dvo;
723 /* m1 is reserved as 0 in Pineview, n is a ring counter */
724 static void pineview_clock(int refclk, intel_clock_t *clock)
726 clock->m = clock->m2 + 2;
727 clock->p = clock->p1 * clock->p2;
728 clock->vco = refclk * clock->m / clock->n;
729 clock->dot = clock->vco / clock->p;
732 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
734 if (IS_PINEVIEW(dev)) {
735 pineview_clock(refclk, clock);
738 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
739 clock->p = clock->p1 * clock->p2;
740 clock->vco = refclk * clock->m / (clock->n + 2);
741 clock->dot = clock->vco / clock->p;
745 * Returns whether any output on the specified pipe is of the specified type
747 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
749 struct drm_device *dev = crtc->dev;
750 struct drm_mode_config *mode_config = &dev->mode_config;
751 struct drm_encoder *l_entry;
753 list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
754 if (l_entry && l_entry->crtc == crtc) {
755 struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
756 if (intel_encoder->type == type)
763 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
765 * Returns whether the given set of divisors are valid for a given refclk with
766 * the given connectors.
769 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
771 const intel_limit_t *limit = intel_limit (crtc);
772 struct drm_device *dev = crtc->dev;
774 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
775 INTELPllInvalid ("p1 out of range\n");
776 if (clock->p < limit->p.min || limit->p.max < clock->p)
777 INTELPllInvalid ("p out of range\n");
778 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
779 INTELPllInvalid ("m2 out of range\n");
780 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
781 INTELPllInvalid ("m1 out of range\n");
782 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
783 INTELPllInvalid ("m1 <= m2\n");
784 if (clock->m < limit->m.min || limit->m.max < clock->m)
785 INTELPllInvalid ("m out of range\n");
786 if (clock->n < limit->n.min || limit->n.max < clock->n)
787 INTELPllInvalid ("n out of range\n");
788 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
789 INTELPllInvalid ("vco out of range\n");
790 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
791 * connector, etc., rather than just a single range.
793 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
794 INTELPllInvalid ("dot out of range\n");
800 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
801 int target, int refclk, intel_clock_t *best_clock)
804 struct drm_device *dev = crtc->dev;
805 struct drm_i915_private *dev_priv = dev->dev_private;
809 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
810 (I915_READ(LVDS)) != 0) {
812 * For LVDS, if the panel is on, just rely on its current
813 * settings for dual-channel. We haven't figured out how to
814 * reliably set up different single/dual channel state, if we
817 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
819 clock.p2 = limit->p2.p2_fast;
821 clock.p2 = limit->p2.p2_slow;
823 if (target < limit->p2.dot_limit)
824 clock.p2 = limit->p2.p2_slow;
826 clock.p2 = limit->p2.p2_fast;
829 memset (best_clock, 0, sizeof (*best_clock));
831 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
833 for (clock.m2 = limit->m2.min;
834 clock.m2 <= limit->m2.max; clock.m2++) {
835 /* m1 is always 0 in Pineview */
836 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
838 for (clock.n = limit->n.min;
839 clock.n <= limit->n.max; clock.n++) {
840 for (clock.p1 = limit->p1.min;
841 clock.p1 <= limit->p1.max; clock.p1++) {
844 intel_clock(dev, refclk, &clock);
846 if (!intel_PLL_is_valid(crtc, &clock))
849 this_err = abs(clock.dot - target);
850 if (this_err < err) {
859 return (err != target);
863 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
864 int target, int refclk, intel_clock_t *best_clock)
866 struct drm_device *dev = crtc->dev;
867 struct drm_i915_private *dev_priv = dev->dev_private;
871 /* approximately equals target * 0.00585 */
872 int err_most = (target >> 8) + (target >> 9);
875 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
878 if (HAS_PCH_SPLIT(dev))
882 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
884 clock.p2 = limit->p2.p2_fast;
886 clock.p2 = limit->p2.p2_slow;
888 if (target < limit->p2.dot_limit)
889 clock.p2 = limit->p2.p2_slow;
891 clock.p2 = limit->p2.p2_fast;
894 memset(best_clock, 0, sizeof(*best_clock));
895 max_n = limit->n.max;
896 /* based on hardware requirement, prefer smaller n to precision */
897 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
898 /* based on hardware requirement, prefere larger m1,m2 */
899 for (clock.m1 = limit->m1.max;
900 clock.m1 >= limit->m1.min; clock.m1--) {
901 for (clock.m2 = limit->m2.max;
902 clock.m2 >= limit->m2.min; clock.m2--) {
903 for (clock.p1 = limit->p1.max;
904 clock.p1 >= limit->p1.min; clock.p1--) {
907 intel_clock(dev, refclk, &clock);
908 if (!intel_PLL_is_valid(crtc, &clock))
910 this_err = abs(clock.dot - target) ;
911 if (this_err < err_most) {
925 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
926 int target, int refclk, intel_clock_t *best_clock)
928 struct drm_device *dev = crtc->dev;
931 /* return directly when it is eDP */
935 if (target < 200000) {
948 intel_clock(dev, refclk, &clock);
949 memcpy(best_clock, &clock, sizeof(intel_clock_t));
953 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
955 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
956 int target, int refclk, intel_clock_t *best_clock)
959 if (target < 200000) {
972 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
973 clock.p = (clock.p1 * clock.p2);
974 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
976 memcpy(best_clock, &clock, sizeof(intel_clock_t));
981 intel_wait_for_vblank(struct drm_device *dev)
983 /* Wait for 20ms, i.e. one cycle at 50hz. */
985 mdelay(20); /* The kernel debugger cannot call msleep() */
990 /* Parameters have changed, update FBC info */
991 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
993 struct drm_device *dev = crtc->dev;
994 struct drm_i915_private *dev_priv = dev->dev_private;
995 struct drm_framebuffer *fb = crtc->fb;
996 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
997 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
998 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1000 u32 fbc_ctl, fbc_ctl2;
1002 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1004 if (fb->pitch < dev_priv->cfb_pitch)
1005 dev_priv->cfb_pitch = fb->pitch;
1007 /* FBC_CTL wants 64B units */
1008 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1009 dev_priv->cfb_fence = obj_priv->fence_reg;
1010 dev_priv->cfb_plane = intel_crtc->plane;
1011 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1013 /* Clear old tags */
1014 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1015 I915_WRITE(FBC_TAG + (i * 4), 0);
1018 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1019 if (obj_priv->tiling_mode != I915_TILING_NONE)
1020 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1021 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1022 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1025 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1027 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1028 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1029 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1030 if (obj_priv->tiling_mode != I915_TILING_NONE)
1031 fbc_ctl |= dev_priv->cfb_fence;
1032 I915_WRITE(FBC_CONTROL, fbc_ctl);
1034 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1035 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1038 void i8xx_disable_fbc(struct drm_device *dev)
1040 struct drm_i915_private *dev_priv = dev->dev_private;
1043 if (!I915_HAS_FBC(dev))
1046 if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
1047 return; /* Already off, just return */
1049 /* Disable compression */
1050 fbc_ctl = I915_READ(FBC_CONTROL);
1051 fbc_ctl &= ~FBC_CTL_EN;
1052 I915_WRITE(FBC_CONTROL, fbc_ctl);
1054 /* Wait for compressing bit to clear */
1055 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10, 0)) {
1056 DRM_DEBUG_KMS("FBC idle timed out\n");
1060 intel_wait_for_vblank(dev);
1062 DRM_DEBUG_KMS("disabled FBC\n");
1065 static bool i8xx_fbc_enabled(struct drm_device *dev)
1067 struct drm_i915_private *dev_priv = dev->dev_private;
1069 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1072 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1074 struct drm_device *dev = crtc->dev;
1075 struct drm_i915_private *dev_priv = dev->dev_private;
1076 struct drm_framebuffer *fb = crtc->fb;
1077 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1078 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1080 int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1082 unsigned long stall_watermark = 200;
1085 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1086 dev_priv->cfb_fence = obj_priv->fence_reg;
1087 dev_priv->cfb_plane = intel_crtc->plane;
1089 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1090 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1091 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1092 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1094 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1097 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1098 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1099 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1100 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1101 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1104 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1106 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1109 void g4x_disable_fbc(struct drm_device *dev)
1111 struct drm_i915_private *dev_priv = dev->dev_private;
1114 /* Disable compression */
1115 dpfc_ctl = I915_READ(DPFC_CONTROL);
1116 dpfc_ctl &= ~DPFC_CTL_EN;
1117 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1118 intel_wait_for_vblank(dev);
1120 DRM_DEBUG_KMS("disabled FBC\n");
1123 static bool g4x_fbc_enabled(struct drm_device *dev)
1125 struct drm_i915_private *dev_priv = dev->dev_private;
1127 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1130 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1132 struct drm_device *dev = crtc->dev;
1133 struct drm_i915_private *dev_priv = dev->dev_private;
1134 struct drm_framebuffer *fb = crtc->fb;
1135 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1136 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1138 int plane = (intel_crtc->plane == 0) ? DPFC_CTL_PLANEA :
1140 unsigned long stall_watermark = 200;
1143 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1144 dev_priv->cfb_fence = obj_priv->fence_reg;
1145 dev_priv->cfb_plane = intel_crtc->plane;
1147 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1148 dpfc_ctl &= DPFC_RESERVED;
1149 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1150 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1151 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1152 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1154 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1157 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1158 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1159 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1160 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1161 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1162 I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1164 I915_WRITE(ILK_DPFC_CONTROL, I915_READ(ILK_DPFC_CONTROL) |
1167 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1170 void ironlake_disable_fbc(struct drm_device *dev)
1172 struct drm_i915_private *dev_priv = dev->dev_private;
1175 /* Disable compression */
1176 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1177 dpfc_ctl &= ~DPFC_CTL_EN;
1178 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1179 intel_wait_for_vblank(dev);
1181 DRM_DEBUG_KMS("disabled FBC\n");
1184 static bool ironlake_fbc_enabled(struct drm_device *dev)
1186 struct drm_i915_private *dev_priv = dev->dev_private;
1188 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1191 bool intel_fbc_enabled(struct drm_device *dev)
1193 struct drm_i915_private *dev_priv = dev->dev_private;
1195 if (!dev_priv->display.fbc_enabled)
1198 return dev_priv->display.fbc_enabled(dev);
1201 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1203 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1205 if (!dev_priv->display.enable_fbc)
1208 dev_priv->display.enable_fbc(crtc, interval);
1211 void intel_disable_fbc(struct drm_device *dev)
1213 struct drm_i915_private *dev_priv = dev->dev_private;
1215 if (!dev_priv->display.disable_fbc)
1218 dev_priv->display.disable_fbc(dev);
1222 * intel_update_fbc - enable/disable FBC as needed
1223 * @crtc: CRTC to point the compressor at
1224 * @mode: mode in use
1226 * Set up the framebuffer compression hardware at mode set time. We
1227 * enable it if possible:
1228 * - plane A only (on pre-965)
1229 * - no pixel mulitply/line duplication
1230 * - no alpha buffer discard
1232 * - framebuffer <= 2048 in width, 1536 in height
1234 * We can't assume that any compression will take place (worst case),
1235 * so the compressed buffer has to be the same size as the uncompressed
1236 * one. It also must reside (along with the line length buffer) in
1239 * We need to enable/disable FBC on a global basis.
1241 static void intel_update_fbc(struct drm_crtc *crtc,
1242 struct drm_display_mode *mode)
1244 struct drm_device *dev = crtc->dev;
1245 struct drm_i915_private *dev_priv = dev->dev_private;
1246 struct drm_framebuffer *fb = crtc->fb;
1247 struct intel_framebuffer *intel_fb;
1248 struct drm_i915_gem_object *obj_priv;
1249 struct drm_crtc *tmp_crtc;
1250 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1251 int plane = intel_crtc->plane;
1252 int crtcs_enabled = 0;
1254 DRM_DEBUG_KMS("\n");
1256 if (!i915_powersave)
1259 if (!I915_HAS_FBC(dev))
1265 intel_fb = to_intel_framebuffer(fb);
1266 obj_priv = to_intel_bo(intel_fb->obj);
1269 * If FBC is already on, we just have to verify that we can
1270 * keep it that way...
1271 * Need to disable if:
1272 * - more than one pipe is active
1273 * - changing FBC params (stride, fence, mode)
1274 * - new fb is too large to fit in compressed buffer
1275 * - going to an unsupported config (interlace, pixel multiply, etc.)
1277 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1278 if (tmp_crtc->enabled)
1281 DRM_DEBUG_KMS("%d pipes active\n", crtcs_enabled);
1282 if (crtcs_enabled > 1) {
1283 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1284 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1287 if (intel_fb->obj->size > dev_priv->cfb_size) {
1288 DRM_DEBUG_KMS("framebuffer too large, disabling "
1290 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1293 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1294 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1295 DRM_DEBUG_KMS("mode incompatible with compression, "
1297 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1300 if ((mode->hdisplay > 2048) ||
1301 (mode->vdisplay > 1536)) {
1302 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1303 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1306 if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1307 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1308 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1311 if (obj_priv->tiling_mode != I915_TILING_X) {
1312 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1313 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1317 /* If the kernel debugger is active, always disable compression */
1318 if (in_dbg_master())
1321 if (intel_fbc_enabled(dev)) {
1322 /* We can re-enable it in this case, but need to update pitch */
1323 if ((fb->pitch > dev_priv->cfb_pitch) ||
1324 (obj_priv->fence_reg != dev_priv->cfb_fence) ||
1325 (plane != dev_priv->cfb_plane))
1326 intel_disable_fbc(dev);
1329 /* Now try to turn it back on if possible */
1330 if (!intel_fbc_enabled(dev))
1331 intel_enable_fbc(crtc, 500);
1336 /* Multiple disables should be harmless */
1337 if (intel_fbc_enabled(dev)) {
1338 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1339 intel_disable_fbc(dev);
1344 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1346 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1350 switch (obj_priv->tiling_mode) {
1351 case I915_TILING_NONE:
1352 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1353 alignment = 128 * 1024;
1354 else if (IS_I965G(dev))
1355 alignment = 4 * 1024;
1357 alignment = 64 * 1024;
1360 /* pin() will align the object as required by fence */
1364 /* FIXME: Is this true? */
1365 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1371 ret = i915_gem_object_pin(obj, alignment);
1375 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1376 * fence, whereas 965+ only requires a fence if using
1377 * framebuffer compression. For simplicity, we always install
1378 * a fence as the cost is not that onerous.
1380 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1381 obj_priv->tiling_mode != I915_TILING_NONE) {
1382 ret = i915_gem_object_get_fence_reg(obj);
1384 i915_gem_object_unpin(obj);
1392 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1394 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1397 struct drm_device *dev = crtc->dev;
1398 struct drm_i915_private *dev_priv = dev->dev_private;
1399 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1400 struct intel_framebuffer *intel_fb;
1401 struct drm_i915_gem_object *obj_priv;
1402 struct drm_gem_object *obj;
1403 int plane = intel_crtc->plane;
1404 unsigned long Start, Offset;
1405 int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1406 int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1407 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1408 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1409 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1417 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1421 intel_fb = to_intel_framebuffer(fb);
1422 obj = intel_fb->obj;
1423 obj_priv = to_intel_bo(obj);
1425 dspcntr = I915_READ(dspcntr_reg);
1426 /* Mask out pixel format bits in case we change it */
1427 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1428 switch (fb->bits_per_pixel) {
1430 dspcntr |= DISPPLANE_8BPP;
1433 if (fb->depth == 15)
1434 dspcntr |= DISPPLANE_15_16BPP;
1436 dspcntr |= DISPPLANE_16BPP;
1440 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1443 DRM_ERROR("Unknown color depth\n");
1446 if (IS_I965G(dev)) {
1447 if (obj_priv->tiling_mode != I915_TILING_NONE)
1448 dspcntr |= DISPPLANE_TILED;
1450 dspcntr &= ~DISPPLANE_TILED;
1453 if (IS_IRONLAKE(dev))
1455 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1457 I915_WRITE(dspcntr_reg, dspcntr);
1459 Start = obj_priv->gtt_offset;
1460 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1462 DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1463 I915_WRITE(dspstride, fb->pitch);
1464 if (IS_I965G(dev)) {
1465 I915_WRITE(dspbase, Offset);
1467 I915_WRITE(dspsurf, Start);
1469 I915_WRITE(dsptileoff, (y << 16) | x);
1471 I915_WRITE(dspbase, Start + Offset);
1475 if ((IS_I965G(dev) || plane == 0))
1476 intel_update_fbc(crtc, &crtc->mode);
1478 intel_wait_for_vblank(dev);
1479 intel_increase_pllclock(crtc, true);
1485 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1486 struct drm_framebuffer *old_fb)
1488 struct drm_device *dev = crtc->dev;
1489 struct drm_i915_private *dev_priv = dev->dev_private;
1490 struct drm_i915_master_private *master_priv;
1491 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1492 struct intel_framebuffer *intel_fb;
1493 struct drm_i915_gem_object *obj_priv;
1494 struct drm_gem_object *obj;
1495 int pipe = intel_crtc->pipe;
1496 int plane = intel_crtc->plane;
1497 unsigned long Start, Offset;
1498 int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1499 int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1500 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1501 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1502 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1508 DRM_DEBUG_KMS("No FB bound\n");
1517 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1521 intel_fb = to_intel_framebuffer(crtc->fb);
1522 obj = intel_fb->obj;
1523 obj_priv = to_intel_bo(obj);
1525 mutex_lock(&dev->struct_mutex);
1526 ret = intel_pin_and_fence_fb_obj(dev, obj);
1528 mutex_unlock(&dev->struct_mutex);
1532 ret = i915_gem_object_set_to_display_plane(obj);
1534 i915_gem_object_unpin(obj);
1535 mutex_unlock(&dev->struct_mutex);
1539 dspcntr = I915_READ(dspcntr_reg);
1540 /* Mask out pixel format bits in case we change it */
1541 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1542 switch (crtc->fb->bits_per_pixel) {
1544 dspcntr |= DISPPLANE_8BPP;
1547 if (crtc->fb->depth == 15)
1548 dspcntr |= DISPPLANE_15_16BPP;
1550 dspcntr |= DISPPLANE_16BPP;
1554 if (crtc->fb->depth == 30)
1555 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1557 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1560 DRM_ERROR("Unknown color depth\n");
1561 i915_gem_object_unpin(obj);
1562 mutex_unlock(&dev->struct_mutex);
1565 if (IS_I965G(dev)) {
1566 if (obj_priv->tiling_mode != I915_TILING_NONE)
1567 dspcntr |= DISPPLANE_TILED;
1569 dspcntr &= ~DISPPLANE_TILED;
1572 if (HAS_PCH_SPLIT(dev))
1574 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1576 I915_WRITE(dspcntr_reg, dspcntr);
1578 Start = obj_priv->gtt_offset;
1579 Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1581 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1582 Start, Offset, x, y, crtc->fb->pitch);
1583 I915_WRITE(dspstride, crtc->fb->pitch);
1584 if (IS_I965G(dev)) {
1585 I915_WRITE(dspsurf, Start);
1586 I915_WRITE(dsptileoff, (y << 16) | x);
1587 I915_WRITE(dspbase, Offset);
1589 I915_WRITE(dspbase, Start + Offset);
1591 POSTING_READ(dspbase);
1593 if ((IS_I965G(dev) || plane == 0))
1594 intel_update_fbc(crtc, &crtc->mode);
1596 intel_wait_for_vblank(dev);
1599 intel_fb = to_intel_framebuffer(old_fb);
1600 obj_priv = to_intel_bo(intel_fb->obj);
1601 i915_gem_object_unpin(intel_fb->obj);
1603 intel_increase_pllclock(crtc, true);
1605 mutex_unlock(&dev->struct_mutex);
1607 if (!dev->primary->master)
1610 master_priv = dev->primary->master->driver_priv;
1611 if (!master_priv->sarea_priv)
1615 master_priv->sarea_priv->pipeB_x = x;
1616 master_priv->sarea_priv->pipeB_y = y;
1618 master_priv->sarea_priv->pipeA_x = x;
1619 master_priv->sarea_priv->pipeA_y = y;
1625 static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1627 struct drm_device *dev = crtc->dev;
1628 struct drm_i915_private *dev_priv = dev->dev_private;
1631 DRM_DEBUG_KMS("\n");
1632 dpa_ctl = I915_READ(DP_A);
1633 dpa_ctl &= ~DP_PLL_ENABLE;
1634 I915_WRITE(DP_A, dpa_ctl);
1637 static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1639 struct drm_device *dev = crtc->dev;
1640 struct drm_i915_private *dev_priv = dev->dev_private;
1643 dpa_ctl = I915_READ(DP_A);
1644 dpa_ctl |= DP_PLL_ENABLE;
1645 I915_WRITE(DP_A, dpa_ctl);
1651 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1653 struct drm_device *dev = crtc->dev;
1654 struct drm_i915_private *dev_priv = dev->dev_private;
1657 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1658 dpa_ctl = I915_READ(DP_A);
1659 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1661 if (clock < 200000) {
1663 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1664 /* workaround for 160Mhz:
1665 1) program 0x4600c bits 15:0 = 0x8124
1666 2) program 0x46010 bit 0 = 1
1667 3) program 0x46034 bit 24 = 1
1668 4) program 0x64000 bit 14 = 1
1670 temp = I915_READ(0x4600c);
1672 I915_WRITE(0x4600c, temp | 0x8124);
1674 temp = I915_READ(0x46010);
1675 I915_WRITE(0x46010, temp | 1);
1677 temp = I915_READ(0x46034);
1678 I915_WRITE(0x46034, temp | (1 << 24));
1680 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1682 I915_WRITE(DP_A, dpa_ctl);
1687 /* The FDI link training functions for ILK/Ibexpeak. */
1688 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1690 struct drm_device *dev = crtc->dev;
1691 struct drm_i915_private *dev_priv = dev->dev_private;
1692 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1693 int pipe = intel_crtc->pipe;
1694 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1695 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1696 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1697 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1698 u32 temp, tries = 0;
1700 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1702 temp = I915_READ(fdi_rx_imr_reg);
1703 temp &= ~FDI_RX_SYMBOL_LOCK;
1704 temp &= ~FDI_RX_BIT_LOCK;
1705 I915_WRITE(fdi_rx_imr_reg, temp);
1706 I915_READ(fdi_rx_imr_reg);
1709 /* enable CPU FDI TX and PCH FDI RX */
1710 temp = I915_READ(fdi_tx_reg);
1711 temp |= FDI_TX_ENABLE;
1713 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1714 temp &= ~FDI_LINK_TRAIN_NONE;
1715 temp |= FDI_LINK_TRAIN_PATTERN_1;
1716 I915_WRITE(fdi_tx_reg, temp);
1717 I915_READ(fdi_tx_reg);
1719 temp = I915_READ(fdi_rx_reg);
1720 temp &= ~FDI_LINK_TRAIN_NONE;
1721 temp |= FDI_LINK_TRAIN_PATTERN_1;
1722 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1723 I915_READ(fdi_rx_reg);
1726 for (tries = 0; tries < 5; tries++) {
1727 temp = I915_READ(fdi_rx_iir_reg);
1728 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1730 if ((temp & FDI_RX_BIT_LOCK)) {
1731 DRM_DEBUG_KMS("FDI train 1 done.\n");
1732 I915_WRITE(fdi_rx_iir_reg,
1733 temp | FDI_RX_BIT_LOCK);
1738 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1741 temp = I915_READ(fdi_tx_reg);
1742 temp &= ~FDI_LINK_TRAIN_NONE;
1743 temp |= FDI_LINK_TRAIN_PATTERN_2;
1744 I915_WRITE(fdi_tx_reg, temp);
1746 temp = I915_READ(fdi_rx_reg);
1747 temp &= ~FDI_LINK_TRAIN_NONE;
1748 temp |= FDI_LINK_TRAIN_PATTERN_2;
1749 I915_WRITE(fdi_rx_reg, temp);
1754 for (tries = 0; tries < 5; tries++) {
1755 temp = I915_READ(fdi_rx_iir_reg);
1756 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1758 if (temp & FDI_RX_SYMBOL_LOCK) {
1759 I915_WRITE(fdi_rx_iir_reg,
1760 temp | FDI_RX_SYMBOL_LOCK);
1761 DRM_DEBUG_KMS("FDI train 2 done.\n");
1766 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1768 DRM_DEBUG_KMS("FDI train done\n");
1771 static int snb_b_fdi_train_param [] = {
1772 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1773 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1774 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1775 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1778 /* The FDI link training functions for SNB/Cougarpoint. */
1779 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1781 struct drm_device *dev = crtc->dev;
1782 struct drm_i915_private *dev_priv = dev->dev_private;
1783 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1784 int pipe = intel_crtc->pipe;
1785 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1786 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1787 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1788 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1791 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1793 temp = I915_READ(fdi_rx_imr_reg);
1794 temp &= ~FDI_RX_SYMBOL_LOCK;
1795 temp &= ~FDI_RX_BIT_LOCK;
1796 I915_WRITE(fdi_rx_imr_reg, temp);
1797 I915_READ(fdi_rx_imr_reg);
1800 /* enable CPU FDI TX and PCH FDI RX */
1801 temp = I915_READ(fdi_tx_reg);
1802 temp |= FDI_TX_ENABLE;
1804 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1805 temp &= ~FDI_LINK_TRAIN_NONE;
1806 temp |= FDI_LINK_TRAIN_PATTERN_1;
1807 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1809 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1810 I915_WRITE(fdi_tx_reg, temp);
1811 I915_READ(fdi_tx_reg);
1813 temp = I915_READ(fdi_rx_reg);
1814 if (HAS_PCH_CPT(dev)) {
1815 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1816 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1818 temp &= ~FDI_LINK_TRAIN_NONE;
1819 temp |= FDI_LINK_TRAIN_PATTERN_1;
1821 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1822 I915_READ(fdi_rx_reg);
1825 for (i = 0; i < 4; i++ ) {
1826 temp = I915_READ(fdi_tx_reg);
1827 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1828 temp |= snb_b_fdi_train_param[i];
1829 I915_WRITE(fdi_tx_reg, temp);
1832 temp = I915_READ(fdi_rx_iir_reg);
1833 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1835 if (temp & FDI_RX_BIT_LOCK) {
1836 I915_WRITE(fdi_rx_iir_reg,
1837 temp | FDI_RX_BIT_LOCK);
1838 DRM_DEBUG_KMS("FDI train 1 done.\n");
1843 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1846 temp = I915_READ(fdi_tx_reg);
1847 temp &= ~FDI_LINK_TRAIN_NONE;
1848 temp |= FDI_LINK_TRAIN_PATTERN_2;
1850 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1852 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1854 I915_WRITE(fdi_tx_reg, temp);
1856 temp = I915_READ(fdi_rx_reg);
1857 if (HAS_PCH_CPT(dev)) {
1858 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1859 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1861 temp &= ~FDI_LINK_TRAIN_NONE;
1862 temp |= FDI_LINK_TRAIN_PATTERN_2;
1864 I915_WRITE(fdi_rx_reg, temp);
1867 for (i = 0; i < 4; i++ ) {
1868 temp = I915_READ(fdi_tx_reg);
1869 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1870 temp |= snb_b_fdi_train_param[i];
1871 I915_WRITE(fdi_tx_reg, temp);
1874 temp = I915_READ(fdi_rx_iir_reg);
1875 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1877 if (temp & FDI_RX_SYMBOL_LOCK) {
1878 I915_WRITE(fdi_rx_iir_reg,
1879 temp | FDI_RX_SYMBOL_LOCK);
1880 DRM_DEBUG_KMS("FDI train 2 done.\n");
1885 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1887 DRM_DEBUG_KMS("FDI train done.\n");
1890 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1892 struct drm_device *dev = crtc->dev;
1893 struct drm_i915_private *dev_priv = dev->dev_private;
1894 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1895 int pipe = intel_crtc->pipe;
1896 int plane = intel_crtc->plane;
1897 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1898 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1899 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1900 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1901 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1902 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1903 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1904 int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1905 int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1906 int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1907 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1908 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1909 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1910 int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1911 int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1912 int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1913 int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1914 int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1915 int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1916 int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1917 int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1918 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1919 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1923 temp = I915_READ(pipeconf_reg);
1924 pipe_bpc = temp & PIPE_BPC_MASK;
1926 /* XXX: When our outputs are all unaware of DPMS modes other than off
1927 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1930 case DRM_MODE_DPMS_ON:
1931 case DRM_MODE_DPMS_STANDBY:
1932 case DRM_MODE_DPMS_SUSPEND:
1933 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
1935 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1936 temp = I915_READ(PCH_LVDS);
1937 if ((temp & LVDS_PORT_EN) == 0) {
1938 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1939 POSTING_READ(PCH_LVDS);
1944 /* enable eDP PLL */
1945 ironlake_enable_pll_edp(crtc);
1948 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1949 temp = I915_READ(fdi_rx_reg);
1951 * make the BPC in FDI Rx be consistent with that in
1954 temp &= ~(0x7 << 16);
1955 temp |= (pipe_bpc << 11);
1957 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1958 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1959 I915_READ(fdi_rx_reg);
1962 /* Switch from Rawclk to PCDclk */
1963 temp = I915_READ(fdi_rx_reg);
1964 I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1965 I915_READ(fdi_rx_reg);
1968 /* Enable CPU FDI TX PLL, always on for Ironlake */
1969 temp = I915_READ(fdi_tx_reg);
1970 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1971 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1972 I915_READ(fdi_tx_reg);
1977 /* Enable panel fitting for LVDS */
1978 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
1979 || HAS_eDP || intel_pch_has_edp(crtc)) {
1980 if (dev_priv->pch_pf_size) {
1981 temp = I915_READ(pf_ctl_reg);
1982 I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1983 I915_WRITE(pf_win_pos, dev_priv->pch_pf_pos);
1984 I915_WRITE(pf_win_size, dev_priv->pch_pf_size);
1986 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1989 /* Enable CPU pipe */
1990 temp = I915_READ(pipeconf_reg);
1991 if ((temp & PIPEACONF_ENABLE) == 0) {
1992 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1993 I915_READ(pipeconf_reg);
1997 /* configure and enable CPU plane */
1998 temp = I915_READ(dspcntr_reg);
1999 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2000 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2001 /* Flush the plane changes */
2002 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2006 /* For PCH output, training FDI link */
2008 gen6_fdi_link_train(crtc);
2010 ironlake_fdi_link_train(crtc);
2012 /* enable PCH DPLL */
2013 temp = I915_READ(pch_dpll_reg);
2014 if ((temp & DPLL_VCO_ENABLE) == 0) {
2015 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
2016 I915_READ(pch_dpll_reg);
2020 if (HAS_PCH_CPT(dev)) {
2021 /* Be sure PCH DPLL SEL is set */
2022 temp = I915_READ(PCH_DPLL_SEL);
2023 if (trans_dpll_sel == 0 &&
2024 (temp & TRANSA_DPLL_ENABLE) == 0)
2025 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2026 else if (trans_dpll_sel == 1 &&
2027 (temp & TRANSB_DPLL_ENABLE) == 0)
2028 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2029 I915_WRITE(PCH_DPLL_SEL, temp);
2030 I915_READ(PCH_DPLL_SEL);
2033 /* set transcoder timing */
2034 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
2035 I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
2036 I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
2038 I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
2039 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
2040 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
2042 /* enable normal train */
2043 temp = I915_READ(fdi_tx_reg);
2044 temp &= ~FDI_LINK_TRAIN_NONE;
2045 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
2046 FDI_TX_ENHANCE_FRAME_ENABLE);
2047 I915_READ(fdi_tx_reg);
2049 temp = I915_READ(fdi_rx_reg);
2050 if (HAS_PCH_CPT(dev)) {
2051 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2052 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2054 temp &= ~FDI_LINK_TRAIN_NONE;
2055 temp |= FDI_LINK_TRAIN_NONE;
2057 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2058 I915_READ(fdi_rx_reg);
2060 /* wait one idle pattern time */
2063 /* For PCH DP, enable TRANS_DP_CTL */
2064 if (HAS_PCH_CPT(dev) &&
2065 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2066 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2069 reg = I915_READ(trans_dp_ctl);
2070 reg &= ~(TRANS_DP_PORT_SEL_MASK |
2071 TRANS_DP_SYNC_MASK);
2072 reg |= (TRANS_DP_OUTPUT_ENABLE |
2073 TRANS_DP_ENH_FRAMING);
2075 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2076 reg |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2077 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2078 reg |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2080 switch (intel_trans_dp_port_sel(crtc)) {
2082 reg |= TRANS_DP_PORT_SEL_B;
2085 reg |= TRANS_DP_PORT_SEL_C;
2088 reg |= TRANS_DP_PORT_SEL_D;
2091 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2092 reg |= TRANS_DP_PORT_SEL_B;
2096 I915_WRITE(trans_dp_ctl, reg);
2097 POSTING_READ(trans_dp_ctl);
2100 /* enable PCH transcoder */
2101 temp = I915_READ(transconf_reg);
2103 * make the BPC in transcoder be consistent with
2104 * that in pipeconf reg.
2106 temp &= ~PIPE_BPC_MASK;
2108 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
2109 I915_READ(transconf_reg);
2111 if (wait_for(I915_READ(transconf_reg) & TRANS_STATE_ENABLE, 10, 0))
2112 DRM_ERROR("failed to enable transcoder\n");
2115 intel_crtc_load_lut(crtc);
2117 intel_update_fbc(crtc, &crtc->mode);
2120 case DRM_MODE_DPMS_OFF:
2121 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2123 drm_vblank_off(dev, pipe);
2124 /* Disable display plane */
2125 temp = I915_READ(dspcntr_reg);
2126 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2127 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2128 /* Flush the plane changes */
2129 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2130 I915_READ(dspbase_reg);
2133 if (dev_priv->cfb_plane == plane &&
2134 dev_priv->display.disable_fbc)
2135 dev_priv->display.disable_fbc(dev);
2137 /* disable cpu pipe, disable after all planes disabled */
2138 temp = I915_READ(pipeconf_reg);
2139 if ((temp & PIPEACONF_ENABLE) != 0) {
2140 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2142 /* wait for cpu pipe off, pipe state */
2143 if (wait_for((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) == 0, 50, 1))
2144 DRM_ERROR("failed to turn off cpu pipe\n");
2146 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
2151 temp = I915_READ(pf_ctl_reg);
2152 if ((temp & PF_ENABLE) != 0) {
2153 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
2154 I915_READ(pf_ctl_reg);
2156 I915_WRITE(pf_win_size, 0);
2157 POSTING_READ(pf_win_size);
2160 /* disable CPU FDI tx and PCH FDI rx */
2161 temp = I915_READ(fdi_tx_reg);
2162 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
2163 I915_READ(fdi_tx_reg);
2165 temp = I915_READ(fdi_rx_reg);
2166 /* BPC in FDI rx is consistent with that in pipeconf */
2167 temp &= ~(0x07 << 16);
2168 temp |= (pipe_bpc << 11);
2169 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
2170 I915_READ(fdi_rx_reg);
2174 /* still set train pattern 1 */
2175 temp = I915_READ(fdi_tx_reg);
2176 temp &= ~FDI_LINK_TRAIN_NONE;
2177 temp |= FDI_LINK_TRAIN_PATTERN_1;
2178 I915_WRITE(fdi_tx_reg, temp);
2179 POSTING_READ(fdi_tx_reg);
2181 temp = I915_READ(fdi_rx_reg);
2182 if (HAS_PCH_CPT(dev)) {
2183 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2184 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2186 temp &= ~FDI_LINK_TRAIN_NONE;
2187 temp |= FDI_LINK_TRAIN_PATTERN_1;
2189 I915_WRITE(fdi_rx_reg, temp);
2190 POSTING_READ(fdi_rx_reg);
2194 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2195 temp = I915_READ(PCH_LVDS);
2196 I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2197 I915_READ(PCH_LVDS);
2201 /* disable PCH transcoder */
2202 temp = I915_READ(transconf_reg);
2203 if ((temp & TRANS_ENABLE) != 0) {
2204 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2206 /* wait for PCH transcoder off, transcoder state */
2207 if (wait_for((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0, 50, 1))
2208 DRM_ERROR("failed to disable transcoder\n");
2211 temp = I915_READ(transconf_reg);
2212 /* BPC in transcoder is consistent with that in pipeconf */
2213 temp &= ~PIPE_BPC_MASK;
2215 I915_WRITE(transconf_reg, temp);
2216 I915_READ(transconf_reg);
2219 if (HAS_PCH_CPT(dev)) {
2220 /* disable TRANS_DP_CTL */
2221 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2224 reg = I915_READ(trans_dp_ctl);
2225 reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2226 I915_WRITE(trans_dp_ctl, reg);
2227 POSTING_READ(trans_dp_ctl);
2229 /* disable DPLL_SEL */
2230 temp = I915_READ(PCH_DPLL_SEL);
2231 if (trans_dpll_sel == 0)
2232 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2234 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2235 I915_WRITE(PCH_DPLL_SEL, temp);
2236 I915_READ(PCH_DPLL_SEL);
2240 /* disable PCH DPLL */
2241 temp = I915_READ(pch_dpll_reg);
2242 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2243 I915_READ(pch_dpll_reg);
2246 ironlake_disable_pll_edp(crtc);
2249 /* Switch from PCDclk to Rawclk */
2250 temp = I915_READ(fdi_rx_reg);
2251 temp &= ~FDI_SEL_PCDCLK;
2252 I915_WRITE(fdi_rx_reg, temp);
2253 I915_READ(fdi_rx_reg);
2255 /* Disable CPU FDI TX PLL */
2256 temp = I915_READ(fdi_tx_reg);
2257 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2258 I915_READ(fdi_tx_reg);
2261 temp = I915_READ(fdi_rx_reg);
2262 temp &= ~FDI_RX_PLL_ENABLE;
2263 I915_WRITE(fdi_rx_reg, temp);
2264 I915_READ(fdi_rx_reg);
2266 /* Wait for the clocks to turn off. */
2272 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2274 struct intel_overlay *overlay;
2277 if (!enable && intel_crtc->overlay) {
2278 overlay = intel_crtc->overlay;
2279 mutex_lock(&overlay->dev->struct_mutex);
2281 ret = intel_overlay_switch_off(overlay);
2285 ret = intel_overlay_recover_from_interrupt(overlay, 0);
2287 /* overlay doesn't react anymore. Usually
2288 * results in a black screen and an unkillable
2291 overlay->hw_wedged = HW_WEDGED;
2295 mutex_unlock(&overlay->dev->struct_mutex);
2297 /* Let userspace switch the overlay on again. In most cases userspace
2298 * has to recompute where to put it anyway. */
2303 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2305 struct drm_device *dev = crtc->dev;
2306 struct drm_i915_private *dev_priv = dev->dev_private;
2307 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2308 int pipe = intel_crtc->pipe;
2309 int plane = intel_crtc->plane;
2310 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2311 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2312 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2313 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2316 /* XXX: When our outputs are all unaware of DPMS modes other than off
2317 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2320 case DRM_MODE_DPMS_ON:
2321 case DRM_MODE_DPMS_STANDBY:
2322 case DRM_MODE_DPMS_SUSPEND:
2323 /* Enable the DPLL */
2324 temp = I915_READ(dpll_reg);
2325 if ((temp & DPLL_VCO_ENABLE) == 0) {
2326 I915_WRITE(dpll_reg, temp);
2327 I915_READ(dpll_reg);
2328 /* Wait for the clocks to stabilize. */
2330 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2331 I915_READ(dpll_reg);
2332 /* Wait for the clocks to stabilize. */
2334 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2335 I915_READ(dpll_reg);
2336 /* Wait for the clocks to stabilize. */
2340 /* Enable the pipe */
2341 temp = I915_READ(pipeconf_reg);
2342 if ((temp & PIPEACONF_ENABLE) == 0)
2343 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2345 /* Enable the plane */
2346 temp = I915_READ(dspcntr_reg);
2347 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2348 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2349 /* Flush the plane changes */
2350 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2353 intel_crtc_load_lut(crtc);
2355 if ((IS_I965G(dev) || plane == 0))
2356 intel_update_fbc(crtc, &crtc->mode);
2358 /* Give the overlay scaler a chance to enable if it's on this pipe */
2359 intel_crtc_dpms_overlay(intel_crtc, true);
2361 case DRM_MODE_DPMS_OFF:
2362 /* Give the overlay scaler a chance to disable if it's on this pipe */
2363 intel_crtc_dpms_overlay(intel_crtc, false);
2364 drm_vblank_off(dev, pipe);
2366 if (dev_priv->cfb_plane == plane &&
2367 dev_priv->display.disable_fbc)
2368 dev_priv->display.disable_fbc(dev);
2370 /* Disable display plane */
2371 temp = I915_READ(dspcntr_reg);
2372 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2373 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2374 /* Flush the plane changes */
2375 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2376 I915_READ(dspbase_reg);
2379 if (!IS_I9XX(dev)) {
2380 /* Wait for vblank for the disable to take effect */
2381 intel_wait_for_vblank(dev);
2384 /* Don't disable pipe A or pipe A PLLs if needed */
2385 if (pipeconf_reg == PIPEACONF &&
2386 (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2389 /* Next, disable display pipes */
2390 temp = I915_READ(pipeconf_reg);
2391 if ((temp & PIPEACONF_ENABLE) != 0) {
2392 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2393 I915_READ(pipeconf_reg);
2396 /* Wait for vblank for the disable to take effect. */
2397 intel_wait_for_vblank(dev);
2399 temp = I915_READ(dpll_reg);
2400 if ((temp & DPLL_VCO_ENABLE) != 0) {
2401 I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2402 I915_READ(dpll_reg);
2405 /* Wait for the clocks to turn off. */
2412 * Sets the power management mode of the pipe and plane.
2414 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2416 struct drm_device *dev = crtc->dev;
2417 struct drm_i915_private *dev_priv = dev->dev_private;
2418 struct drm_i915_master_private *master_priv;
2419 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2420 int pipe = intel_crtc->pipe;
2423 intel_crtc->dpms_mode = mode;
2424 intel_crtc->cursor_on = mode == DRM_MODE_DPMS_ON;
2426 /* When switching on the display, ensure that SR is disabled
2427 * with multiple pipes prior to enabling to new pipe.
2429 * When switching off the display, make sure the cursor is
2430 * properly hidden prior to disabling the pipe.
2432 if (mode == DRM_MODE_DPMS_ON)
2433 intel_update_watermarks(dev);
2435 intel_crtc_update_cursor(crtc);
2437 dev_priv->display.dpms(crtc, mode);
2439 if (mode == DRM_MODE_DPMS_ON)
2440 intel_crtc_update_cursor(crtc);
2442 intel_update_watermarks(dev);
2444 if (!dev->primary->master)
2447 master_priv = dev->primary->master->driver_priv;
2448 if (!master_priv->sarea_priv)
2451 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2455 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2456 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2459 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2460 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2463 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2468 static void intel_crtc_prepare (struct drm_crtc *crtc)
2470 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2471 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2474 static void intel_crtc_commit (struct drm_crtc *crtc)
2476 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2477 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2480 void intel_encoder_prepare (struct drm_encoder *encoder)
2482 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2483 /* lvds has its own version of prepare see intel_lvds_prepare */
2484 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2487 void intel_encoder_commit (struct drm_encoder *encoder)
2489 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2490 /* lvds has its own version of commit see intel_lvds_commit */
2491 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2494 void intel_encoder_destroy(struct drm_encoder *encoder)
2496 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
2498 if (intel_encoder->ddc_bus)
2499 intel_i2c_destroy(intel_encoder->ddc_bus);
2501 if (intel_encoder->i2c_bus)
2502 intel_i2c_destroy(intel_encoder->i2c_bus);
2504 drm_encoder_cleanup(encoder);
2505 kfree(intel_encoder);
2508 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2509 struct drm_display_mode *mode,
2510 struct drm_display_mode *adjusted_mode)
2512 struct drm_device *dev = crtc->dev;
2513 if (HAS_PCH_SPLIT(dev)) {
2514 /* FDI link clock is fixed at 2.7G */
2515 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2521 static int i945_get_display_clock_speed(struct drm_device *dev)
2526 static int i915_get_display_clock_speed(struct drm_device *dev)
2531 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2536 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2540 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2542 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2545 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2546 case GC_DISPLAY_CLOCK_333_MHZ:
2549 case GC_DISPLAY_CLOCK_190_200_MHZ:
2555 static int i865_get_display_clock_speed(struct drm_device *dev)
2560 static int i855_get_display_clock_speed(struct drm_device *dev)
2563 /* Assume that the hardware is in the high speed state. This
2564 * should be the default.
2566 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2567 case GC_CLOCK_133_200:
2568 case GC_CLOCK_100_200:
2570 case GC_CLOCK_166_250:
2572 case GC_CLOCK_100_133:
2576 /* Shouldn't happen */
2580 static int i830_get_display_clock_speed(struct drm_device *dev)
2586 * Return the pipe currently connected to the panel fitter,
2587 * or -1 if the panel fitter is not present or not in use
2589 int intel_panel_fitter_pipe (struct drm_device *dev)
2591 struct drm_i915_private *dev_priv = dev->dev_private;
2594 /* i830 doesn't have a panel fitter */
2598 pfit_control = I915_READ(PFIT_CONTROL);
2600 /* See if the panel fitter is in use */
2601 if ((pfit_control & PFIT_ENABLE) == 0)
2604 /* 965 can place panel fitter on either pipe */
2606 return (pfit_control >> 29) & 0x3;
2608 /* older chips can only use pipe 1 */
2621 fdi_reduce_ratio(u32 *num, u32 *den)
2623 while (*num > 0xffffff || *den > 0xffffff) {
2629 #define DATA_N 0x800000
2630 #define LINK_N 0x80000
2633 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2634 int link_clock, struct fdi_m_n *m_n)
2638 m_n->tu = 64; /* default size */
2640 temp = (u64) DATA_N * pixel_clock;
2641 temp = div_u64(temp, link_clock);
2642 m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2643 m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2644 m_n->gmch_n = DATA_N;
2645 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2647 temp = (u64) LINK_N * pixel_clock;
2648 m_n->link_m = div_u64(temp, link_clock);
2649 m_n->link_n = LINK_N;
2650 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2654 struct intel_watermark_params {
2655 unsigned long fifo_size;
2656 unsigned long max_wm;
2657 unsigned long default_wm;
2658 unsigned long guard_size;
2659 unsigned long cacheline_size;
2662 /* Pineview has different values for various configs */
2663 static struct intel_watermark_params pineview_display_wm = {
2664 PINEVIEW_DISPLAY_FIFO,
2668 PINEVIEW_FIFO_LINE_SIZE
2670 static struct intel_watermark_params pineview_display_hplloff_wm = {
2671 PINEVIEW_DISPLAY_FIFO,
2673 PINEVIEW_DFT_HPLLOFF_WM,
2675 PINEVIEW_FIFO_LINE_SIZE
2677 static struct intel_watermark_params pineview_cursor_wm = {
2678 PINEVIEW_CURSOR_FIFO,
2679 PINEVIEW_CURSOR_MAX_WM,
2680 PINEVIEW_CURSOR_DFT_WM,
2681 PINEVIEW_CURSOR_GUARD_WM,
2682 PINEVIEW_FIFO_LINE_SIZE,
2684 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2685 PINEVIEW_CURSOR_FIFO,
2686 PINEVIEW_CURSOR_MAX_WM,
2687 PINEVIEW_CURSOR_DFT_WM,
2688 PINEVIEW_CURSOR_GUARD_WM,
2689 PINEVIEW_FIFO_LINE_SIZE
2691 static struct intel_watermark_params g4x_wm_info = {
2698 static struct intel_watermark_params g4x_cursor_wm_info = {
2705 static struct intel_watermark_params i965_cursor_wm_info = {
2710 I915_FIFO_LINE_SIZE,
2712 static struct intel_watermark_params i945_wm_info = {
2719 static struct intel_watermark_params i915_wm_info = {
2726 static struct intel_watermark_params i855_wm_info = {
2733 static struct intel_watermark_params i830_wm_info = {
2741 static struct intel_watermark_params ironlake_display_wm_info = {
2749 static struct intel_watermark_params ironlake_cursor_wm_info = {
2757 static struct intel_watermark_params ironlake_display_srwm_info = {
2758 ILK_DISPLAY_SR_FIFO,
2759 ILK_DISPLAY_MAX_SRWM,
2760 ILK_DISPLAY_DFT_SRWM,
2765 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2767 ILK_CURSOR_MAX_SRWM,
2768 ILK_CURSOR_DFT_SRWM,
2774 * intel_calculate_wm - calculate watermark level
2775 * @clock_in_khz: pixel clock
2776 * @wm: chip FIFO params
2777 * @pixel_size: display pixel size
2778 * @latency_ns: memory latency for the platform
2780 * Calculate the watermark level (the level at which the display plane will
2781 * start fetching from memory again). Each chip has a different display
2782 * FIFO size and allocation, so the caller needs to figure that out and pass
2783 * in the correct intel_watermark_params structure.
2785 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2786 * on the pixel size. When it reaches the watermark level, it'll start
2787 * fetching FIFO line sized based chunks from memory until the FIFO fills
2788 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2789 * will occur, and a display engine hang could result.
2791 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2792 struct intel_watermark_params *wm,
2794 unsigned long latency_ns)
2796 long entries_required, wm_size;
2799 * Note: we need to make sure we don't overflow for various clock &
2801 * clocks go from a few thousand to several hundred thousand.
2802 * latency is usually a few thousand
2804 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2806 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2808 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2810 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2812 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2814 /* Don't promote wm_size to unsigned... */
2815 if (wm_size > (long)wm->max_wm)
2816 wm_size = wm->max_wm;
2818 wm_size = wm->default_wm;
2819 DRM_ERROR("Insufficient FIFO for plane, expect flickering:"
2820 " entries required = %ld, available = %lu.\n",
2821 entries_required + wm->guard_size,
2828 struct cxsr_latency {
2831 unsigned long fsb_freq;
2832 unsigned long mem_freq;
2833 unsigned long display_sr;
2834 unsigned long display_hpll_disable;
2835 unsigned long cursor_sr;
2836 unsigned long cursor_hpll_disable;
2839 static const struct cxsr_latency cxsr_latency_table[] = {
2840 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2841 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2842 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2843 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
2844 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
2846 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2847 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2848 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2849 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
2850 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
2852 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2853 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2854 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2855 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
2856 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
2858 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2859 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2860 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2861 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
2862 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
2864 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2865 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2866 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2867 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
2868 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
2870 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2871 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2872 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2873 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
2874 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
2877 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2882 const struct cxsr_latency *latency;
2885 if (fsb == 0 || mem == 0)
2888 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2889 latency = &cxsr_latency_table[i];
2890 if (is_desktop == latency->is_desktop &&
2891 is_ddr3 == latency->is_ddr3 &&
2892 fsb == latency->fsb_freq && mem == latency->mem_freq)
2896 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2901 static void pineview_disable_cxsr(struct drm_device *dev)
2903 struct drm_i915_private *dev_priv = dev->dev_private;
2905 /* deactivate cxsr */
2906 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2910 * Latency for FIFO fetches is dependent on several factors:
2911 * - memory configuration (speed, channels)
2913 * - current MCH state
2914 * It can be fairly high in some situations, so here we assume a fairly
2915 * pessimal value. It's a tradeoff between extra memory fetches (if we
2916 * set this value too high, the FIFO will fetch frequently to stay full)
2917 * and power consumption (set it too low to save power and we might see
2918 * FIFO underruns and display "flicker").
2920 * A value of 5us seems to be a good balance; safe for very low end
2921 * platforms but not overly aggressive on lower latency configs.
2923 static const int latency_ns = 5000;
2925 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2927 struct drm_i915_private *dev_priv = dev->dev_private;
2928 uint32_t dsparb = I915_READ(DSPARB);
2931 size = dsparb & 0x7f;
2933 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
2935 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2936 plane ? "B" : "A", size);
2941 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2943 struct drm_i915_private *dev_priv = dev->dev_private;
2944 uint32_t dsparb = I915_READ(DSPARB);
2947 size = dsparb & 0x1ff;
2949 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
2950 size >>= 1; /* Convert to cachelines */
2952 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2953 plane ? "B" : "A", size);
2958 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2960 struct drm_i915_private *dev_priv = dev->dev_private;
2961 uint32_t dsparb = I915_READ(DSPARB);
2964 size = dsparb & 0x7f;
2965 size >>= 2; /* Convert to cachelines */
2967 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2974 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2976 struct drm_i915_private *dev_priv = dev->dev_private;
2977 uint32_t dsparb = I915_READ(DSPARB);
2980 size = dsparb & 0x7f;
2981 size >>= 1; /* Convert to cachelines */
2983 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2984 plane ? "B" : "A", size);
2989 static void pineview_update_wm(struct drm_device *dev, int planea_clock,
2990 int planeb_clock, int sr_hdisplay, int unused,
2993 struct drm_i915_private *dev_priv = dev->dev_private;
2994 const struct cxsr_latency *latency;
2999 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3000 dev_priv->fsb_freq, dev_priv->mem_freq);
3002 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3003 pineview_disable_cxsr(dev);
3007 if (!planea_clock || !planeb_clock) {
3008 sr_clock = planea_clock ? planea_clock : planeb_clock;
3011 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3012 pixel_size, latency->display_sr);
3013 reg = I915_READ(DSPFW1);
3014 reg &= ~DSPFW_SR_MASK;
3015 reg |= wm << DSPFW_SR_SHIFT;
3016 I915_WRITE(DSPFW1, reg);
3017 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3020 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3021 pixel_size, latency->cursor_sr);
3022 reg = I915_READ(DSPFW3);
3023 reg &= ~DSPFW_CURSOR_SR_MASK;
3024 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3025 I915_WRITE(DSPFW3, reg);
3027 /* Display HPLL off SR */
3028 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3029 pixel_size, latency->display_hpll_disable);
3030 reg = I915_READ(DSPFW3);
3031 reg &= ~DSPFW_HPLL_SR_MASK;
3032 reg |= wm & DSPFW_HPLL_SR_MASK;
3033 I915_WRITE(DSPFW3, reg);
3035 /* cursor HPLL off SR */
3036 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3037 pixel_size, latency->cursor_hpll_disable);
3038 reg = I915_READ(DSPFW3);
3039 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3040 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3041 I915_WRITE(DSPFW3, reg);
3042 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3046 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3047 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3049 pineview_disable_cxsr(dev);
3050 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3054 static void g4x_update_wm(struct drm_device *dev, int planea_clock,
3055 int planeb_clock, int sr_hdisplay, int sr_htotal,
3058 struct drm_i915_private *dev_priv = dev->dev_private;
3059 int total_size, cacheline_size;
3060 int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3061 struct intel_watermark_params planea_params, planeb_params;
3062 unsigned long line_time_us;
3063 int sr_clock, sr_entries = 0, entries_required;
3065 /* Create copies of the base settings for each pipe */
3066 planea_params = planeb_params = g4x_wm_info;
3068 /* Grab a couple of global values before we overwrite them */
3069 total_size = planea_params.fifo_size;
3070 cacheline_size = planea_params.cacheline_size;
3073 * Note: we need to make sure we don't overflow for various clock &
3075 * clocks go from a few thousand to several hundred thousand.
3076 * latency is usually a few thousand
3078 entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3080 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3081 planea_wm = entries_required + planea_params.guard_size;
3083 entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3085 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3086 planeb_wm = entries_required + planeb_params.guard_size;
3088 cursora_wm = cursorb_wm = 16;
3091 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3093 /* Calc sr entries for one plane configs */
3094 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3095 /* self-refresh has much higher latency */
3096 static const int sr_latency_ns = 12000;
3098 sr_clock = planea_clock ? planea_clock : planeb_clock;
3099 line_time_us = ((sr_htotal * 1000) / sr_clock);
3101 /* Use ns/us then divide to preserve precision */
3102 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3103 pixel_size * sr_hdisplay;
3104 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3106 entries_required = (((sr_latency_ns / line_time_us) +
3107 1000) / 1000) * pixel_size * 64;
3108 entries_required = DIV_ROUND_UP(entries_required,
3109 g4x_cursor_wm_info.cacheline_size);
3110 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3112 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3113 cursor_sr = g4x_cursor_wm_info.max_wm;
3114 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3115 "cursor %d\n", sr_entries, cursor_sr);
3117 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3119 /* Turn off self refresh if both pipes are enabled */
3120 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3124 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3125 planea_wm, planeb_wm, sr_entries);
3130 I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3131 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3132 (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3133 I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3134 (cursora_wm << DSPFW_CURSORA_SHIFT));
3135 /* HPLL off in SR has some issues on G4x... disable it */
3136 I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3137 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3140 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3141 int planeb_clock, int sr_hdisplay, int sr_htotal,
3144 struct drm_i915_private *dev_priv = dev->dev_private;
3145 unsigned long line_time_us;
3146 int sr_clock, sr_entries, srwm = 1;
3149 /* Calc sr entries for one plane configs */
3150 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3151 /* self-refresh has much higher latency */
3152 static const int sr_latency_ns = 12000;
3154 sr_clock = planea_clock ? planea_clock : planeb_clock;
3155 line_time_us = ((sr_htotal * 1000) / sr_clock);
3157 /* Use ns/us then divide to preserve precision */
3158 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3159 pixel_size * sr_hdisplay;
3160 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3161 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3162 srwm = I965_FIFO_SIZE - sr_entries;
3167 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3169 sr_entries = DIV_ROUND_UP(sr_entries,
3170 i965_cursor_wm_info.cacheline_size);
3171 cursor_sr = i965_cursor_wm_info.fifo_size -
3172 (sr_entries + i965_cursor_wm_info.guard_size);
3174 if (cursor_sr > i965_cursor_wm_info.max_wm)
3175 cursor_sr = i965_cursor_wm_info.max_wm;
3177 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3178 "cursor %d\n", srwm, cursor_sr);
3181 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3183 /* Turn off self refresh if both pipes are enabled */
3185 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3189 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3192 /* 965 has limitations... */
3193 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3195 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3196 /* update cursor SR watermark */
3197 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3200 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3201 int planeb_clock, int sr_hdisplay, int sr_htotal,
3204 struct drm_i915_private *dev_priv = dev->dev_private;
3207 int total_size, cacheline_size, cwm, srwm = 1;
3208 int planea_wm, planeb_wm;
3209 struct intel_watermark_params planea_params, planeb_params;
3210 unsigned long line_time_us;
3211 int sr_clock, sr_entries = 0;
3213 /* Create copies of the base settings for each pipe */
3214 if (IS_I965GM(dev) || IS_I945GM(dev))
3215 planea_params = planeb_params = i945_wm_info;
3216 else if (IS_I9XX(dev))
3217 planea_params = planeb_params = i915_wm_info;
3219 planea_params = planeb_params = i855_wm_info;
3221 /* Grab a couple of global values before we overwrite them */
3222 total_size = planea_params.fifo_size;
3223 cacheline_size = planea_params.cacheline_size;
3225 /* Update per-plane FIFO sizes */
3226 planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3227 planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3229 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3230 pixel_size, latency_ns);
3231 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3232 pixel_size, latency_ns);
3233 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3236 * Overlay gets an aggressive default since video jitter is bad.
3240 /* Calc sr entries for one plane configs */
3241 if (HAS_FW_BLC(dev) && sr_hdisplay &&
3242 (!planea_clock || !planeb_clock)) {
3243 /* self-refresh has much higher latency */
3244 static const int sr_latency_ns = 6000;
3246 sr_clock = planea_clock ? planea_clock : planeb_clock;
3247 line_time_us = ((sr_htotal * 1000) / sr_clock);
3249 /* Use ns/us then divide to preserve precision */
3250 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3251 pixel_size * sr_hdisplay;
3252 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3253 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3254 srwm = total_size - sr_entries;
3258 if (IS_I945G(dev) || IS_I945GM(dev))
3259 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3260 else if (IS_I915GM(dev)) {
3261 /* 915M has a smaller SRWM field */
3262 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3263 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3266 /* Turn off self refresh if both pipes are enabled */
3267 if (IS_I945G(dev) || IS_I945GM(dev)) {
3268 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3270 } else if (IS_I915GM(dev)) {
3271 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3275 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3276 planea_wm, planeb_wm, cwm, srwm);
3278 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3279 fwater_hi = (cwm & 0x1f);
3281 /* Set request length to 8 cachelines per fetch */
3282 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3283 fwater_hi = fwater_hi | (1 << 8);
3285 I915_WRITE(FW_BLC, fwater_lo);
3286 I915_WRITE(FW_BLC2, fwater_hi);
3289 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3290 int unused2, int unused3, int pixel_size)
3292 struct drm_i915_private *dev_priv = dev->dev_private;
3293 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3296 i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3298 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3299 pixel_size, latency_ns);
3300 fwater_lo |= (3<<8) | planea_wm;
3302 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3304 I915_WRITE(FW_BLC, fwater_lo);
3307 #define ILK_LP0_PLANE_LATENCY 700
3308 #define ILK_LP0_CURSOR_LATENCY 1300
3310 static void ironlake_update_wm(struct drm_device *dev, int planea_clock,
3311 int planeb_clock, int sr_hdisplay, int sr_htotal,
3314 struct drm_i915_private *dev_priv = dev->dev_private;
3315 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3316 int sr_wm, cursor_wm;
3317 unsigned long line_time_us;
3318 int sr_clock, entries_required;
3321 int planea_htotal = 0, planeb_htotal = 0;
3322 struct drm_crtc *crtc;
3324 /* Need htotal for all active display plane */
3325 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3326 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3327 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
3328 if (intel_crtc->plane == 0)
3329 planea_htotal = crtc->mode.htotal;
3331 planeb_htotal = crtc->mode.htotal;
3335 /* Calculate and update the watermark for plane A */
3337 entries_required = ((planea_clock / 1000) * pixel_size *
3338 ILK_LP0_PLANE_LATENCY) / 1000;
3339 entries_required = DIV_ROUND_UP(entries_required,
3340 ironlake_display_wm_info.cacheline_size);
3341 planea_wm = entries_required +
3342 ironlake_display_wm_info.guard_size;
3344 if (planea_wm > (int)ironlake_display_wm_info.max_wm)
3345 planea_wm = ironlake_display_wm_info.max_wm;
3347 /* Use the large buffer method to calculate cursor watermark */
3348 line_time_us = (planea_htotal * 1000) / planea_clock;
3350 /* Use ns/us then divide to preserve precision */
3351 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3353 /* calculate the cursor watermark for cursor A */
3354 entries_required = line_count * 64 * pixel_size;
3355 entries_required = DIV_ROUND_UP(entries_required,
3356 ironlake_cursor_wm_info.cacheline_size);
3357 cursora_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3358 if (cursora_wm > ironlake_cursor_wm_info.max_wm)
3359 cursora_wm = ironlake_cursor_wm_info.max_wm;
3361 reg_value = I915_READ(WM0_PIPEA_ILK);
3362 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3363 reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
3364 (cursora_wm & WM0_PIPE_CURSOR_MASK);
3365 I915_WRITE(WM0_PIPEA_ILK, reg_value);
3366 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3367 "cursor: %d\n", planea_wm, cursora_wm);
3369 /* Calculate and update the watermark for plane B */
3371 entries_required = ((planeb_clock / 1000) * pixel_size *
3372 ILK_LP0_PLANE_LATENCY) / 1000;
3373 entries_required = DIV_ROUND_UP(entries_required,
3374 ironlake_display_wm_info.cacheline_size);
3375 planeb_wm = entries_required +
3376 ironlake_display_wm_info.guard_size;
3378 if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
3379 planeb_wm = ironlake_display_wm_info.max_wm;
3381 /* Use the large buffer method to calculate cursor watermark */
3382 line_time_us = (planeb_htotal * 1000) / planeb_clock;
3384 /* Use ns/us then divide to preserve precision */
3385 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3387 /* calculate the cursor watermark for cursor B */
3388 entries_required = line_count * 64 * pixel_size;
3389 entries_required = DIV_ROUND_UP(entries_required,
3390 ironlake_cursor_wm_info.cacheline_size);
3391 cursorb_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3392 if (cursorb_wm > ironlake_cursor_wm_info.max_wm)
3393 cursorb_wm = ironlake_cursor_wm_info.max_wm;
3395 reg_value = I915_READ(WM0_PIPEB_ILK);
3396 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3397 reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
3398 (cursorb_wm & WM0_PIPE_CURSOR_MASK);
3399 I915_WRITE(WM0_PIPEB_ILK, reg_value);
3400 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3401 "cursor: %d\n", planeb_wm, cursorb_wm);
3405 * Calculate and update the self-refresh watermark only when one
3406 * display plane is used.
3408 if (!planea_clock || !planeb_clock) {
3410 /* Read the self-refresh latency. The unit is 0.5us */
3411 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3413 sr_clock = planea_clock ? planea_clock : planeb_clock;
3414 line_time_us = ((sr_htotal * 1000) / sr_clock);
3416 /* Use ns/us then divide to preserve precision */
3417 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3420 /* calculate the self-refresh watermark for display plane */
3421 entries_required = line_count * sr_hdisplay * pixel_size;
3422 entries_required = DIV_ROUND_UP(entries_required,
3423 ironlake_display_srwm_info.cacheline_size);
3424 sr_wm = entries_required +
3425 ironlake_display_srwm_info.guard_size;
3427 /* calculate the self-refresh watermark for display cursor */
3428 entries_required = line_count * pixel_size * 64;
3429 entries_required = DIV_ROUND_UP(entries_required,
3430 ironlake_cursor_srwm_info.cacheline_size);
3431 cursor_wm = entries_required +
3432 ironlake_cursor_srwm_info.guard_size;
3434 /* configure watermark and enable self-refresh */
3435 reg_value = I915_READ(WM1_LP_ILK);
3436 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
3437 WM1_LP_CURSOR_MASK);
3438 reg_value |= WM1_LP_SR_EN |
3439 (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3440 (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
3442 I915_WRITE(WM1_LP_ILK, reg_value);
3443 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3444 "cursor %d\n", sr_wm, cursor_wm);
3447 /* Turn off self refresh if both pipes are enabled */
3448 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
3452 * intel_update_watermarks - update FIFO watermark values based on current modes
3454 * Calculate watermark values for the various WM regs based on current mode
3455 * and plane configuration.
3457 * There are several cases to deal with here:
3458 * - normal (i.e. non-self-refresh)
3459 * - self-refresh (SR) mode
3460 * - lines are large relative to FIFO size (buffer can hold up to 2)
3461 * - lines are small relative to FIFO size (buffer can hold more than 2
3462 * lines), so need to account for TLB latency
3464 * The normal calculation is:
3465 * watermark = dotclock * bytes per pixel * latency
3466 * where latency is platform & configuration dependent (we assume pessimal
3469 * The SR calculation is:
3470 * watermark = (trunc(latency/line time)+1) * surface width *
3473 * line time = htotal / dotclock
3474 * surface width = hdisplay for normal plane and 64 for cursor
3475 * and latency is assumed to be high, as above.
3477 * The final value programmed to the register should always be rounded up,
3478 * and include an extra 2 entries to account for clock crossings.
3480 * We don't use the sprite, so we can ignore that. And on Crestline we have
3481 * to set the non-SR watermarks to 8.
3483 static void intel_update_watermarks(struct drm_device *dev)
3485 struct drm_i915_private *dev_priv = dev->dev_private;
3486 struct drm_crtc *crtc;
3487 int sr_hdisplay = 0;
3488 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3489 int enabled = 0, pixel_size = 0;
3492 if (!dev_priv->display.update_wm)
3495 /* Get the clock config from both planes */
3496 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3497 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3498 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
3500 if (intel_crtc->plane == 0) {
3501 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3502 intel_crtc->pipe, crtc->mode.clock);
3503 planea_clock = crtc->mode.clock;
3505 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3506 intel_crtc->pipe, crtc->mode.clock);
3507 planeb_clock = crtc->mode.clock;
3509 sr_hdisplay = crtc->mode.hdisplay;
3510 sr_clock = crtc->mode.clock;
3511 sr_htotal = crtc->mode.htotal;
3513 pixel_size = crtc->fb->bits_per_pixel / 8;
3515 pixel_size = 4; /* by default */
3522 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3523 sr_hdisplay, sr_htotal, pixel_size);
3526 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3527 struct drm_display_mode *mode,
3528 struct drm_display_mode *adjusted_mode,
3530 struct drm_framebuffer *old_fb)
3532 struct drm_device *dev = crtc->dev;
3533 struct drm_i915_private *dev_priv = dev->dev_private;
3534 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3535 int pipe = intel_crtc->pipe;
3536 int plane = intel_crtc->plane;
3537 int fp_reg = (pipe == 0) ? FPA0 : FPB0;
3538 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3539 int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
3540 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
3541 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
3542 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
3543 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
3544 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
3545 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
3546 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
3547 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
3548 int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
3549 int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
3550 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
3551 int refclk, num_connectors = 0;
3552 intel_clock_t clock, reduced_clock;
3553 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3554 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3555 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3556 bool is_edp = false;
3557 struct drm_mode_config *mode_config = &dev->mode_config;
3558 struct drm_encoder *encoder;
3559 struct intel_encoder *intel_encoder = NULL;
3560 const intel_limit_t *limit;
3562 struct fdi_m_n m_n = {0};
3563 int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
3564 int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
3565 int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
3566 int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
3567 int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
3568 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
3569 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
3570 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
3571 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
3572 int lvds_reg = LVDS;
3574 int sdvo_pixel_multiply;
3577 drm_vblank_pre_modeset(dev, pipe);
3579 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
3581 if (!encoder || encoder->crtc != crtc)
3584 intel_encoder = enc_to_intel_encoder(encoder);
3586 switch (intel_encoder->type) {
3587 case INTEL_OUTPUT_LVDS:
3590 case INTEL_OUTPUT_SDVO:
3591 case INTEL_OUTPUT_HDMI:
3593 if (intel_encoder->needs_tv_clock)
3596 case INTEL_OUTPUT_DVO:
3599 case INTEL_OUTPUT_TVOUT:
3602 case INTEL_OUTPUT_ANALOG:
3605 case INTEL_OUTPUT_DISPLAYPORT:
3608 case INTEL_OUTPUT_EDP:
3616 if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3617 refclk = dev_priv->lvds_ssc_freq * 1000;
3618 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3620 } else if (IS_I9XX(dev)) {
3622 if (HAS_PCH_SPLIT(dev))
3623 refclk = 120000; /* 120Mhz refclk */
3630 * Returns a set of divisors for the desired target clock with the given
3631 * refclk, or FALSE. The returned values represent the clock equation:
3632 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3634 limit = intel_limit(crtc);
3635 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3637 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3638 drm_vblank_post_modeset(dev, pipe);
3642 /* Ensure that the cursor is valid for the new mode before changing... */
3643 intel_crtc_update_cursor(crtc);
3645 if (is_lvds && dev_priv->lvds_downclock_avail) {
3646 has_reduced_clock = limit->find_pll(limit, crtc,
3647 dev_priv->lvds_downclock,
3650 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3652 * If the different P is found, it means that we can't
3653 * switch the display clock by using the FP0/FP1.
3654 * In such case we will disable the LVDS downclock
3657 DRM_DEBUG_KMS("Different P is found for "
3658 "LVDS clock/downclock\n");
3659 has_reduced_clock = 0;
3662 /* SDVO TV has fixed PLL values depend on its clock range,
3663 this mirrors vbios setting. */
3664 if (is_sdvo && is_tv) {
3665 if (adjusted_mode->clock >= 100000
3666 && adjusted_mode->clock < 140500) {
3672 } else if (adjusted_mode->clock >= 140500
3673 && adjusted_mode->clock <= 200000) {
3683 if (HAS_PCH_SPLIT(dev)) {
3684 int lane = 0, link_bw, bpp;
3685 /* eDP doesn't require FDI link, so just set DP M/N
3686 according to current link config */
3688 target_clock = mode->clock;
3689 intel_edp_link_config(intel_encoder,
3692 /* DP over FDI requires target mode clock
3693 instead of link clock */
3695 target_clock = mode->clock;
3697 target_clock = adjusted_mode->clock;
3701 /* determine panel color depth */
3702 temp = I915_READ(pipeconf_reg);
3703 temp &= ~PIPE_BPC_MASK;
3705 int lvds_reg = I915_READ(PCH_LVDS);
3706 /* the BPC will be 6 if it is 18-bit LVDS panel */
3707 if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3711 } else if (is_edp || (is_dp && intel_pch_has_edp(crtc))) {
3712 switch (dev_priv->edp_bpp/3) {
3728 I915_WRITE(pipeconf_reg, temp);
3729 I915_READ(pipeconf_reg);
3731 switch (temp & PIPE_BPC_MASK) {
3745 DRM_ERROR("unknown pipe bpc value\n");
3751 * Account for spread spectrum to avoid
3752 * oversubscribing the link. Max center spread
3753 * is 2.5%; use 5% for safety's sake.
3755 u32 bps = target_clock * bpp * 21 / 20;
3756 lane = bps / (link_bw * 8) + 1;
3759 intel_crtc->fdi_lanes = lane;
3761 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3764 /* Ironlake: try to setup display ref clock before DPLL
3765 * enabling. This is only under driver's control after
3766 * PCH B stepping, previous chipset stepping should be
3767 * ignoring this setting.
3769 if (HAS_PCH_SPLIT(dev)) {
3770 temp = I915_READ(PCH_DREF_CONTROL);
3771 /* Always enable nonspread source */
3772 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3773 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3774 I915_WRITE(PCH_DREF_CONTROL, temp);
3775 POSTING_READ(PCH_DREF_CONTROL);
3777 temp &= ~DREF_SSC_SOURCE_MASK;
3778 temp |= DREF_SSC_SOURCE_ENABLE;
3779 I915_WRITE(PCH_DREF_CONTROL, temp);
3780 POSTING_READ(PCH_DREF_CONTROL);
3785 if (dev_priv->lvds_use_ssc) {
3786 temp |= DREF_SSC1_ENABLE;
3787 I915_WRITE(PCH_DREF_CONTROL, temp);
3788 POSTING_READ(PCH_DREF_CONTROL);
3792 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3793 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3794 I915_WRITE(PCH_DREF_CONTROL, temp);
3795 POSTING_READ(PCH_DREF_CONTROL);
3797 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3798 I915_WRITE(PCH_DREF_CONTROL, temp);
3799 POSTING_READ(PCH_DREF_CONTROL);
3804 if (IS_PINEVIEW(dev)) {
3805 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3806 if (has_reduced_clock)
3807 fp2 = (1 << reduced_clock.n) << 16 |
3808 reduced_clock.m1 << 8 | reduced_clock.m2;
3810 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3811 if (has_reduced_clock)
3812 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3816 if (!HAS_PCH_SPLIT(dev))
3817 dpll = DPLL_VGA_MODE_DIS;
3821 dpll |= DPLLB_MODE_LVDS;
3823 dpll |= DPLLB_MODE_DAC_SERIAL;
3825 dpll |= DPLL_DVO_HIGH_SPEED;
3826 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3827 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3828 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3829 else if (HAS_PCH_SPLIT(dev))
3830 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3833 dpll |= DPLL_DVO_HIGH_SPEED;
3835 /* compute bitmask from p1 value */
3836 if (IS_PINEVIEW(dev))
3837 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3839 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3841 if (HAS_PCH_SPLIT(dev))
3842 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3843 if (IS_G4X(dev) && has_reduced_clock)
3844 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3848 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3851 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3854 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3857 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3860 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3861 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3864 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3867 dpll |= PLL_P1_DIVIDE_BY_TWO;
3869 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3871 dpll |= PLL_P2_DIVIDE_BY_4;
3875 if (is_sdvo && is_tv)
3876 dpll |= PLL_REF_INPUT_TVCLKINBC;
3878 /* XXX: just matching BIOS for now */
3879 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3881 else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3882 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3884 dpll |= PLL_REF_INPUT_DREFCLK;
3886 /* setup pipeconf */
3887 pipeconf = I915_READ(pipeconf_reg);
3889 /* Set up the display plane register */
3890 dspcntr = DISPPLANE_GAMMA_ENABLE;
3892 /* Ironlake's plane is forced to pipe, bit 24 is to
3893 enable color space conversion */
3894 if (!HAS_PCH_SPLIT(dev)) {
3896 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3898 dspcntr |= DISPPLANE_SEL_PIPE_B;
3901 if (pipe == 0 && !IS_I965G(dev)) {
3902 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3905 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3909 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3910 pipeconf |= PIPEACONF_DOUBLE_WIDE;
3912 pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3915 dspcntr |= DISPLAY_PLANE_ENABLE;
3916 pipeconf |= PIPEACONF_ENABLE;
3917 dpll |= DPLL_VCO_ENABLE;
3920 /* Disable the panel fitter if it was on our pipe */
3921 if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
3922 I915_WRITE(PFIT_CONTROL, 0);
3924 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3925 drm_mode_debug_printmodeline(mode);
3927 /* assign to Ironlake registers */
3928 if (HAS_PCH_SPLIT(dev)) {
3929 fp_reg = pch_fp_reg;
3930 dpll_reg = pch_dpll_reg;
3934 ironlake_disable_pll_edp(crtc);
3935 } else if ((dpll & DPLL_VCO_ENABLE)) {
3936 I915_WRITE(fp_reg, fp);
3937 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3938 I915_READ(dpll_reg);
3942 /* enable transcoder DPLL */
3943 if (HAS_PCH_CPT(dev)) {
3944 temp = I915_READ(PCH_DPLL_SEL);
3945 if (trans_dpll_sel == 0)
3946 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3948 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3949 I915_WRITE(PCH_DPLL_SEL, temp);
3950 I915_READ(PCH_DPLL_SEL);
3954 if (HAS_PCH_SPLIT(dev)) {
3955 pipeconf &= ~PIPE_ENABLE_DITHER;
3956 pipeconf &= ~PIPE_DITHER_TYPE_MASK;
3959 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3960 * This is an exception to the general rule that mode_set doesn't turn
3966 if (HAS_PCH_SPLIT(dev))
3967 lvds_reg = PCH_LVDS;
3969 lvds = I915_READ(lvds_reg);
3970 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3972 if (HAS_PCH_CPT(dev))
3973 lvds |= PORT_TRANS_B_SEL_CPT;
3975 lvds |= LVDS_PIPEB_SELECT;
3977 if (HAS_PCH_CPT(dev))
3978 lvds &= ~PORT_TRANS_SEL_MASK;
3980 lvds &= ~LVDS_PIPEB_SELECT;
3982 /* set the corresponsding LVDS_BORDER bit */
3983 lvds |= dev_priv->lvds_border_bits;
3984 /* Set the B0-B3 data pairs corresponding to whether we're going to
3985 * set the DPLLs for dual-channel mode or not.
3988 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3990 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3992 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3993 * appropriately here, but we need to look more thoroughly into how
3994 * panels behave in the two modes.
3996 /* set the dithering flag */
3997 if (IS_I965G(dev)) {
3998 if (dev_priv->lvds_dither) {
3999 if (HAS_PCH_SPLIT(dev)) {
4000 pipeconf |= PIPE_ENABLE_DITHER;
4001 pipeconf |= PIPE_DITHER_TYPE_ST01;
4003 lvds |= LVDS_ENABLE_DITHER;
4005 if (!HAS_PCH_SPLIT(dev)) {
4006 lvds &= ~LVDS_ENABLE_DITHER;
4010 I915_WRITE(lvds_reg, lvds);
4011 I915_READ(lvds_reg);
4014 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4015 else if (HAS_PCH_SPLIT(dev)) {
4016 /* For non-DP output, clear any trans DP clock recovery setting.*/
4018 I915_WRITE(TRANSA_DATA_M1, 0);
4019 I915_WRITE(TRANSA_DATA_N1, 0);
4020 I915_WRITE(TRANSA_DP_LINK_M1, 0);
4021 I915_WRITE(TRANSA_DP_LINK_N1, 0);
4023 I915_WRITE(TRANSB_DATA_M1, 0);
4024 I915_WRITE(TRANSB_DATA_N1, 0);
4025 I915_WRITE(TRANSB_DP_LINK_M1, 0);
4026 I915_WRITE(TRANSB_DP_LINK_N1, 0);
4031 I915_WRITE(fp_reg, fp);
4032 I915_WRITE(dpll_reg, dpll);
4033 I915_READ(dpll_reg);
4034 /* Wait for the clocks to stabilize. */
4037 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
4039 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
4040 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
4041 ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
4043 I915_WRITE(dpll_md_reg, 0);
4045 /* write it again -- the BIOS does, after all */
4046 I915_WRITE(dpll_reg, dpll);
4048 I915_READ(dpll_reg);
4049 /* Wait for the clocks to stabilize. */
4053 if (is_lvds && has_reduced_clock && i915_powersave) {
4054 I915_WRITE(fp_reg + 4, fp2);
4055 intel_crtc->lowfreq_avail = true;
4056 if (HAS_PIPE_CXSR(dev)) {
4057 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4058 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4061 I915_WRITE(fp_reg + 4, fp);
4062 intel_crtc->lowfreq_avail = false;
4063 if (HAS_PIPE_CXSR(dev)) {
4064 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4065 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4069 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4070 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4071 /* the chip adds 2 halflines automatically */
4072 adjusted_mode->crtc_vdisplay -= 1;
4073 adjusted_mode->crtc_vtotal -= 1;
4074 adjusted_mode->crtc_vblank_start -= 1;
4075 adjusted_mode->crtc_vblank_end -= 1;
4076 adjusted_mode->crtc_vsync_end -= 1;
4077 adjusted_mode->crtc_vsync_start -= 1;
4079 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4081 I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
4082 ((adjusted_mode->crtc_htotal - 1) << 16));
4083 I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
4084 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4085 I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
4086 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4087 I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
4088 ((adjusted_mode->crtc_vtotal - 1) << 16));
4089 I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
4090 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4091 I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
4092 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4093 /* pipesrc and dspsize control the size that is scaled from, which should
4094 * always be the user's requested size.
4096 if (!HAS_PCH_SPLIT(dev)) {
4097 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
4098 (mode->hdisplay - 1));
4099 I915_WRITE(dsppos_reg, 0);
4101 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4103 if (HAS_PCH_SPLIT(dev)) {
4104 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
4105 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
4106 I915_WRITE(link_m1_reg, m_n.link_m);
4107 I915_WRITE(link_n1_reg, m_n.link_n);
4110 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4112 /* enable FDI RX PLL too */
4113 temp = I915_READ(fdi_rx_reg);
4114 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
4115 I915_READ(fdi_rx_reg);
4118 /* enable FDI TX PLL too */
4119 temp = I915_READ(fdi_tx_reg);
4120 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
4121 I915_READ(fdi_tx_reg);
4123 /* enable FDI RX PCDCLK */
4124 temp = I915_READ(fdi_rx_reg);
4125 I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
4126 I915_READ(fdi_rx_reg);
4131 I915_WRITE(pipeconf_reg, pipeconf);
4132 I915_READ(pipeconf_reg);
4134 intel_wait_for_vblank(dev);
4136 if (IS_IRONLAKE(dev)) {
4137 /* enable address swizzle for tiling buffer */
4138 temp = I915_READ(DISP_ARB_CTL);
4139 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4142 I915_WRITE(dspcntr_reg, dspcntr);
4144 /* Flush the plane changes */
4145 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4147 intel_update_watermarks(dev);
4149 drm_vblank_post_modeset(dev, pipe);
4154 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4155 void intel_crtc_load_lut(struct drm_crtc *crtc)
4157 struct drm_device *dev = crtc->dev;
4158 struct drm_i915_private *dev_priv = dev->dev_private;
4159 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4160 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4163 /* The clocks have to be on to load the palette. */
4167 /* use legacy palette for Ironlake */
4168 if (HAS_PCH_SPLIT(dev))
4169 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4172 for (i = 0; i < 256; i++) {
4173 I915_WRITE(palreg + 4 * i,
4174 (intel_crtc->lut_r[i] << 16) |
4175 (intel_crtc->lut_g[i] << 8) |
4176 intel_crtc->lut_b[i]);
4180 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4182 struct drm_device *dev = crtc->dev;
4183 struct drm_i915_private *dev_priv = dev->dev_private;
4184 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4185 bool visible = base != 0;
4188 if (intel_crtc->cursor_visible == visible)
4191 cntl = I915_READ(CURACNTR);
4193 /* On these chipsets we can only modify the base whilst
4194 * the cursor is disabled.
4196 I915_WRITE(CURABASE, base);
4198 cntl &= ~(CURSOR_FORMAT_MASK);
4199 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4200 cntl |= CURSOR_ENABLE |
4201 CURSOR_GAMMA_ENABLE |
4204 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4205 I915_WRITE(CURACNTR, cntl);
4207 intel_crtc->cursor_visible = visible;
4210 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4212 struct drm_device *dev = crtc->dev;
4213 struct drm_i915_private *dev_priv = dev->dev_private;
4214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4215 int pipe = intel_crtc->pipe;
4216 bool visible = base != 0;
4218 if (intel_crtc->cursor_visible != visible) {
4219 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4221 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4222 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4223 cntl |= pipe << 28; /* Connect to correct pipe */
4225 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4226 cntl |= CURSOR_MODE_DISABLE;
4228 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4230 intel_crtc->cursor_visible = visible;
4232 /* and commit changes on next vblank */
4233 I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4236 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4237 static void intel_crtc_update_cursor(struct drm_crtc *crtc)
4239 struct drm_device *dev = crtc->dev;
4240 struct drm_i915_private *dev_priv = dev->dev_private;
4241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4242 int pipe = intel_crtc->pipe;
4243 int x = intel_crtc->cursor_x;
4244 int y = intel_crtc->cursor_y;
4250 if (intel_crtc->cursor_on && crtc->fb) {
4251 base = intel_crtc->cursor_addr;
4252 if (x > (int) crtc->fb->width)
4255 if (y > (int) crtc->fb->height)
4261 if (x + intel_crtc->cursor_width < 0)
4264 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4267 pos |= x << CURSOR_X_SHIFT;
4270 if (y + intel_crtc->cursor_height < 0)
4273 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4276 pos |= y << CURSOR_Y_SHIFT;
4278 visible = base != 0;
4279 if (!visible && !intel_crtc->cursor_visible)
4282 I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4283 if (IS_845G(dev) || IS_I865G(dev))
4284 i845_update_cursor(crtc, base);
4286 i9xx_update_cursor(crtc, base);
4289 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4292 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4293 struct drm_file *file_priv,
4295 uint32_t width, uint32_t height)
4297 struct drm_device *dev = crtc->dev;
4298 struct drm_i915_private *dev_priv = dev->dev_private;
4299 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4300 struct drm_gem_object *bo;
4301 struct drm_i915_gem_object *obj_priv;
4305 DRM_DEBUG_KMS("\n");
4307 /* if we want to turn off the cursor ignore width and height */
4309 DRM_DEBUG_KMS("cursor off\n");
4312 mutex_lock(&dev->struct_mutex);
4316 /* Currently we only support 64x64 cursors */
4317 if (width != 64 || height != 64) {
4318 DRM_ERROR("we currently only support 64x64 cursors\n");
4322 bo = drm_gem_object_lookup(dev, file_priv, handle);
4326 obj_priv = to_intel_bo(bo);
4328 if (bo->size < width * height * 4) {
4329 DRM_ERROR("buffer is to small\n");
4334 /* we only need to pin inside GTT if cursor is non-phy */
4335 mutex_lock(&dev->struct_mutex);
4336 if (!dev_priv->info->cursor_needs_physical) {
4337 ret = i915_gem_object_pin(bo, PAGE_SIZE);
4339 DRM_ERROR("failed to pin cursor bo\n");
4343 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4345 DRM_ERROR("failed to move cursor bo into the GTT\n");
4349 addr = obj_priv->gtt_offset;
4351 int align = IS_I830(dev) ? 16 * 1024 : 256;
4352 ret = i915_gem_attach_phys_object(dev, bo,
4353 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4356 DRM_ERROR("failed to attach phys object\n");
4359 addr = obj_priv->phys_obj->handle->busaddr;
4363 I915_WRITE(CURSIZE, (height << 12) | width);
4366 if (intel_crtc->cursor_bo) {
4367 if (dev_priv->info->cursor_needs_physical) {
4368 if (intel_crtc->cursor_bo != bo)
4369 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4371 i915_gem_object_unpin(intel_crtc->cursor_bo);
4372 drm_gem_object_unreference(intel_crtc->cursor_bo);
4375 mutex_unlock(&dev->struct_mutex);
4377 intel_crtc->cursor_addr = addr;
4378 intel_crtc->cursor_bo = bo;
4379 intel_crtc->cursor_width = width;
4380 intel_crtc->cursor_height = height;
4382 intel_crtc_update_cursor(crtc);
4386 i915_gem_object_unpin(bo);
4388 mutex_unlock(&dev->struct_mutex);
4390 drm_gem_object_unreference_unlocked(bo);
4394 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4396 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4398 intel_crtc->cursor_x = x;
4399 intel_crtc->cursor_y = y;
4401 intel_crtc_update_cursor(crtc);
4406 /** Sets the color ramps on behalf of RandR */
4407 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4408 u16 blue, int regno)
4410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4412 intel_crtc->lut_r[regno] = red >> 8;
4413 intel_crtc->lut_g[regno] = green >> 8;
4414 intel_crtc->lut_b[regno] = blue >> 8;
4417 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4418 u16 *blue, int regno)
4420 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4422 *red = intel_crtc->lut_r[regno] << 8;
4423 *green = intel_crtc->lut_g[regno] << 8;
4424 *blue = intel_crtc->lut_b[regno] << 8;
4427 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4428 u16 *blue, uint32_t size)
4430 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4436 for (i = 0; i < 256; i++) {
4437 intel_crtc->lut_r[i] = red[i] >> 8;
4438 intel_crtc->lut_g[i] = green[i] >> 8;
4439 intel_crtc->lut_b[i] = blue[i] >> 8;
4442 intel_crtc_load_lut(crtc);
4446 * Get a pipe with a simple mode set on it for doing load-based monitor
4449 * It will be up to the load-detect code to adjust the pipe as appropriate for
4450 * its requirements. The pipe will be connected to no other encoders.
4452 * Currently this code will only succeed if there is a pipe with no encoders
4453 * configured for it. In the future, it could choose to temporarily disable
4454 * some outputs to free up a pipe for its use.
4456 * \return crtc, or NULL if no pipes are available.
4459 /* VESA 640x480x72Hz mode to set on the pipe */
4460 static struct drm_display_mode load_detect_mode = {
4461 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4462 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4465 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4466 struct drm_connector *connector,
4467 struct drm_display_mode *mode,
4470 struct intel_crtc *intel_crtc;
4471 struct drm_crtc *possible_crtc;
4472 struct drm_crtc *supported_crtc =NULL;
4473 struct drm_encoder *encoder = &intel_encoder->enc;
4474 struct drm_crtc *crtc = NULL;
4475 struct drm_device *dev = encoder->dev;
4476 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4477 struct drm_crtc_helper_funcs *crtc_funcs;
4481 * Algorithm gets a little messy:
4482 * - if the connector already has an assigned crtc, use it (but make
4483 * sure it's on first)
4484 * - try to find the first unused crtc that can drive this connector,
4485 * and use that if we find one
4486 * - if there are no unused crtcs available, try to use the first
4487 * one we found that supports the connector
4490 /* See if we already have a CRTC for this connector */
4491 if (encoder->crtc) {
4492 crtc = encoder->crtc;
4493 /* Make sure the crtc and connector are running */
4494 intel_crtc = to_intel_crtc(crtc);
4495 *dpms_mode = intel_crtc->dpms_mode;
4496 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4497 crtc_funcs = crtc->helper_private;
4498 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4499 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4504 /* Find an unused one (if possible) */
4505 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4507 if (!(encoder->possible_crtcs & (1 << i)))
4509 if (!possible_crtc->enabled) {
4510 crtc = possible_crtc;
4513 if (!supported_crtc)
4514 supported_crtc = possible_crtc;
4518 * If we didn't find an unused CRTC, don't use any.
4524 encoder->crtc = crtc;
4525 connector->encoder = encoder;
4526 intel_encoder->load_detect_temp = true;
4528 intel_crtc = to_intel_crtc(crtc);
4529 *dpms_mode = intel_crtc->dpms_mode;
4531 if (!crtc->enabled) {
4533 mode = &load_detect_mode;
4534 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4536 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4537 crtc_funcs = crtc->helper_private;
4538 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4541 /* Add this connector to the crtc */
4542 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4543 encoder_funcs->commit(encoder);
4545 /* let the connector get through one full cycle before testing */
4546 intel_wait_for_vblank(dev);
4551 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4552 struct drm_connector *connector, int dpms_mode)
4554 struct drm_encoder *encoder = &intel_encoder->enc;
4555 struct drm_device *dev = encoder->dev;
4556 struct drm_crtc *crtc = encoder->crtc;
4557 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4558 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4560 if (intel_encoder->load_detect_temp) {
4561 encoder->crtc = NULL;
4562 connector->encoder = NULL;
4563 intel_encoder->load_detect_temp = false;
4564 crtc->enabled = drm_helper_crtc_in_use(crtc);
4565 drm_helper_disable_unused_functions(dev);
4568 /* Switch crtc and encoder back off if necessary */
4569 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4570 if (encoder->crtc == crtc)
4571 encoder_funcs->dpms(encoder, dpms_mode);
4572 crtc_funcs->dpms(crtc, dpms_mode);
4576 /* Returns the clock of the currently programmed mode of the given pipe. */
4577 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4579 struct drm_i915_private *dev_priv = dev->dev_private;
4580 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4581 int pipe = intel_crtc->pipe;
4582 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4584 intel_clock_t clock;
4586 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4587 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4589 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4591 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4592 if (IS_PINEVIEW(dev)) {
4593 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4594 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4596 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4597 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4601 if (IS_PINEVIEW(dev))
4602 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4603 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4605 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4606 DPLL_FPA01_P1_POST_DIV_SHIFT);
4608 switch (dpll & DPLL_MODE_MASK) {
4609 case DPLLB_MODE_DAC_SERIAL:
4610 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4613 case DPLLB_MODE_LVDS:
4614 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4618 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4619 "mode\n", (int)(dpll & DPLL_MODE_MASK));
4623 /* XXX: Handle the 100Mhz refclk */
4624 intel_clock(dev, 96000, &clock);
4626 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4629 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4630 DPLL_FPA01_P1_POST_DIV_SHIFT);
4633 if ((dpll & PLL_REF_INPUT_MASK) ==
4634 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4635 /* XXX: might not be 66MHz */
4636 intel_clock(dev, 66000, &clock);
4638 intel_clock(dev, 48000, &clock);
4640 if (dpll & PLL_P1_DIVIDE_BY_TWO)
4643 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4644 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4646 if (dpll & PLL_P2_DIVIDE_BY_4)
4651 intel_clock(dev, 48000, &clock);
4655 /* XXX: It would be nice to validate the clocks, but we can't reuse
4656 * i830PllIsValid() because it relies on the xf86_config connector
4657 * configuration being accurate, which it isn't necessarily.
4663 /** Returns the currently programmed mode of the given pipe. */
4664 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4665 struct drm_crtc *crtc)
4667 struct drm_i915_private *dev_priv = dev->dev_private;
4668 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4669 int pipe = intel_crtc->pipe;
4670 struct drm_display_mode *mode;
4671 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4672 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4673 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4674 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4676 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4680 mode->clock = intel_crtc_clock_get(dev, crtc);
4681 mode->hdisplay = (htot & 0xffff) + 1;
4682 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4683 mode->hsync_start = (hsync & 0xffff) + 1;
4684 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4685 mode->vdisplay = (vtot & 0xffff) + 1;
4686 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4687 mode->vsync_start = (vsync & 0xffff) + 1;
4688 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4690 drm_mode_set_name(mode);
4691 drm_mode_set_crtcinfo(mode, 0);
4696 #define GPU_IDLE_TIMEOUT 500 /* ms */
4698 /* When this timer fires, we've been idle for awhile */
4699 static void intel_gpu_idle_timer(unsigned long arg)
4701 struct drm_device *dev = (struct drm_device *)arg;
4702 drm_i915_private_t *dev_priv = dev->dev_private;
4704 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4706 dev_priv->busy = false;
4708 queue_work(dev_priv->wq, &dev_priv->idle_work);
4711 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4713 static void intel_crtc_idle_timer(unsigned long arg)
4715 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4716 struct drm_crtc *crtc = &intel_crtc->base;
4717 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4719 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4721 intel_crtc->busy = false;
4723 queue_work(dev_priv->wq, &dev_priv->idle_work);
4726 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
4728 struct drm_device *dev = crtc->dev;
4729 drm_i915_private_t *dev_priv = dev->dev_private;
4730 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4731 int pipe = intel_crtc->pipe;
4732 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4733 int dpll = I915_READ(dpll_reg);
4735 if (HAS_PCH_SPLIT(dev))
4738 if (!dev_priv->lvds_downclock_avail)
4741 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4742 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4744 /* Unlock panel regs */
4745 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4748 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4749 I915_WRITE(dpll_reg, dpll);
4750 dpll = I915_READ(dpll_reg);
4751 intel_wait_for_vblank(dev);
4752 dpll = I915_READ(dpll_reg);
4753 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4754 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4756 /* ...and lock them again */
4757 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4760 /* Schedule downclock */
4762 mod_timer(&intel_crtc->idle_timer, jiffies +
4763 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4766 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4768 struct drm_device *dev = crtc->dev;
4769 drm_i915_private_t *dev_priv = dev->dev_private;
4770 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4771 int pipe = intel_crtc->pipe;
4772 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4773 int dpll = I915_READ(dpll_reg);
4775 if (HAS_PCH_SPLIT(dev))
4778 if (!dev_priv->lvds_downclock_avail)
4782 * Since this is called by a timer, we should never get here in
4785 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4786 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4788 /* Unlock panel regs */
4789 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4792 dpll |= DISPLAY_RATE_SELECT_FPA1;
4793 I915_WRITE(dpll_reg, dpll);
4794 dpll = I915_READ(dpll_reg);
4795 intel_wait_for_vblank(dev);
4796 dpll = I915_READ(dpll_reg);
4797 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4798 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4800 /* ...and lock them again */
4801 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4807 * intel_idle_update - adjust clocks for idleness
4808 * @work: work struct
4810 * Either the GPU or display (or both) went idle. Check the busy status
4811 * here and adjust the CRTC and GPU clocks as necessary.
4813 static void intel_idle_update(struct work_struct *work)
4815 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4817 struct drm_device *dev = dev_priv->dev;
4818 struct drm_crtc *crtc;
4819 struct intel_crtc *intel_crtc;
4822 if (!i915_powersave)
4825 mutex_lock(&dev->struct_mutex);
4827 i915_update_gfx_val(dev_priv);
4829 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4830 /* Skip inactive CRTCs */
4835 intel_crtc = to_intel_crtc(crtc);
4836 if (!intel_crtc->busy)
4837 intel_decrease_pllclock(crtc);
4840 if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4841 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4842 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4845 mutex_unlock(&dev->struct_mutex);
4849 * intel_mark_busy - mark the GPU and possibly the display busy
4851 * @obj: object we're operating on
4853 * Callers can use this function to indicate that the GPU is busy processing
4854 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
4855 * buffer), we'll also mark the display as busy, so we know to increase its
4858 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4860 drm_i915_private_t *dev_priv = dev->dev_private;
4861 struct drm_crtc *crtc = NULL;
4862 struct intel_framebuffer *intel_fb;
4863 struct intel_crtc *intel_crtc;
4865 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4868 if (!dev_priv->busy) {
4869 if (IS_I945G(dev) || IS_I945GM(dev)) {
4872 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4873 fw_blc_self = I915_READ(FW_BLC_SELF);
4874 fw_blc_self &= ~FW_BLC_SELF_EN;
4875 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4877 dev_priv->busy = true;
4879 mod_timer(&dev_priv->idle_timer, jiffies +
4880 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4882 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4886 intel_crtc = to_intel_crtc(crtc);
4887 intel_fb = to_intel_framebuffer(crtc->fb);
4888 if (intel_fb->obj == obj) {
4889 if (!intel_crtc->busy) {
4890 if (IS_I945G(dev) || IS_I945GM(dev)) {
4893 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4894 fw_blc_self = I915_READ(FW_BLC_SELF);
4895 fw_blc_self &= ~FW_BLC_SELF_EN;
4896 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4898 /* Non-busy -> busy, upclock */
4899 intel_increase_pllclock(crtc, true);
4900 intel_crtc->busy = true;
4902 /* Busy -> busy, put off timer */
4903 mod_timer(&intel_crtc->idle_timer, jiffies +
4904 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4910 static void intel_crtc_destroy(struct drm_crtc *crtc)
4912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4914 drm_crtc_cleanup(crtc);
4918 struct intel_unpin_work {
4919 struct work_struct work;
4920 struct drm_device *dev;
4921 struct drm_gem_object *old_fb_obj;
4922 struct drm_gem_object *pending_flip_obj;
4923 struct drm_pending_vblank_event *event;
4927 static void intel_unpin_work_fn(struct work_struct *__work)
4929 struct intel_unpin_work *work =
4930 container_of(__work, struct intel_unpin_work, work);
4932 mutex_lock(&work->dev->struct_mutex);
4933 i915_gem_object_unpin(work->old_fb_obj);
4934 drm_gem_object_unreference(work->pending_flip_obj);
4935 drm_gem_object_unreference(work->old_fb_obj);
4936 mutex_unlock(&work->dev->struct_mutex);
4940 static void do_intel_finish_page_flip(struct drm_device *dev,
4941 struct drm_crtc *crtc)
4943 drm_i915_private_t *dev_priv = dev->dev_private;
4944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4945 struct intel_unpin_work *work;
4946 struct drm_i915_gem_object *obj_priv;
4947 struct drm_pending_vblank_event *e;
4949 unsigned long flags;
4951 /* Ignore early vblank irqs */
4952 if (intel_crtc == NULL)
4955 spin_lock_irqsave(&dev->event_lock, flags);
4956 work = intel_crtc->unpin_work;
4957 if (work == NULL || !work->pending) {
4958 spin_unlock_irqrestore(&dev->event_lock, flags);
4962 intel_crtc->unpin_work = NULL;
4963 drm_vblank_put(dev, intel_crtc->pipe);
4967 do_gettimeofday(&now);
4968 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4969 e->event.tv_sec = now.tv_sec;
4970 e->event.tv_usec = now.tv_usec;
4971 list_add_tail(&e->base.link,
4972 &e->base.file_priv->event_list);
4973 wake_up_interruptible(&e->base.file_priv->event_wait);
4976 spin_unlock_irqrestore(&dev->event_lock, flags);
4978 obj_priv = to_intel_bo(work->pending_flip_obj);
4980 /* Initial scanout buffer will have a 0 pending flip count */
4981 if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4982 atomic_dec_and_test(&obj_priv->pending_flip))
4983 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4984 schedule_work(&work->work);
4986 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
4989 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4991 drm_i915_private_t *dev_priv = dev->dev_private;
4992 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4994 do_intel_finish_page_flip(dev, crtc);
4997 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
4999 drm_i915_private_t *dev_priv = dev->dev_private;
5000 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5002 do_intel_finish_page_flip(dev, crtc);
5005 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5007 drm_i915_private_t *dev_priv = dev->dev_private;
5008 struct intel_crtc *intel_crtc =
5009 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5010 unsigned long flags;
5012 spin_lock_irqsave(&dev->event_lock, flags);
5013 if (intel_crtc->unpin_work) {
5014 intel_crtc->unpin_work->pending = 1;
5016 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5018 spin_unlock_irqrestore(&dev->event_lock, flags);
5021 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5022 struct drm_framebuffer *fb,
5023 struct drm_pending_vblank_event *event)
5025 struct drm_device *dev = crtc->dev;
5026 struct drm_i915_private *dev_priv = dev->dev_private;
5027 struct intel_framebuffer *intel_fb;
5028 struct drm_i915_gem_object *obj_priv;
5029 struct drm_gem_object *obj;
5030 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5031 struct intel_unpin_work *work;
5032 unsigned long flags, offset;
5033 int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
5037 work = kzalloc(sizeof *work, GFP_KERNEL);
5041 work->event = event;
5042 work->dev = crtc->dev;
5043 intel_fb = to_intel_framebuffer(crtc->fb);
5044 work->old_fb_obj = intel_fb->obj;
5045 INIT_WORK(&work->work, intel_unpin_work_fn);
5047 /* We borrow the event spin lock for protecting unpin_work */
5048 spin_lock_irqsave(&dev->event_lock, flags);
5049 if (intel_crtc->unpin_work) {
5050 spin_unlock_irqrestore(&dev->event_lock, flags);
5053 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5056 intel_crtc->unpin_work = work;
5057 spin_unlock_irqrestore(&dev->event_lock, flags);
5059 intel_fb = to_intel_framebuffer(fb);
5060 obj = intel_fb->obj;
5062 mutex_lock(&dev->struct_mutex);
5063 ret = intel_pin_and_fence_fb_obj(dev, obj);
5067 /* Reference the objects for the scheduled work. */
5068 drm_gem_object_reference(work->old_fb_obj);
5069 drm_gem_object_reference(obj);
5072 ret = i915_gem_object_flush_write_domain(obj);
5076 ret = drm_vblank_get(dev, intel_crtc->pipe);
5080 obj_priv = to_intel_bo(obj);
5081 atomic_inc(&obj_priv->pending_flip);
5082 work->pending_flip_obj = obj;
5084 if (intel_crtc->plane)
5085 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5087 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5089 if (IS_GEN3(dev) || IS_GEN2(dev)) {
5091 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5096 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5097 offset = obj_priv->gtt_offset;
5098 offset += (crtc->y * fb->pitch) + (crtc->x * (fb->bits_per_pixel) / 8);
5101 if (IS_I965G(dev)) {
5102 OUT_RING(MI_DISPLAY_FLIP |
5103 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5104 OUT_RING(fb->pitch);
5105 OUT_RING(offset | obj_priv->tiling_mode);
5106 pipesrc = I915_READ(pipesrc_reg);
5107 OUT_RING(pipesrc & 0x0fff0fff);
5108 } else if (IS_GEN3(dev)) {
5109 OUT_RING(MI_DISPLAY_FLIP_I915 |
5110 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5111 OUT_RING(fb->pitch);
5115 OUT_RING(MI_DISPLAY_FLIP |
5116 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5117 OUT_RING(fb->pitch);
5123 mutex_unlock(&dev->struct_mutex);
5125 trace_i915_flip_request(intel_crtc->plane, obj);
5130 drm_gem_object_unreference(work->old_fb_obj);
5131 drm_gem_object_unreference(obj);
5133 mutex_unlock(&dev->struct_mutex);
5135 spin_lock_irqsave(&dev->event_lock, flags);
5136 intel_crtc->unpin_work = NULL;
5137 spin_unlock_irqrestore(&dev->event_lock, flags);
5144 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
5145 .dpms = intel_crtc_dpms,
5146 .mode_fixup = intel_crtc_mode_fixup,
5147 .mode_set = intel_crtc_mode_set,
5148 .mode_set_base = intel_pipe_set_base,
5149 .mode_set_base_atomic = intel_pipe_set_base_atomic,
5150 .prepare = intel_crtc_prepare,
5151 .commit = intel_crtc_commit,
5152 .load_lut = intel_crtc_load_lut,
5155 static const struct drm_crtc_funcs intel_crtc_funcs = {
5156 .cursor_set = intel_crtc_cursor_set,
5157 .cursor_move = intel_crtc_cursor_move,
5158 .gamma_set = intel_crtc_gamma_set,
5159 .set_config = drm_crtc_helper_set_config,
5160 .destroy = intel_crtc_destroy,
5161 .page_flip = intel_crtc_page_flip,
5165 static void intel_crtc_init(struct drm_device *dev, int pipe)
5167 drm_i915_private_t *dev_priv = dev->dev_private;
5168 struct intel_crtc *intel_crtc;
5171 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5172 if (intel_crtc == NULL)
5175 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5177 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5178 intel_crtc->pipe = pipe;
5179 intel_crtc->plane = pipe;
5180 for (i = 0; i < 256; i++) {
5181 intel_crtc->lut_r[i] = i;
5182 intel_crtc->lut_g[i] = i;
5183 intel_crtc->lut_b[i] = i;
5186 /* Swap pipes & planes for FBC on pre-965 */
5187 intel_crtc->pipe = pipe;
5188 intel_crtc->plane = pipe;
5189 if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
5190 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5191 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
5194 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5195 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5196 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5197 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5199 intel_crtc->cursor_addr = 0;
5200 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
5201 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5203 intel_crtc->busy = false;
5205 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5206 (unsigned long)intel_crtc);
5209 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5210 struct drm_file *file_priv)
5212 drm_i915_private_t *dev_priv = dev->dev_private;
5213 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5214 struct drm_mode_object *drmmode_obj;
5215 struct intel_crtc *crtc;
5218 DRM_ERROR("called with no initialization\n");
5222 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5223 DRM_MODE_OBJECT_CRTC);
5226 DRM_ERROR("no such CRTC id\n");
5230 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5231 pipe_from_crtc_id->pipe = crtc->pipe;
5236 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
5238 struct drm_crtc *crtc = NULL;
5240 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5242 if (intel_crtc->pipe == pipe)
5248 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5251 struct drm_encoder *encoder;
5254 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5255 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5256 if (type_mask & intel_encoder->clone_mask)
5257 index_mask |= (1 << entry);
5264 static void intel_setup_outputs(struct drm_device *dev)
5266 struct drm_i915_private *dev_priv = dev->dev_private;
5267 struct drm_encoder *encoder;
5268 bool dpd_is_edp = false;
5270 if (IS_MOBILE(dev) && !IS_I830(dev))
5271 intel_lvds_init(dev);
5273 if (HAS_PCH_SPLIT(dev)) {
5274 dpd_is_edp = intel_dpd_is_edp(dev);
5276 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5277 intel_dp_init(dev, DP_A);
5279 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5280 intel_dp_init(dev, PCH_DP_D);
5283 intel_crt_init(dev);
5285 if (HAS_PCH_SPLIT(dev)) {
5288 if (I915_READ(HDMIB) & PORT_DETECTED) {
5289 /* PCH SDVOB multiplex with HDMIB */
5290 found = intel_sdvo_init(dev, PCH_SDVOB);
5292 intel_hdmi_init(dev, HDMIB);
5293 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5294 intel_dp_init(dev, PCH_DP_B);
5297 if (I915_READ(HDMIC) & PORT_DETECTED)
5298 intel_hdmi_init(dev, HDMIC);
5300 if (I915_READ(HDMID) & PORT_DETECTED)
5301 intel_hdmi_init(dev, HDMID);
5303 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5304 intel_dp_init(dev, PCH_DP_C);
5306 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5307 intel_dp_init(dev, PCH_DP_D);
5309 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5312 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5313 DRM_DEBUG_KMS("probing SDVOB\n");
5314 found = intel_sdvo_init(dev, SDVOB);
5315 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5316 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5317 intel_hdmi_init(dev, SDVOB);
5320 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5321 DRM_DEBUG_KMS("probing DP_B\n");
5322 intel_dp_init(dev, DP_B);
5326 /* Before G4X SDVOC doesn't have its own detect register */
5328 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5329 DRM_DEBUG_KMS("probing SDVOC\n");
5330 found = intel_sdvo_init(dev, SDVOC);
5333 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5335 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5336 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5337 intel_hdmi_init(dev, SDVOC);
5339 if (SUPPORTS_INTEGRATED_DP(dev)) {
5340 DRM_DEBUG_KMS("probing DP_C\n");
5341 intel_dp_init(dev, DP_C);
5345 if (SUPPORTS_INTEGRATED_DP(dev) &&
5346 (I915_READ(DP_D) & DP_DETECTED)) {
5347 DRM_DEBUG_KMS("probing DP_D\n");
5348 intel_dp_init(dev, DP_D);
5350 } else if (IS_GEN2(dev))
5351 intel_dvo_init(dev);
5353 if (SUPPORTS_TV(dev))
5356 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5357 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5359 encoder->possible_crtcs = intel_encoder->crtc_mask;
5360 encoder->possible_clones = intel_encoder_clones(dev,
5361 intel_encoder->clone_mask);
5365 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5367 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5369 drm_framebuffer_cleanup(fb);
5370 drm_gem_object_unreference_unlocked(intel_fb->obj);
5375 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5376 struct drm_file *file_priv,
5377 unsigned int *handle)
5379 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5380 struct drm_gem_object *object = intel_fb->obj;
5382 return drm_gem_handle_create(file_priv, object, handle);
5385 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5386 .destroy = intel_user_framebuffer_destroy,
5387 .create_handle = intel_user_framebuffer_create_handle,
5390 int intel_framebuffer_init(struct drm_device *dev,
5391 struct intel_framebuffer *intel_fb,
5392 struct drm_mode_fb_cmd *mode_cmd,
5393 struct drm_gem_object *obj)
5397 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5399 DRM_ERROR("framebuffer init failed %d\n", ret);
5403 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5404 intel_fb->obj = obj;
5408 static struct drm_framebuffer *
5409 intel_user_framebuffer_create(struct drm_device *dev,
5410 struct drm_file *filp,
5411 struct drm_mode_fb_cmd *mode_cmd)
5413 struct drm_gem_object *obj;
5414 struct intel_framebuffer *intel_fb;
5417 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5421 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5425 ret = intel_framebuffer_init(dev, intel_fb,
5428 drm_gem_object_unreference_unlocked(obj);
5433 return &intel_fb->base;
5436 static const struct drm_mode_config_funcs intel_mode_funcs = {
5437 .fb_create = intel_user_framebuffer_create,
5438 .output_poll_changed = intel_fb_output_poll_changed,
5441 static struct drm_gem_object *
5442 intel_alloc_context_page(struct drm_device *dev)
5444 struct drm_gem_object *ctx;
5447 ctx = i915_gem_alloc_object(dev, 4096);
5449 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5453 mutex_lock(&dev->struct_mutex);
5454 ret = i915_gem_object_pin(ctx, 4096);
5456 DRM_ERROR("failed to pin power context: %d\n", ret);
5460 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
5462 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5465 mutex_unlock(&dev->struct_mutex);
5470 i915_gem_object_unpin(ctx);
5472 drm_gem_object_unreference(ctx);
5473 mutex_unlock(&dev->struct_mutex);
5477 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5479 struct drm_i915_private *dev_priv = dev->dev_private;
5482 rgvswctl = I915_READ16(MEMSWCTL);
5483 if (rgvswctl & MEMCTL_CMD_STS) {
5484 DRM_DEBUG("gpu busy, RCS change rejected\n");
5485 return false; /* still busy with another command */
5488 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5489 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5490 I915_WRITE16(MEMSWCTL, rgvswctl);
5491 POSTING_READ16(MEMSWCTL);
5493 rgvswctl |= MEMCTL_CMD_STS;
5494 I915_WRITE16(MEMSWCTL, rgvswctl);
5499 void ironlake_enable_drps(struct drm_device *dev)
5501 struct drm_i915_private *dev_priv = dev->dev_private;
5502 u32 rgvmodectl = I915_READ(MEMMODECTL);
5503 u8 fmax, fmin, fstart, vstart;
5505 /* 100ms RC evaluation intervals */
5506 I915_WRITE(RCUPEI, 100000);
5507 I915_WRITE(RCDNEI, 100000);
5509 /* Set max/min thresholds to 90ms and 80ms respectively */
5510 I915_WRITE(RCBMAXAVG, 90000);
5511 I915_WRITE(RCBMINAVG, 80000);
5513 I915_WRITE(MEMIHYST, 1);
5515 /* Set up min, max, and cur for interrupt handling */
5516 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5517 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5518 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5519 MEMMODE_FSTART_SHIFT;
5522 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5525 dev_priv->fmax = fstart; /* IPS callback will increase this */
5526 dev_priv->fstart = fstart;
5528 dev_priv->max_delay = fmax;
5529 dev_priv->min_delay = fmin;
5530 dev_priv->cur_delay = fstart;
5532 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5535 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5538 * Interrupts will be enabled in ironlake_irq_postinstall
5541 I915_WRITE(VIDSTART, vstart);
5542 POSTING_READ(VIDSTART);
5544 rgvmodectl |= MEMMODE_SWMODE_EN;
5545 I915_WRITE(MEMMODECTL, rgvmodectl);
5547 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 1, 0))
5548 DRM_ERROR("stuck trying to change perf mode\n");
5551 ironlake_set_drps(dev, fstart);
5553 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5555 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5556 dev_priv->last_count2 = I915_READ(0x112f4);
5557 getrawmonotonic(&dev_priv->last_time2);
5560 void ironlake_disable_drps(struct drm_device *dev)
5562 struct drm_i915_private *dev_priv = dev->dev_private;
5563 u16 rgvswctl = I915_READ16(MEMSWCTL);
5565 /* Ack interrupts, disable EFC interrupt */
5566 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5567 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5568 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5569 I915_WRITE(DEIIR, DE_PCU_EVENT);
5570 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5572 /* Go back to the starting frequency */
5573 ironlake_set_drps(dev, dev_priv->fstart);
5575 rgvswctl |= MEMCTL_CMD_STS;
5576 I915_WRITE(MEMSWCTL, rgvswctl);
5581 static unsigned long intel_pxfreq(u32 vidfreq)
5584 int div = (vidfreq & 0x3f0000) >> 16;
5585 int post = (vidfreq & 0x3000) >> 12;
5586 int pre = (vidfreq & 0x7);
5591 freq = ((div * 133333) / ((1<<post) * pre));
5596 void intel_init_emon(struct drm_device *dev)
5598 struct drm_i915_private *dev_priv = dev->dev_private;
5603 /* Disable to program */
5607 /* Program energy weights for various events */
5608 I915_WRITE(SDEW, 0x15040d00);
5609 I915_WRITE(CSIEW0, 0x007f0000);
5610 I915_WRITE(CSIEW1, 0x1e220004);
5611 I915_WRITE(CSIEW2, 0x04000004);
5613 for (i = 0; i < 5; i++)
5614 I915_WRITE(PEW + (i * 4), 0);
5615 for (i = 0; i < 3; i++)
5616 I915_WRITE(DEW + (i * 4), 0);
5618 /* Program P-state weights to account for frequency power adjustment */
5619 for (i = 0; i < 16; i++) {
5620 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5621 unsigned long freq = intel_pxfreq(pxvidfreq);
5622 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5627 val *= (freq / 1000);
5629 val /= (127*127*900);
5631 DRM_ERROR("bad pxval: %ld\n", val);
5634 /* Render standby states get 0 weight */
5638 for (i = 0; i < 4; i++) {
5639 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5640 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5641 I915_WRITE(PXW + (i * 4), val);
5644 /* Adjust magic regs to magic values (more experimental results) */
5645 I915_WRITE(OGW0, 0);
5646 I915_WRITE(OGW1, 0);
5647 I915_WRITE(EG0, 0x00007f00);
5648 I915_WRITE(EG1, 0x0000000e);
5649 I915_WRITE(EG2, 0x000e0000);
5650 I915_WRITE(EG3, 0x68000300);
5651 I915_WRITE(EG4, 0x42000000);
5652 I915_WRITE(EG5, 0x00140031);
5656 for (i = 0; i < 8; i++)
5657 I915_WRITE(PXWL + (i * 4), 0);
5659 /* Enable PMON + select events */
5660 I915_WRITE(ECR, 0x80000019);
5662 lcfuse = I915_READ(LCFUSE02);
5664 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5667 void intel_init_clock_gating(struct drm_device *dev)
5669 struct drm_i915_private *dev_priv = dev->dev_private;
5672 * Disable clock gating reported to work incorrectly according to the
5673 * specs, but enable as much else as we can.
5675 if (HAS_PCH_SPLIT(dev)) {
5676 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5678 if (IS_IRONLAKE(dev)) {
5679 /* Required for FBC */
5680 dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5681 /* Required for CxSR */
5682 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5684 I915_WRITE(PCH_3DCGDIS0,
5685 MARIUNIT_CLOCK_GATE_DISABLE |
5686 SVSMUNIT_CLOCK_GATE_DISABLE);
5689 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5692 * According to the spec the following bits should be set in
5693 * order to enable memory self-refresh
5694 * The bit 22/21 of 0x42004
5695 * The bit 5 of 0x42020
5696 * The bit 15 of 0x45000
5698 if (IS_IRONLAKE(dev)) {
5699 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5700 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5701 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5702 I915_WRITE(ILK_DSPCLK_GATE,
5703 (I915_READ(ILK_DSPCLK_GATE) |
5704 ILK_DPARB_CLK_GATE));
5705 I915_WRITE(DISP_ARB_CTL,
5706 (I915_READ(DISP_ARB_CTL) |
5710 * Based on the document from hardware guys the following bits
5711 * should be set unconditionally in order to enable FBC.
5712 * The bit 22 of 0x42000
5713 * The bit 22 of 0x42004
5714 * The bit 7,8,9 of 0x42020.
5716 if (IS_IRONLAKE_M(dev)) {
5717 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5718 I915_READ(ILK_DISPLAY_CHICKEN1) |
5720 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5721 I915_READ(ILK_DISPLAY_CHICKEN2) |
5723 I915_WRITE(ILK_DSPCLK_GATE,
5724 I915_READ(ILK_DSPCLK_GATE) |
5731 } else if (IS_G4X(dev)) {
5732 uint32_t dspclk_gate;
5733 I915_WRITE(RENCLK_GATE_D1, 0);
5734 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5735 GS_UNIT_CLOCK_GATE_DISABLE |
5736 CL_UNIT_CLOCK_GATE_DISABLE);
5737 I915_WRITE(RAMCLK_GATE_D, 0);
5738 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5739 OVRUNIT_CLOCK_GATE_DISABLE |
5740 OVCUNIT_CLOCK_GATE_DISABLE;
5742 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5743 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5744 } else if (IS_I965GM(dev)) {
5745 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5746 I915_WRITE(RENCLK_GATE_D2, 0);
5747 I915_WRITE(DSPCLK_GATE_D, 0);
5748 I915_WRITE(RAMCLK_GATE_D, 0);
5749 I915_WRITE16(DEUC, 0);
5750 } else if (IS_I965G(dev)) {
5751 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5752 I965_RCC_CLOCK_GATE_DISABLE |
5753 I965_RCPB_CLOCK_GATE_DISABLE |
5754 I965_ISC_CLOCK_GATE_DISABLE |
5755 I965_FBC_CLOCK_GATE_DISABLE);
5756 I915_WRITE(RENCLK_GATE_D2, 0);
5757 } else if (IS_I9XX(dev)) {
5758 u32 dstate = I915_READ(D_STATE);
5760 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5761 DSTATE_DOT_CLOCK_GATING;
5762 I915_WRITE(D_STATE, dstate);
5763 } else if (IS_I85X(dev) || IS_I865G(dev)) {
5764 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5765 } else if (IS_I830(dev)) {
5766 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5770 * GPU can automatically power down the render unit if given a page
5773 if (IS_IRONLAKE_M(dev)) {
5774 if (dev_priv->renderctx == NULL)
5775 dev_priv->renderctx = intel_alloc_context_page(dev);
5776 if (dev_priv->renderctx) {
5777 struct drm_i915_gem_object *obj_priv;
5778 obj_priv = to_intel_bo(dev_priv->renderctx);
5781 OUT_RING(MI_SET_CONTEXT);
5782 OUT_RING(obj_priv->gtt_offset |
5784 MI_SAVE_EXT_STATE_EN |
5785 MI_RESTORE_EXT_STATE_EN |
5786 MI_RESTORE_INHIBIT);
5792 DRM_DEBUG_KMS("Failed to allocate render context."
5798 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5799 struct drm_i915_gem_object *obj_priv = NULL;
5801 if (dev_priv->pwrctx) {
5802 obj_priv = to_intel_bo(dev_priv->pwrctx);
5804 struct drm_gem_object *pwrctx;
5806 pwrctx = intel_alloc_context_page(dev);
5808 dev_priv->pwrctx = pwrctx;
5809 obj_priv = to_intel_bo(pwrctx);
5814 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5815 I915_WRITE(MCHBAR_RENDER_STANDBY,
5816 I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5821 /* Set up chip specific display functions */
5822 static void intel_init_display(struct drm_device *dev)
5824 struct drm_i915_private *dev_priv = dev->dev_private;
5826 /* We always want a DPMS function */
5827 if (HAS_PCH_SPLIT(dev))
5828 dev_priv->display.dpms = ironlake_crtc_dpms;
5830 dev_priv->display.dpms = i9xx_crtc_dpms;
5832 if (I915_HAS_FBC(dev)) {
5833 if (IS_IRONLAKE_M(dev)) {
5834 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5835 dev_priv->display.enable_fbc = ironlake_enable_fbc;
5836 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5837 } else if (IS_GM45(dev)) {
5838 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5839 dev_priv->display.enable_fbc = g4x_enable_fbc;
5840 dev_priv->display.disable_fbc = g4x_disable_fbc;
5841 } else if (IS_I965GM(dev)) {
5842 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5843 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5844 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5846 /* 855GM needs testing */
5849 /* Returns the core display clock speed */
5850 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5851 dev_priv->display.get_display_clock_speed =
5852 i945_get_display_clock_speed;
5853 else if (IS_I915G(dev))
5854 dev_priv->display.get_display_clock_speed =
5855 i915_get_display_clock_speed;
5856 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5857 dev_priv->display.get_display_clock_speed =
5858 i9xx_misc_get_display_clock_speed;
5859 else if (IS_I915GM(dev))
5860 dev_priv->display.get_display_clock_speed =
5861 i915gm_get_display_clock_speed;
5862 else if (IS_I865G(dev))
5863 dev_priv->display.get_display_clock_speed =
5864 i865_get_display_clock_speed;
5865 else if (IS_I85X(dev))
5866 dev_priv->display.get_display_clock_speed =
5867 i855_get_display_clock_speed;
5869 dev_priv->display.get_display_clock_speed =
5870 i830_get_display_clock_speed;
5872 /* For FIFO watermark updates */
5873 if (HAS_PCH_SPLIT(dev)) {
5874 if (IS_IRONLAKE(dev)) {
5875 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5876 dev_priv->display.update_wm = ironlake_update_wm;
5878 DRM_DEBUG_KMS("Failed to get proper latency. "
5880 dev_priv->display.update_wm = NULL;
5883 dev_priv->display.update_wm = NULL;
5884 } else if (IS_PINEVIEW(dev)) {
5885 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5888 dev_priv->mem_freq)) {
5889 DRM_INFO("failed to find known CxSR latency "
5890 "(found ddr%s fsb freq %d, mem freq %d), "
5892 (dev_priv->is_ddr3 == 1) ? "3": "2",
5893 dev_priv->fsb_freq, dev_priv->mem_freq);
5894 /* Disable CxSR and never update its watermark again */
5895 pineview_disable_cxsr(dev);
5896 dev_priv->display.update_wm = NULL;
5898 dev_priv->display.update_wm = pineview_update_wm;
5899 } else if (IS_G4X(dev))
5900 dev_priv->display.update_wm = g4x_update_wm;
5901 else if (IS_I965G(dev))
5902 dev_priv->display.update_wm = i965_update_wm;
5903 else if (IS_I9XX(dev)) {
5904 dev_priv->display.update_wm = i9xx_update_wm;
5905 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5906 } else if (IS_I85X(dev)) {
5907 dev_priv->display.update_wm = i9xx_update_wm;
5908 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5910 dev_priv->display.update_wm = i830_update_wm;
5912 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5914 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5919 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
5920 * resume, or other times. This quirk makes sure that's the case for
5923 static void quirk_pipea_force (struct drm_device *dev)
5925 struct drm_i915_private *dev_priv = dev->dev_private;
5927 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
5928 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
5931 struct intel_quirk {
5933 int subsystem_vendor;
5934 int subsystem_device;
5935 void (*hook)(struct drm_device *dev);
5938 struct intel_quirk intel_quirks[] = {
5939 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
5940 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
5941 /* HP Mini needs pipe A force quirk (LP: #322104) */
5942 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
5944 /* Thinkpad R31 needs pipe A force quirk */
5945 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
5946 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
5947 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
5949 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
5950 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
5951 /* ThinkPad X40 needs pipe A force quirk */
5953 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
5954 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
5956 /* 855 & before need to leave pipe A & dpll A up */
5957 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5958 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5961 static void intel_init_quirks(struct drm_device *dev)
5963 struct pci_dev *d = dev->pdev;
5966 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
5967 struct intel_quirk *q = &intel_quirks[i];
5969 if (d->device == q->device &&
5970 (d->subsystem_vendor == q->subsystem_vendor ||
5971 q->subsystem_vendor == PCI_ANY_ID) &&
5972 (d->subsystem_device == q->subsystem_device ||
5973 q->subsystem_device == PCI_ANY_ID))
5978 /* Disable the VGA plane that we never use */
5979 static void i915_disable_vga(struct drm_device *dev)
5981 struct drm_i915_private *dev_priv = dev->dev_private;
5985 if (HAS_PCH_SPLIT(dev))
5986 vga_reg = CPU_VGACNTRL;
5990 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5991 outb(1, VGA_SR_INDEX);
5992 sr1 = inb(VGA_SR_DATA);
5993 outb(sr1 | 1<<5, VGA_SR_DATA);
5994 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5997 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
5998 POSTING_READ(vga_reg);
6001 void intel_modeset_init(struct drm_device *dev)
6003 struct drm_i915_private *dev_priv = dev->dev_private;
6006 drm_mode_config_init(dev);
6008 dev->mode_config.min_width = 0;
6009 dev->mode_config.min_height = 0;
6011 dev->mode_config.funcs = (void *)&intel_mode_funcs;
6013 intel_init_quirks(dev);
6015 intel_init_display(dev);
6017 if (IS_I965G(dev)) {
6018 dev->mode_config.max_width = 8192;
6019 dev->mode_config.max_height = 8192;
6020 } else if (IS_I9XX(dev)) {
6021 dev->mode_config.max_width = 4096;
6022 dev->mode_config.max_height = 4096;
6024 dev->mode_config.max_width = 2048;
6025 dev->mode_config.max_height = 2048;
6028 /* set memory base */
6030 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
6032 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
6034 if (IS_MOBILE(dev) || IS_I9XX(dev))
6035 dev_priv->num_pipe = 2;
6037 dev_priv->num_pipe = 1;
6038 DRM_DEBUG_KMS("%d display pipe%s available.\n",
6039 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6041 for (i = 0; i < dev_priv->num_pipe; i++) {
6042 intel_crtc_init(dev, i);
6045 intel_setup_outputs(dev);
6047 intel_init_clock_gating(dev);
6049 /* Just disable it once at startup */
6050 i915_disable_vga(dev);
6052 if (IS_IRONLAKE_M(dev)) {
6053 ironlake_enable_drps(dev);
6054 intel_init_emon(dev);
6057 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6058 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6059 (unsigned long)dev);
6061 intel_setup_overlay(dev);
6064 void intel_modeset_cleanup(struct drm_device *dev)
6066 struct drm_i915_private *dev_priv = dev->dev_private;
6067 struct drm_crtc *crtc;
6068 struct intel_crtc *intel_crtc;
6070 mutex_lock(&dev->struct_mutex);
6072 drm_kms_helper_poll_fini(dev);
6073 intel_fbdev_fini(dev);
6075 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6076 /* Skip inactive CRTCs */
6080 intel_crtc = to_intel_crtc(crtc);
6081 intel_increase_pllclock(crtc, false);
6082 del_timer_sync(&intel_crtc->idle_timer);
6085 del_timer_sync(&dev_priv->idle_timer);
6087 if (dev_priv->display.disable_fbc)
6088 dev_priv->display.disable_fbc(dev);
6090 if (dev_priv->renderctx) {
6091 struct drm_i915_gem_object *obj_priv;
6093 obj_priv = to_intel_bo(dev_priv->renderctx);
6094 I915_WRITE(CCID, obj_priv->gtt_offset &~ CCID_EN);
6096 i915_gem_object_unpin(dev_priv->renderctx);
6097 drm_gem_object_unreference(dev_priv->renderctx);
6100 if (dev_priv->pwrctx) {
6101 struct drm_i915_gem_object *obj_priv;
6103 obj_priv = to_intel_bo(dev_priv->pwrctx);
6104 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
6106 i915_gem_object_unpin(dev_priv->pwrctx);
6107 drm_gem_object_unreference(dev_priv->pwrctx);
6110 if (IS_IRONLAKE_M(dev))
6111 ironlake_disable_drps(dev);
6113 mutex_unlock(&dev->struct_mutex);
6115 drm_mode_config_cleanup(dev);
6120 * Return which encoder is currently attached for connector.
6122 struct drm_encoder *intel_attached_encoder (struct drm_connector *connector)
6124 struct drm_mode_object *obj;
6125 struct drm_encoder *encoder;
6128 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
6129 if (connector->encoder_ids[i] == 0)
6132 obj = drm_mode_object_find(connector->dev,
6133 connector->encoder_ids[i],
6134 DRM_MODE_OBJECT_ENCODER);
6138 encoder = obj_to_encoder(obj);
6145 * set vga decode state - true == enable VGA decode
6147 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6149 struct drm_i915_private *dev_priv = dev->dev_private;
6152 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6154 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6156 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6157 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);