2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/vgaarb.h>
34 #include "intel_drv.h"
37 #include "i915_trace.h"
38 #include "drm_dp_helper.h"
40 #include "drm_crtc_helper.h"
42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
45 static void intel_update_watermarks(struct drm_device *dev);
46 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
47 static void intel_crtc_update_cursor(struct drm_crtc *crtc);
70 #define INTEL_P2_NUM 2
71 typedef struct intel_limit intel_limit_t;
73 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
76 int, int, intel_clock_t *);
79 #define I8XX_DOT_MIN 25000
80 #define I8XX_DOT_MAX 350000
81 #define I8XX_VCO_MIN 930000
82 #define I8XX_VCO_MAX 1400000
86 #define I8XX_M_MAX 140
87 #define I8XX_M1_MIN 18
88 #define I8XX_M1_MAX 26
90 #define I8XX_M2_MAX 16
92 #define I8XX_P_MAX 128
94 #define I8XX_P1_MAX 33
95 #define I8XX_P1_LVDS_MIN 1
96 #define I8XX_P1_LVDS_MAX 6
97 #define I8XX_P2_SLOW 4
98 #define I8XX_P2_FAST 2
99 #define I8XX_P2_LVDS_SLOW 14
100 #define I8XX_P2_LVDS_FAST 7
101 #define I8XX_P2_SLOW_LIMIT 165000
103 #define I9XX_DOT_MIN 20000
104 #define I9XX_DOT_MAX 400000
105 #define I9XX_VCO_MIN 1400000
106 #define I9XX_VCO_MAX 2800000
107 #define PINEVIEW_VCO_MIN 1700000
108 #define PINEVIEW_VCO_MAX 3500000
111 /* Pineview's Ncounter is a ring counter */
112 #define PINEVIEW_N_MIN 3
113 #define PINEVIEW_N_MAX 6
114 #define I9XX_M_MIN 70
115 #define I9XX_M_MAX 120
116 #define PINEVIEW_M_MIN 2
117 #define PINEVIEW_M_MAX 256
118 #define I9XX_M1_MIN 10
119 #define I9XX_M1_MAX 22
120 #define I9XX_M2_MIN 5
121 #define I9XX_M2_MAX 9
122 /* Pineview M1 is reserved, and must be 0 */
123 #define PINEVIEW_M1_MIN 0
124 #define PINEVIEW_M1_MAX 0
125 #define PINEVIEW_M2_MIN 0
126 #define PINEVIEW_M2_MAX 254
127 #define I9XX_P_SDVO_DAC_MIN 5
128 #define I9XX_P_SDVO_DAC_MAX 80
129 #define I9XX_P_LVDS_MIN 7
130 #define I9XX_P_LVDS_MAX 98
131 #define PINEVIEW_P_LVDS_MIN 7
132 #define PINEVIEW_P_LVDS_MAX 112
133 #define I9XX_P1_MIN 1
134 #define I9XX_P1_MAX 8
135 #define I9XX_P2_SDVO_DAC_SLOW 10
136 #define I9XX_P2_SDVO_DAC_FAST 5
137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
138 #define I9XX_P2_LVDS_SLOW 14
139 #define I9XX_P2_LVDS_FAST 7
140 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
142 /*The parameter is for SDVO on G4x platform*/
143 #define G4X_DOT_SDVO_MIN 25000
144 #define G4X_DOT_SDVO_MAX 270000
145 #define G4X_VCO_MIN 1750000
146 #define G4X_VCO_MAX 3500000
147 #define G4X_N_SDVO_MIN 1
148 #define G4X_N_SDVO_MAX 4
149 #define G4X_M_SDVO_MIN 104
150 #define G4X_M_SDVO_MAX 138
151 #define G4X_M1_SDVO_MIN 17
152 #define G4X_M1_SDVO_MAX 23
153 #define G4X_M2_SDVO_MIN 5
154 #define G4X_M2_SDVO_MAX 11
155 #define G4X_P_SDVO_MIN 10
156 #define G4X_P_SDVO_MAX 30
157 #define G4X_P1_SDVO_MIN 1
158 #define G4X_P1_SDVO_MAX 3
159 #define G4X_P2_SDVO_SLOW 10
160 #define G4X_P2_SDVO_FAST 10
161 #define G4X_P2_SDVO_LIMIT 270000
163 /*The parameter is for HDMI_DAC on G4x platform*/
164 #define G4X_DOT_HDMI_DAC_MIN 22000
165 #define G4X_DOT_HDMI_DAC_MAX 400000
166 #define G4X_N_HDMI_DAC_MIN 1
167 #define G4X_N_HDMI_DAC_MAX 4
168 #define G4X_M_HDMI_DAC_MIN 104
169 #define G4X_M_HDMI_DAC_MAX 138
170 #define G4X_M1_HDMI_DAC_MIN 16
171 #define G4X_M1_HDMI_DAC_MAX 23
172 #define G4X_M2_HDMI_DAC_MIN 5
173 #define G4X_M2_HDMI_DAC_MAX 11
174 #define G4X_P_HDMI_DAC_MIN 5
175 #define G4X_P_HDMI_DAC_MAX 80
176 #define G4X_P1_HDMI_DAC_MIN 1
177 #define G4X_P1_HDMI_DAC_MAX 8
178 #define G4X_P2_HDMI_DAC_SLOW 10
179 #define G4X_P2_HDMI_DAC_FAST 5
180 #define G4X_P2_HDMI_DAC_LIMIT 165000
182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
220 /*The parameter is for DISPLAY PORT on G4x platform*/
221 #define G4X_DOT_DISPLAY_PORT_MIN 161670
222 #define G4X_DOT_DISPLAY_PORT_MAX 227000
223 #define G4X_N_DISPLAY_PORT_MIN 1
224 #define G4X_N_DISPLAY_PORT_MAX 2
225 #define G4X_M_DISPLAY_PORT_MIN 97
226 #define G4X_M_DISPLAY_PORT_MAX 108
227 #define G4X_M1_DISPLAY_PORT_MIN 0x10
228 #define G4X_M1_DISPLAY_PORT_MAX 0x12
229 #define G4X_M2_DISPLAY_PORT_MIN 0x05
230 #define G4X_M2_DISPLAY_PORT_MAX 0x06
231 #define G4X_P_DISPLAY_PORT_MIN 10
232 #define G4X_P_DISPLAY_PORT_MAX 20
233 #define G4X_P1_DISPLAY_PORT_MIN 1
234 #define G4X_P1_DISPLAY_PORT_MAX 2
235 #define G4X_P2_DISPLAY_PORT_SLOW 10
236 #define G4X_P2_DISPLAY_PORT_FAST 10
237 #define G4X_P2_DISPLAY_PORT_LIMIT 0
239 /* Ironlake / Sandybridge */
240 /* as we calculate clock using (register_value + 2) for
241 N/M1/M2, so here the range value for them is (actual_value-2).
243 #define IRONLAKE_DOT_MIN 25000
244 #define IRONLAKE_DOT_MAX 350000
245 #define IRONLAKE_VCO_MIN 1760000
246 #define IRONLAKE_VCO_MAX 3510000
247 #define IRONLAKE_M1_MIN 12
248 #define IRONLAKE_M1_MAX 22
249 #define IRONLAKE_M2_MIN 5
250 #define IRONLAKE_M2_MAX 9
251 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
253 /* We have parameter ranges for different type of outputs. */
255 /* DAC & HDMI Refclk 120Mhz */
256 #define IRONLAKE_DAC_N_MIN 1
257 #define IRONLAKE_DAC_N_MAX 5
258 #define IRONLAKE_DAC_M_MIN 79
259 #define IRONLAKE_DAC_M_MAX 127
260 #define IRONLAKE_DAC_P_MIN 5
261 #define IRONLAKE_DAC_P_MAX 80
262 #define IRONLAKE_DAC_P1_MIN 1
263 #define IRONLAKE_DAC_P1_MAX 8
264 #define IRONLAKE_DAC_P2_SLOW 10
265 #define IRONLAKE_DAC_P2_FAST 5
267 /* LVDS single-channel 120Mhz refclk */
268 #define IRONLAKE_LVDS_S_N_MIN 1
269 #define IRONLAKE_LVDS_S_N_MAX 3
270 #define IRONLAKE_LVDS_S_M_MIN 79
271 #define IRONLAKE_LVDS_S_M_MAX 118
272 #define IRONLAKE_LVDS_S_P_MIN 28
273 #define IRONLAKE_LVDS_S_P_MAX 112
274 #define IRONLAKE_LVDS_S_P1_MIN 2
275 #define IRONLAKE_LVDS_S_P1_MAX 8
276 #define IRONLAKE_LVDS_S_P2_SLOW 14
277 #define IRONLAKE_LVDS_S_P2_FAST 14
279 /* LVDS dual-channel 120Mhz refclk */
280 #define IRONLAKE_LVDS_D_N_MIN 1
281 #define IRONLAKE_LVDS_D_N_MAX 3
282 #define IRONLAKE_LVDS_D_M_MIN 79
283 #define IRONLAKE_LVDS_D_M_MAX 127
284 #define IRONLAKE_LVDS_D_P_MIN 14
285 #define IRONLAKE_LVDS_D_P_MAX 56
286 #define IRONLAKE_LVDS_D_P1_MIN 2
287 #define IRONLAKE_LVDS_D_P1_MAX 8
288 #define IRONLAKE_LVDS_D_P2_SLOW 7
289 #define IRONLAKE_LVDS_D_P2_FAST 7
291 /* LVDS single-channel 100Mhz refclk */
292 #define IRONLAKE_LVDS_S_SSC_N_MIN 1
293 #define IRONLAKE_LVDS_S_SSC_N_MAX 2
294 #define IRONLAKE_LVDS_S_SSC_M_MIN 79
295 #define IRONLAKE_LVDS_S_SSC_M_MAX 126
296 #define IRONLAKE_LVDS_S_SSC_P_MIN 28
297 #define IRONLAKE_LVDS_S_SSC_P_MAX 112
298 #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
299 #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
301 #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
303 /* LVDS dual-channel 100Mhz refclk */
304 #define IRONLAKE_LVDS_D_SSC_N_MIN 1
305 #define IRONLAKE_LVDS_D_SSC_N_MAX 3
306 #define IRONLAKE_LVDS_D_SSC_M_MIN 79
307 #define IRONLAKE_LVDS_D_SSC_M_MAX 126
308 #define IRONLAKE_LVDS_D_SSC_P_MIN 14
309 #define IRONLAKE_LVDS_D_SSC_P_MAX 42
310 #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
311 #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
313 #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
316 #define IRONLAKE_DP_N_MIN 1
317 #define IRONLAKE_DP_N_MAX 2
318 #define IRONLAKE_DP_M_MIN 81
319 #define IRONLAKE_DP_M_MAX 90
320 #define IRONLAKE_DP_P_MIN 10
321 #define IRONLAKE_DP_P_MAX 20
322 #define IRONLAKE_DP_P2_FAST 10
323 #define IRONLAKE_DP_P2_SLOW 10
324 #define IRONLAKE_DP_P2_LIMIT 0
325 #define IRONLAKE_DP_P1_MIN 1
326 #define IRONLAKE_DP_P1_MAX 2
329 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
333 int target, int refclk, intel_clock_t *best_clock);
335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
336 int target, int refclk, intel_clock_t *best_clock);
339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
340 int target, int refclk, intel_clock_t *best_clock);
342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
343 int target, int refclk, intel_clock_t *best_clock);
345 static const intel_limit_t intel_limits_i8xx_dvo = {
346 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
347 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
348 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
349 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
350 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
351 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
352 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
353 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
354 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
355 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
356 .find_pll = intel_find_best_PLL,
359 static const intel_limit_t intel_limits_i8xx_lvds = {
360 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
361 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
362 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
363 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
364 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
365 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
366 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
367 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
368 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
369 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
370 .find_pll = intel_find_best_PLL,
373 static const intel_limit_t intel_limits_i9xx_sdvo = {
374 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
375 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
376 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
377 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
378 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
379 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
380 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
381 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
382 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
383 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
384 .find_pll = intel_find_best_PLL,
387 static const intel_limit_t intel_limits_i9xx_lvds = {
388 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
389 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
390 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
391 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
392 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
393 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
394 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
395 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
396 /* The single-channel range is 25-112Mhz, and dual-channel
397 * is 80-224Mhz. Prefer single channel as much as possible.
399 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
400 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
401 .find_pll = intel_find_best_PLL,
404 /* below parameter and function is for G4X Chipset Family*/
405 static const intel_limit_t intel_limits_g4x_sdvo = {
406 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
407 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
408 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
409 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
410 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
411 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
412 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
413 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
414 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
415 .p2_slow = G4X_P2_SDVO_SLOW,
416 .p2_fast = G4X_P2_SDVO_FAST
418 .find_pll = intel_g4x_find_best_PLL,
421 static const intel_limit_t intel_limits_g4x_hdmi = {
422 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
423 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
424 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
425 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
426 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
427 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
428 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
429 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
430 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
431 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
432 .p2_fast = G4X_P2_HDMI_DAC_FAST
434 .find_pll = intel_g4x_find_best_PLL,
437 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
438 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
439 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
440 .vco = { .min = G4X_VCO_MIN,
441 .max = G4X_VCO_MAX },
442 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
443 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
444 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
445 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
446 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
447 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
448 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
449 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
450 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
451 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
452 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
453 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
454 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
455 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
456 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
458 .find_pll = intel_g4x_find_best_PLL,
461 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
462 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
463 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
464 .vco = { .min = G4X_VCO_MIN,
465 .max = G4X_VCO_MAX },
466 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
467 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
468 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
469 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
470 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
471 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
472 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
473 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
474 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
475 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
476 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
477 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
478 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
479 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
480 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
482 .find_pll = intel_g4x_find_best_PLL,
485 static const intel_limit_t intel_limits_g4x_display_port = {
486 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
487 .max = G4X_DOT_DISPLAY_PORT_MAX },
488 .vco = { .min = G4X_VCO_MIN,
490 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
491 .max = G4X_N_DISPLAY_PORT_MAX },
492 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
493 .max = G4X_M_DISPLAY_PORT_MAX },
494 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
495 .max = G4X_M1_DISPLAY_PORT_MAX },
496 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
497 .max = G4X_M2_DISPLAY_PORT_MAX },
498 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
499 .max = G4X_P_DISPLAY_PORT_MAX },
500 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
501 .max = G4X_P1_DISPLAY_PORT_MAX},
502 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
503 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
504 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
505 .find_pll = intel_find_pll_g4x_dp,
508 static const intel_limit_t intel_limits_pineview_sdvo = {
509 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
510 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
511 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
512 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
513 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
514 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
515 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
516 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
517 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
518 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
519 .find_pll = intel_find_best_PLL,
522 static const intel_limit_t intel_limits_pineview_lvds = {
523 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
524 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
525 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
526 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
527 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
528 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
529 .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
530 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
531 /* Pineview only supports single-channel mode. */
532 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
533 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
534 .find_pll = intel_find_best_PLL,
537 static const intel_limit_t intel_limits_ironlake_dac = {
538 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
539 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
540 .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
541 .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
542 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
543 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
544 .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
545 .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
546 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
547 .p2_slow = IRONLAKE_DAC_P2_SLOW,
548 .p2_fast = IRONLAKE_DAC_P2_FAST },
549 .find_pll = intel_g4x_find_best_PLL,
552 static const intel_limit_t intel_limits_ironlake_single_lvds = {
553 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
554 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
555 .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
556 .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
557 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
558 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
559 .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
560 .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
561 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
562 .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
563 .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
564 .find_pll = intel_g4x_find_best_PLL,
567 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
568 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
569 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
570 .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
571 .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
572 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
573 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
574 .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
575 .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
576 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
577 .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
578 .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
579 .find_pll = intel_g4x_find_best_PLL,
582 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
583 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
584 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
585 .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
586 .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
587 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
588 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
589 .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
590 .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
591 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
592 .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
593 .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
594 .find_pll = intel_g4x_find_best_PLL,
597 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
598 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
599 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
600 .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
601 .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
602 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
603 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
604 .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
605 .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
606 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
607 .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
608 .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
609 .find_pll = intel_g4x_find_best_PLL,
612 static const intel_limit_t intel_limits_ironlake_display_port = {
613 .dot = { .min = IRONLAKE_DOT_MIN,
614 .max = IRONLAKE_DOT_MAX },
615 .vco = { .min = IRONLAKE_VCO_MIN,
616 .max = IRONLAKE_VCO_MAX},
617 .n = { .min = IRONLAKE_DP_N_MIN,
618 .max = IRONLAKE_DP_N_MAX },
619 .m = { .min = IRONLAKE_DP_M_MIN,
620 .max = IRONLAKE_DP_M_MAX },
621 .m1 = { .min = IRONLAKE_M1_MIN,
622 .max = IRONLAKE_M1_MAX },
623 .m2 = { .min = IRONLAKE_M2_MIN,
624 .max = IRONLAKE_M2_MAX },
625 .p = { .min = IRONLAKE_DP_P_MIN,
626 .max = IRONLAKE_DP_P_MAX },
627 .p1 = { .min = IRONLAKE_DP_P1_MIN,
628 .max = IRONLAKE_DP_P1_MAX},
629 .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
630 .p2_slow = IRONLAKE_DP_P2_SLOW,
631 .p2_fast = IRONLAKE_DP_P2_FAST },
632 .find_pll = intel_find_pll_ironlake_dp,
635 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
637 struct drm_device *dev = crtc->dev;
638 struct drm_i915_private *dev_priv = dev->dev_private;
639 const intel_limit_t *limit;
642 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
643 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
646 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
647 LVDS_CLKB_POWER_UP) {
648 /* LVDS dual channel */
650 limit = &intel_limits_ironlake_dual_lvds_100m;
652 limit = &intel_limits_ironlake_dual_lvds;
655 limit = &intel_limits_ironlake_single_lvds_100m;
657 limit = &intel_limits_ironlake_single_lvds;
659 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
661 limit = &intel_limits_ironlake_display_port;
663 limit = &intel_limits_ironlake_dac;
668 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
670 struct drm_device *dev = crtc->dev;
671 struct drm_i915_private *dev_priv = dev->dev_private;
672 const intel_limit_t *limit;
674 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
675 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
677 /* LVDS with dual channel */
678 limit = &intel_limits_g4x_dual_channel_lvds;
680 /* LVDS with dual channel */
681 limit = &intel_limits_g4x_single_channel_lvds;
682 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
683 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
684 limit = &intel_limits_g4x_hdmi;
685 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
686 limit = &intel_limits_g4x_sdvo;
687 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
688 limit = &intel_limits_g4x_display_port;
689 } else /* The option is for other outputs */
690 limit = &intel_limits_i9xx_sdvo;
695 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
697 struct drm_device *dev = crtc->dev;
698 const intel_limit_t *limit;
700 if (HAS_PCH_SPLIT(dev))
701 limit = intel_ironlake_limit(crtc);
702 else if (IS_G4X(dev)) {
703 limit = intel_g4x_limit(crtc);
704 } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
705 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
706 limit = &intel_limits_i9xx_lvds;
708 limit = &intel_limits_i9xx_sdvo;
709 } else if (IS_PINEVIEW(dev)) {
710 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
711 limit = &intel_limits_pineview_lvds;
713 limit = &intel_limits_pineview_sdvo;
715 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
716 limit = &intel_limits_i8xx_lvds;
718 limit = &intel_limits_i8xx_dvo;
723 /* m1 is reserved as 0 in Pineview, n is a ring counter */
724 static void pineview_clock(int refclk, intel_clock_t *clock)
726 clock->m = clock->m2 + 2;
727 clock->p = clock->p1 * clock->p2;
728 clock->vco = refclk * clock->m / clock->n;
729 clock->dot = clock->vco / clock->p;
732 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
734 if (IS_PINEVIEW(dev)) {
735 pineview_clock(refclk, clock);
738 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
739 clock->p = clock->p1 * clock->p2;
740 clock->vco = refclk * clock->m / (clock->n + 2);
741 clock->dot = clock->vco / clock->p;
745 * Returns whether any output on the specified pipe is of the specified type
747 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
749 struct drm_device *dev = crtc->dev;
750 struct drm_mode_config *mode_config = &dev->mode_config;
751 struct drm_encoder *l_entry;
753 list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
754 if (l_entry && l_entry->crtc == crtc) {
755 struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
756 if (intel_encoder->type == type)
763 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
765 * Returns whether the given set of divisors are valid for a given refclk with
766 * the given connectors.
769 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
771 const intel_limit_t *limit = intel_limit (crtc);
772 struct drm_device *dev = crtc->dev;
774 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
775 INTELPllInvalid ("p1 out of range\n");
776 if (clock->p < limit->p.min || limit->p.max < clock->p)
777 INTELPllInvalid ("p out of range\n");
778 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
779 INTELPllInvalid ("m2 out of range\n");
780 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
781 INTELPllInvalid ("m1 out of range\n");
782 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
783 INTELPllInvalid ("m1 <= m2\n");
784 if (clock->m < limit->m.min || limit->m.max < clock->m)
785 INTELPllInvalid ("m out of range\n");
786 if (clock->n < limit->n.min || limit->n.max < clock->n)
787 INTELPllInvalid ("n out of range\n");
788 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
789 INTELPllInvalid ("vco out of range\n");
790 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
791 * connector, etc., rather than just a single range.
793 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
794 INTELPllInvalid ("dot out of range\n");
800 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
801 int target, int refclk, intel_clock_t *best_clock)
804 struct drm_device *dev = crtc->dev;
805 struct drm_i915_private *dev_priv = dev->dev_private;
809 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
810 (I915_READ(LVDS)) != 0) {
812 * For LVDS, if the panel is on, just rely on its current
813 * settings for dual-channel. We haven't figured out how to
814 * reliably set up different single/dual channel state, if we
817 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
819 clock.p2 = limit->p2.p2_fast;
821 clock.p2 = limit->p2.p2_slow;
823 if (target < limit->p2.dot_limit)
824 clock.p2 = limit->p2.p2_slow;
826 clock.p2 = limit->p2.p2_fast;
829 memset (best_clock, 0, sizeof (*best_clock));
831 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
833 for (clock.m2 = limit->m2.min;
834 clock.m2 <= limit->m2.max; clock.m2++) {
835 /* m1 is always 0 in Pineview */
836 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
838 for (clock.n = limit->n.min;
839 clock.n <= limit->n.max; clock.n++) {
840 for (clock.p1 = limit->p1.min;
841 clock.p1 <= limit->p1.max; clock.p1++) {
844 intel_clock(dev, refclk, &clock);
846 if (!intel_PLL_is_valid(crtc, &clock))
849 this_err = abs(clock.dot - target);
850 if (this_err < err) {
859 return (err != target);
863 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
864 int target, int refclk, intel_clock_t *best_clock)
866 struct drm_device *dev = crtc->dev;
867 struct drm_i915_private *dev_priv = dev->dev_private;
871 /* approximately equals target * 0.00585 */
872 int err_most = (target >> 8) + (target >> 9);
875 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
878 if (HAS_PCH_SPLIT(dev))
882 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
884 clock.p2 = limit->p2.p2_fast;
886 clock.p2 = limit->p2.p2_slow;
888 if (target < limit->p2.dot_limit)
889 clock.p2 = limit->p2.p2_slow;
891 clock.p2 = limit->p2.p2_fast;
894 memset(best_clock, 0, sizeof(*best_clock));
895 max_n = limit->n.max;
896 /* based on hardware requirement, prefer smaller n to precision */
897 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
898 /* based on hardware requirement, prefere larger m1,m2 */
899 for (clock.m1 = limit->m1.max;
900 clock.m1 >= limit->m1.min; clock.m1--) {
901 for (clock.m2 = limit->m2.max;
902 clock.m2 >= limit->m2.min; clock.m2--) {
903 for (clock.p1 = limit->p1.max;
904 clock.p1 >= limit->p1.min; clock.p1--) {
907 intel_clock(dev, refclk, &clock);
908 if (!intel_PLL_is_valid(crtc, &clock))
910 this_err = abs(clock.dot - target) ;
911 if (this_err < err_most) {
925 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
926 int target, int refclk, intel_clock_t *best_clock)
928 struct drm_device *dev = crtc->dev;
931 /* return directly when it is eDP */
935 if (target < 200000) {
948 intel_clock(dev, refclk, &clock);
949 memcpy(best_clock, &clock, sizeof(intel_clock_t));
953 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
955 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
956 int target, int refclk, intel_clock_t *best_clock)
959 if (target < 200000) {
972 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
973 clock.p = (clock.p1 * clock.p2);
974 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
976 memcpy(best_clock, &clock, sizeof(intel_clock_t));
981 * intel_wait_for_vblank - wait for vblank on a given pipe
983 * @pipe: pipe to wait for
985 * Wait for vblank to occur on a given pipe. Needed for various bits of
988 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
990 struct drm_i915_private *dev_priv = dev->dev_private;
991 int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
993 /* Wait for vblank interrupt bit to set */
994 if (wait_for((I915_READ(pipestat_reg) &
995 PIPE_VBLANK_INTERRUPT_STATUS),
997 DRM_DEBUG_KMS("vblank wait timed out\n");
1001 * intel_wait_for_vblank_off - wait for vblank after disabling a pipe
1003 * @pipe: pipe to wait for
1005 * After disabling a pipe, we can't wait for vblank in the usual way,
1006 * spinning on the vblank interrupt status bit, since we won't actually
1007 * see an interrupt when the pipe is disabled.
1009 * So this function waits for the display line value to settle (it
1010 * usually ends up stopping at the start of the next frame).
1012 void intel_wait_for_vblank_off(struct drm_device *dev, int pipe)
1014 struct drm_i915_private *dev_priv = dev->dev_private;
1015 int pipedsl_reg = (pipe == 0 ? PIPEADSL : PIPEBDSL);
1016 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1019 /* Wait for the display line to settle */
1021 last_line = I915_READ(pipedsl_reg) & DSL_LINEMASK;
1023 } while (((I915_READ(pipedsl_reg) & DSL_LINEMASK) != last_line) &&
1024 time_after(timeout, jiffies));
1026 if (time_after(jiffies, timeout))
1027 DRM_DEBUG_KMS("vblank wait timed out\n");
1030 /* Parameters have changed, update FBC info */
1031 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1033 struct drm_device *dev = crtc->dev;
1034 struct drm_i915_private *dev_priv = dev->dev_private;
1035 struct drm_framebuffer *fb = crtc->fb;
1036 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1037 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1040 u32 fbc_ctl, fbc_ctl2;
1042 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1044 if (fb->pitch < dev_priv->cfb_pitch)
1045 dev_priv->cfb_pitch = fb->pitch;
1047 /* FBC_CTL wants 64B units */
1048 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1049 dev_priv->cfb_fence = obj_priv->fence_reg;
1050 dev_priv->cfb_plane = intel_crtc->plane;
1051 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1053 /* Clear old tags */
1054 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1055 I915_WRITE(FBC_TAG + (i * 4), 0);
1058 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1059 if (obj_priv->tiling_mode != I915_TILING_NONE)
1060 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1061 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1062 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1065 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1067 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1068 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1069 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1070 if (obj_priv->tiling_mode != I915_TILING_NONE)
1071 fbc_ctl |= dev_priv->cfb_fence;
1072 I915_WRITE(FBC_CONTROL, fbc_ctl);
1074 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1075 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1078 void i8xx_disable_fbc(struct drm_device *dev)
1080 struct drm_i915_private *dev_priv = dev->dev_private;
1083 if (!I915_HAS_FBC(dev))
1086 if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
1087 return; /* Already off, just return */
1089 /* Disable compression */
1090 fbc_ctl = I915_READ(FBC_CONTROL);
1091 fbc_ctl &= ~FBC_CTL_EN;
1092 I915_WRITE(FBC_CONTROL, fbc_ctl);
1094 /* Wait for compressing bit to clear */
1095 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10, 0)) {
1096 DRM_DEBUG_KMS("FBC idle timed out\n");
1100 DRM_DEBUG_KMS("disabled FBC\n");
1103 static bool i8xx_fbc_enabled(struct drm_device *dev)
1105 struct drm_i915_private *dev_priv = dev->dev_private;
1107 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1110 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1112 struct drm_device *dev = crtc->dev;
1113 struct drm_i915_private *dev_priv = dev->dev_private;
1114 struct drm_framebuffer *fb = crtc->fb;
1115 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1116 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1117 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1118 int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1120 unsigned long stall_watermark = 200;
1123 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1124 dev_priv->cfb_fence = obj_priv->fence_reg;
1125 dev_priv->cfb_plane = intel_crtc->plane;
1127 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1128 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1129 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1130 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1132 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1135 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1136 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1137 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1138 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1139 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1142 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1144 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1147 void g4x_disable_fbc(struct drm_device *dev)
1149 struct drm_i915_private *dev_priv = dev->dev_private;
1152 /* Disable compression */
1153 dpfc_ctl = I915_READ(DPFC_CONTROL);
1154 dpfc_ctl &= ~DPFC_CTL_EN;
1155 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1157 DRM_DEBUG_KMS("disabled FBC\n");
1160 static bool g4x_fbc_enabled(struct drm_device *dev)
1162 struct drm_i915_private *dev_priv = dev->dev_private;
1164 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1167 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1169 struct drm_device *dev = crtc->dev;
1170 struct drm_i915_private *dev_priv = dev->dev_private;
1171 struct drm_framebuffer *fb = crtc->fb;
1172 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1173 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1175 int plane = (intel_crtc->plane == 0) ? DPFC_CTL_PLANEA :
1177 unsigned long stall_watermark = 200;
1180 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1181 dev_priv->cfb_fence = obj_priv->fence_reg;
1182 dev_priv->cfb_plane = intel_crtc->plane;
1184 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1185 dpfc_ctl &= DPFC_RESERVED;
1186 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1187 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1188 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1189 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1191 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1194 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1195 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1196 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1197 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1198 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1199 I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1201 I915_WRITE(ILK_DPFC_CONTROL, I915_READ(ILK_DPFC_CONTROL) |
1204 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1207 void ironlake_disable_fbc(struct drm_device *dev)
1209 struct drm_i915_private *dev_priv = dev->dev_private;
1212 /* Disable compression */
1213 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1214 dpfc_ctl &= ~DPFC_CTL_EN;
1215 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1217 DRM_DEBUG_KMS("disabled FBC\n");
1220 static bool ironlake_fbc_enabled(struct drm_device *dev)
1222 struct drm_i915_private *dev_priv = dev->dev_private;
1224 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1227 bool intel_fbc_enabled(struct drm_device *dev)
1229 struct drm_i915_private *dev_priv = dev->dev_private;
1231 if (!dev_priv->display.fbc_enabled)
1234 return dev_priv->display.fbc_enabled(dev);
1237 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1239 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1241 if (!dev_priv->display.enable_fbc)
1244 dev_priv->display.enable_fbc(crtc, interval);
1247 void intel_disable_fbc(struct drm_device *dev)
1249 struct drm_i915_private *dev_priv = dev->dev_private;
1251 if (!dev_priv->display.disable_fbc)
1254 dev_priv->display.disable_fbc(dev);
1258 * intel_update_fbc - enable/disable FBC as needed
1259 * @crtc: CRTC to point the compressor at
1260 * @mode: mode in use
1262 * Set up the framebuffer compression hardware at mode set time. We
1263 * enable it if possible:
1264 * - plane A only (on pre-965)
1265 * - no pixel mulitply/line duplication
1266 * - no alpha buffer discard
1268 * - framebuffer <= 2048 in width, 1536 in height
1270 * We can't assume that any compression will take place (worst case),
1271 * so the compressed buffer has to be the same size as the uncompressed
1272 * one. It also must reside (along with the line length buffer) in
1275 * We need to enable/disable FBC on a global basis.
1277 static void intel_update_fbc(struct drm_crtc *crtc,
1278 struct drm_display_mode *mode)
1280 struct drm_device *dev = crtc->dev;
1281 struct drm_i915_private *dev_priv = dev->dev_private;
1282 struct drm_framebuffer *fb = crtc->fb;
1283 struct intel_framebuffer *intel_fb;
1284 struct drm_i915_gem_object *obj_priv;
1285 struct drm_crtc *tmp_crtc;
1286 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1287 int plane = intel_crtc->plane;
1288 int crtcs_enabled = 0;
1290 DRM_DEBUG_KMS("\n");
1292 if (!i915_powersave)
1295 if (!I915_HAS_FBC(dev))
1301 intel_fb = to_intel_framebuffer(fb);
1302 obj_priv = to_intel_bo(intel_fb->obj);
1305 * If FBC is already on, we just have to verify that we can
1306 * keep it that way...
1307 * Need to disable if:
1308 * - more than one pipe is active
1309 * - changing FBC params (stride, fence, mode)
1310 * - new fb is too large to fit in compressed buffer
1311 * - going to an unsupported config (interlace, pixel multiply, etc.)
1313 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1314 if (tmp_crtc->enabled)
1317 DRM_DEBUG_KMS("%d pipes active\n", crtcs_enabled);
1318 if (crtcs_enabled > 1) {
1319 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1320 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1323 if (intel_fb->obj->size > dev_priv->cfb_size) {
1324 DRM_DEBUG_KMS("framebuffer too large, disabling "
1326 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1329 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1330 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1331 DRM_DEBUG_KMS("mode incompatible with compression, "
1333 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1336 if ((mode->hdisplay > 2048) ||
1337 (mode->vdisplay > 1536)) {
1338 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1339 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1342 if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1343 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1344 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1347 if (obj_priv->tiling_mode != I915_TILING_X) {
1348 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1349 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1353 /* If the kernel debugger is active, always disable compression */
1354 if (in_dbg_master())
1357 if (intel_fbc_enabled(dev)) {
1358 /* We can re-enable it in this case, but need to update pitch */
1359 if ((fb->pitch > dev_priv->cfb_pitch) ||
1360 (obj_priv->fence_reg != dev_priv->cfb_fence) ||
1361 (plane != dev_priv->cfb_plane))
1362 intel_disable_fbc(dev);
1365 /* Now try to turn it back on if possible */
1366 if (!intel_fbc_enabled(dev))
1367 intel_enable_fbc(crtc, 500);
1372 /* Multiple disables should be harmless */
1373 if (intel_fbc_enabled(dev)) {
1374 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1375 intel_disable_fbc(dev);
1380 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1382 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1386 switch (obj_priv->tiling_mode) {
1387 case I915_TILING_NONE:
1388 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1389 alignment = 128 * 1024;
1390 else if (IS_I965G(dev))
1391 alignment = 4 * 1024;
1393 alignment = 64 * 1024;
1396 /* pin() will align the object as required by fence */
1400 /* FIXME: Is this true? */
1401 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1407 ret = i915_gem_object_pin(obj, alignment);
1411 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1412 * fence, whereas 965+ only requires a fence if using
1413 * framebuffer compression. For simplicity, we always install
1414 * a fence as the cost is not that onerous.
1416 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1417 obj_priv->tiling_mode != I915_TILING_NONE) {
1418 ret = i915_gem_object_get_fence_reg(obj);
1420 i915_gem_object_unpin(obj);
1428 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1430 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1433 struct drm_device *dev = crtc->dev;
1434 struct drm_i915_private *dev_priv = dev->dev_private;
1435 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1436 struct intel_framebuffer *intel_fb;
1437 struct drm_i915_gem_object *obj_priv;
1438 struct drm_gem_object *obj;
1439 int plane = intel_crtc->plane;
1440 unsigned long Start, Offset;
1441 int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1442 int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1443 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1444 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1445 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1453 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1457 intel_fb = to_intel_framebuffer(fb);
1458 obj = intel_fb->obj;
1459 obj_priv = to_intel_bo(obj);
1461 dspcntr = I915_READ(dspcntr_reg);
1462 /* Mask out pixel format bits in case we change it */
1463 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1464 switch (fb->bits_per_pixel) {
1466 dspcntr |= DISPPLANE_8BPP;
1469 if (fb->depth == 15)
1470 dspcntr |= DISPPLANE_15_16BPP;
1472 dspcntr |= DISPPLANE_16BPP;
1476 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1479 DRM_ERROR("Unknown color depth\n");
1482 if (IS_I965G(dev)) {
1483 if (obj_priv->tiling_mode != I915_TILING_NONE)
1484 dspcntr |= DISPPLANE_TILED;
1486 dspcntr &= ~DISPPLANE_TILED;
1489 if (IS_IRONLAKE(dev))
1491 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1493 I915_WRITE(dspcntr_reg, dspcntr);
1495 Start = obj_priv->gtt_offset;
1496 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1498 DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1499 I915_WRITE(dspstride, fb->pitch);
1500 if (IS_I965G(dev)) {
1501 I915_WRITE(dspbase, Offset);
1503 I915_WRITE(dspsurf, Start);
1505 I915_WRITE(dsptileoff, (y << 16) | x);
1507 I915_WRITE(dspbase, Start + Offset);
1511 if ((IS_I965G(dev) || plane == 0))
1512 intel_update_fbc(crtc, &crtc->mode);
1514 intel_wait_for_vblank(dev, intel_crtc->pipe);
1515 intel_increase_pllclock(crtc, true);
1521 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1522 struct drm_framebuffer *old_fb)
1524 struct drm_device *dev = crtc->dev;
1525 struct drm_i915_private *dev_priv = dev->dev_private;
1526 struct drm_i915_master_private *master_priv;
1527 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1528 struct intel_framebuffer *intel_fb;
1529 struct drm_i915_gem_object *obj_priv;
1530 struct drm_gem_object *obj;
1531 int pipe = intel_crtc->pipe;
1532 int plane = intel_crtc->plane;
1533 unsigned long Start, Offset;
1534 int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1535 int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1536 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1537 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1538 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1544 DRM_DEBUG_KMS("No FB bound\n");
1553 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1557 intel_fb = to_intel_framebuffer(crtc->fb);
1558 obj = intel_fb->obj;
1559 obj_priv = to_intel_bo(obj);
1561 mutex_lock(&dev->struct_mutex);
1562 ret = intel_pin_and_fence_fb_obj(dev, obj);
1564 mutex_unlock(&dev->struct_mutex);
1568 ret = i915_gem_object_set_to_display_plane(obj);
1570 i915_gem_object_unpin(obj);
1571 mutex_unlock(&dev->struct_mutex);
1575 dspcntr = I915_READ(dspcntr_reg);
1576 /* Mask out pixel format bits in case we change it */
1577 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1578 switch (crtc->fb->bits_per_pixel) {
1580 dspcntr |= DISPPLANE_8BPP;
1583 if (crtc->fb->depth == 15)
1584 dspcntr |= DISPPLANE_15_16BPP;
1586 dspcntr |= DISPPLANE_16BPP;
1590 if (crtc->fb->depth == 30)
1591 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1593 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1596 DRM_ERROR("Unknown color depth\n");
1597 i915_gem_object_unpin(obj);
1598 mutex_unlock(&dev->struct_mutex);
1601 if (IS_I965G(dev)) {
1602 if (obj_priv->tiling_mode != I915_TILING_NONE)
1603 dspcntr |= DISPPLANE_TILED;
1605 dspcntr &= ~DISPPLANE_TILED;
1608 if (HAS_PCH_SPLIT(dev))
1610 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1612 I915_WRITE(dspcntr_reg, dspcntr);
1614 Start = obj_priv->gtt_offset;
1615 Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1617 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1618 Start, Offset, x, y, crtc->fb->pitch);
1619 I915_WRITE(dspstride, crtc->fb->pitch);
1620 if (IS_I965G(dev)) {
1621 I915_WRITE(dspsurf, Start);
1622 I915_WRITE(dsptileoff, (y << 16) | x);
1623 I915_WRITE(dspbase, Offset);
1625 I915_WRITE(dspbase, Start + Offset);
1627 POSTING_READ(dspbase);
1629 if ((IS_I965G(dev) || plane == 0))
1630 intel_update_fbc(crtc, &crtc->mode);
1632 intel_wait_for_vblank(dev, pipe);
1635 intel_fb = to_intel_framebuffer(old_fb);
1636 obj_priv = to_intel_bo(intel_fb->obj);
1637 i915_gem_object_unpin(intel_fb->obj);
1639 intel_increase_pllclock(crtc, true);
1641 mutex_unlock(&dev->struct_mutex);
1643 if (!dev->primary->master)
1646 master_priv = dev->primary->master->driver_priv;
1647 if (!master_priv->sarea_priv)
1651 master_priv->sarea_priv->pipeB_x = x;
1652 master_priv->sarea_priv->pipeB_y = y;
1654 master_priv->sarea_priv->pipeA_x = x;
1655 master_priv->sarea_priv->pipeA_y = y;
1661 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1663 struct drm_device *dev = crtc->dev;
1664 struct drm_i915_private *dev_priv = dev->dev_private;
1667 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1668 dpa_ctl = I915_READ(DP_A);
1669 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1671 if (clock < 200000) {
1673 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1674 /* workaround for 160Mhz:
1675 1) program 0x4600c bits 15:0 = 0x8124
1676 2) program 0x46010 bit 0 = 1
1677 3) program 0x46034 bit 24 = 1
1678 4) program 0x64000 bit 14 = 1
1680 temp = I915_READ(0x4600c);
1682 I915_WRITE(0x4600c, temp | 0x8124);
1684 temp = I915_READ(0x46010);
1685 I915_WRITE(0x46010, temp | 1);
1687 temp = I915_READ(0x46034);
1688 I915_WRITE(0x46034, temp | (1 << 24));
1690 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1692 I915_WRITE(DP_A, dpa_ctl);
1697 /* The FDI link training functions for ILK/Ibexpeak. */
1698 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1700 struct drm_device *dev = crtc->dev;
1701 struct drm_i915_private *dev_priv = dev->dev_private;
1702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1703 int pipe = intel_crtc->pipe;
1704 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1705 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1706 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1707 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1708 u32 temp, tries = 0;
1710 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1712 temp = I915_READ(fdi_rx_imr_reg);
1713 temp &= ~FDI_RX_SYMBOL_LOCK;
1714 temp &= ~FDI_RX_BIT_LOCK;
1715 I915_WRITE(fdi_rx_imr_reg, temp);
1716 I915_READ(fdi_rx_imr_reg);
1719 /* enable CPU FDI TX and PCH FDI RX */
1720 temp = I915_READ(fdi_tx_reg);
1721 temp |= FDI_TX_ENABLE;
1723 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1724 temp &= ~FDI_LINK_TRAIN_NONE;
1725 temp |= FDI_LINK_TRAIN_PATTERN_1;
1726 I915_WRITE(fdi_tx_reg, temp);
1727 I915_READ(fdi_tx_reg);
1729 temp = I915_READ(fdi_rx_reg);
1730 temp &= ~FDI_LINK_TRAIN_NONE;
1731 temp |= FDI_LINK_TRAIN_PATTERN_1;
1732 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1733 I915_READ(fdi_rx_reg);
1736 for (tries = 0; tries < 5; tries++) {
1737 temp = I915_READ(fdi_rx_iir_reg);
1738 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1740 if ((temp & FDI_RX_BIT_LOCK)) {
1741 DRM_DEBUG_KMS("FDI train 1 done.\n");
1742 I915_WRITE(fdi_rx_iir_reg,
1743 temp | FDI_RX_BIT_LOCK);
1748 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1751 temp = I915_READ(fdi_tx_reg);
1752 temp &= ~FDI_LINK_TRAIN_NONE;
1753 temp |= FDI_LINK_TRAIN_PATTERN_2;
1754 I915_WRITE(fdi_tx_reg, temp);
1756 temp = I915_READ(fdi_rx_reg);
1757 temp &= ~FDI_LINK_TRAIN_NONE;
1758 temp |= FDI_LINK_TRAIN_PATTERN_2;
1759 I915_WRITE(fdi_rx_reg, temp);
1764 for (tries = 0; tries < 5; tries++) {
1765 temp = I915_READ(fdi_rx_iir_reg);
1766 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1768 if (temp & FDI_RX_SYMBOL_LOCK) {
1769 I915_WRITE(fdi_rx_iir_reg,
1770 temp | FDI_RX_SYMBOL_LOCK);
1771 DRM_DEBUG_KMS("FDI train 2 done.\n");
1776 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1778 DRM_DEBUG_KMS("FDI train done\n");
1781 static int snb_b_fdi_train_param [] = {
1782 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1783 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1784 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1785 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1788 /* The FDI link training functions for SNB/Cougarpoint. */
1789 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1791 struct drm_device *dev = crtc->dev;
1792 struct drm_i915_private *dev_priv = dev->dev_private;
1793 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1794 int pipe = intel_crtc->pipe;
1795 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1796 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1797 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1798 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1801 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1803 temp = I915_READ(fdi_rx_imr_reg);
1804 temp &= ~FDI_RX_SYMBOL_LOCK;
1805 temp &= ~FDI_RX_BIT_LOCK;
1806 I915_WRITE(fdi_rx_imr_reg, temp);
1807 I915_READ(fdi_rx_imr_reg);
1810 /* enable CPU FDI TX and PCH FDI RX */
1811 temp = I915_READ(fdi_tx_reg);
1812 temp |= FDI_TX_ENABLE;
1814 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1815 temp &= ~FDI_LINK_TRAIN_NONE;
1816 temp |= FDI_LINK_TRAIN_PATTERN_1;
1817 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1819 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1820 I915_WRITE(fdi_tx_reg, temp);
1821 I915_READ(fdi_tx_reg);
1823 temp = I915_READ(fdi_rx_reg);
1824 if (HAS_PCH_CPT(dev)) {
1825 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1826 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1828 temp &= ~FDI_LINK_TRAIN_NONE;
1829 temp |= FDI_LINK_TRAIN_PATTERN_1;
1831 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1832 I915_READ(fdi_rx_reg);
1835 for (i = 0; i < 4; i++ ) {
1836 temp = I915_READ(fdi_tx_reg);
1837 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1838 temp |= snb_b_fdi_train_param[i];
1839 I915_WRITE(fdi_tx_reg, temp);
1842 temp = I915_READ(fdi_rx_iir_reg);
1843 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1845 if (temp & FDI_RX_BIT_LOCK) {
1846 I915_WRITE(fdi_rx_iir_reg,
1847 temp | FDI_RX_BIT_LOCK);
1848 DRM_DEBUG_KMS("FDI train 1 done.\n");
1853 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1856 temp = I915_READ(fdi_tx_reg);
1857 temp &= ~FDI_LINK_TRAIN_NONE;
1858 temp |= FDI_LINK_TRAIN_PATTERN_2;
1860 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1862 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1864 I915_WRITE(fdi_tx_reg, temp);
1866 temp = I915_READ(fdi_rx_reg);
1867 if (HAS_PCH_CPT(dev)) {
1868 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1869 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1871 temp &= ~FDI_LINK_TRAIN_NONE;
1872 temp |= FDI_LINK_TRAIN_PATTERN_2;
1874 I915_WRITE(fdi_rx_reg, temp);
1877 for (i = 0; i < 4; i++ ) {
1878 temp = I915_READ(fdi_tx_reg);
1879 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1880 temp |= snb_b_fdi_train_param[i];
1881 I915_WRITE(fdi_tx_reg, temp);
1884 temp = I915_READ(fdi_rx_iir_reg);
1885 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1887 if (temp & FDI_RX_SYMBOL_LOCK) {
1888 I915_WRITE(fdi_rx_iir_reg,
1889 temp | FDI_RX_SYMBOL_LOCK);
1890 DRM_DEBUG_KMS("FDI train 2 done.\n");
1895 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1897 DRM_DEBUG_KMS("FDI train done.\n");
1900 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1902 struct drm_device *dev = crtc->dev;
1903 struct drm_i915_private *dev_priv = dev->dev_private;
1904 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1905 int pipe = intel_crtc->pipe;
1906 int plane = intel_crtc->plane;
1907 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1908 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1909 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1910 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1911 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1912 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1913 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1914 int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1915 int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1916 int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1917 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1918 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1919 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1920 int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1921 int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1922 int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1923 int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1924 int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1925 int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1926 int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1927 int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1928 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1929 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1933 temp = I915_READ(pipeconf_reg);
1934 pipe_bpc = temp & PIPE_BPC_MASK;
1936 /* XXX: When our outputs are all unaware of DPMS modes other than off
1937 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1940 case DRM_MODE_DPMS_ON:
1941 case DRM_MODE_DPMS_STANDBY:
1942 case DRM_MODE_DPMS_SUSPEND:
1943 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
1945 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1946 temp = I915_READ(PCH_LVDS);
1947 if ((temp & LVDS_PORT_EN) == 0) {
1948 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1949 POSTING_READ(PCH_LVDS);
1955 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1956 temp = I915_READ(fdi_rx_reg);
1958 * make the BPC in FDI Rx be consistent with that in
1961 temp &= ~(0x7 << 16);
1962 temp |= (pipe_bpc << 11);
1964 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1965 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1966 I915_READ(fdi_rx_reg);
1969 /* Switch from Rawclk to PCDclk */
1970 temp = I915_READ(fdi_rx_reg);
1971 I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1972 I915_READ(fdi_rx_reg);
1975 /* Enable CPU FDI TX PLL, always on for Ironlake */
1976 temp = I915_READ(fdi_tx_reg);
1977 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1978 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1979 I915_READ(fdi_tx_reg);
1984 /* Enable panel fitting for LVDS */
1985 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
1986 || HAS_eDP || intel_pch_has_edp(crtc)) {
1987 if (dev_priv->pch_pf_size) {
1988 temp = I915_READ(pf_ctl_reg);
1989 I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1990 I915_WRITE(pf_win_pos, dev_priv->pch_pf_pos);
1991 I915_WRITE(pf_win_size, dev_priv->pch_pf_size);
1993 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1996 /* Enable CPU pipe */
1997 temp = I915_READ(pipeconf_reg);
1998 if ((temp & PIPEACONF_ENABLE) == 0) {
1999 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2000 I915_READ(pipeconf_reg);
2004 /* configure and enable CPU plane */
2005 temp = I915_READ(dspcntr_reg);
2006 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2007 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2008 /* Flush the plane changes */
2009 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2013 /* For PCH output, training FDI link */
2015 gen6_fdi_link_train(crtc);
2017 ironlake_fdi_link_train(crtc);
2019 /* enable PCH DPLL */
2020 temp = I915_READ(pch_dpll_reg);
2021 if ((temp & DPLL_VCO_ENABLE) == 0) {
2022 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
2023 I915_READ(pch_dpll_reg);
2027 if (HAS_PCH_CPT(dev)) {
2028 /* Be sure PCH DPLL SEL is set */
2029 temp = I915_READ(PCH_DPLL_SEL);
2030 if (trans_dpll_sel == 0 &&
2031 (temp & TRANSA_DPLL_ENABLE) == 0)
2032 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2033 else if (trans_dpll_sel == 1 &&
2034 (temp & TRANSB_DPLL_ENABLE) == 0)
2035 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2036 I915_WRITE(PCH_DPLL_SEL, temp);
2037 I915_READ(PCH_DPLL_SEL);
2040 /* set transcoder timing */
2041 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
2042 I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
2043 I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
2045 I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
2046 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
2047 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
2049 /* enable normal train */
2050 temp = I915_READ(fdi_tx_reg);
2051 temp &= ~FDI_LINK_TRAIN_NONE;
2052 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
2053 FDI_TX_ENHANCE_FRAME_ENABLE);
2054 I915_READ(fdi_tx_reg);
2056 temp = I915_READ(fdi_rx_reg);
2057 if (HAS_PCH_CPT(dev)) {
2058 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2059 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2061 temp &= ~FDI_LINK_TRAIN_NONE;
2062 temp |= FDI_LINK_TRAIN_NONE;
2064 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2065 I915_READ(fdi_rx_reg);
2067 /* wait one idle pattern time */
2070 /* For PCH DP, enable TRANS_DP_CTL */
2071 if (HAS_PCH_CPT(dev) &&
2072 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2073 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2076 reg = I915_READ(trans_dp_ctl);
2077 reg &= ~(TRANS_DP_PORT_SEL_MASK |
2078 TRANS_DP_SYNC_MASK);
2079 reg |= (TRANS_DP_OUTPUT_ENABLE |
2080 TRANS_DP_ENH_FRAMING);
2082 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2083 reg |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2084 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2085 reg |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2087 switch (intel_trans_dp_port_sel(crtc)) {
2089 reg |= TRANS_DP_PORT_SEL_B;
2092 reg |= TRANS_DP_PORT_SEL_C;
2095 reg |= TRANS_DP_PORT_SEL_D;
2098 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2099 reg |= TRANS_DP_PORT_SEL_B;
2103 I915_WRITE(trans_dp_ctl, reg);
2104 POSTING_READ(trans_dp_ctl);
2107 /* enable PCH transcoder */
2108 temp = I915_READ(transconf_reg);
2110 * make the BPC in transcoder be consistent with
2111 * that in pipeconf reg.
2113 temp &= ~PIPE_BPC_MASK;
2115 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
2116 I915_READ(transconf_reg);
2118 if (wait_for(I915_READ(transconf_reg) & TRANS_STATE_ENABLE, 10, 0))
2119 DRM_ERROR("failed to enable transcoder\n");
2122 intel_crtc_load_lut(crtc);
2124 intel_update_fbc(crtc, &crtc->mode);
2127 case DRM_MODE_DPMS_OFF:
2128 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2130 drm_vblank_off(dev, pipe);
2131 /* Disable display plane */
2132 temp = I915_READ(dspcntr_reg);
2133 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2134 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2135 /* Flush the plane changes */
2136 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2137 I915_READ(dspbase_reg);
2140 if (dev_priv->cfb_plane == plane &&
2141 dev_priv->display.disable_fbc)
2142 dev_priv->display.disable_fbc(dev);
2144 /* disable cpu pipe, disable after all planes disabled */
2145 temp = I915_READ(pipeconf_reg);
2146 if ((temp & PIPEACONF_ENABLE) != 0) {
2147 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2149 /* wait for cpu pipe off, pipe state */
2150 if (wait_for((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) == 0, 50, 1))
2151 DRM_ERROR("failed to turn off cpu pipe\n");
2153 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
2158 temp = I915_READ(pf_ctl_reg);
2159 if ((temp & PF_ENABLE) != 0) {
2160 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
2161 I915_READ(pf_ctl_reg);
2163 I915_WRITE(pf_win_size, 0);
2164 POSTING_READ(pf_win_size);
2167 /* disable CPU FDI tx and PCH FDI rx */
2168 temp = I915_READ(fdi_tx_reg);
2169 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
2170 I915_READ(fdi_tx_reg);
2172 temp = I915_READ(fdi_rx_reg);
2173 /* BPC in FDI rx is consistent with that in pipeconf */
2174 temp &= ~(0x07 << 16);
2175 temp |= (pipe_bpc << 11);
2176 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
2177 I915_READ(fdi_rx_reg);
2181 /* still set train pattern 1 */
2182 temp = I915_READ(fdi_tx_reg);
2183 temp &= ~FDI_LINK_TRAIN_NONE;
2184 temp |= FDI_LINK_TRAIN_PATTERN_1;
2185 I915_WRITE(fdi_tx_reg, temp);
2186 POSTING_READ(fdi_tx_reg);
2188 temp = I915_READ(fdi_rx_reg);
2189 if (HAS_PCH_CPT(dev)) {
2190 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2191 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2193 temp &= ~FDI_LINK_TRAIN_NONE;
2194 temp |= FDI_LINK_TRAIN_PATTERN_1;
2196 I915_WRITE(fdi_rx_reg, temp);
2197 POSTING_READ(fdi_rx_reg);
2201 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2202 temp = I915_READ(PCH_LVDS);
2203 I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2204 I915_READ(PCH_LVDS);
2208 /* disable PCH transcoder */
2209 temp = I915_READ(transconf_reg);
2210 if ((temp & TRANS_ENABLE) != 0) {
2211 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2213 /* wait for PCH transcoder off, transcoder state */
2214 if (wait_for((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0, 50, 1))
2215 DRM_ERROR("failed to disable transcoder\n");
2218 temp = I915_READ(transconf_reg);
2219 /* BPC in transcoder is consistent with that in pipeconf */
2220 temp &= ~PIPE_BPC_MASK;
2222 I915_WRITE(transconf_reg, temp);
2223 I915_READ(transconf_reg);
2226 if (HAS_PCH_CPT(dev)) {
2227 /* disable TRANS_DP_CTL */
2228 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2231 reg = I915_READ(trans_dp_ctl);
2232 reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2233 I915_WRITE(trans_dp_ctl, reg);
2234 POSTING_READ(trans_dp_ctl);
2236 /* disable DPLL_SEL */
2237 temp = I915_READ(PCH_DPLL_SEL);
2238 if (trans_dpll_sel == 0)
2239 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2241 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2242 I915_WRITE(PCH_DPLL_SEL, temp);
2243 I915_READ(PCH_DPLL_SEL);
2247 /* disable PCH DPLL */
2248 temp = I915_READ(pch_dpll_reg);
2249 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2250 I915_READ(pch_dpll_reg);
2252 /* Switch from PCDclk to Rawclk */
2253 temp = I915_READ(fdi_rx_reg);
2254 temp &= ~FDI_SEL_PCDCLK;
2255 I915_WRITE(fdi_rx_reg, temp);
2256 I915_READ(fdi_rx_reg);
2258 /* Disable CPU FDI TX PLL */
2259 temp = I915_READ(fdi_tx_reg);
2260 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2261 I915_READ(fdi_tx_reg);
2264 temp = I915_READ(fdi_rx_reg);
2265 temp &= ~FDI_RX_PLL_ENABLE;
2266 I915_WRITE(fdi_rx_reg, temp);
2267 I915_READ(fdi_rx_reg);
2269 /* Wait for the clocks to turn off. */
2275 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2277 struct intel_overlay *overlay;
2280 if (!enable && intel_crtc->overlay) {
2281 overlay = intel_crtc->overlay;
2282 mutex_lock(&overlay->dev->struct_mutex);
2284 ret = intel_overlay_switch_off(overlay);
2288 ret = intel_overlay_recover_from_interrupt(overlay, 0);
2290 /* overlay doesn't react anymore. Usually
2291 * results in a black screen and an unkillable
2294 overlay->hw_wedged = HW_WEDGED;
2298 mutex_unlock(&overlay->dev->struct_mutex);
2300 /* Let userspace switch the overlay on again. In most cases userspace
2301 * has to recompute where to put it anyway. */
2306 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2308 struct drm_device *dev = crtc->dev;
2309 struct drm_i915_private *dev_priv = dev->dev_private;
2310 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2311 int pipe = intel_crtc->pipe;
2312 int plane = intel_crtc->plane;
2313 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2314 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2315 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2316 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2319 /* XXX: When our outputs are all unaware of DPMS modes other than off
2320 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2323 case DRM_MODE_DPMS_ON:
2324 case DRM_MODE_DPMS_STANDBY:
2325 case DRM_MODE_DPMS_SUSPEND:
2326 /* Enable the DPLL */
2327 temp = I915_READ(dpll_reg);
2328 if ((temp & DPLL_VCO_ENABLE) == 0) {
2329 I915_WRITE(dpll_reg, temp);
2330 I915_READ(dpll_reg);
2331 /* Wait for the clocks to stabilize. */
2333 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2334 I915_READ(dpll_reg);
2335 /* Wait for the clocks to stabilize. */
2337 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2338 I915_READ(dpll_reg);
2339 /* Wait for the clocks to stabilize. */
2343 /* Enable the pipe */
2344 temp = I915_READ(pipeconf_reg);
2345 if ((temp & PIPEACONF_ENABLE) == 0)
2346 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2348 /* Enable the plane */
2349 temp = I915_READ(dspcntr_reg);
2350 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2351 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2352 /* Flush the plane changes */
2353 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2356 intel_crtc_load_lut(crtc);
2358 if ((IS_I965G(dev) || plane == 0))
2359 intel_update_fbc(crtc, &crtc->mode);
2361 /* Give the overlay scaler a chance to enable if it's on this pipe */
2362 intel_crtc_dpms_overlay(intel_crtc, true);
2364 case DRM_MODE_DPMS_OFF:
2365 /* Give the overlay scaler a chance to disable if it's on this pipe */
2366 intel_crtc_dpms_overlay(intel_crtc, false);
2367 drm_vblank_off(dev, pipe);
2369 if (dev_priv->cfb_plane == plane &&
2370 dev_priv->display.disable_fbc)
2371 dev_priv->display.disable_fbc(dev);
2373 /* Disable display plane */
2374 temp = I915_READ(dspcntr_reg);
2375 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2376 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2377 /* Flush the plane changes */
2378 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2379 I915_READ(dspbase_reg);
2382 /* Wait for vblank for the disable to take effect */
2383 intel_wait_for_vblank_off(dev, pipe);
2385 /* Don't disable pipe A or pipe A PLLs if needed */
2386 if (pipeconf_reg == PIPEACONF &&
2387 (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2390 /* Next, disable display pipes */
2391 temp = I915_READ(pipeconf_reg);
2392 if ((temp & PIPEACONF_ENABLE) != 0) {
2393 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2394 I915_READ(pipeconf_reg);
2397 /* Wait for vblank for the disable to take effect. */
2398 intel_wait_for_vblank_off(dev, pipe);
2400 temp = I915_READ(dpll_reg);
2401 if ((temp & DPLL_VCO_ENABLE) != 0) {
2402 I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2403 I915_READ(dpll_reg);
2406 /* Wait for the clocks to turn off. */
2413 * Sets the power management mode of the pipe and plane.
2415 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2417 struct drm_device *dev = crtc->dev;
2418 struct drm_i915_private *dev_priv = dev->dev_private;
2419 struct drm_i915_master_private *master_priv;
2420 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2421 int pipe = intel_crtc->pipe;
2424 intel_crtc->dpms_mode = mode;
2425 intel_crtc->cursor_on = mode == DRM_MODE_DPMS_ON;
2427 /* When switching on the display, ensure that SR is disabled
2428 * with multiple pipes prior to enabling to new pipe.
2430 * When switching off the display, make sure the cursor is
2431 * properly hidden prior to disabling the pipe.
2433 if (mode == DRM_MODE_DPMS_ON)
2434 intel_update_watermarks(dev);
2436 intel_crtc_update_cursor(crtc);
2438 dev_priv->display.dpms(crtc, mode);
2440 if (mode == DRM_MODE_DPMS_ON)
2441 intel_crtc_update_cursor(crtc);
2443 intel_update_watermarks(dev);
2445 if (!dev->primary->master)
2448 master_priv = dev->primary->master->driver_priv;
2449 if (!master_priv->sarea_priv)
2452 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2456 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2457 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2460 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2461 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2464 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2469 static void intel_crtc_prepare (struct drm_crtc *crtc)
2471 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2472 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2475 static void intel_crtc_commit (struct drm_crtc *crtc)
2477 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2478 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2481 void intel_encoder_prepare (struct drm_encoder *encoder)
2483 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2484 /* lvds has its own version of prepare see intel_lvds_prepare */
2485 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2488 void intel_encoder_commit (struct drm_encoder *encoder)
2490 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2491 /* lvds has its own version of commit see intel_lvds_commit */
2492 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2495 void intel_encoder_destroy(struct drm_encoder *encoder)
2497 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
2499 if (intel_encoder->ddc_bus)
2500 intel_i2c_destroy(intel_encoder->ddc_bus);
2502 if (intel_encoder->i2c_bus)
2503 intel_i2c_destroy(intel_encoder->i2c_bus);
2505 drm_encoder_cleanup(encoder);
2506 kfree(intel_encoder);
2509 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2510 struct drm_display_mode *mode,
2511 struct drm_display_mode *adjusted_mode)
2513 struct drm_device *dev = crtc->dev;
2514 if (HAS_PCH_SPLIT(dev)) {
2515 /* FDI link clock is fixed at 2.7G */
2516 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2522 static int i945_get_display_clock_speed(struct drm_device *dev)
2527 static int i915_get_display_clock_speed(struct drm_device *dev)
2532 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2537 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2541 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2543 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2546 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2547 case GC_DISPLAY_CLOCK_333_MHZ:
2550 case GC_DISPLAY_CLOCK_190_200_MHZ:
2556 static int i865_get_display_clock_speed(struct drm_device *dev)
2561 static int i855_get_display_clock_speed(struct drm_device *dev)
2564 /* Assume that the hardware is in the high speed state. This
2565 * should be the default.
2567 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2568 case GC_CLOCK_133_200:
2569 case GC_CLOCK_100_200:
2571 case GC_CLOCK_166_250:
2573 case GC_CLOCK_100_133:
2577 /* Shouldn't happen */
2581 static int i830_get_display_clock_speed(struct drm_device *dev)
2587 * Return the pipe currently connected to the panel fitter,
2588 * or -1 if the panel fitter is not present or not in use
2590 int intel_panel_fitter_pipe (struct drm_device *dev)
2592 struct drm_i915_private *dev_priv = dev->dev_private;
2595 /* i830 doesn't have a panel fitter */
2599 pfit_control = I915_READ(PFIT_CONTROL);
2601 /* See if the panel fitter is in use */
2602 if ((pfit_control & PFIT_ENABLE) == 0)
2605 /* 965 can place panel fitter on either pipe */
2607 return (pfit_control >> 29) & 0x3;
2609 /* older chips can only use pipe 1 */
2622 fdi_reduce_ratio(u32 *num, u32 *den)
2624 while (*num > 0xffffff || *den > 0xffffff) {
2630 #define DATA_N 0x800000
2631 #define LINK_N 0x80000
2634 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2635 int link_clock, struct fdi_m_n *m_n)
2639 m_n->tu = 64; /* default size */
2641 temp = (u64) DATA_N * pixel_clock;
2642 temp = div_u64(temp, link_clock);
2643 m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2644 m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2645 m_n->gmch_n = DATA_N;
2646 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2648 temp = (u64) LINK_N * pixel_clock;
2649 m_n->link_m = div_u64(temp, link_clock);
2650 m_n->link_n = LINK_N;
2651 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2655 struct intel_watermark_params {
2656 unsigned long fifo_size;
2657 unsigned long max_wm;
2658 unsigned long default_wm;
2659 unsigned long guard_size;
2660 unsigned long cacheline_size;
2663 /* Pineview has different values for various configs */
2664 static struct intel_watermark_params pineview_display_wm = {
2665 PINEVIEW_DISPLAY_FIFO,
2669 PINEVIEW_FIFO_LINE_SIZE
2671 static struct intel_watermark_params pineview_display_hplloff_wm = {
2672 PINEVIEW_DISPLAY_FIFO,
2674 PINEVIEW_DFT_HPLLOFF_WM,
2676 PINEVIEW_FIFO_LINE_SIZE
2678 static struct intel_watermark_params pineview_cursor_wm = {
2679 PINEVIEW_CURSOR_FIFO,
2680 PINEVIEW_CURSOR_MAX_WM,
2681 PINEVIEW_CURSOR_DFT_WM,
2682 PINEVIEW_CURSOR_GUARD_WM,
2683 PINEVIEW_FIFO_LINE_SIZE,
2685 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2686 PINEVIEW_CURSOR_FIFO,
2687 PINEVIEW_CURSOR_MAX_WM,
2688 PINEVIEW_CURSOR_DFT_WM,
2689 PINEVIEW_CURSOR_GUARD_WM,
2690 PINEVIEW_FIFO_LINE_SIZE
2692 static struct intel_watermark_params g4x_wm_info = {
2699 static struct intel_watermark_params g4x_cursor_wm_info = {
2706 static struct intel_watermark_params i965_cursor_wm_info = {
2711 I915_FIFO_LINE_SIZE,
2713 static struct intel_watermark_params i945_wm_info = {
2720 static struct intel_watermark_params i915_wm_info = {
2727 static struct intel_watermark_params i855_wm_info = {
2734 static struct intel_watermark_params i830_wm_info = {
2742 static struct intel_watermark_params ironlake_display_wm_info = {
2750 static struct intel_watermark_params ironlake_cursor_wm_info = {
2758 static struct intel_watermark_params ironlake_display_srwm_info = {
2759 ILK_DISPLAY_SR_FIFO,
2760 ILK_DISPLAY_MAX_SRWM,
2761 ILK_DISPLAY_DFT_SRWM,
2766 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2768 ILK_CURSOR_MAX_SRWM,
2769 ILK_CURSOR_DFT_SRWM,
2775 * intel_calculate_wm - calculate watermark level
2776 * @clock_in_khz: pixel clock
2777 * @wm: chip FIFO params
2778 * @pixel_size: display pixel size
2779 * @latency_ns: memory latency for the platform
2781 * Calculate the watermark level (the level at which the display plane will
2782 * start fetching from memory again). Each chip has a different display
2783 * FIFO size and allocation, so the caller needs to figure that out and pass
2784 * in the correct intel_watermark_params structure.
2786 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2787 * on the pixel size. When it reaches the watermark level, it'll start
2788 * fetching FIFO line sized based chunks from memory until the FIFO fills
2789 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2790 * will occur, and a display engine hang could result.
2792 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2793 struct intel_watermark_params *wm,
2795 unsigned long latency_ns)
2797 long entries_required, wm_size;
2800 * Note: we need to make sure we don't overflow for various clock &
2802 * clocks go from a few thousand to several hundred thousand.
2803 * latency is usually a few thousand
2805 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2807 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2809 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2811 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2813 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2815 /* Don't promote wm_size to unsigned... */
2816 if (wm_size > (long)wm->max_wm)
2817 wm_size = wm->max_wm;
2819 wm_size = wm->default_wm;
2820 DRM_ERROR("Insufficient FIFO for plane, expect flickering:"
2821 " entries required = %ld, available = %lu.\n",
2822 entries_required + wm->guard_size,
2829 struct cxsr_latency {
2832 unsigned long fsb_freq;
2833 unsigned long mem_freq;
2834 unsigned long display_sr;
2835 unsigned long display_hpll_disable;
2836 unsigned long cursor_sr;
2837 unsigned long cursor_hpll_disable;
2840 static const struct cxsr_latency cxsr_latency_table[] = {
2841 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2842 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2843 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2844 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
2845 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
2847 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2848 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2849 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2850 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
2851 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
2853 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2854 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2855 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2856 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
2857 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
2859 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2860 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2861 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2862 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
2863 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
2865 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2866 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2867 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2868 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
2869 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
2871 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2872 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2873 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2874 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
2875 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
2878 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2883 const struct cxsr_latency *latency;
2886 if (fsb == 0 || mem == 0)
2889 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2890 latency = &cxsr_latency_table[i];
2891 if (is_desktop == latency->is_desktop &&
2892 is_ddr3 == latency->is_ddr3 &&
2893 fsb == latency->fsb_freq && mem == latency->mem_freq)
2897 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2902 static void pineview_disable_cxsr(struct drm_device *dev)
2904 struct drm_i915_private *dev_priv = dev->dev_private;
2906 /* deactivate cxsr */
2907 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2911 * Latency for FIFO fetches is dependent on several factors:
2912 * - memory configuration (speed, channels)
2914 * - current MCH state
2915 * It can be fairly high in some situations, so here we assume a fairly
2916 * pessimal value. It's a tradeoff between extra memory fetches (if we
2917 * set this value too high, the FIFO will fetch frequently to stay full)
2918 * and power consumption (set it too low to save power and we might see
2919 * FIFO underruns and display "flicker").
2921 * A value of 5us seems to be a good balance; safe for very low end
2922 * platforms but not overly aggressive on lower latency configs.
2924 static const int latency_ns = 5000;
2926 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2928 struct drm_i915_private *dev_priv = dev->dev_private;
2929 uint32_t dsparb = I915_READ(DSPARB);
2932 size = dsparb & 0x7f;
2934 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
2936 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2937 plane ? "B" : "A", size);
2942 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2944 struct drm_i915_private *dev_priv = dev->dev_private;
2945 uint32_t dsparb = I915_READ(DSPARB);
2948 size = dsparb & 0x1ff;
2950 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
2951 size >>= 1; /* Convert to cachelines */
2953 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2954 plane ? "B" : "A", size);
2959 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2961 struct drm_i915_private *dev_priv = dev->dev_private;
2962 uint32_t dsparb = I915_READ(DSPARB);
2965 size = dsparb & 0x7f;
2966 size >>= 2; /* Convert to cachelines */
2968 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2975 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2977 struct drm_i915_private *dev_priv = dev->dev_private;
2978 uint32_t dsparb = I915_READ(DSPARB);
2981 size = dsparb & 0x7f;
2982 size >>= 1; /* Convert to cachelines */
2984 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2985 plane ? "B" : "A", size);
2990 static void pineview_update_wm(struct drm_device *dev, int planea_clock,
2991 int planeb_clock, int sr_hdisplay, int unused,
2994 struct drm_i915_private *dev_priv = dev->dev_private;
2995 const struct cxsr_latency *latency;
3000 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3001 dev_priv->fsb_freq, dev_priv->mem_freq);
3003 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3004 pineview_disable_cxsr(dev);
3008 if (!planea_clock || !planeb_clock) {
3009 sr_clock = planea_clock ? planea_clock : planeb_clock;
3012 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3013 pixel_size, latency->display_sr);
3014 reg = I915_READ(DSPFW1);
3015 reg &= ~DSPFW_SR_MASK;
3016 reg |= wm << DSPFW_SR_SHIFT;
3017 I915_WRITE(DSPFW1, reg);
3018 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3021 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3022 pixel_size, latency->cursor_sr);
3023 reg = I915_READ(DSPFW3);
3024 reg &= ~DSPFW_CURSOR_SR_MASK;
3025 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3026 I915_WRITE(DSPFW3, reg);
3028 /* Display HPLL off SR */
3029 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3030 pixel_size, latency->display_hpll_disable);
3031 reg = I915_READ(DSPFW3);
3032 reg &= ~DSPFW_HPLL_SR_MASK;
3033 reg |= wm & DSPFW_HPLL_SR_MASK;
3034 I915_WRITE(DSPFW3, reg);
3036 /* cursor HPLL off SR */
3037 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3038 pixel_size, latency->cursor_hpll_disable);
3039 reg = I915_READ(DSPFW3);
3040 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3041 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3042 I915_WRITE(DSPFW3, reg);
3043 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3047 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3048 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3050 pineview_disable_cxsr(dev);
3051 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3055 static void g4x_update_wm(struct drm_device *dev, int planea_clock,
3056 int planeb_clock, int sr_hdisplay, int sr_htotal,
3059 struct drm_i915_private *dev_priv = dev->dev_private;
3060 int total_size, cacheline_size;
3061 int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3062 struct intel_watermark_params planea_params, planeb_params;
3063 unsigned long line_time_us;
3064 int sr_clock, sr_entries = 0, entries_required;
3066 /* Create copies of the base settings for each pipe */
3067 planea_params = planeb_params = g4x_wm_info;
3069 /* Grab a couple of global values before we overwrite them */
3070 total_size = planea_params.fifo_size;
3071 cacheline_size = planea_params.cacheline_size;
3074 * Note: we need to make sure we don't overflow for various clock &
3076 * clocks go from a few thousand to several hundred thousand.
3077 * latency is usually a few thousand
3079 entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3081 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3082 planea_wm = entries_required + planea_params.guard_size;
3084 entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3086 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3087 planeb_wm = entries_required + planeb_params.guard_size;
3089 cursora_wm = cursorb_wm = 16;
3092 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3094 /* Calc sr entries for one plane configs */
3095 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3096 /* self-refresh has much higher latency */
3097 static const int sr_latency_ns = 12000;
3099 sr_clock = planea_clock ? planea_clock : planeb_clock;
3100 line_time_us = ((sr_htotal * 1000) / sr_clock);
3102 /* Use ns/us then divide to preserve precision */
3103 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3104 pixel_size * sr_hdisplay;
3105 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3107 entries_required = (((sr_latency_ns / line_time_us) +
3108 1000) / 1000) * pixel_size * 64;
3109 entries_required = DIV_ROUND_UP(entries_required,
3110 g4x_cursor_wm_info.cacheline_size);
3111 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3113 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3114 cursor_sr = g4x_cursor_wm_info.max_wm;
3115 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3116 "cursor %d\n", sr_entries, cursor_sr);
3118 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3120 /* Turn off self refresh if both pipes are enabled */
3121 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3125 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3126 planea_wm, planeb_wm, sr_entries);
3131 I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3132 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3133 (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3134 I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3135 (cursora_wm << DSPFW_CURSORA_SHIFT));
3136 /* HPLL off in SR has some issues on G4x... disable it */
3137 I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3138 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3141 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3142 int planeb_clock, int sr_hdisplay, int sr_htotal,
3145 struct drm_i915_private *dev_priv = dev->dev_private;
3146 unsigned long line_time_us;
3147 int sr_clock, sr_entries, srwm = 1;
3150 /* Calc sr entries for one plane configs */
3151 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3152 /* self-refresh has much higher latency */
3153 static const int sr_latency_ns = 12000;
3155 sr_clock = planea_clock ? planea_clock : planeb_clock;
3156 line_time_us = ((sr_htotal * 1000) / sr_clock);
3158 /* Use ns/us then divide to preserve precision */
3159 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3160 pixel_size * sr_hdisplay;
3161 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3162 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3163 srwm = I965_FIFO_SIZE - sr_entries;
3168 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3170 sr_entries = DIV_ROUND_UP(sr_entries,
3171 i965_cursor_wm_info.cacheline_size);
3172 cursor_sr = i965_cursor_wm_info.fifo_size -
3173 (sr_entries + i965_cursor_wm_info.guard_size);
3175 if (cursor_sr > i965_cursor_wm_info.max_wm)
3176 cursor_sr = i965_cursor_wm_info.max_wm;
3178 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3179 "cursor %d\n", srwm, cursor_sr);
3182 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3184 /* Turn off self refresh if both pipes are enabled */
3186 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3190 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3193 /* 965 has limitations... */
3194 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3196 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3197 /* update cursor SR watermark */
3198 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3201 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3202 int planeb_clock, int sr_hdisplay, int sr_htotal,
3205 struct drm_i915_private *dev_priv = dev->dev_private;
3208 int total_size, cacheline_size, cwm, srwm = 1;
3209 int planea_wm, planeb_wm;
3210 struct intel_watermark_params planea_params, planeb_params;
3211 unsigned long line_time_us;
3212 int sr_clock, sr_entries = 0;
3214 /* Create copies of the base settings for each pipe */
3215 if (IS_I965GM(dev) || IS_I945GM(dev))
3216 planea_params = planeb_params = i945_wm_info;
3217 else if (IS_I9XX(dev))
3218 planea_params = planeb_params = i915_wm_info;
3220 planea_params = planeb_params = i855_wm_info;
3222 /* Grab a couple of global values before we overwrite them */
3223 total_size = planea_params.fifo_size;
3224 cacheline_size = planea_params.cacheline_size;
3226 /* Update per-plane FIFO sizes */
3227 planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3228 planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3230 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3231 pixel_size, latency_ns);
3232 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3233 pixel_size, latency_ns);
3234 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3237 * Overlay gets an aggressive default since video jitter is bad.
3241 /* Calc sr entries for one plane configs */
3242 if (HAS_FW_BLC(dev) && sr_hdisplay &&
3243 (!planea_clock || !planeb_clock)) {
3244 /* self-refresh has much higher latency */
3245 static const int sr_latency_ns = 6000;
3247 sr_clock = planea_clock ? planea_clock : planeb_clock;
3248 line_time_us = ((sr_htotal * 1000) / sr_clock);
3250 /* Use ns/us then divide to preserve precision */
3251 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3252 pixel_size * sr_hdisplay;
3253 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3254 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3255 srwm = total_size - sr_entries;
3259 if (IS_I945G(dev) || IS_I945GM(dev))
3260 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3261 else if (IS_I915GM(dev)) {
3262 /* 915M has a smaller SRWM field */
3263 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3264 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3267 /* Turn off self refresh if both pipes are enabled */
3268 if (IS_I945G(dev) || IS_I945GM(dev)) {
3269 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3271 } else if (IS_I915GM(dev)) {
3272 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3276 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3277 planea_wm, planeb_wm, cwm, srwm);
3279 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3280 fwater_hi = (cwm & 0x1f);
3282 /* Set request length to 8 cachelines per fetch */
3283 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3284 fwater_hi = fwater_hi | (1 << 8);
3286 I915_WRITE(FW_BLC, fwater_lo);
3287 I915_WRITE(FW_BLC2, fwater_hi);
3290 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3291 int unused2, int unused3, int pixel_size)
3293 struct drm_i915_private *dev_priv = dev->dev_private;
3294 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3297 i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3299 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3300 pixel_size, latency_ns);
3301 fwater_lo |= (3<<8) | planea_wm;
3303 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3305 I915_WRITE(FW_BLC, fwater_lo);
3308 #define ILK_LP0_PLANE_LATENCY 700
3309 #define ILK_LP0_CURSOR_LATENCY 1300
3311 static void ironlake_update_wm(struct drm_device *dev, int planea_clock,
3312 int planeb_clock, int sr_hdisplay, int sr_htotal,
3315 struct drm_i915_private *dev_priv = dev->dev_private;
3316 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3317 int sr_wm, cursor_wm;
3318 unsigned long line_time_us;
3319 int sr_clock, entries_required;
3322 int planea_htotal = 0, planeb_htotal = 0;
3323 struct drm_crtc *crtc;
3325 /* Need htotal for all active display plane */
3326 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3327 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3328 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
3329 if (intel_crtc->plane == 0)
3330 planea_htotal = crtc->mode.htotal;
3332 planeb_htotal = crtc->mode.htotal;
3336 /* Calculate and update the watermark for plane A */
3338 entries_required = ((planea_clock / 1000) * pixel_size *
3339 ILK_LP0_PLANE_LATENCY) / 1000;
3340 entries_required = DIV_ROUND_UP(entries_required,
3341 ironlake_display_wm_info.cacheline_size);
3342 planea_wm = entries_required +
3343 ironlake_display_wm_info.guard_size;
3345 if (planea_wm > (int)ironlake_display_wm_info.max_wm)
3346 planea_wm = ironlake_display_wm_info.max_wm;
3348 /* Use the large buffer method to calculate cursor watermark */
3349 line_time_us = (planea_htotal * 1000) / planea_clock;
3351 /* Use ns/us then divide to preserve precision */
3352 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3354 /* calculate the cursor watermark for cursor A */
3355 entries_required = line_count * 64 * pixel_size;
3356 entries_required = DIV_ROUND_UP(entries_required,
3357 ironlake_cursor_wm_info.cacheline_size);
3358 cursora_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3359 if (cursora_wm > ironlake_cursor_wm_info.max_wm)
3360 cursora_wm = ironlake_cursor_wm_info.max_wm;
3362 reg_value = I915_READ(WM0_PIPEA_ILK);
3363 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3364 reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
3365 (cursora_wm & WM0_PIPE_CURSOR_MASK);
3366 I915_WRITE(WM0_PIPEA_ILK, reg_value);
3367 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3368 "cursor: %d\n", planea_wm, cursora_wm);
3370 /* Calculate and update the watermark for plane B */
3372 entries_required = ((planeb_clock / 1000) * pixel_size *
3373 ILK_LP0_PLANE_LATENCY) / 1000;
3374 entries_required = DIV_ROUND_UP(entries_required,
3375 ironlake_display_wm_info.cacheline_size);
3376 planeb_wm = entries_required +
3377 ironlake_display_wm_info.guard_size;
3379 if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
3380 planeb_wm = ironlake_display_wm_info.max_wm;
3382 /* Use the large buffer method to calculate cursor watermark */
3383 line_time_us = (planeb_htotal * 1000) / planeb_clock;
3385 /* Use ns/us then divide to preserve precision */
3386 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3388 /* calculate the cursor watermark for cursor B */
3389 entries_required = line_count * 64 * pixel_size;
3390 entries_required = DIV_ROUND_UP(entries_required,
3391 ironlake_cursor_wm_info.cacheline_size);
3392 cursorb_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3393 if (cursorb_wm > ironlake_cursor_wm_info.max_wm)
3394 cursorb_wm = ironlake_cursor_wm_info.max_wm;
3396 reg_value = I915_READ(WM0_PIPEB_ILK);
3397 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3398 reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
3399 (cursorb_wm & WM0_PIPE_CURSOR_MASK);
3400 I915_WRITE(WM0_PIPEB_ILK, reg_value);
3401 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3402 "cursor: %d\n", planeb_wm, cursorb_wm);
3406 * Calculate and update the self-refresh watermark only when one
3407 * display plane is used.
3409 if (!planea_clock || !planeb_clock) {
3411 /* Read the self-refresh latency. The unit is 0.5us */
3412 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3414 sr_clock = planea_clock ? planea_clock : planeb_clock;
3415 line_time_us = ((sr_htotal * 1000) / sr_clock);
3417 /* Use ns/us then divide to preserve precision */
3418 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3421 /* calculate the self-refresh watermark for display plane */
3422 entries_required = line_count * sr_hdisplay * pixel_size;
3423 entries_required = DIV_ROUND_UP(entries_required,
3424 ironlake_display_srwm_info.cacheline_size);
3425 sr_wm = entries_required +
3426 ironlake_display_srwm_info.guard_size;
3428 /* calculate the self-refresh watermark for display cursor */
3429 entries_required = line_count * pixel_size * 64;
3430 entries_required = DIV_ROUND_UP(entries_required,
3431 ironlake_cursor_srwm_info.cacheline_size);
3432 cursor_wm = entries_required +
3433 ironlake_cursor_srwm_info.guard_size;
3435 /* configure watermark and enable self-refresh */
3436 reg_value = I915_READ(WM1_LP_ILK);
3437 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
3438 WM1_LP_CURSOR_MASK);
3439 reg_value |= WM1_LP_SR_EN |
3440 (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3441 (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
3443 I915_WRITE(WM1_LP_ILK, reg_value);
3444 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3445 "cursor %d\n", sr_wm, cursor_wm);
3448 /* Turn off self refresh if both pipes are enabled */
3449 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
3453 * intel_update_watermarks - update FIFO watermark values based on current modes
3455 * Calculate watermark values for the various WM regs based on current mode
3456 * and plane configuration.
3458 * There are several cases to deal with here:
3459 * - normal (i.e. non-self-refresh)
3460 * - self-refresh (SR) mode
3461 * - lines are large relative to FIFO size (buffer can hold up to 2)
3462 * - lines are small relative to FIFO size (buffer can hold more than 2
3463 * lines), so need to account for TLB latency
3465 * The normal calculation is:
3466 * watermark = dotclock * bytes per pixel * latency
3467 * where latency is platform & configuration dependent (we assume pessimal
3470 * The SR calculation is:
3471 * watermark = (trunc(latency/line time)+1) * surface width *
3474 * line time = htotal / dotclock
3475 * surface width = hdisplay for normal plane and 64 for cursor
3476 * and latency is assumed to be high, as above.
3478 * The final value programmed to the register should always be rounded up,
3479 * and include an extra 2 entries to account for clock crossings.
3481 * We don't use the sprite, so we can ignore that. And on Crestline we have
3482 * to set the non-SR watermarks to 8.
3484 static void intel_update_watermarks(struct drm_device *dev)
3486 struct drm_i915_private *dev_priv = dev->dev_private;
3487 struct drm_crtc *crtc;
3488 int sr_hdisplay = 0;
3489 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3490 int enabled = 0, pixel_size = 0;
3493 if (!dev_priv->display.update_wm)
3496 /* Get the clock config from both planes */
3497 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3498 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3499 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
3501 if (intel_crtc->plane == 0) {
3502 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3503 intel_crtc->pipe, crtc->mode.clock);
3504 planea_clock = crtc->mode.clock;
3506 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3507 intel_crtc->pipe, crtc->mode.clock);
3508 planeb_clock = crtc->mode.clock;
3510 sr_hdisplay = crtc->mode.hdisplay;
3511 sr_clock = crtc->mode.clock;
3512 sr_htotal = crtc->mode.htotal;
3514 pixel_size = crtc->fb->bits_per_pixel / 8;
3516 pixel_size = 4; /* by default */
3523 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3524 sr_hdisplay, sr_htotal, pixel_size);
3527 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3528 struct drm_display_mode *mode,
3529 struct drm_display_mode *adjusted_mode,
3531 struct drm_framebuffer *old_fb)
3533 struct drm_device *dev = crtc->dev;
3534 struct drm_i915_private *dev_priv = dev->dev_private;
3535 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3536 int pipe = intel_crtc->pipe;
3537 int plane = intel_crtc->plane;
3538 int fp_reg = (pipe == 0) ? FPA0 : FPB0;
3539 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3540 int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
3541 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
3542 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
3543 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
3544 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
3545 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
3546 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
3547 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
3548 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
3549 int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
3550 int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
3551 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
3552 int refclk, num_connectors = 0;
3553 intel_clock_t clock, reduced_clock;
3554 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3555 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3556 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3557 bool is_edp = false;
3558 struct drm_mode_config *mode_config = &dev->mode_config;
3559 struct drm_encoder *encoder;
3560 struct intel_encoder *intel_encoder = NULL;
3561 const intel_limit_t *limit;
3563 struct fdi_m_n m_n = {0};
3564 int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
3565 int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
3566 int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
3567 int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
3568 int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
3569 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
3570 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
3571 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
3572 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
3573 int lvds_reg = LVDS;
3575 int sdvo_pixel_multiply;
3578 drm_vblank_pre_modeset(dev, pipe);
3580 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
3582 if (!encoder || encoder->crtc != crtc)
3585 intel_encoder = enc_to_intel_encoder(encoder);
3587 switch (intel_encoder->type) {
3588 case INTEL_OUTPUT_LVDS:
3591 case INTEL_OUTPUT_SDVO:
3592 case INTEL_OUTPUT_HDMI:
3594 if (intel_encoder->needs_tv_clock)
3597 case INTEL_OUTPUT_DVO:
3600 case INTEL_OUTPUT_TVOUT:
3603 case INTEL_OUTPUT_ANALOG:
3606 case INTEL_OUTPUT_DISPLAYPORT:
3609 case INTEL_OUTPUT_EDP:
3617 if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3618 refclk = dev_priv->lvds_ssc_freq * 1000;
3619 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3621 } else if (IS_I9XX(dev)) {
3623 if (HAS_PCH_SPLIT(dev))
3624 refclk = 120000; /* 120Mhz refclk */
3631 * Returns a set of divisors for the desired target clock with the given
3632 * refclk, or FALSE. The returned values represent the clock equation:
3633 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3635 limit = intel_limit(crtc);
3636 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3638 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3639 drm_vblank_post_modeset(dev, pipe);
3643 /* Ensure that the cursor is valid for the new mode before changing... */
3644 intel_crtc_update_cursor(crtc);
3646 if (is_lvds && dev_priv->lvds_downclock_avail) {
3647 has_reduced_clock = limit->find_pll(limit, crtc,
3648 dev_priv->lvds_downclock,
3651 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3653 * If the different P is found, it means that we can't
3654 * switch the display clock by using the FP0/FP1.
3655 * In such case we will disable the LVDS downclock
3658 DRM_DEBUG_KMS("Different P is found for "
3659 "LVDS clock/downclock\n");
3660 has_reduced_clock = 0;
3663 /* SDVO TV has fixed PLL values depend on its clock range,
3664 this mirrors vbios setting. */
3665 if (is_sdvo && is_tv) {
3666 if (adjusted_mode->clock >= 100000
3667 && adjusted_mode->clock < 140500) {
3673 } else if (adjusted_mode->clock >= 140500
3674 && adjusted_mode->clock <= 200000) {
3684 if (HAS_PCH_SPLIT(dev)) {
3685 int lane = 0, link_bw, bpp;
3686 /* eDP doesn't require FDI link, so just set DP M/N
3687 according to current link config */
3689 target_clock = mode->clock;
3690 intel_edp_link_config(intel_encoder,
3693 /* DP over FDI requires target mode clock
3694 instead of link clock */
3696 target_clock = mode->clock;
3698 target_clock = adjusted_mode->clock;
3702 /* determine panel color depth */
3703 temp = I915_READ(pipeconf_reg);
3704 temp &= ~PIPE_BPC_MASK;
3706 int lvds_reg = I915_READ(PCH_LVDS);
3707 /* the BPC will be 6 if it is 18-bit LVDS panel */
3708 if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3712 } else if (is_edp || (is_dp && intel_pch_has_edp(crtc))) {
3713 switch (dev_priv->edp_bpp/3) {
3729 I915_WRITE(pipeconf_reg, temp);
3730 I915_READ(pipeconf_reg);
3732 switch (temp & PIPE_BPC_MASK) {
3746 DRM_ERROR("unknown pipe bpc value\n");
3752 * Account for spread spectrum to avoid
3753 * oversubscribing the link. Max center spread
3754 * is 2.5%; use 5% for safety's sake.
3756 u32 bps = target_clock * bpp * 21 / 20;
3757 lane = bps / (link_bw * 8) + 1;
3760 intel_crtc->fdi_lanes = lane;
3762 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3765 /* Ironlake: try to setup display ref clock before DPLL
3766 * enabling. This is only under driver's control after
3767 * PCH B stepping, previous chipset stepping should be
3768 * ignoring this setting.
3770 if (HAS_PCH_SPLIT(dev)) {
3771 temp = I915_READ(PCH_DREF_CONTROL);
3772 /* Always enable nonspread source */
3773 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3774 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3775 I915_WRITE(PCH_DREF_CONTROL, temp);
3776 POSTING_READ(PCH_DREF_CONTROL);
3778 temp &= ~DREF_SSC_SOURCE_MASK;
3779 temp |= DREF_SSC_SOURCE_ENABLE;
3780 I915_WRITE(PCH_DREF_CONTROL, temp);
3781 POSTING_READ(PCH_DREF_CONTROL);
3786 if (dev_priv->lvds_use_ssc) {
3787 temp |= DREF_SSC1_ENABLE;
3788 I915_WRITE(PCH_DREF_CONTROL, temp);
3789 POSTING_READ(PCH_DREF_CONTROL);
3793 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3794 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3795 I915_WRITE(PCH_DREF_CONTROL, temp);
3796 POSTING_READ(PCH_DREF_CONTROL);
3798 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3799 I915_WRITE(PCH_DREF_CONTROL, temp);
3800 POSTING_READ(PCH_DREF_CONTROL);
3805 if (IS_PINEVIEW(dev)) {
3806 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3807 if (has_reduced_clock)
3808 fp2 = (1 << reduced_clock.n) << 16 |
3809 reduced_clock.m1 << 8 | reduced_clock.m2;
3811 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3812 if (has_reduced_clock)
3813 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3817 if (!HAS_PCH_SPLIT(dev))
3818 dpll = DPLL_VGA_MODE_DIS;
3822 dpll |= DPLLB_MODE_LVDS;
3824 dpll |= DPLLB_MODE_DAC_SERIAL;
3826 dpll |= DPLL_DVO_HIGH_SPEED;
3827 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3828 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3829 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3830 else if (HAS_PCH_SPLIT(dev))
3831 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3834 dpll |= DPLL_DVO_HIGH_SPEED;
3836 /* compute bitmask from p1 value */
3837 if (IS_PINEVIEW(dev))
3838 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3840 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3842 if (HAS_PCH_SPLIT(dev))
3843 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3844 if (IS_G4X(dev) && has_reduced_clock)
3845 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3849 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3852 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3855 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3858 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3861 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3862 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3865 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3868 dpll |= PLL_P1_DIVIDE_BY_TWO;
3870 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3872 dpll |= PLL_P2_DIVIDE_BY_4;
3876 if (is_sdvo && is_tv)
3877 dpll |= PLL_REF_INPUT_TVCLKINBC;
3879 /* XXX: just matching BIOS for now */
3880 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3882 else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3883 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3885 dpll |= PLL_REF_INPUT_DREFCLK;
3887 /* setup pipeconf */
3888 pipeconf = I915_READ(pipeconf_reg);
3890 /* Set up the display plane register */
3891 dspcntr = DISPPLANE_GAMMA_ENABLE;
3893 /* Ironlake's plane is forced to pipe, bit 24 is to
3894 enable color space conversion */
3895 if (!HAS_PCH_SPLIT(dev)) {
3897 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3899 dspcntr |= DISPPLANE_SEL_PIPE_B;
3902 if (pipe == 0 && !IS_I965G(dev)) {
3903 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3906 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3910 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3911 pipeconf |= PIPEACONF_DOUBLE_WIDE;
3913 pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3916 dspcntr |= DISPLAY_PLANE_ENABLE;
3917 pipeconf |= PIPEACONF_ENABLE;
3918 dpll |= DPLL_VCO_ENABLE;
3921 /* Disable the panel fitter if it was on our pipe */
3922 if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
3923 I915_WRITE(PFIT_CONTROL, 0);
3925 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3926 drm_mode_debug_printmodeline(mode);
3928 /* assign to Ironlake registers */
3929 if (HAS_PCH_SPLIT(dev)) {
3930 fp_reg = pch_fp_reg;
3931 dpll_reg = pch_dpll_reg;
3935 I915_WRITE(fp_reg, fp);
3936 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3937 I915_READ(dpll_reg);
3941 /* enable transcoder DPLL */
3942 if (HAS_PCH_CPT(dev)) {
3943 temp = I915_READ(PCH_DPLL_SEL);
3944 if (trans_dpll_sel == 0)
3945 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3947 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3948 I915_WRITE(PCH_DPLL_SEL, temp);
3949 I915_READ(PCH_DPLL_SEL);
3953 if (HAS_PCH_SPLIT(dev)) {
3954 pipeconf &= ~PIPE_ENABLE_DITHER;
3955 pipeconf &= ~PIPE_DITHER_TYPE_MASK;
3958 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3959 * This is an exception to the general rule that mode_set doesn't turn
3965 if (HAS_PCH_SPLIT(dev))
3966 lvds_reg = PCH_LVDS;
3968 lvds = I915_READ(lvds_reg);
3969 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3971 if (HAS_PCH_CPT(dev))
3972 lvds |= PORT_TRANS_B_SEL_CPT;
3974 lvds |= LVDS_PIPEB_SELECT;
3976 if (HAS_PCH_CPT(dev))
3977 lvds &= ~PORT_TRANS_SEL_MASK;
3979 lvds &= ~LVDS_PIPEB_SELECT;
3981 /* set the corresponsding LVDS_BORDER bit */
3982 lvds |= dev_priv->lvds_border_bits;
3983 /* Set the B0-B3 data pairs corresponding to whether we're going to
3984 * set the DPLLs for dual-channel mode or not.
3987 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3989 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3991 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3992 * appropriately here, but we need to look more thoroughly into how
3993 * panels behave in the two modes.
3995 /* set the dithering flag */
3996 if (IS_I965G(dev)) {
3997 if (dev_priv->lvds_dither) {
3998 if (HAS_PCH_SPLIT(dev)) {
3999 pipeconf |= PIPE_ENABLE_DITHER;
4000 pipeconf |= PIPE_DITHER_TYPE_ST01;
4002 lvds |= LVDS_ENABLE_DITHER;
4004 if (!HAS_PCH_SPLIT(dev)) {
4005 lvds &= ~LVDS_ENABLE_DITHER;
4009 I915_WRITE(lvds_reg, lvds);
4010 I915_READ(lvds_reg);
4013 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4014 else if (HAS_PCH_SPLIT(dev)) {
4015 /* For non-DP output, clear any trans DP clock recovery setting.*/
4017 I915_WRITE(TRANSA_DATA_M1, 0);
4018 I915_WRITE(TRANSA_DATA_N1, 0);
4019 I915_WRITE(TRANSA_DP_LINK_M1, 0);
4020 I915_WRITE(TRANSA_DP_LINK_N1, 0);
4022 I915_WRITE(TRANSB_DATA_M1, 0);
4023 I915_WRITE(TRANSB_DATA_N1, 0);
4024 I915_WRITE(TRANSB_DP_LINK_M1, 0);
4025 I915_WRITE(TRANSB_DP_LINK_N1, 0);
4030 I915_WRITE(fp_reg, fp);
4031 I915_WRITE(dpll_reg, dpll);
4032 I915_READ(dpll_reg);
4033 /* Wait for the clocks to stabilize. */
4036 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
4038 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
4039 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
4040 ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
4042 I915_WRITE(dpll_md_reg, 0);
4044 /* write it again -- the BIOS does, after all */
4045 I915_WRITE(dpll_reg, dpll);
4047 I915_READ(dpll_reg);
4048 /* Wait for the clocks to stabilize. */
4052 if (is_lvds && has_reduced_clock && i915_powersave) {
4053 I915_WRITE(fp_reg + 4, fp2);
4054 intel_crtc->lowfreq_avail = true;
4055 if (HAS_PIPE_CXSR(dev)) {
4056 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4057 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4060 I915_WRITE(fp_reg + 4, fp);
4061 intel_crtc->lowfreq_avail = false;
4062 if (HAS_PIPE_CXSR(dev)) {
4063 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4064 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4068 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4069 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4070 /* the chip adds 2 halflines automatically */
4071 adjusted_mode->crtc_vdisplay -= 1;
4072 adjusted_mode->crtc_vtotal -= 1;
4073 adjusted_mode->crtc_vblank_start -= 1;
4074 adjusted_mode->crtc_vblank_end -= 1;
4075 adjusted_mode->crtc_vsync_end -= 1;
4076 adjusted_mode->crtc_vsync_start -= 1;
4078 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4080 I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
4081 ((adjusted_mode->crtc_htotal - 1) << 16));
4082 I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
4083 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4084 I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
4085 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4086 I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
4087 ((adjusted_mode->crtc_vtotal - 1) << 16));
4088 I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
4089 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4090 I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
4091 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4092 /* pipesrc and dspsize control the size that is scaled from, which should
4093 * always be the user's requested size.
4095 if (!HAS_PCH_SPLIT(dev)) {
4096 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
4097 (mode->hdisplay - 1));
4098 I915_WRITE(dsppos_reg, 0);
4100 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4102 if (HAS_PCH_SPLIT(dev)) {
4103 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
4104 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
4105 I915_WRITE(link_m1_reg, m_n.link_m);
4106 I915_WRITE(link_n1_reg, m_n.link_n);
4109 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4111 /* enable FDI RX PLL too */
4112 temp = I915_READ(fdi_rx_reg);
4113 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
4114 I915_READ(fdi_rx_reg);
4117 /* enable FDI TX PLL too */
4118 temp = I915_READ(fdi_tx_reg);
4119 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
4120 I915_READ(fdi_tx_reg);
4122 /* enable FDI RX PCDCLK */
4123 temp = I915_READ(fdi_rx_reg);
4124 I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
4125 I915_READ(fdi_rx_reg);
4130 I915_WRITE(pipeconf_reg, pipeconf);
4131 I915_READ(pipeconf_reg);
4133 intel_wait_for_vblank(dev, pipe);
4135 if (IS_IRONLAKE(dev)) {
4136 /* enable address swizzle for tiling buffer */
4137 temp = I915_READ(DISP_ARB_CTL);
4138 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4141 I915_WRITE(dspcntr_reg, dspcntr);
4143 /* Flush the plane changes */
4144 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4146 intel_update_watermarks(dev);
4148 drm_vblank_post_modeset(dev, pipe);
4153 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4154 void intel_crtc_load_lut(struct drm_crtc *crtc)
4156 struct drm_device *dev = crtc->dev;
4157 struct drm_i915_private *dev_priv = dev->dev_private;
4158 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4159 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4162 /* The clocks have to be on to load the palette. */
4166 /* use legacy palette for Ironlake */
4167 if (HAS_PCH_SPLIT(dev))
4168 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4171 for (i = 0; i < 256; i++) {
4172 I915_WRITE(palreg + 4 * i,
4173 (intel_crtc->lut_r[i] << 16) |
4174 (intel_crtc->lut_g[i] << 8) |
4175 intel_crtc->lut_b[i]);
4179 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4181 struct drm_device *dev = crtc->dev;
4182 struct drm_i915_private *dev_priv = dev->dev_private;
4183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4184 bool visible = base != 0;
4187 if (intel_crtc->cursor_visible == visible)
4190 cntl = I915_READ(CURACNTR);
4192 /* On these chipsets we can only modify the base whilst
4193 * the cursor is disabled.
4195 I915_WRITE(CURABASE, base);
4197 cntl &= ~(CURSOR_FORMAT_MASK);
4198 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4199 cntl |= CURSOR_ENABLE |
4200 CURSOR_GAMMA_ENABLE |
4203 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4204 I915_WRITE(CURACNTR, cntl);
4206 intel_crtc->cursor_visible = visible;
4209 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4211 struct drm_device *dev = crtc->dev;
4212 struct drm_i915_private *dev_priv = dev->dev_private;
4213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4214 int pipe = intel_crtc->pipe;
4215 bool visible = base != 0;
4217 if (intel_crtc->cursor_visible != visible) {
4218 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4220 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4221 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4222 cntl |= pipe << 28; /* Connect to correct pipe */
4224 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4225 cntl |= CURSOR_MODE_DISABLE;
4227 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4229 intel_crtc->cursor_visible = visible;
4231 /* and commit changes on next vblank */
4232 I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4235 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4236 static void intel_crtc_update_cursor(struct drm_crtc *crtc)
4238 struct drm_device *dev = crtc->dev;
4239 struct drm_i915_private *dev_priv = dev->dev_private;
4240 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4241 int pipe = intel_crtc->pipe;
4242 int x = intel_crtc->cursor_x;
4243 int y = intel_crtc->cursor_y;
4249 if (intel_crtc->cursor_on && crtc->fb) {
4250 base = intel_crtc->cursor_addr;
4251 if (x > (int) crtc->fb->width)
4254 if (y > (int) crtc->fb->height)
4260 if (x + intel_crtc->cursor_width < 0)
4263 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4266 pos |= x << CURSOR_X_SHIFT;
4269 if (y + intel_crtc->cursor_height < 0)
4272 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4275 pos |= y << CURSOR_Y_SHIFT;
4277 visible = base != 0;
4278 if (!visible && !intel_crtc->cursor_visible)
4281 I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4282 if (IS_845G(dev) || IS_I865G(dev))
4283 i845_update_cursor(crtc, base);
4285 i9xx_update_cursor(crtc, base);
4288 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4291 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4292 struct drm_file *file_priv,
4294 uint32_t width, uint32_t height)
4296 struct drm_device *dev = crtc->dev;
4297 struct drm_i915_private *dev_priv = dev->dev_private;
4298 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4299 struct drm_gem_object *bo;
4300 struct drm_i915_gem_object *obj_priv;
4304 DRM_DEBUG_KMS("\n");
4306 /* if we want to turn off the cursor ignore width and height */
4308 DRM_DEBUG_KMS("cursor off\n");
4311 mutex_lock(&dev->struct_mutex);
4315 /* Currently we only support 64x64 cursors */
4316 if (width != 64 || height != 64) {
4317 DRM_ERROR("we currently only support 64x64 cursors\n");
4321 bo = drm_gem_object_lookup(dev, file_priv, handle);
4325 obj_priv = to_intel_bo(bo);
4327 if (bo->size < width * height * 4) {
4328 DRM_ERROR("buffer is to small\n");
4333 /* we only need to pin inside GTT if cursor is non-phy */
4334 mutex_lock(&dev->struct_mutex);
4335 if (!dev_priv->info->cursor_needs_physical) {
4336 ret = i915_gem_object_pin(bo, PAGE_SIZE);
4338 DRM_ERROR("failed to pin cursor bo\n");
4342 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4344 DRM_ERROR("failed to move cursor bo into the GTT\n");
4348 addr = obj_priv->gtt_offset;
4350 int align = IS_I830(dev) ? 16 * 1024 : 256;
4351 ret = i915_gem_attach_phys_object(dev, bo,
4352 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4355 DRM_ERROR("failed to attach phys object\n");
4358 addr = obj_priv->phys_obj->handle->busaddr;
4362 I915_WRITE(CURSIZE, (height << 12) | width);
4365 if (intel_crtc->cursor_bo) {
4366 if (dev_priv->info->cursor_needs_physical) {
4367 if (intel_crtc->cursor_bo != bo)
4368 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4370 i915_gem_object_unpin(intel_crtc->cursor_bo);
4371 drm_gem_object_unreference(intel_crtc->cursor_bo);
4374 mutex_unlock(&dev->struct_mutex);
4376 intel_crtc->cursor_addr = addr;
4377 intel_crtc->cursor_bo = bo;
4378 intel_crtc->cursor_width = width;
4379 intel_crtc->cursor_height = height;
4381 intel_crtc_update_cursor(crtc);
4385 i915_gem_object_unpin(bo);
4387 mutex_unlock(&dev->struct_mutex);
4389 drm_gem_object_unreference_unlocked(bo);
4393 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4397 intel_crtc->cursor_x = x;
4398 intel_crtc->cursor_y = y;
4400 intel_crtc_update_cursor(crtc);
4405 /** Sets the color ramps on behalf of RandR */
4406 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4407 u16 blue, int regno)
4409 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4411 intel_crtc->lut_r[regno] = red >> 8;
4412 intel_crtc->lut_g[regno] = green >> 8;
4413 intel_crtc->lut_b[regno] = blue >> 8;
4416 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4417 u16 *blue, int regno)
4419 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4421 *red = intel_crtc->lut_r[regno] << 8;
4422 *green = intel_crtc->lut_g[regno] << 8;
4423 *blue = intel_crtc->lut_b[regno] << 8;
4426 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4427 u16 *blue, uint32_t start, uint32_t size)
4429 int end = (start + size > 256) ? 256 : start + size, i;
4430 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4432 for (i = start; i < end; i++) {
4433 intel_crtc->lut_r[i] = red[i] >> 8;
4434 intel_crtc->lut_g[i] = green[i] >> 8;
4435 intel_crtc->lut_b[i] = blue[i] >> 8;
4438 intel_crtc_load_lut(crtc);
4442 * Get a pipe with a simple mode set on it for doing load-based monitor
4445 * It will be up to the load-detect code to adjust the pipe as appropriate for
4446 * its requirements. The pipe will be connected to no other encoders.
4448 * Currently this code will only succeed if there is a pipe with no encoders
4449 * configured for it. In the future, it could choose to temporarily disable
4450 * some outputs to free up a pipe for its use.
4452 * \return crtc, or NULL if no pipes are available.
4455 /* VESA 640x480x72Hz mode to set on the pipe */
4456 static struct drm_display_mode load_detect_mode = {
4457 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4458 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4461 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4462 struct drm_connector *connector,
4463 struct drm_display_mode *mode,
4466 struct intel_crtc *intel_crtc;
4467 struct drm_crtc *possible_crtc;
4468 struct drm_crtc *supported_crtc =NULL;
4469 struct drm_encoder *encoder = &intel_encoder->enc;
4470 struct drm_crtc *crtc = NULL;
4471 struct drm_device *dev = encoder->dev;
4472 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4473 struct drm_crtc_helper_funcs *crtc_funcs;
4477 * Algorithm gets a little messy:
4478 * - if the connector already has an assigned crtc, use it (but make
4479 * sure it's on first)
4480 * - try to find the first unused crtc that can drive this connector,
4481 * and use that if we find one
4482 * - if there are no unused crtcs available, try to use the first
4483 * one we found that supports the connector
4486 /* See if we already have a CRTC for this connector */
4487 if (encoder->crtc) {
4488 crtc = encoder->crtc;
4489 /* Make sure the crtc and connector are running */
4490 intel_crtc = to_intel_crtc(crtc);
4491 *dpms_mode = intel_crtc->dpms_mode;
4492 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4493 crtc_funcs = crtc->helper_private;
4494 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4495 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4500 /* Find an unused one (if possible) */
4501 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4503 if (!(encoder->possible_crtcs & (1 << i)))
4505 if (!possible_crtc->enabled) {
4506 crtc = possible_crtc;
4509 if (!supported_crtc)
4510 supported_crtc = possible_crtc;
4514 * If we didn't find an unused CRTC, don't use any.
4520 encoder->crtc = crtc;
4521 connector->encoder = encoder;
4522 intel_encoder->load_detect_temp = true;
4524 intel_crtc = to_intel_crtc(crtc);
4525 *dpms_mode = intel_crtc->dpms_mode;
4527 if (!crtc->enabled) {
4529 mode = &load_detect_mode;
4530 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4532 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4533 crtc_funcs = crtc->helper_private;
4534 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4537 /* Add this connector to the crtc */
4538 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4539 encoder_funcs->commit(encoder);
4541 /* let the connector get through one full cycle before testing */
4542 intel_wait_for_vblank(dev, intel_crtc->pipe);
4547 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4548 struct drm_connector *connector, int dpms_mode)
4550 struct drm_encoder *encoder = &intel_encoder->enc;
4551 struct drm_device *dev = encoder->dev;
4552 struct drm_crtc *crtc = encoder->crtc;
4553 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4554 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4556 if (intel_encoder->load_detect_temp) {
4557 encoder->crtc = NULL;
4558 connector->encoder = NULL;
4559 intel_encoder->load_detect_temp = false;
4560 crtc->enabled = drm_helper_crtc_in_use(crtc);
4561 drm_helper_disable_unused_functions(dev);
4564 /* Switch crtc and encoder back off if necessary */
4565 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4566 if (encoder->crtc == crtc)
4567 encoder_funcs->dpms(encoder, dpms_mode);
4568 crtc_funcs->dpms(crtc, dpms_mode);
4572 /* Returns the clock of the currently programmed mode of the given pipe. */
4573 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4575 struct drm_i915_private *dev_priv = dev->dev_private;
4576 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4577 int pipe = intel_crtc->pipe;
4578 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4580 intel_clock_t clock;
4582 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4583 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4585 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4587 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4588 if (IS_PINEVIEW(dev)) {
4589 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4590 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4592 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4593 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4597 if (IS_PINEVIEW(dev))
4598 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4599 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4601 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4602 DPLL_FPA01_P1_POST_DIV_SHIFT);
4604 switch (dpll & DPLL_MODE_MASK) {
4605 case DPLLB_MODE_DAC_SERIAL:
4606 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4609 case DPLLB_MODE_LVDS:
4610 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4614 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4615 "mode\n", (int)(dpll & DPLL_MODE_MASK));
4619 /* XXX: Handle the 100Mhz refclk */
4620 intel_clock(dev, 96000, &clock);
4622 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4625 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4626 DPLL_FPA01_P1_POST_DIV_SHIFT);
4629 if ((dpll & PLL_REF_INPUT_MASK) ==
4630 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4631 /* XXX: might not be 66MHz */
4632 intel_clock(dev, 66000, &clock);
4634 intel_clock(dev, 48000, &clock);
4636 if (dpll & PLL_P1_DIVIDE_BY_TWO)
4639 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4640 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4642 if (dpll & PLL_P2_DIVIDE_BY_4)
4647 intel_clock(dev, 48000, &clock);
4651 /* XXX: It would be nice to validate the clocks, but we can't reuse
4652 * i830PllIsValid() because it relies on the xf86_config connector
4653 * configuration being accurate, which it isn't necessarily.
4659 /** Returns the currently programmed mode of the given pipe. */
4660 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4661 struct drm_crtc *crtc)
4663 struct drm_i915_private *dev_priv = dev->dev_private;
4664 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4665 int pipe = intel_crtc->pipe;
4666 struct drm_display_mode *mode;
4667 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4668 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4669 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4670 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4672 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4676 mode->clock = intel_crtc_clock_get(dev, crtc);
4677 mode->hdisplay = (htot & 0xffff) + 1;
4678 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4679 mode->hsync_start = (hsync & 0xffff) + 1;
4680 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4681 mode->vdisplay = (vtot & 0xffff) + 1;
4682 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4683 mode->vsync_start = (vsync & 0xffff) + 1;
4684 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4686 drm_mode_set_name(mode);
4687 drm_mode_set_crtcinfo(mode, 0);
4692 #define GPU_IDLE_TIMEOUT 500 /* ms */
4694 /* When this timer fires, we've been idle for awhile */
4695 static void intel_gpu_idle_timer(unsigned long arg)
4697 struct drm_device *dev = (struct drm_device *)arg;
4698 drm_i915_private_t *dev_priv = dev->dev_private;
4700 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4702 dev_priv->busy = false;
4704 queue_work(dev_priv->wq, &dev_priv->idle_work);
4707 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4709 static void intel_crtc_idle_timer(unsigned long arg)
4711 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4712 struct drm_crtc *crtc = &intel_crtc->base;
4713 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4715 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4717 intel_crtc->busy = false;
4719 queue_work(dev_priv->wq, &dev_priv->idle_work);
4722 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
4724 struct drm_device *dev = crtc->dev;
4725 drm_i915_private_t *dev_priv = dev->dev_private;
4726 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4727 int pipe = intel_crtc->pipe;
4728 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4729 int dpll = I915_READ(dpll_reg);
4731 if (HAS_PCH_SPLIT(dev))
4734 if (!dev_priv->lvds_downclock_avail)
4737 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4738 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4740 /* Unlock panel regs */
4741 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4744 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4745 I915_WRITE(dpll_reg, dpll);
4746 dpll = I915_READ(dpll_reg);
4747 intel_wait_for_vblank(dev, pipe);
4748 dpll = I915_READ(dpll_reg);
4749 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4750 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4752 /* ...and lock them again */
4753 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4756 /* Schedule downclock */
4758 mod_timer(&intel_crtc->idle_timer, jiffies +
4759 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4762 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4764 struct drm_device *dev = crtc->dev;
4765 drm_i915_private_t *dev_priv = dev->dev_private;
4766 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4767 int pipe = intel_crtc->pipe;
4768 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4769 int dpll = I915_READ(dpll_reg);
4771 if (HAS_PCH_SPLIT(dev))
4774 if (!dev_priv->lvds_downclock_avail)
4778 * Since this is called by a timer, we should never get here in
4781 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4782 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4784 /* Unlock panel regs */
4785 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4788 dpll |= DISPLAY_RATE_SELECT_FPA1;
4789 I915_WRITE(dpll_reg, dpll);
4790 dpll = I915_READ(dpll_reg);
4791 intel_wait_for_vblank(dev, pipe);
4792 dpll = I915_READ(dpll_reg);
4793 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4794 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4796 /* ...and lock them again */
4797 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4803 * intel_idle_update - adjust clocks for idleness
4804 * @work: work struct
4806 * Either the GPU or display (or both) went idle. Check the busy status
4807 * here and adjust the CRTC and GPU clocks as necessary.
4809 static void intel_idle_update(struct work_struct *work)
4811 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4813 struct drm_device *dev = dev_priv->dev;
4814 struct drm_crtc *crtc;
4815 struct intel_crtc *intel_crtc;
4818 if (!i915_powersave)
4821 mutex_lock(&dev->struct_mutex);
4823 i915_update_gfx_val(dev_priv);
4825 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4826 /* Skip inactive CRTCs */
4831 intel_crtc = to_intel_crtc(crtc);
4832 if (!intel_crtc->busy)
4833 intel_decrease_pllclock(crtc);
4836 if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4837 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4838 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4841 mutex_unlock(&dev->struct_mutex);
4845 * intel_mark_busy - mark the GPU and possibly the display busy
4847 * @obj: object we're operating on
4849 * Callers can use this function to indicate that the GPU is busy processing
4850 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
4851 * buffer), we'll also mark the display as busy, so we know to increase its
4854 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4856 drm_i915_private_t *dev_priv = dev->dev_private;
4857 struct drm_crtc *crtc = NULL;
4858 struct intel_framebuffer *intel_fb;
4859 struct intel_crtc *intel_crtc;
4861 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4864 if (!dev_priv->busy) {
4865 if (IS_I945G(dev) || IS_I945GM(dev)) {
4868 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4869 fw_blc_self = I915_READ(FW_BLC_SELF);
4870 fw_blc_self &= ~FW_BLC_SELF_EN;
4871 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4873 dev_priv->busy = true;
4875 mod_timer(&dev_priv->idle_timer, jiffies +
4876 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4878 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4882 intel_crtc = to_intel_crtc(crtc);
4883 intel_fb = to_intel_framebuffer(crtc->fb);
4884 if (intel_fb->obj == obj) {
4885 if (!intel_crtc->busy) {
4886 if (IS_I945G(dev) || IS_I945GM(dev)) {
4889 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4890 fw_blc_self = I915_READ(FW_BLC_SELF);
4891 fw_blc_self &= ~FW_BLC_SELF_EN;
4892 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4894 /* Non-busy -> busy, upclock */
4895 intel_increase_pllclock(crtc, true);
4896 intel_crtc->busy = true;
4898 /* Busy -> busy, put off timer */
4899 mod_timer(&intel_crtc->idle_timer, jiffies +
4900 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4906 static void intel_crtc_destroy(struct drm_crtc *crtc)
4908 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4910 drm_crtc_cleanup(crtc);
4914 struct intel_unpin_work {
4915 struct work_struct work;
4916 struct drm_device *dev;
4917 struct drm_gem_object *old_fb_obj;
4918 struct drm_gem_object *pending_flip_obj;
4919 struct drm_pending_vblank_event *event;
4923 static void intel_unpin_work_fn(struct work_struct *__work)
4925 struct intel_unpin_work *work =
4926 container_of(__work, struct intel_unpin_work, work);
4928 mutex_lock(&work->dev->struct_mutex);
4929 i915_gem_object_unpin(work->old_fb_obj);
4930 drm_gem_object_unreference(work->pending_flip_obj);
4931 drm_gem_object_unreference(work->old_fb_obj);
4932 mutex_unlock(&work->dev->struct_mutex);
4936 static void do_intel_finish_page_flip(struct drm_device *dev,
4937 struct drm_crtc *crtc)
4939 drm_i915_private_t *dev_priv = dev->dev_private;
4940 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4941 struct intel_unpin_work *work;
4942 struct drm_i915_gem_object *obj_priv;
4943 struct drm_pending_vblank_event *e;
4945 unsigned long flags;
4947 /* Ignore early vblank irqs */
4948 if (intel_crtc == NULL)
4951 spin_lock_irqsave(&dev->event_lock, flags);
4952 work = intel_crtc->unpin_work;
4953 if (work == NULL || !work->pending) {
4954 spin_unlock_irqrestore(&dev->event_lock, flags);
4958 intel_crtc->unpin_work = NULL;
4959 drm_vblank_put(dev, intel_crtc->pipe);
4963 do_gettimeofday(&now);
4964 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4965 e->event.tv_sec = now.tv_sec;
4966 e->event.tv_usec = now.tv_usec;
4967 list_add_tail(&e->base.link,
4968 &e->base.file_priv->event_list);
4969 wake_up_interruptible(&e->base.file_priv->event_wait);
4972 spin_unlock_irqrestore(&dev->event_lock, flags);
4974 obj_priv = to_intel_bo(work->pending_flip_obj);
4976 /* Initial scanout buffer will have a 0 pending flip count */
4977 if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4978 atomic_dec_and_test(&obj_priv->pending_flip))
4979 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4980 schedule_work(&work->work);
4982 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
4985 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4987 drm_i915_private_t *dev_priv = dev->dev_private;
4988 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4990 do_intel_finish_page_flip(dev, crtc);
4993 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
4995 drm_i915_private_t *dev_priv = dev->dev_private;
4996 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
4998 do_intel_finish_page_flip(dev, crtc);
5001 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5003 drm_i915_private_t *dev_priv = dev->dev_private;
5004 struct intel_crtc *intel_crtc =
5005 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5006 unsigned long flags;
5008 spin_lock_irqsave(&dev->event_lock, flags);
5009 if (intel_crtc->unpin_work) {
5010 intel_crtc->unpin_work->pending = 1;
5012 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5014 spin_unlock_irqrestore(&dev->event_lock, flags);
5017 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5018 struct drm_framebuffer *fb,
5019 struct drm_pending_vblank_event *event)
5021 struct drm_device *dev = crtc->dev;
5022 struct drm_i915_private *dev_priv = dev->dev_private;
5023 struct intel_framebuffer *intel_fb;
5024 struct drm_i915_gem_object *obj_priv;
5025 struct drm_gem_object *obj;
5026 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5027 struct intel_unpin_work *work;
5028 unsigned long flags, offset;
5029 int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
5033 work = kzalloc(sizeof *work, GFP_KERNEL);
5037 work->event = event;
5038 work->dev = crtc->dev;
5039 intel_fb = to_intel_framebuffer(crtc->fb);
5040 work->old_fb_obj = intel_fb->obj;
5041 INIT_WORK(&work->work, intel_unpin_work_fn);
5043 /* We borrow the event spin lock for protecting unpin_work */
5044 spin_lock_irqsave(&dev->event_lock, flags);
5045 if (intel_crtc->unpin_work) {
5046 spin_unlock_irqrestore(&dev->event_lock, flags);
5049 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5052 intel_crtc->unpin_work = work;
5053 spin_unlock_irqrestore(&dev->event_lock, flags);
5055 intel_fb = to_intel_framebuffer(fb);
5056 obj = intel_fb->obj;
5058 mutex_lock(&dev->struct_mutex);
5059 ret = intel_pin_and_fence_fb_obj(dev, obj);
5063 /* Reference the objects for the scheduled work. */
5064 drm_gem_object_reference(work->old_fb_obj);
5065 drm_gem_object_reference(obj);
5068 ret = i915_gem_object_flush_write_domain(obj);
5072 ret = drm_vblank_get(dev, intel_crtc->pipe);
5076 obj_priv = to_intel_bo(obj);
5077 atomic_inc(&obj_priv->pending_flip);
5078 work->pending_flip_obj = obj;
5080 if (intel_crtc->plane)
5081 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5083 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5085 if (IS_GEN3(dev) || IS_GEN2(dev)) {
5087 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5092 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5093 offset = obj_priv->gtt_offset;
5094 offset += (crtc->y * fb->pitch) + (crtc->x * (fb->bits_per_pixel) / 8);
5097 if (IS_I965G(dev)) {
5098 OUT_RING(MI_DISPLAY_FLIP |
5099 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5100 OUT_RING(fb->pitch);
5101 OUT_RING(offset | obj_priv->tiling_mode);
5102 pipesrc = I915_READ(pipesrc_reg);
5103 OUT_RING(pipesrc & 0x0fff0fff);
5104 } else if (IS_GEN3(dev)) {
5105 OUT_RING(MI_DISPLAY_FLIP_I915 |
5106 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5107 OUT_RING(fb->pitch);
5111 OUT_RING(MI_DISPLAY_FLIP |
5112 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5113 OUT_RING(fb->pitch);
5119 mutex_unlock(&dev->struct_mutex);
5121 trace_i915_flip_request(intel_crtc->plane, obj);
5126 drm_gem_object_unreference(work->old_fb_obj);
5127 drm_gem_object_unreference(obj);
5129 mutex_unlock(&dev->struct_mutex);
5131 spin_lock_irqsave(&dev->event_lock, flags);
5132 intel_crtc->unpin_work = NULL;
5133 spin_unlock_irqrestore(&dev->event_lock, flags);
5140 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
5141 .dpms = intel_crtc_dpms,
5142 .mode_fixup = intel_crtc_mode_fixup,
5143 .mode_set = intel_crtc_mode_set,
5144 .mode_set_base = intel_pipe_set_base,
5145 .mode_set_base_atomic = intel_pipe_set_base_atomic,
5146 .prepare = intel_crtc_prepare,
5147 .commit = intel_crtc_commit,
5148 .load_lut = intel_crtc_load_lut,
5151 static const struct drm_crtc_funcs intel_crtc_funcs = {
5152 .cursor_set = intel_crtc_cursor_set,
5153 .cursor_move = intel_crtc_cursor_move,
5154 .gamma_set = intel_crtc_gamma_set,
5155 .set_config = drm_crtc_helper_set_config,
5156 .destroy = intel_crtc_destroy,
5157 .page_flip = intel_crtc_page_flip,
5161 static void intel_crtc_init(struct drm_device *dev, int pipe)
5163 drm_i915_private_t *dev_priv = dev->dev_private;
5164 struct intel_crtc *intel_crtc;
5167 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5168 if (intel_crtc == NULL)
5171 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5173 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5174 intel_crtc->pipe = pipe;
5175 intel_crtc->plane = pipe;
5176 for (i = 0; i < 256; i++) {
5177 intel_crtc->lut_r[i] = i;
5178 intel_crtc->lut_g[i] = i;
5179 intel_crtc->lut_b[i] = i;
5182 /* Swap pipes & planes for FBC on pre-965 */
5183 intel_crtc->pipe = pipe;
5184 intel_crtc->plane = pipe;
5185 if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
5186 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5187 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
5190 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5191 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5192 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5193 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5195 intel_crtc->cursor_addr = 0;
5196 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
5197 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5199 intel_crtc->busy = false;
5201 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5202 (unsigned long)intel_crtc);
5205 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5206 struct drm_file *file_priv)
5208 drm_i915_private_t *dev_priv = dev->dev_private;
5209 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5210 struct drm_mode_object *drmmode_obj;
5211 struct intel_crtc *crtc;
5214 DRM_ERROR("called with no initialization\n");
5218 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5219 DRM_MODE_OBJECT_CRTC);
5222 DRM_ERROR("no such CRTC id\n");
5226 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5227 pipe_from_crtc_id->pipe = crtc->pipe;
5232 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
5234 struct drm_crtc *crtc = NULL;
5236 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5237 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5238 if (intel_crtc->pipe == pipe)
5244 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5247 struct drm_encoder *encoder;
5250 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5251 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5252 if (type_mask & intel_encoder->clone_mask)
5253 index_mask |= (1 << entry);
5260 static void intel_setup_outputs(struct drm_device *dev)
5262 struct drm_i915_private *dev_priv = dev->dev_private;
5263 struct drm_encoder *encoder;
5264 bool dpd_is_edp = false;
5266 if (IS_MOBILE(dev) && !IS_I830(dev))
5267 intel_lvds_init(dev);
5269 if (HAS_PCH_SPLIT(dev)) {
5270 dpd_is_edp = intel_dpd_is_edp(dev);
5272 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5273 intel_dp_init(dev, DP_A);
5275 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5276 intel_dp_init(dev, PCH_DP_D);
5279 intel_crt_init(dev);
5281 if (HAS_PCH_SPLIT(dev)) {
5284 if (I915_READ(HDMIB) & PORT_DETECTED) {
5285 /* PCH SDVOB multiplex with HDMIB */
5286 found = intel_sdvo_init(dev, PCH_SDVOB);
5288 intel_hdmi_init(dev, HDMIB);
5289 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5290 intel_dp_init(dev, PCH_DP_B);
5293 if (I915_READ(HDMIC) & PORT_DETECTED)
5294 intel_hdmi_init(dev, HDMIC);
5296 if (I915_READ(HDMID) & PORT_DETECTED)
5297 intel_hdmi_init(dev, HDMID);
5299 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5300 intel_dp_init(dev, PCH_DP_C);
5302 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5303 intel_dp_init(dev, PCH_DP_D);
5305 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5308 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5309 DRM_DEBUG_KMS("probing SDVOB\n");
5310 found = intel_sdvo_init(dev, SDVOB);
5311 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5312 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5313 intel_hdmi_init(dev, SDVOB);
5316 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5317 DRM_DEBUG_KMS("probing DP_B\n");
5318 intel_dp_init(dev, DP_B);
5322 /* Before G4X SDVOC doesn't have its own detect register */
5324 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5325 DRM_DEBUG_KMS("probing SDVOC\n");
5326 found = intel_sdvo_init(dev, SDVOC);
5329 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5331 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5332 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5333 intel_hdmi_init(dev, SDVOC);
5335 if (SUPPORTS_INTEGRATED_DP(dev)) {
5336 DRM_DEBUG_KMS("probing DP_C\n");
5337 intel_dp_init(dev, DP_C);
5341 if (SUPPORTS_INTEGRATED_DP(dev) &&
5342 (I915_READ(DP_D) & DP_DETECTED)) {
5343 DRM_DEBUG_KMS("probing DP_D\n");
5344 intel_dp_init(dev, DP_D);
5346 } else if (IS_GEN2(dev))
5347 intel_dvo_init(dev);
5349 if (SUPPORTS_TV(dev))
5352 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5353 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5355 encoder->possible_crtcs = intel_encoder->crtc_mask;
5356 encoder->possible_clones = intel_encoder_clones(dev,
5357 intel_encoder->clone_mask);
5361 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5363 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5365 drm_framebuffer_cleanup(fb);
5366 drm_gem_object_unreference_unlocked(intel_fb->obj);
5371 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5372 struct drm_file *file_priv,
5373 unsigned int *handle)
5375 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5376 struct drm_gem_object *object = intel_fb->obj;
5378 return drm_gem_handle_create(file_priv, object, handle);
5381 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5382 .destroy = intel_user_framebuffer_destroy,
5383 .create_handle = intel_user_framebuffer_create_handle,
5386 int intel_framebuffer_init(struct drm_device *dev,
5387 struct intel_framebuffer *intel_fb,
5388 struct drm_mode_fb_cmd *mode_cmd,
5389 struct drm_gem_object *obj)
5393 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5395 DRM_ERROR("framebuffer init failed %d\n", ret);
5399 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5400 intel_fb->obj = obj;
5404 static struct drm_framebuffer *
5405 intel_user_framebuffer_create(struct drm_device *dev,
5406 struct drm_file *filp,
5407 struct drm_mode_fb_cmd *mode_cmd)
5409 struct drm_gem_object *obj;
5410 struct intel_framebuffer *intel_fb;
5413 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5415 return ERR_PTR(-ENOENT);
5417 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5419 return ERR_PTR(-ENOMEM);
5421 ret = intel_framebuffer_init(dev, intel_fb,
5424 drm_gem_object_unreference_unlocked(obj);
5426 return ERR_PTR(ret);
5429 return &intel_fb->base;
5432 static const struct drm_mode_config_funcs intel_mode_funcs = {
5433 .fb_create = intel_user_framebuffer_create,
5434 .output_poll_changed = intel_fb_output_poll_changed,
5437 static struct drm_gem_object *
5438 intel_alloc_context_page(struct drm_device *dev)
5440 struct drm_gem_object *ctx;
5443 ctx = i915_gem_alloc_object(dev, 4096);
5445 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5449 mutex_lock(&dev->struct_mutex);
5450 ret = i915_gem_object_pin(ctx, 4096);
5452 DRM_ERROR("failed to pin power context: %d\n", ret);
5456 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
5458 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5461 mutex_unlock(&dev->struct_mutex);
5466 i915_gem_object_unpin(ctx);
5468 drm_gem_object_unreference(ctx);
5469 mutex_unlock(&dev->struct_mutex);
5473 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5475 struct drm_i915_private *dev_priv = dev->dev_private;
5478 rgvswctl = I915_READ16(MEMSWCTL);
5479 if (rgvswctl & MEMCTL_CMD_STS) {
5480 DRM_DEBUG("gpu busy, RCS change rejected\n");
5481 return false; /* still busy with another command */
5484 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5485 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5486 I915_WRITE16(MEMSWCTL, rgvswctl);
5487 POSTING_READ16(MEMSWCTL);
5489 rgvswctl |= MEMCTL_CMD_STS;
5490 I915_WRITE16(MEMSWCTL, rgvswctl);
5495 void ironlake_enable_drps(struct drm_device *dev)
5497 struct drm_i915_private *dev_priv = dev->dev_private;
5498 u32 rgvmodectl = I915_READ(MEMMODECTL);
5499 u8 fmax, fmin, fstart, vstart;
5501 /* 100ms RC evaluation intervals */
5502 I915_WRITE(RCUPEI, 100000);
5503 I915_WRITE(RCDNEI, 100000);
5505 /* Set max/min thresholds to 90ms and 80ms respectively */
5506 I915_WRITE(RCBMAXAVG, 90000);
5507 I915_WRITE(RCBMINAVG, 80000);
5509 I915_WRITE(MEMIHYST, 1);
5511 /* Set up min, max, and cur for interrupt handling */
5512 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5513 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5514 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5515 MEMMODE_FSTART_SHIFT;
5518 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5521 dev_priv->fmax = fstart; /* IPS callback will increase this */
5522 dev_priv->fstart = fstart;
5524 dev_priv->max_delay = fmax;
5525 dev_priv->min_delay = fmin;
5526 dev_priv->cur_delay = fstart;
5528 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5531 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5534 * Interrupts will be enabled in ironlake_irq_postinstall
5537 I915_WRITE(VIDSTART, vstart);
5538 POSTING_READ(VIDSTART);
5540 rgvmodectl |= MEMMODE_SWMODE_EN;
5541 I915_WRITE(MEMMODECTL, rgvmodectl);
5543 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 1, 0))
5544 DRM_ERROR("stuck trying to change perf mode\n");
5547 ironlake_set_drps(dev, fstart);
5549 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5551 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5552 dev_priv->last_count2 = I915_READ(0x112f4);
5553 getrawmonotonic(&dev_priv->last_time2);
5556 void ironlake_disable_drps(struct drm_device *dev)
5558 struct drm_i915_private *dev_priv = dev->dev_private;
5559 u16 rgvswctl = I915_READ16(MEMSWCTL);
5561 /* Ack interrupts, disable EFC interrupt */
5562 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5563 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5564 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5565 I915_WRITE(DEIIR, DE_PCU_EVENT);
5566 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5568 /* Go back to the starting frequency */
5569 ironlake_set_drps(dev, dev_priv->fstart);
5571 rgvswctl |= MEMCTL_CMD_STS;
5572 I915_WRITE(MEMSWCTL, rgvswctl);
5577 static unsigned long intel_pxfreq(u32 vidfreq)
5580 int div = (vidfreq & 0x3f0000) >> 16;
5581 int post = (vidfreq & 0x3000) >> 12;
5582 int pre = (vidfreq & 0x7);
5587 freq = ((div * 133333) / ((1<<post) * pre));
5592 void intel_init_emon(struct drm_device *dev)
5594 struct drm_i915_private *dev_priv = dev->dev_private;
5599 /* Disable to program */
5603 /* Program energy weights for various events */
5604 I915_WRITE(SDEW, 0x15040d00);
5605 I915_WRITE(CSIEW0, 0x007f0000);
5606 I915_WRITE(CSIEW1, 0x1e220004);
5607 I915_WRITE(CSIEW2, 0x04000004);
5609 for (i = 0; i < 5; i++)
5610 I915_WRITE(PEW + (i * 4), 0);
5611 for (i = 0; i < 3; i++)
5612 I915_WRITE(DEW + (i * 4), 0);
5614 /* Program P-state weights to account for frequency power adjustment */
5615 for (i = 0; i < 16; i++) {
5616 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5617 unsigned long freq = intel_pxfreq(pxvidfreq);
5618 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5623 val *= (freq / 1000);
5625 val /= (127*127*900);
5627 DRM_ERROR("bad pxval: %ld\n", val);
5630 /* Render standby states get 0 weight */
5634 for (i = 0; i < 4; i++) {
5635 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5636 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5637 I915_WRITE(PXW + (i * 4), val);
5640 /* Adjust magic regs to magic values (more experimental results) */
5641 I915_WRITE(OGW0, 0);
5642 I915_WRITE(OGW1, 0);
5643 I915_WRITE(EG0, 0x00007f00);
5644 I915_WRITE(EG1, 0x0000000e);
5645 I915_WRITE(EG2, 0x000e0000);
5646 I915_WRITE(EG3, 0x68000300);
5647 I915_WRITE(EG4, 0x42000000);
5648 I915_WRITE(EG5, 0x00140031);
5652 for (i = 0; i < 8; i++)
5653 I915_WRITE(PXWL + (i * 4), 0);
5655 /* Enable PMON + select events */
5656 I915_WRITE(ECR, 0x80000019);
5658 lcfuse = I915_READ(LCFUSE02);
5660 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5663 void intel_init_clock_gating(struct drm_device *dev)
5665 struct drm_i915_private *dev_priv = dev->dev_private;
5668 * Disable clock gating reported to work incorrectly according to the
5669 * specs, but enable as much else as we can.
5671 if (HAS_PCH_SPLIT(dev)) {
5672 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5674 if (IS_IRONLAKE(dev)) {
5675 /* Required for FBC */
5676 dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5677 /* Required for CxSR */
5678 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5680 I915_WRITE(PCH_3DCGDIS0,
5681 MARIUNIT_CLOCK_GATE_DISABLE |
5682 SVSMUNIT_CLOCK_GATE_DISABLE);
5685 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5688 * According to the spec the following bits should be set in
5689 * order to enable memory self-refresh
5690 * The bit 22/21 of 0x42004
5691 * The bit 5 of 0x42020
5692 * The bit 15 of 0x45000
5694 if (IS_IRONLAKE(dev)) {
5695 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5696 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5697 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5698 I915_WRITE(ILK_DSPCLK_GATE,
5699 (I915_READ(ILK_DSPCLK_GATE) |
5700 ILK_DPARB_CLK_GATE));
5701 I915_WRITE(DISP_ARB_CTL,
5702 (I915_READ(DISP_ARB_CTL) |
5706 * Based on the document from hardware guys the following bits
5707 * should be set unconditionally in order to enable FBC.
5708 * The bit 22 of 0x42000
5709 * The bit 22 of 0x42004
5710 * The bit 7,8,9 of 0x42020.
5712 if (IS_IRONLAKE_M(dev)) {
5713 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5714 I915_READ(ILK_DISPLAY_CHICKEN1) |
5716 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5717 I915_READ(ILK_DISPLAY_CHICKEN2) |
5719 I915_WRITE(ILK_DSPCLK_GATE,
5720 I915_READ(ILK_DSPCLK_GATE) |
5727 } else if (IS_G4X(dev)) {
5728 uint32_t dspclk_gate;
5729 I915_WRITE(RENCLK_GATE_D1, 0);
5730 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5731 GS_UNIT_CLOCK_GATE_DISABLE |
5732 CL_UNIT_CLOCK_GATE_DISABLE);
5733 I915_WRITE(RAMCLK_GATE_D, 0);
5734 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5735 OVRUNIT_CLOCK_GATE_DISABLE |
5736 OVCUNIT_CLOCK_GATE_DISABLE;
5738 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5739 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5740 } else if (IS_I965GM(dev)) {
5741 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5742 I915_WRITE(RENCLK_GATE_D2, 0);
5743 I915_WRITE(DSPCLK_GATE_D, 0);
5744 I915_WRITE(RAMCLK_GATE_D, 0);
5745 I915_WRITE16(DEUC, 0);
5746 } else if (IS_I965G(dev)) {
5747 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5748 I965_RCC_CLOCK_GATE_DISABLE |
5749 I965_RCPB_CLOCK_GATE_DISABLE |
5750 I965_ISC_CLOCK_GATE_DISABLE |
5751 I965_FBC_CLOCK_GATE_DISABLE);
5752 I915_WRITE(RENCLK_GATE_D2, 0);
5753 } else if (IS_I9XX(dev)) {
5754 u32 dstate = I915_READ(D_STATE);
5756 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5757 DSTATE_DOT_CLOCK_GATING;
5758 I915_WRITE(D_STATE, dstate);
5759 } else if (IS_I85X(dev) || IS_I865G(dev)) {
5760 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5761 } else if (IS_I830(dev)) {
5762 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5766 * GPU can automatically power down the render unit if given a page
5769 if (IS_IRONLAKE_M(dev)) {
5770 if (dev_priv->renderctx == NULL)
5771 dev_priv->renderctx = intel_alloc_context_page(dev);
5772 if (dev_priv->renderctx) {
5773 struct drm_i915_gem_object *obj_priv;
5774 obj_priv = to_intel_bo(dev_priv->renderctx);
5777 OUT_RING(MI_SET_CONTEXT);
5778 OUT_RING(obj_priv->gtt_offset |
5780 MI_SAVE_EXT_STATE_EN |
5781 MI_RESTORE_EXT_STATE_EN |
5782 MI_RESTORE_INHIBIT);
5788 DRM_DEBUG_KMS("Failed to allocate render context."
5794 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5795 struct drm_i915_gem_object *obj_priv = NULL;
5797 if (dev_priv->pwrctx) {
5798 obj_priv = to_intel_bo(dev_priv->pwrctx);
5800 struct drm_gem_object *pwrctx;
5802 pwrctx = intel_alloc_context_page(dev);
5804 dev_priv->pwrctx = pwrctx;
5805 obj_priv = to_intel_bo(pwrctx);
5810 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5811 I915_WRITE(MCHBAR_RENDER_STANDBY,
5812 I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5817 /* Set up chip specific display functions */
5818 static void intel_init_display(struct drm_device *dev)
5820 struct drm_i915_private *dev_priv = dev->dev_private;
5822 /* We always want a DPMS function */
5823 if (HAS_PCH_SPLIT(dev))
5824 dev_priv->display.dpms = ironlake_crtc_dpms;
5826 dev_priv->display.dpms = i9xx_crtc_dpms;
5828 if (I915_HAS_FBC(dev)) {
5829 if (IS_IRONLAKE_M(dev)) {
5830 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5831 dev_priv->display.enable_fbc = ironlake_enable_fbc;
5832 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5833 } else if (IS_GM45(dev)) {
5834 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5835 dev_priv->display.enable_fbc = g4x_enable_fbc;
5836 dev_priv->display.disable_fbc = g4x_disable_fbc;
5837 } else if (IS_I965GM(dev)) {
5838 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5839 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5840 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5842 /* 855GM needs testing */
5845 /* Returns the core display clock speed */
5846 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5847 dev_priv->display.get_display_clock_speed =
5848 i945_get_display_clock_speed;
5849 else if (IS_I915G(dev))
5850 dev_priv->display.get_display_clock_speed =
5851 i915_get_display_clock_speed;
5852 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5853 dev_priv->display.get_display_clock_speed =
5854 i9xx_misc_get_display_clock_speed;
5855 else if (IS_I915GM(dev))
5856 dev_priv->display.get_display_clock_speed =
5857 i915gm_get_display_clock_speed;
5858 else if (IS_I865G(dev))
5859 dev_priv->display.get_display_clock_speed =
5860 i865_get_display_clock_speed;
5861 else if (IS_I85X(dev))
5862 dev_priv->display.get_display_clock_speed =
5863 i855_get_display_clock_speed;
5865 dev_priv->display.get_display_clock_speed =
5866 i830_get_display_clock_speed;
5868 /* For FIFO watermark updates */
5869 if (HAS_PCH_SPLIT(dev)) {
5870 if (IS_IRONLAKE(dev)) {
5871 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5872 dev_priv->display.update_wm = ironlake_update_wm;
5874 DRM_DEBUG_KMS("Failed to get proper latency. "
5876 dev_priv->display.update_wm = NULL;
5879 dev_priv->display.update_wm = NULL;
5880 } else if (IS_PINEVIEW(dev)) {
5881 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5884 dev_priv->mem_freq)) {
5885 DRM_INFO("failed to find known CxSR latency "
5886 "(found ddr%s fsb freq %d, mem freq %d), "
5888 (dev_priv->is_ddr3 == 1) ? "3": "2",
5889 dev_priv->fsb_freq, dev_priv->mem_freq);
5890 /* Disable CxSR and never update its watermark again */
5891 pineview_disable_cxsr(dev);
5892 dev_priv->display.update_wm = NULL;
5894 dev_priv->display.update_wm = pineview_update_wm;
5895 } else if (IS_G4X(dev))
5896 dev_priv->display.update_wm = g4x_update_wm;
5897 else if (IS_I965G(dev))
5898 dev_priv->display.update_wm = i965_update_wm;
5899 else if (IS_I9XX(dev)) {
5900 dev_priv->display.update_wm = i9xx_update_wm;
5901 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5902 } else if (IS_I85X(dev)) {
5903 dev_priv->display.update_wm = i9xx_update_wm;
5904 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5906 dev_priv->display.update_wm = i830_update_wm;
5908 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5910 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5915 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
5916 * resume, or other times. This quirk makes sure that's the case for
5919 static void quirk_pipea_force (struct drm_device *dev)
5921 struct drm_i915_private *dev_priv = dev->dev_private;
5923 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
5924 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
5927 struct intel_quirk {
5929 int subsystem_vendor;
5930 int subsystem_device;
5931 void (*hook)(struct drm_device *dev);
5934 struct intel_quirk intel_quirks[] = {
5935 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
5936 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
5937 /* HP Mini needs pipe A force quirk (LP: #322104) */
5938 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
5940 /* Thinkpad R31 needs pipe A force quirk */
5941 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
5942 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
5943 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
5945 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
5946 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
5947 /* ThinkPad X40 needs pipe A force quirk */
5949 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
5950 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
5952 /* 855 & before need to leave pipe A & dpll A up */
5953 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5954 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5957 static void intel_init_quirks(struct drm_device *dev)
5959 struct pci_dev *d = dev->pdev;
5962 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
5963 struct intel_quirk *q = &intel_quirks[i];
5965 if (d->device == q->device &&
5966 (d->subsystem_vendor == q->subsystem_vendor ||
5967 q->subsystem_vendor == PCI_ANY_ID) &&
5968 (d->subsystem_device == q->subsystem_device ||
5969 q->subsystem_device == PCI_ANY_ID))
5974 /* Disable the VGA plane that we never use */
5975 static void i915_disable_vga(struct drm_device *dev)
5977 struct drm_i915_private *dev_priv = dev->dev_private;
5981 if (HAS_PCH_SPLIT(dev))
5982 vga_reg = CPU_VGACNTRL;
5986 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5987 outb(1, VGA_SR_INDEX);
5988 sr1 = inb(VGA_SR_DATA);
5989 outb(sr1 | 1<<5, VGA_SR_DATA);
5990 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5993 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
5994 POSTING_READ(vga_reg);
5997 void intel_modeset_init(struct drm_device *dev)
5999 struct drm_i915_private *dev_priv = dev->dev_private;
6002 drm_mode_config_init(dev);
6004 dev->mode_config.min_width = 0;
6005 dev->mode_config.min_height = 0;
6007 dev->mode_config.funcs = (void *)&intel_mode_funcs;
6009 intel_init_quirks(dev);
6011 intel_init_display(dev);
6013 if (IS_I965G(dev)) {
6014 dev->mode_config.max_width = 8192;
6015 dev->mode_config.max_height = 8192;
6016 } else if (IS_I9XX(dev)) {
6017 dev->mode_config.max_width = 4096;
6018 dev->mode_config.max_height = 4096;
6020 dev->mode_config.max_width = 2048;
6021 dev->mode_config.max_height = 2048;
6024 /* set memory base */
6026 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
6028 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
6030 if (IS_MOBILE(dev) || IS_I9XX(dev))
6031 dev_priv->num_pipe = 2;
6033 dev_priv->num_pipe = 1;
6034 DRM_DEBUG_KMS("%d display pipe%s available.\n",
6035 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6037 for (i = 0; i < dev_priv->num_pipe; i++) {
6038 intel_crtc_init(dev, i);
6041 intel_setup_outputs(dev);
6043 intel_init_clock_gating(dev);
6045 /* Just disable it once at startup */
6046 i915_disable_vga(dev);
6048 if (IS_IRONLAKE_M(dev)) {
6049 ironlake_enable_drps(dev);
6050 intel_init_emon(dev);
6053 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6054 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6055 (unsigned long)dev);
6057 intel_setup_overlay(dev);
6060 void intel_modeset_cleanup(struct drm_device *dev)
6062 struct drm_i915_private *dev_priv = dev->dev_private;
6063 struct drm_crtc *crtc;
6064 struct intel_crtc *intel_crtc;
6066 mutex_lock(&dev->struct_mutex);
6068 drm_kms_helper_poll_fini(dev);
6069 intel_fbdev_fini(dev);
6071 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6072 /* Skip inactive CRTCs */
6076 intel_crtc = to_intel_crtc(crtc);
6077 intel_increase_pllclock(crtc, false);
6078 del_timer_sync(&intel_crtc->idle_timer);
6081 del_timer_sync(&dev_priv->idle_timer);
6083 if (dev_priv->display.disable_fbc)
6084 dev_priv->display.disable_fbc(dev);
6086 if (dev_priv->renderctx) {
6087 struct drm_i915_gem_object *obj_priv;
6089 obj_priv = to_intel_bo(dev_priv->renderctx);
6090 I915_WRITE(CCID, obj_priv->gtt_offset &~ CCID_EN);
6092 i915_gem_object_unpin(dev_priv->renderctx);
6093 drm_gem_object_unreference(dev_priv->renderctx);
6096 if (dev_priv->pwrctx) {
6097 struct drm_i915_gem_object *obj_priv;
6099 obj_priv = to_intel_bo(dev_priv->pwrctx);
6100 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
6102 i915_gem_object_unpin(dev_priv->pwrctx);
6103 drm_gem_object_unreference(dev_priv->pwrctx);
6106 if (IS_IRONLAKE_M(dev))
6107 ironlake_disable_drps(dev);
6109 mutex_unlock(&dev->struct_mutex);
6111 drm_mode_config_cleanup(dev);
6116 * Return which encoder is currently attached for connector.
6118 struct drm_encoder *intel_attached_encoder (struct drm_connector *connector)
6120 struct drm_mode_object *obj;
6121 struct drm_encoder *encoder;
6124 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
6125 if (connector->encoder_ids[i] == 0)
6128 obj = drm_mode_object_find(connector->dev,
6129 connector->encoder_ids[i],
6130 DRM_MODE_OBJECT_ENCODER);
6134 encoder = obj_to_encoder(obj);
6141 * set vga decode state - true == enable VGA decode
6143 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6145 struct drm_i915_private *dev_priv = dev->dev_private;
6148 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6150 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6152 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6153 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);